hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include "hw.h"
  14 #include "pci.h"
  15 #include "scsi-disk.h"
  16
  17 //#define DEBUG_LSI
  18 //#define DEBUG_LSI_REG
  19
  20 #ifdef DEBUG_LSI
  21 #define DPRINTF(fmt, args...) \
  22 do { printf("lsi_scsi: " fmt , ##args); } while (0)
  23 #define BADF(fmt, args...) \
  24 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
  25 #else
  26 #define DPRINTF(fmt, args...) do {} while(0)
  27 #define BADF(fmt, args...) \
  28 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
  29 #endif
  30
  31 #define LSI_SCNTL0_TRG    0x01
  32 #define LSI_SCNTL0_AAP    0x02
  33 #define LSI_SCNTL0_EPC    0x08
  34 #define LSI_SCNTL0_WATN   0x10
  35 #define LSI_SCNTL0_START  0x20
  36
  37 #define LSI_SCNTL1_SST    0x01
  38 #define LSI_SCNTL1_IARB   0x02
  39 #define LSI_SCNTL1_AESP   0x04
  40 #define LSI_SCNTL1_RST    0x08
  41 #define LSI_SCNTL1_CON    0x10
  42 #define LSI_SCNTL1_DHP    0x20
  43 #define LSI_SCNTL1_ADB    0x40
  44 #define LSI_SCNTL1_EXC    0x80
  45
  46 #define LSI_SCNTL2_WSR    0x01
  47 #define LSI_SCNTL2_VUE0   0x02
  48 #define LSI_SCNTL2_VUE1   0x04
  49 #define LSI_SCNTL2_WSS    0x08
  50 #define LSI_SCNTL2_SLPHBEN 0x10
  51 #define LSI_SCNTL2_SLPMD  0x20
  52 #define LSI_SCNTL2_CHM    0x40
  53 #define LSI_SCNTL2_SDU    0x80
  54
  55 #define LSI_ISTAT0_DIP    0x01
  56 #define LSI_ISTAT0_SIP    0x02
  57 #define LSI_ISTAT0_INTF   0x04
  58 #define LSI_ISTAT0_CON    0x08
  59 #define LSI_ISTAT0_SEM    0x10
  60 #define LSI_ISTAT0_SIGP   0x20
  61 #define LSI_ISTAT0_SRST   0x40
  62 #define LSI_ISTAT0_ABRT   0x80
  63
  64 #define LSI_ISTAT1_SI     0x01
  65 #define LSI_ISTAT1_SRUN   0x02
  66 #define LSI_ISTAT1_FLSH   0x04
  67
  68 #define LSI_SSTAT0_SDP0   0x01
  69 #define LSI_SSTAT0_RST    0x02
  70 #define LSI_SSTAT0_WOA    0x04
  71 #define LSI_SSTAT0_LOA    0x08
  72 #define LSI_SSTAT0_AIP    0x10
  73 #define LSI_SSTAT0_OLF    0x20
  74 #define LSI_SSTAT0_ORF    0x40
  75 #define LSI_SSTAT0_ILF    0x80
  76
  77 #define LSI_SIST0_PAR     0x01
  78 #define LSI_SIST0_RST     0x02
  79 #define LSI_SIST0_UDC     0x04
  80 #define LSI_SIST0_SGE     0x08
  81 #define LSI_SIST0_RSL     0x10
  82 #define LSI_SIST0_SEL     0x20
  83 #define LSI_SIST0_CMP     0x40
  84 #define LSI_SIST0_MA      0x80
  85
  86 #define LSI_SIST1_HTH     0x01
  87 #define LSI_SIST1_GEN     0x02
  88 #define LSI_SIST1_STO     0x04
  89 #define LSI_SIST1_SBMC    0x10
  90
  91 #define LSI_SOCL_IO       0x01
  92 #define LSI_SOCL_CD       0x02
  93 #define LSI_SOCL_MSG      0x04
  94 #define LSI_SOCL_ATN      0x08
  95 #define LSI_SOCL_SEL      0x10
  96 #define LSI_SOCL_BSY      0x20
  97 #define LSI_SOCL_ACK      0x40
  98 #define LSI_SOCL_REQ      0x80
  99
 100 #define LSI_DSTAT_IID     0x01
 101 #define LSI_DSTAT_SIR     0x04
 102 #define LSI_DSTAT_SSI     0x08
 103 #define LSI_DSTAT_ABRT    0x10
 104 #define LSI_DSTAT_BF      0x20
 105 #define LSI_DSTAT_MDPE    0x40
 106 #define LSI_DSTAT_DFE     0x80
 107
 108 #define LSI_DCNTL_COM     0x01
 109 #define LSI_DCNTL_IRQD    0x02
 110 #define LSI_DCNTL_STD     0x04
 111 #define LSI_DCNTL_IRQM    0x08
 112 #define LSI_DCNTL_SSM     0x10
 113 #define LSI_DCNTL_PFEN    0x20
 114 #define LSI_DCNTL_PFF     0x40
 115 #define LSI_DCNTL_CLSE    0x80
 116
 117 #define LSI_DMODE_MAN     0x01
 118 #define LSI_DMODE_BOF     0x02
 119 #define LSI_DMODE_ERMP    0x04
 120 #define LSI_DMODE_ERL     0x08
 121 #define LSI_DMODE_DIOM    0x10
 122 #define LSI_DMODE_SIOM    0x20
 123
 124 #define LSI_CTEST2_DACK   0x01
 125 #define LSI_CTEST2_DREQ   0x02
 126 #define LSI_CTEST2_TEOP   0x04
 127 #define LSI_CTEST2_PCICIE 0x08
 128 #define LSI_CTEST2_CM     0x10
 129 #define LSI_CTEST2_CIO    0x20
 130 #define LSI_CTEST2_SIGP   0x40
 131 #define LSI_CTEST2_DDIR   0x80
 132
 133 #define LSI_CTEST5_BL2    0x04
 134 #define LSI_CTEST5_DDIR   0x08
 135 #define LSI_CTEST5_MASR   0x10
 136 #define LSI_CTEST5_DFSN   0x20
 137 #define LSI_CTEST5_BBCK   0x40
 138 #define LSI_CTEST5_ADCK   0x80
 139
 140 #define LSI_CCNTL0_DILS   0x01
 141 #define LSI_CCNTL0_DISFC  0x10
 142 #define LSI_CCNTL0_ENNDJ  0x20
 143 #define LSI_CCNTL0_PMJCTL 0x40
 144 #define LSI_CCNTL0_ENPMJ  0x80
 145
 146 #define LSI_CCNTL1_EN64DBMV  0x01
 147 #define LSI_CCNTL1_EN64TIBMV 0x02
 148 #define LSI_CCNTL1_64TIMOD   0x04
 149 #define LSI_CCNTL1_DDAC      0x08
 150 #define LSI_CCNTL1_ZMOD      0x80
 151
 152 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
 153
 154 #define PHASE_DO          0
 155 #define PHASE_DI          1
 156 #define PHASE_CMD         2
 157 #define PHASE_ST          3
 158 #define PHASE_MO          6
 159 #define PHASE_MI          7
 160 #define PHASE_MASK        7
 161
 162 /* Maximum length of MSG IN data.  */
 163 #define LSI_MAX_MSGIN_LEN 8
 164
 165 /* Flag set if this is a tagged command.  */
 166 #define LSI_TAG_VALID     (1 << 16)
 167
 168 typedef struct {
 169     uint32_t tag;
 170     uint32_t pending;
 171     int out;
 172 } lsi_queue;
 173
 174 typedef struct {
 175     PCIDevice pci_dev;
 176     int mmio_io_addr;
 177     int ram_io_addr;
 178     uint32_t script_ram_base;
 179
 180     int carry; /* ??? Should this be an a visible register somewhere?  */
 181     int sense;
 182     /* Action to take at the end of a MSG IN phase.
 183        0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN.  */
 184     int msg_action;
 185     int msg_len;
 186     uint8_t msg[LSI_MAX_MSGIN_LEN];
 187     /* 0 if SCRIPTS are running or stopped.
 188      * 1 if a Wait Reselect instruction has been issued.
 189      * 2 if processing DMA from lsi_execute_script.
 190      * 3 if a DMA operation is in progress.  */
 191     int waiting;
 192     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 193     SCSIDevice *current_dev;
 194     int current_lun;
 195     /* The tag is a combination of the device ID and the SCSI tag.  */
 196     uint32_t current_tag;
 197     uint32_t current_dma_len;
 198     int command_complete;
 199     uint8_t *dma_buf;
 200     lsi_queue *queue;
 201     int queue_len;
 202     int active_commands;
 203
 204     uint32_t dsa;
 205     uint32_t temp;
 206     uint32_t dnad;
 207     uint32_t dbc;
 208     uint8_t istat0;
 209     uint8_t istat1;
 210     uint8_t dcmd;
 211     uint8_t dstat;
 212     uint8_t dien;
 213     uint8_t sist0;
 214     uint8_t sist1;
 215     uint8_t sien0;
 216     uint8_t sien1;
 217     uint8_t mbox0;
 218     uint8_t mbox1;
 219     uint8_t dfifo;
 220     uint8_t ctest2;
 221     uint8_t ctest3;
 222     uint8_t ctest4;
 223     uint8_t ctest5;
 224     uint8_t ccntl0;
 225     uint8_t ccntl1;
 226     uint32_t dsp;
 227     uint32_t dsps;
 228     uint8_t dmode;
 229     uint8_t dcntl;
 230     uint8_t scntl0;
 231     uint8_t scntl1;
 232     uint8_t scntl2;
 233     uint8_t scntl3;
 234     uint8_t sstat0;
 235     uint8_t sstat1;
 236     uint8_t scid;
 237     uint8_t sxfer;
 238     uint8_t socl;
 239     uint8_t sdid;
 240     uint8_t ssid;
 241     uint8_t sfbr;
 242     uint8_t stest1;
 243     uint8_t stest2;
 244     uint8_t stest3;
 245     uint8_t sidl;
 246     uint8_t stime0;
 247     uint8_t respid0;
 248     uint8_t respid1;
 249     uint32_t mmrs;
 250     uint32_t mmws;
 251     uint32_t sfs;
 252     uint32_t drs;
 253     uint32_t sbms;
 254     uint32_t dmbs;
 255     uint32_t dnad64;
 256     uint32_t pmjad1;
 257     uint32_t pmjad2;
 258     uint32_t rbc;
 259     uint32_t ua;
 260     uint32_t ia;
 261     uint32_t sbc;
 262     uint32_t csbc;
 263     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
 264
 265     /* Script ram is stored as 32-bit words in host byteorder.  */
 266     uint32_t script_ram[2048];
 267 } LSIState;
 268
 269 static void lsi_soft_reset(LSIState *s)
 270 {
 271     DPRINTF("Reset\n");
 272     s->carry = 0;
 273
 274     s->waiting = 0;
 275     s->dsa = 0;
 276     s->dnad = 0;
 277     s->dbc = 0;
 278     s->temp = 0;
 279     memset(s->scratch, 0, sizeof(s->scratch));
 280     s->istat0 = 0;
 281     s->istat1 = 0;
 282     s->dcmd = 0;
 283     s->dstat = 0;
 284     s->dien = 0;
 285     s->sist0 = 0;
 286     s->sist1 = 0;
 287     s->sien0 = 0;
 288     s->sien1 = 0;
 289     s->mbox0 = 0;
 290     s->mbox1 = 0;
 291     s->dfifo = 0;
 292     s->ctest2 = 0;
 293     s->ctest3 = 0;
 294     s->ctest4 = 0;
 295     s->ctest5 = 0;
 296     s->ccntl0 = 0;
 297     s->ccntl1 = 0;
 298     s->dsp = 0;
 299     s->dsps = 0;
 300     s->dmode = 0;
 301     s->dcntl = 0;
 302     s->scntl0 = 0xc0;
 303     s->scntl1 = 0;
 304     s->scntl2 = 0;
 305     s->scntl3 = 0;
 306     s->sstat0 = 0;
 307     s->sstat1 = 0;
 308     s->scid = 7;
 309     s->sxfer = 0;
 310     s->socl = 0;
 311     s->stest1 = 0;
 312     s->stest2 = 0;
 313     s->stest3 = 0;
 314     s->sidl = 0;
 315     s->stime0 = 0;
 316     s->respid0 = 0x80;
 317     s->respid1 = 0;
 318     s->mmrs = 0;
 319     s->mmws = 0;
 320     s->sfs = 0;
 321     s->drs = 0;
 322     s->sbms = 0;
 323     s->dmbs = 0;
 324     s->dnad64 = 0;
 325     s->pmjad1 = 0;
 326     s->pmjad2 = 0;
 327     s->rbc = 0;
 328     s->ua = 0;
 329     s->ia = 0;
 330     s->sbc = 0;
 331     s->csbc = 0;
 332 }
 333
 334 static int lsi_dma_40bit(LSIState *s)
 335 {
 336     if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
 337         return 1;
 338     return 0;
 339 }
 340
 341 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 342 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 343 static void lsi_execute_script(LSIState *s);
 344
 345 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 346 {
 347     uint32_t buf;
 348
 349     /* Optimize reading from SCRIPTS RAM.  */
 350     if ((addr & 0xffffe000) == s->script_ram_base) {
 351         return s->script_ram[(addr & 0x1fff) >> 2];
 352     }
 353     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 354     return cpu_to_le32(buf);
 355 }
 356
 357 static void lsi_stop_script(LSIState *s)
 358 {
 359     s->istat1 &= ~LSI_ISTAT1_SRUN;
 360 }
 361
 362 static void lsi_update_irq(LSIState *s)
 363 {
 364     int level;
 365     static int last_level;
 366
 367     /* It's unclear whether the DIP/SIP bits should be cleared when the
 368        Interrupt Status Registers are cleared or when istat0 is read.
 369        We currently do the formwer, which seems to work.  */
 370     level = 0;
 371     if (s->dstat) {
 372         if (s->dstat & s->dien)
 373             level = 1;
 374         s->istat0 |= LSI_ISTAT0_DIP;
 375     } else {
 376         s->istat0 &= ~LSI_ISTAT0_DIP;
 377     }
 378
 379     if (s->sist0 || s->sist1) {
 380         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 381             level = 1;
 382         s->istat0 |= LSI_ISTAT0_SIP;
 383     } else {
 384         s->istat0 &= ~LSI_ISTAT0_SIP;
 385     }
 386     if (s->istat0 & LSI_ISTAT0_INTF)
 387         level = 1;
 388
 389     if (level != last_level) {
 390         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 391                 level, s->dstat, s->sist1, s->sist0);
 392         last_level = level;
 393     }
 394     qemu_set_irq(s->pci_dev.irq[0], level);
 395 }
 396
 397 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 398 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 399 {
 400     uint32_t mask0;
 401     uint32_t mask1;
 402
 403     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 404             stat1, stat0, s->sist1, s->sist0);
 405     s->sist0 |= stat0;
 406     s->sist1 |= stat1;
 407     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 408        we don't stop processing when raising STO.  Instead continue
 409        execution and stop at the next insn that accesses the SCSI bus.  */
 410     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 411     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 412     mask1 &= ~LSI_SIST1_STO;
 413     if (s->sist0 & mask0 || s->sist1 & mask1) {
 414         lsi_stop_script(s);
 415     }
 416     lsi_update_irq(s);
 417 }
 418
 419 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 420 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 421 {
 422     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 423     s->dstat |= stat;
 424     lsi_update_irq(s);
 425     lsi_stop_script(s);
 426 }
 427
 428 static inline void lsi_set_phase(LSIState *s, int phase)
 429 {
 430     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 431 }
 432
 433 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 434 {
 435     /* Trigger a phase mismatch.  */
 436     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 437         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 438             s->dsp = s->pmjad1;
 439         } else {
 440             s->dsp = s->pmjad2;
 441         }
 442         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 443     } else {
 444         DPRINTF("Phase mismatch interrupt\n");
 445         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 446         lsi_stop_script(s);
 447     }
 448     lsi_set_phase(s, new_phase);
 449 }
 450
 451
 452 /* Resume SCRIPTS execution after a DMA operation.  */
 453 static void lsi_resume_script(LSIState *s)
 454 {
 455     if (s->waiting != 2) {
 456         s->waiting = 0;
 457         lsi_execute_script(s);
 458     } else {
 459         s->waiting = 0;
 460     }
 461 }
 462
 463 /* Initiate a SCSI layer data transfer.  */
 464 static void lsi_do_dma(LSIState *s, int out)
 465 {
 466     uint32_t count;
 467     target_phys_addr_t addr;
 468
 469     if (!s->current_dma_len) {
 470         /* Wait until data is available.  */
 471         DPRINTF("DMA no data available\n");
 472         return;
 473     }
 474
 475     count = s->dbc;
 476     if (count > s->current_dma_len)
 477         count = s->current_dma_len;
 478
 479     addr = s->dnad;
 480     if (lsi_dma_40bit(s))
 481         addr |= ((uint64_t)s->dnad64 << 32);
 482     else if (s->sbms)
 483         addr |= ((uint64_t)s->sbms << 32);
 484
 485     DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count);
 486     s->csbc += count;
 487     s->dnad += count;
 488     s->dbc -= count;
 489
 490     if (s->dma_buf == NULL) {
 491         s->dma_buf = s->current_dev->get_buf(s->current_dev,
 492                                              s->current_tag);
 493     }
 494
 495     /* ??? Set SFBR to first data byte.  */
 496     if (out) {
 497         cpu_physical_memory_read(addr, s->dma_buf, count);
 498     } else {
 499         cpu_physical_memory_write(addr, s->dma_buf, count);
 500     }
 501     s->current_dma_len -= count;
 502     if (s->current_dma_len == 0) {
 503         s->dma_buf = NULL;
 504         if (out) {
 505             /* Write the data.  */
 506             s->current_dev->write_data(s->current_dev, s->current_tag);
 507         } else {
 508             /* Request any remaining data.  */
 509             s->current_dev->read_data(s->current_dev, s->current_tag);
 510         }
 511     } else {
 512         s->dma_buf += count;
 513         lsi_resume_script(s);
 514     }
 515 }
 516
 517
 518 /* Add a command to the queue.  */
 519 static void lsi_queue_command(LSIState *s)
 520 {
 521     lsi_queue *p;
 522
 523     DPRINTF("Queueing tag=0x%x\n", s->current_tag);
 524     if (s->queue_len == s->active_commands) {
 525         s->queue_len++;
 526         s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
 527     }
 528     p = &s->queue[s->active_commands++];
 529     p->tag = s->current_tag;
 530     p->pending = 0;
 531     p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 532 }
 533
 534 /* Queue a byte for a MSG IN phase.  */
 535 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
 536 {
 537     if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
 538         BADF("MSG IN data too long\n");
 539     } else {
 540         DPRINTF("MSG IN 0x%02x\n", data);
 541         s->msg[s->msg_len++] = data;
 542     }
 543 }
 544
 545 /* Perform reselection to continue a command.  */
 546 static void lsi_reselect(LSIState *s, uint32_t tag)
 547 {
 548     lsi_queue *p;
 549     int n;
 550     int id;
 551
 552     p = NULL;
 553     for (n = 0; n < s->active_commands; n++) {
 554         p = &s->queue[n];
 555         if (p->tag == tag)
 556             break;
 557     }
 558     if (n == s->active_commands) {
 559         BADF("Reselected non-existant command tag=0x%x\n", tag);
 560         return;
 561     }
 562     id = (tag >> 8) & 0xf;
 563     s->ssid = id | 0x80;
 564     DPRINTF("Reselected target %d\n", id);
 565     s->current_dev = s->scsi_dev[id];
 566     s->current_tag = tag;
 567     s->scntl1 |= LSI_SCNTL1_CON;
 568     lsi_set_phase(s, PHASE_MI);
 569     s->msg_action = p->out ? 2 : 3;
 570     s->current_dma_len = p->pending;
 571     s->dma_buf = NULL;
 572     lsi_add_msg_byte(s, 0x80);
 573     if (s->current_tag & LSI_TAG_VALID) {
 574         lsi_add_msg_byte(s, 0x20);
 575         lsi_add_msg_byte(s, tag & 0xff);
 576     }
 577
 578     s->active_commands--;
 579     if (n != s->active_commands) {
 580         s->queue[n] = s->queue[s->active_commands];
 581     }
 582 }
 583
 584 /* Record that data is available for a queued command.  Returns zero if
 585    the device was reselected, nonzero if the IO is deferred.  */
 586 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
 587 {
 588     lsi_queue *p;
 589     int i;
 590     for (i = 0; i < s->active_commands; i++) {
 591         p = &s->queue[i];
 592         if (p->tag == tag) {
 593             if (p->pending) {
 594                 BADF("Multiple IO pending for tag %d\n", tag);
 595             }
 596             p->pending = arg;
 597             if (s->waiting == 1) {
 598                 /* Reselect device.  */
 599                 lsi_reselect(s, tag);
 600                 return 0;
 601             } else {
 602                DPRINTF("Queueing IO tag=0x%x\n", tag);
 603                 p->pending = arg;
 604                 return 1;
 605             }
 606         }
 607     }
 608     BADF("IO with unknown tag %d\n", tag);
 609     return 1;
 610 }
 611
 612 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 613 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
 614                                  uint32_t arg)
 615 {
 616     LSIState *s = (LSIState *)opaque;
 617     int out;
 618
 619     out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 620     if (reason == SCSI_REASON_DONE) {
 621         DPRINTF("Command complete sense=%d\n", (int)arg);
 622         s->sense = arg;
 623         s->command_complete = 2;
 624         if (s->waiting && s->dbc != 0) {
 625             /* Raise phase mismatch for short transfers.  */
 626             lsi_bad_phase(s, out, PHASE_ST);
 627         } else {
 628             lsi_set_phase(s, PHASE_ST);
 629         }
 630         lsi_resume_script(s);
 631         return;
 632     }
 633
 634     if (s->waiting == 1 || tag != s->current_tag) {
 635         if (lsi_queue_tag(s, tag, arg))
 636             return;
 637     }
 638     DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
 639     s->current_dma_len = arg;
 640     s->command_complete = 1;
 641     if (!s->waiting)
 642         return;
 643     if (s->waiting == 1 || s->dbc == 0) {
 644         lsi_resume_script(s);
 645     } else {
 646         lsi_do_dma(s, out);
 647     }
 648 }
 649
 650 static void lsi_do_command(LSIState *s)
 651 {
 652     uint8_t buf[16];
 653     int n;
 654
 655     DPRINTF("Send command len=%d\n", s->dbc);
 656     if (s->dbc > 16)
 657         s->dbc = 16;
 658     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 659     s->sfbr = buf[0];
 660     s->command_complete = 0;
 661     n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
 662                                      s->current_lun);
 663     if (n > 0) {
 664         lsi_set_phase(s, PHASE_DI);
 665         s->current_dev->read_data(s->current_dev, s->current_tag);
 666     } else if (n < 0) {
 667         lsi_set_phase(s, PHASE_DO);
 668         s->current_dev->write_data(s->current_dev, s->current_tag);
 669     }
 670
 671     if (!s->command_complete) {
 672         if (n) {
 673             /* Command did not complete immediately so disconnect.  */
 674             lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
 675             lsi_add_msg_byte(s, 4); /* DISCONNECT */
 676             /* wait data */
 677             lsi_set_phase(s, PHASE_MI);
 678             s->msg_action = 1;
 679             lsi_queue_command(s);
 680         } else {
 681             /* wait command complete */
 682             lsi_set_phase(s, PHASE_DI);
 683         }
 684     }
 685 }
 686
 687 static void lsi_do_status(LSIState *s)
 688 {
 689     uint8_t sense;
 690     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 691     if (s->dbc != 1)
 692         BADF("Bad Status move\n");
 693     s->dbc = 1;
 694     sense = s->sense;
 695     s->sfbr = sense;
 696     cpu_physical_memory_write(s->dnad, &sense, 1);
 697     lsi_set_phase(s, PHASE_MI);
 698     s->msg_action = 1;
 699     lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
 700 }
 701
 702 static void lsi_disconnect(LSIState *s)
 703 {
 704     s->scntl1 &= ~LSI_SCNTL1_CON;
 705     s->sstat1 &= ~PHASE_MASK;
 706 }
 707
 708 static void lsi_do_msgin(LSIState *s)
 709 {
 710     int len;
 711     DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
 712     s->sfbr = s->msg[0];
 713     len = s->msg_len;
 714     if (len > s->dbc)
 715         len = s->dbc;
 716     cpu_physical_memory_write(s->dnad, s->msg, len);
 717     /* Linux drivers rely on the last byte being in the SIDL.  */
 718     s->sidl = s->msg[len - 1];
 719     s->msg_len -= len;
 720     if (s->msg_len) {
 721         memmove(s->msg, s->msg + len, s->msg_len);
 722     } else {
 723         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 724            switch to PHASE_MO.  */
 725         switch (s->msg_action) {
 726         case 0:
 727             lsi_set_phase(s, PHASE_CMD);
 728             break;
 729         case 1:
 730             lsi_disconnect(s);
 731             break;
 732         case 2:
 733             lsi_set_phase(s, PHASE_DO);
 734             break;
 735         case 3:
 736             lsi_set_phase(s, PHASE_DI);
 737             break;
 738         default:
 739             abort();
 740         }
 741     }
 742 }
 743
 744 /* Read the next byte during a MSGOUT phase.  */
 745 static uint8_t lsi_get_msgbyte(LSIState *s)
 746 {
 747     uint8_t data;
 748     cpu_physical_memory_read(s->dnad, &data, 1);
 749     s->dnad++;
 750     s->dbc--;
 751     return data;
 752 }
 753
 754 static void lsi_do_msgout(LSIState *s)
 755 {
 756     uint8_t msg;
 757     int len;
 758
 759     DPRINTF("MSG out len=%d\n", s->dbc);
 760     while (s->dbc) {
 761         msg = lsi_get_msgbyte(s);
 762         s->sfbr = msg;
 763
 764         switch (msg) {
 765         case 0x00:
 766             DPRINTF("MSG: Disconnect\n");
 767             lsi_disconnect(s);
 768             break;
 769         case 0x08:
 770             DPRINTF("MSG: No Operation\n");
 771             lsi_set_phase(s, PHASE_CMD);
 772             break;
 773         case 0x01:
 774             len = lsi_get_msgbyte(s);
 775             msg = lsi_get_msgbyte(s);
 776             DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
 777             switch (msg) {
 778             case 1:
 779                 DPRINTF("SDTR (ignored)\n");
 780                 s->dbc -= 2;
 781                 break;
 782             case 3:
 783                 DPRINTF("WDTR (ignored)\n");
 784                 s->dbc -= 1;
 785                 break;
 786             default:
 787                 goto bad;
 788             }
 789             break;
 790         case 0x20: /* SIMPLE queue */
 791             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 792             DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
 793             break;
 794         case 0x21: /* HEAD of queue */
 795             BADF("HEAD queue not implemented\n");
 796             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 797             break;
 798         case 0x22: /* ORDERED queue */
 799             BADF("ORDERED queue not implemented\n");
 800             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 801             break;
 802         default:
 803             if ((msg & 0x80) == 0) {
 804                 goto bad;
 805             }
 806             s->current_lun = msg & 7;
 807             DPRINTF("Select LUN %d\n", s->current_lun);
 808             lsi_set_phase(s, PHASE_CMD);
 809             break;
 810         }
 811     }
 812     return;
 813 bad:
 814     BADF("Unimplemented message 0x%02x\n", msg);
 815     lsi_set_phase(s, PHASE_MI);
 816     lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
 817     s->msg_action = 0;
 818 }
 819
 820 /* Sign extend a 24-bit value.  */
 821 static inline int32_t sxt24(int32_t n)
 822 {
 823     return (n << 8) >> 8;
 824 }
 825
 826 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 827 {
 828     int n;
 829     uint8_t buf[TARGET_PAGE_SIZE];
 830
 831     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 832     while (count) {
 833         n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
 834         cpu_physical_memory_read(src, buf, n);
 835         cpu_physical_memory_write(dest, buf, n);
 836         src += n;
 837         dest += n;
 838         count -= n;
 839     }
 840 }
 841
 842 static void lsi_wait_reselect(LSIState *s)
 843 {
 844     int i;
 845     DPRINTF("Wait Reselect\n");
 846     if (s->current_dma_len)
 847         BADF("Reselect with pending DMA\n");
 848     for (i = 0; i < s->active_commands; i++) {
 849         if (s->queue[i].pending) {
 850             lsi_reselect(s, s->queue[i].tag);
 851             break;
 852         }
 853     }
 854     if (s->current_dma_len == 0) {
 855         s->waiting = 1;
 856     }
 857 }
 858
 859 static void lsi_execute_script(LSIState *s)
 860 {
 861     uint32_t insn;
 862     uint32_t addr, addr_high;
 863     int opcode;
 864     int insn_processed = 0;
 865
 866     s->istat1 |= LSI_ISTAT1_SRUN;
 867 again:
 868     insn_processed++;
 869     insn = read_dword(s, s->dsp);
 870     addr = read_dword(s, s->dsp + 4);
 871     addr_high = 0;
 872     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 873     s->dsps = addr;
 874     s->dcmd = insn >> 24;
 875     s->dsp += 8;
 876     switch (insn >> 30) {
 877     case 0: /* Block move.  */
 878         if (s->sist1 & LSI_SIST1_STO) {
 879             DPRINTF("Delayed select timeout\n");
 880             lsi_stop_script(s);
 881             break;
 882         }
 883         s->dbc = insn & 0xffffff;
 884         s->rbc = s->dbc;
 885         if (insn & (1 << 29)) {
 886             /* Indirect addressing.  */
 887             addr = read_dword(s, addr);
 888         } else if (insn & (1 << 28)) {
 889             uint32_t buf[2];
 890             int32_t offset;
 891             /* Table indirect addressing.  */
 892             offset = sxt24(addr);
 893             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 894             /* byte count is stored in bits 0:23 only */
 895             s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
 896             s->rbc = s->dbc;
 897             addr = cpu_to_le32(buf[1]);
 898
 899             /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
 900              * table, bits [31:24] */
 901             if (lsi_dma_40bit(s))
 902                 addr_high = cpu_to_le32(buf[0]) >> 24;
 903         }
 904         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 905             DPRINTF("Wrong phase got %d expected %d\n",
 906                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 907             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 908             break;
 909         }
 910         s->dnad = addr;
 911         s->dnad64 = addr_high;
 912         /* ??? Set ESA.  */
 913         s->ia = s->dsp - 8;
 914         switch (s->sstat1 & 0x7) {
 915         case PHASE_DO:
 916             s->waiting = 2;
 917             lsi_do_dma(s, 1);
 918             if (s->waiting)
 919                 s->waiting = 3;
 920             break;
 921         case PHASE_DI:
 922             s->waiting = 2;
 923             s->current_dma_len = s->dbc;
 924             lsi_do_dma(s, 0);
 925             if (s->waiting)
 926                 s->waiting = 3;
 927             break;
 928         case PHASE_CMD:
 929             lsi_do_command(s);
 930             break;
 931         case PHASE_ST:
 932             lsi_do_status(s);
 933             break;
 934         case PHASE_MO:
 935             lsi_do_msgout(s);
 936             break;
 937         case PHASE_MI:
 938             lsi_do_msgin(s);
 939             break;
 940         default:
 941             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
 942             exit(1);
 943         }
 944         s->dfifo = s->dbc & 0xff;
 945         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
 946         s->sbc = s->dbc;
 947         s->rbc -= s->dbc;
 948         s->ua = addr + s->dbc;
 949         break;
 950
 951     case 1: /* IO or Read/Write instruction.  */
 952         opcode = (insn >> 27) & 7;
 953         if (opcode < 5) {
 954             uint32_t id;
 955
 956             if (insn & (1 << 25)) {
 957                 id = read_dword(s, s->dsa + sxt24(insn));
 958             } else {
 959                 id = addr;
 960             }
 961             id = (id >> 16) & 0xf;
 962             if (insn & (1 << 26)) {
 963                 addr = s->dsp + sxt24(addr);
 964             }
 965             s->dnad = addr;
 966             switch (opcode) {
 967             case 0: /* Select */
 968                 s->sdid = id;
 969                 if (s->current_dma_len && (s->ssid & 0xf) == id) {
 970                     DPRINTF("Already reselected by target %d\n", id);
 971                     break;
 972                 }
 973                 s->sstat0 |= LSI_SSTAT0_WOA;
 974                 s->scntl1 &= ~LSI_SCNTL1_IARB;
 975                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
 976                     DPRINTF("Selected absent target %d\n", id);
 977                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
 978                     lsi_disconnect(s);
 979                     break;
 980                 }
 981                 DPRINTF("Selected target %d%s\n",
 982                         id, insn & (1 << 3) ? " ATN" : "");
 983                 /* ??? Linux drivers compain when this is set.  Maybe
 984                    it only applies in low-level mode (unimplemented).
 985                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
 986                 s->current_dev = s->scsi_dev[id];
 987                 s->current_tag = id << 8;
 988                 s->scntl1 |= LSI_SCNTL1_CON;
 989                 if (insn & (1 << 3)) {
 990                     s->socl |= LSI_SOCL_ATN;
 991                 }
 992                 lsi_set_phase(s, PHASE_MO);
 993                 break;
 994             case 1: /* Disconnect */
 995                 DPRINTF("Wait Disconect\n");
 996                 s->scntl1 &= ~LSI_SCNTL1_CON;
 997                 break;
 998             case 2: /* Wait Reselect */
 999                 lsi_wait_reselect(s);
1000                 break;
1001             case 3: /* Set */
1002                 DPRINTF("Set%s%s%s%s\n",
1003                         insn & (1 << 3) ? " ATN" : "",
1004                         insn & (1 << 6) ? " ACK" : "",
1005                         insn & (1 << 9) ? " TM" : "",
1006                         insn & (1 << 10) ? " CC" : "");
1007                 if (insn & (1 << 3)) {
1008                     s->socl |= LSI_SOCL_ATN;
1009                     lsi_set_phase(s, PHASE_MO);
1010                 }
1011                 if (insn & (1 << 9)) {
1012                     BADF("Target mode not implemented\n");
1013                     exit(1);
1014                 }
1015                 if (insn & (1 << 10))
1016                     s->carry = 1;
1017                 break;
1018             case 4: /* Clear */
1019                 DPRINTF("Clear%s%s%s%s\n",
1020                         insn & (1 << 3) ? " ATN" : "",
1021                         insn & (1 << 6) ? " ACK" : "",
1022                         insn & (1 << 9) ? " TM" : "",
1023                         insn & (1 << 10) ? " CC" : "");
1024                 if (insn & (1 << 3)) {
1025                     s->socl &= ~LSI_SOCL_ATN;
1026                 }
1027                 if (insn & (1 << 10))
1028                     s->carry = 0;
1029                 break;
1030             }
1031         } else {
1032             uint8_t op0;
1033             uint8_t op1;
1034             uint8_t data8;
1035             int reg;
1036             int operator;
1037 #ifdef DEBUG_LSI
1038             static const char *opcode_names[3] =
1039                 {"Write", "Read", "Read-Modify-Write"};
1040             static const char *operator_names[8] =
1041                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1042 #endif
1043
1044             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1045             data8 = (insn >> 8) & 0xff;
1046             opcode = (insn >> 27) & 7;
1047             operator = (insn >> 24) & 7;
1048             DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1049                     opcode_names[opcode - 5], reg,
1050                     operator_names[operator], data8, s->sfbr,
1051                     (insn & (1 << 23)) ? " SFBR" : "");
1052             op0 = op1 = 0;
1053             switch (opcode) {
1054             case 5: /* From SFBR */
1055                 op0 = s->sfbr;
1056                 op1 = data8;
1057                 break;
1058             case 6: /* To SFBR */
1059                 if (operator)
1060                     op0 = lsi_reg_readb(s, reg);
1061                 op1 = data8;
1062                 break;
1063             case 7: /* Read-modify-write */
1064                 if (operator)
1065                     op0 = lsi_reg_readb(s, reg);
1066                 if (insn & (1 << 23)) {
1067                     op1 = s->sfbr;
1068                 } else {
1069                     op1 = data8;
1070                 }
1071                 break;
1072             }
1073
1074             switch (operator) {
1075             case 0: /* move */
1076                 op0 = op1;
1077                 break;
1078             case 1: /* Shift left */
1079                 op1 = op0 >> 7;
1080                 op0 = (op0 << 1) | s->carry;
1081                 s->carry = op1;
1082                 break;
1083             case 2: /* OR */
1084                 op0 |= op1;
1085                 break;
1086             case 3: /* XOR */
1087                 op0 ^= op1;
1088                 break;
1089             case 4: /* AND */
1090                 op0 &= op1;
1091                 break;
1092             case 5: /* SHR */
1093                 op1 = op0 & 1;
1094                 op0 = (op0 >> 1) | (s->carry << 7);
1095                 s->carry = op1;
1096                 break;
1097             case 6: /* ADD */
1098                 op0 += op1;
1099                 s->carry = op0 < op1;
1100                 break;
1101             case 7: /* ADC */
1102                 op0 += op1 + s->carry;
1103                 if (s->carry)
1104                     s->carry = op0 <= op1;
1105                 else
1106                     s->carry = op0 < op1;
1107                 break;
1108             }
1109
1110             switch (opcode) {
1111             case 5: /* From SFBR */
1112             case 7: /* Read-modify-write */
1113                 lsi_reg_writeb(s, reg, op0);
1114                 break;
1115             case 6: /* To SFBR */
1116                 s->sfbr = op0;
1117                 break;
1118             }
1119         }
1120         break;
1121
1122     case 2: /* Transfer Control.  */
1123         {
1124             int cond;
1125             int jmp;
1126
1127             if ((insn & 0x002e0000) == 0) {
1128                 DPRINTF("NOP\n");
1129                 break;
1130             }
1131             if (s->sist1 & LSI_SIST1_STO) {
1132                 DPRINTF("Delayed select timeout\n");
1133                 lsi_stop_script(s);
1134                 break;
1135             }
1136             cond = jmp = (insn & (1 << 19)) != 0;
1137             if (cond == jmp && (insn & (1 << 21))) {
1138                 DPRINTF("Compare carry %d\n", s->carry == jmp);
1139                 cond = s->carry != 0;
1140             }
1141             if (cond == jmp && (insn & (1 << 17))) {
1142                 DPRINTF("Compare phase %d %c= %d\n",
1143                         (s->sstat1 & PHASE_MASK),
1144                         jmp ? '=' : '!',
1145                         ((insn >> 24) & 7));
1146                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1147             }
1148             if (cond == jmp && (insn & (1 << 18))) {
1149                 uint8_t mask;
1150
1151                 mask = (~insn >> 8) & 0xff;
1152                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1153                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1154                 cond = (s->sfbr & mask) == (insn & mask);
1155             }
1156             if (cond == jmp) {
1157                 if (insn & (1 << 23)) {
1158                     /* Relative address.  */
1159                     addr = s->dsp + sxt24(addr);
1160                 }
1161                 switch ((insn >> 27) & 7) {
1162                 case 0: /* Jump */
1163                     DPRINTF("Jump to 0x%08x\n", addr);
1164                     s->dsp = addr;
1165                     break;
1166                 case 1: /* Call */
1167                     DPRINTF("Call 0x%08x\n", addr);
1168                     s->temp = s->dsp;
1169                     s->dsp = addr;
1170                     break;
1171                 case 2: /* Return */
1172                     DPRINTF("Return to 0x%08x\n", s->temp);
1173                     s->dsp = s->temp;
1174                     break;
1175                 case 3: /* Interrupt */
1176                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
1177                     if ((insn & (1 << 20)) != 0) {
1178                         s->istat0 |= LSI_ISTAT0_INTF;
1179                         lsi_update_irq(s);
1180                     } else {
1181                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1182                     }
1183                     break;
1184                 default:
1185                     DPRINTF("Illegal transfer control\n");
1186                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1187                     break;
1188                 }
1189             } else {
1190                 DPRINTF("Control condition failed\n");
1191             }
1192         }
1193         break;
1194
1195     case 3:
1196         if ((insn & (1 << 29)) == 0) {
1197             /* Memory move.  */
1198             uint32_t dest;
1199             /* ??? The docs imply the destination address is loaded into
1200                the TEMP register.  However the Linux drivers rely on
1201                the value being presrved.  */
1202             dest = read_dword(s, s->dsp);
1203             s->dsp += 4;
1204             lsi_memcpy(s, dest, addr, insn & 0xffffff);
1205         } else {
1206             uint8_t data[7];
1207             int reg;
1208             int n;
1209             int i;
1210
1211             if (insn & (1 << 28)) {
1212                 addr = s->dsa + sxt24(addr);
1213             }
1214             n = (insn & 7);
1215             reg = (insn >> 16) & 0xff;
1216             if (insn & (1 << 24)) {
1217                 cpu_physical_memory_read(addr, data, n);
1218                 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1219                         addr, *(int *)data);
1220                 for (i = 0; i < n; i++) {
1221                     lsi_reg_writeb(s, reg + i, data[i]);
1222                 }
1223             } else {
1224                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1225                 for (i = 0; i < n; i++) {
1226                     data[i] = lsi_reg_readb(s, reg + i);
1227                 }
1228                 cpu_physical_memory_write(addr, data, n);
1229             }
1230         }
1231     }
1232     if (insn_processed > 10000 && !s->waiting) {
1233         /* Some windows drivers make the device spin waiting for a memory
1234            location to change.  If we have been executed a lot of code then
1235            assume this is the case and force an unexpected device disconnect.
1236            This is apparently sufficient to beat the drivers into submission.
1237          */
1238         if (!(s->sien0 & LSI_SIST0_UDC))
1239             fprintf(stderr, "inf. loop with UDC masked\n");
1240         lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1241         lsi_disconnect(s);
1242     } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1243         if (s->dcntl & LSI_DCNTL_SSM) {
1244             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1245         } else {
1246             goto again;
1247         }
1248     }
1249     DPRINTF("SCRIPTS execution stopped\n");
1250 }
1251
1252 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1253 {
1254     uint8_t tmp;
1255 #define CASE_GET_REG32(name, addr) \
1256     case addr: return s->name & 0xff; \
1257     case addr + 1: return (s->name >> 8) & 0xff; \
1258     case addr + 2: return (s->name >> 16) & 0xff; \
1259     case addr + 3: return (s->name >> 24) & 0xff;
1260
1261 #ifdef DEBUG_LSI_REG
1262     DPRINTF("Read reg %x\n", offset);
1263 #endif
1264     switch (offset) {
1265     case 0x00: /* SCNTL0 */
1266         return s->scntl0;
1267     case 0x01: /* SCNTL1 */
1268         return s->scntl1;
1269     case 0x02: /* SCNTL2 */
1270         return s->scntl2;
1271     case 0x03: /* SCNTL3 */
1272         return s->scntl3;
1273     case 0x04: /* SCID */
1274         return s->scid;
1275     case 0x05: /* SXFER */
1276         return s->sxfer;
1277     case 0x06: /* SDID */
1278         return s->sdid;
1279     case 0x07: /* GPREG0 */
1280         return 0x7f;
1281     case 0x08: /* Revision ID */
1282         return 0x00;
1283     case 0xa: /* SSID */
1284         return s->ssid;
1285     case 0xb: /* SBCL */
1286         /* ??? This is not correct. However it's (hopefully) only
1287            used for diagnostics, so should be ok.  */
1288         return 0;
1289     case 0xc: /* DSTAT */
1290         tmp = s->dstat | 0x80;
1291         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1292             s->dstat = 0;
1293         lsi_update_irq(s);
1294         return tmp;
1295     case 0x0d: /* SSTAT0 */
1296         return s->sstat0;
1297     case 0x0e: /* SSTAT1 */
1298         return s->sstat1;
1299     case 0x0f: /* SSTAT2 */
1300         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1301     CASE_GET_REG32(dsa, 0x10)
1302     case 0x14: /* ISTAT0 */
1303         return s->istat0;
1304     case 0x16: /* MBOX0 */
1305         return s->mbox0;
1306     case 0x17: /* MBOX1 */
1307         return s->mbox1;
1308     case 0x18: /* CTEST0 */
1309         return 0xff;
1310     case 0x19: /* CTEST1 */
1311         return 0;
1312     case 0x1a: /* CTEST2 */
1313         tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
1314         if (s->istat0 & LSI_ISTAT0_SIGP) {
1315             s->istat0 &= ~LSI_ISTAT0_SIGP;
1316             tmp |= LSI_CTEST2_SIGP;
1317         }
1318         return tmp;
1319     case 0x1b: /* CTEST3 */
1320         return s->ctest3;
1321     CASE_GET_REG32(temp, 0x1c)
1322     case 0x20: /* DFIFO */
1323         return 0;
1324     case 0x21: /* CTEST4 */
1325         return s->ctest4;
1326     case 0x22: /* CTEST5 */
1327         return s->ctest5;
1328     case 0x23: /* CTEST6 */
1329          return 0;
1330     case 0x24: /* DBC[0:7] */
1331         return s->dbc & 0xff;
1332     case 0x25: /* DBC[8:15] */
1333         return (s->dbc >> 8) & 0xff;
1334     case 0x26: /* DBC[16->23] */
1335         return (s->dbc >> 16) & 0xff;
1336     case 0x27: /* DCMD */
1337         return s->dcmd;
1338     CASE_GET_REG32(dsp, 0x2c)
1339     CASE_GET_REG32(dsps, 0x30)
1340     CASE_GET_REG32(scratch[0], 0x34)
1341     case 0x38: /* DMODE */
1342         return s->dmode;
1343     case 0x39: /* DIEN */
1344         return s->dien;
1345     case 0x3b: /* DCNTL */
1346         return s->dcntl;
1347     case 0x40: /* SIEN0 */
1348         return s->sien0;
1349     case 0x41: /* SIEN1 */
1350         return s->sien1;
1351     case 0x42: /* SIST0 */
1352         tmp = s->sist0;
1353         s->sist0 = 0;
1354         lsi_update_irq(s);
1355         return tmp;
1356     case 0x43: /* SIST1 */
1357         tmp = s->sist1;
1358         s->sist1 = 0;
1359         lsi_update_irq(s);
1360         return tmp;
1361     case 0x46: /* MACNTL */
1362         return 0x0f;
1363     case 0x47: /* GPCNTL0 */
1364         return 0x0f;
1365     case 0x48: /* STIME0 */
1366         return s->stime0;
1367     case 0x4a: /* RESPID0 */
1368         return s->respid0;
1369     case 0x4b: /* RESPID1 */
1370         return s->respid1;
1371     case 0x4d: /* STEST1 */
1372         return s->stest1;
1373     case 0x4e: /* STEST2 */
1374         return s->stest2;
1375     case 0x4f: /* STEST3 */
1376         return s->stest3;
1377     case 0x50: /* SIDL */
1378         /* This is needed by the linux drivers.  We currently only update it
1379            during the MSG IN phase.  */
1380         return s->sidl;
1381     case 0x52: /* STEST4 */
1382         return 0xe0;
1383     case 0x56: /* CCNTL0 */
1384         return s->ccntl0;
1385     case 0x57: /* CCNTL1 */
1386         return s->ccntl1;
1387     case 0x58: /* SBDL */
1388         /* Some drivers peek at the data bus during the MSG IN phase.  */
1389         if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1390             return s->msg[0];
1391         return 0;
1392     case 0x59: /* SBDL high */
1393         return 0;
1394     CASE_GET_REG32(mmrs, 0xa0)
1395     CASE_GET_REG32(mmws, 0xa4)
1396     CASE_GET_REG32(sfs, 0xa8)
1397     CASE_GET_REG32(drs, 0xac)
1398     CASE_GET_REG32(sbms, 0xb0)
1399     CASE_GET_REG32(dmbs, 0xb4)
1400     CASE_GET_REG32(dnad64, 0xb8)
1401     CASE_GET_REG32(pmjad1, 0xc0)
1402     CASE_GET_REG32(pmjad2, 0xc4)
1403     CASE_GET_REG32(rbc, 0xc8)
1404     CASE_GET_REG32(ua, 0xcc)
1405     CASE_GET_REG32(ia, 0xd4)
1406     CASE_GET_REG32(sbc, 0xd8)
1407     CASE_GET_REG32(csbc, 0xdc)
1408     }
1409     if (offset >= 0x5c && offset < 0xa0) {
1410         int n;
1411         int shift;
1412         n = (offset - 0x58) >> 2;
1413         shift = (offset & 3) * 8;
1414         return (s->scratch[n] >> shift) & 0xff;
1415     }
1416     BADF("readb 0x%x\n", offset);
1417     exit(1);
1418 #undef CASE_GET_REG32
1419 }
1420
1421 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1422 {
1423 #define CASE_SET_REG32(name, addr) \
1424     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1425     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1426     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1427     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1428
1429 #ifdef DEBUG_LSI_REG
1430     DPRINTF("Write reg %x = %02x\n", offset, val);
1431 #endif
1432     switch (offset) {
1433     case 0x00: /* SCNTL0 */
1434         s->scntl0 = val;
1435         if (val & LSI_SCNTL0_START) {
1436             BADF("Start sequence not implemented\n");
1437         }
1438         break;
1439     case 0x01: /* SCNTL1 */
1440         s->scntl1 = val & ~LSI_SCNTL1_SST;
1441         if (val & LSI_SCNTL1_IARB) {
1442             BADF("Immediate Arbritration not implemented\n");
1443         }
1444         if (val & LSI_SCNTL1_RST) {
1445             s->sstat0 |= LSI_SSTAT0_RST;
1446             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1447         } else {
1448             s->sstat0 &= ~LSI_SSTAT0_RST;
1449         }
1450         break;
1451     case 0x02: /* SCNTL2 */
1452         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1453         s->scntl2 = val;
1454         break;
1455     case 0x03: /* SCNTL3 */
1456         s->scntl3 = val;
1457         break;
1458     case 0x04: /* SCID */
1459         s->scid = val;
1460         break;
1461     case 0x05: /* SXFER */
1462         s->sxfer = val;
1463         break;
1464     case 0x06: /* SDID */
1465         if ((val & 0xf) != (s->ssid & 0xf))
1466             BADF("Destination ID does not match SSID\n");
1467         s->sdid = val & 0xf;
1468         break;
1469     case 0x07: /* GPREG0 */
1470         break;
1471     case 0x08: /* SFBR */
1472         /* The CPU is not allowed to write to this register.  However the
1473            SCRIPTS register move instructions are.  */
1474         s->sfbr = val;
1475         break;
1476     case 0x0a: case 0x0b:
1477         /* Openserver writes to these readonly registers on startup */
1478         return;
1479     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1480         /* Linux writes to these readonly registers on startup.  */
1481         return;
1482     CASE_SET_REG32(dsa, 0x10)
1483     case 0x14: /* ISTAT0 */
1484         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1485         if (val & LSI_ISTAT0_ABRT) {
1486             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1487         }
1488         if (val & LSI_ISTAT0_INTF) {
1489             s->istat0 &= ~LSI_ISTAT0_INTF;
1490             lsi_update_irq(s);
1491         }
1492         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1493             DPRINTF("Woken by SIGP\n");
1494             s->waiting = 0;
1495             s->dsp = s->dnad;
1496             lsi_execute_script(s);
1497         }
1498         if (val & LSI_ISTAT0_SRST) {
1499             lsi_soft_reset(s);
1500         }
1501         break;
1502     case 0x16: /* MBOX0 */
1503         s->mbox0 = val;
1504         break;
1505     case 0x17: /* MBOX1 */
1506         s->mbox1 = val;
1507         break;
1508     case 0x1a: /* CTEST2 */
1509         s->ctest2 = val & LSI_CTEST2_PCICIE;
1510         break;
1511     case 0x1b: /* CTEST3 */
1512         s->ctest3 = val & 0x0f;
1513         break;
1514     CASE_SET_REG32(temp, 0x1c)
1515     case 0x21: /* CTEST4 */
1516         if (val & 7) {
1517            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1518         }
1519         s->ctest4 = val;
1520         break;
1521     case 0x22: /* CTEST5 */
1522         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1523             BADF("CTEST5 DMA increment not implemented\n");
1524         }
1525         s->ctest5 = val;
1526         break;
1527     case 0x2c: /* DSP[0:7] */
1528         s->dsp &= 0xffffff00;
1529         s->dsp |= val;
1530         break;
1531     case 0x2d: /* DSP[8:15] */
1532         s->dsp &= 0xffff00ff;
1533         s->dsp |= val << 8;
1534         break;
1535     case 0x2e: /* DSP[16:23] */
1536         s->dsp &= 0xff00ffff;
1537         s->dsp |= val << 16;
1538         break;
1539     case 0x2f: /* DSP[24:31] */
1540         s->dsp &= 0x00ffffff;
1541         s->dsp |= val << 24;
1542         if ((s->dmode & LSI_DMODE_MAN) == 0
1543             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1544             lsi_execute_script(s);
1545         break;
1546     CASE_SET_REG32(dsps, 0x30)
1547     CASE_SET_REG32(scratch[0], 0x34)
1548     case 0x38: /* DMODE */
1549         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1550             BADF("IO mappings not implemented\n");
1551         }
1552         s->dmode = val;
1553         break;
1554     case 0x39: /* DIEN */
1555         s->dien = val;
1556         lsi_update_irq(s);
1557         break;
1558     case 0x3b: /* DCNTL */
1559         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1560         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1561             lsi_execute_script(s);
1562         break;
1563     case 0x40: /* SIEN0 */
1564         s->sien0 = val;
1565         lsi_update_irq(s);
1566         break;
1567     case 0x41: /* SIEN1 */
1568         s->sien1 = val;
1569         lsi_update_irq(s);
1570         break;
1571     case 0x47: /* GPCNTL0 */
1572         break;
1573     case 0x48: /* STIME0 */
1574         s->stime0 = val;
1575         break;
1576     case 0x49: /* STIME1 */
1577         if (val & 0xf) {
1578             DPRINTF("General purpose timer not implemented\n");
1579             /* ??? Raising the interrupt immediately seems to be sufficient
1580                to keep the FreeBSD driver happy.  */
1581             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1582         }
1583         break;
1584     case 0x4a: /* RESPID0 */
1585         s->respid0 = val;
1586         break;
1587     case 0x4b: /* RESPID1 */
1588         s->respid1 = val;
1589         break;
1590     case 0x4d: /* STEST1 */
1591         s->stest1 = val;
1592         break;
1593     case 0x4e: /* STEST2 */
1594         if (val & 1) {
1595             BADF("Low level mode not implemented\n");
1596         }
1597         s->stest2 = val;
1598         break;
1599     case 0x4f: /* STEST3 */
1600         if (val & 0x41) {
1601             BADF("SCSI FIFO test mode not implemented\n");
1602         }
1603         s->stest3 = val;
1604         break;
1605     case 0x56: /* CCNTL0 */
1606         s->ccntl0 = val;
1607         break;
1608     case 0x57: /* CCNTL1 */
1609         s->ccntl1 = val;
1610         break;
1611     CASE_SET_REG32(mmrs, 0xa0)
1612     CASE_SET_REG32(mmws, 0xa4)
1613     CASE_SET_REG32(sfs, 0xa8)
1614     CASE_SET_REG32(drs, 0xac)
1615     CASE_SET_REG32(sbms, 0xb0)
1616     CASE_SET_REG32(dmbs, 0xb4)
1617     CASE_SET_REG32(dnad64, 0xb8)
1618     CASE_SET_REG32(pmjad1, 0xc0)
1619     CASE_SET_REG32(pmjad2, 0xc4)
1620     CASE_SET_REG32(rbc, 0xc8)
1621     CASE_SET_REG32(ua, 0xcc)
1622     CASE_SET_REG32(ia, 0xd4)
1623     CASE_SET_REG32(sbc, 0xd8)
1624     CASE_SET_REG32(csbc, 0xdc)
1625     default:
1626         if (offset >= 0x5c && offset < 0xa0) {
1627             int n;
1628             int shift;
1629             n = (offset - 0x58) >> 2;
1630             shift = (offset & 3) * 8;
1631             s->scratch[n] &= ~(0xff << shift);
1632             s->scratch[n] |= (val & 0xff) << shift;
1633         } else {
1634             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1635         }
1636     }
1637 #undef CASE_SET_REG32
1638 }
1639
1640 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1641 {
1642     LSIState *s = (LSIState *)opaque;
1643
1644     lsi_reg_writeb(s, addr & 0xff, val);
1645 }
1646
1647 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1648 {
1649     LSIState *s = (LSIState *)opaque;
1650
1651     addr &= 0xff;
1652     lsi_reg_writeb(s, addr, val & 0xff);
1653     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1654 }
1655
1656 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1657 {
1658     LSIState *s = (LSIState *)opaque;
1659
1660     addr &= 0xff;
1661     lsi_reg_writeb(s, addr, val & 0xff);
1662     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1663     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1664     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1665 }
1666
1667 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1668 {
1669     LSIState *s = (LSIState *)opaque;
1670
1671     return lsi_reg_readb(s, addr & 0xff);
1672 }
1673
1674 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1675 {
1676     LSIState *s = (LSIState *)opaque;
1677     uint32_t val;
1678
1679     addr &= 0xff;
1680     val = lsi_reg_readb(s, addr);
1681     val |= lsi_reg_readb(s, addr + 1) << 8;
1682     return val;
1683 }
1684
1685 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1686 {
1687     LSIState *s = (LSIState *)opaque;
1688     uint32_t val;
1689     addr &= 0xff;
1690     val = lsi_reg_readb(s, addr);
1691     val |= lsi_reg_readb(s, addr + 1) << 8;
1692     val |= lsi_reg_readb(s, addr + 2) << 16;
1693     val |= lsi_reg_readb(s, addr + 3) << 24;
1694     return val;
1695 }
1696
1697 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1698     lsi_mmio_readb,
1699     lsi_mmio_readw,
1700     lsi_mmio_readl,
1701 };
1702
1703 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1704     lsi_mmio_writeb,
1705     lsi_mmio_writew,
1706     lsi_mmio_writel,
1707 };
1708
1709 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1710 {
1711     LSIState *s = (LSIState *)opaque;
1712     uint32_t newval;
1713     int shift;
1714
1715     addr &= 0x1fff;
1716     newval = s->script_ram[addr >> 2];
1717     shift = (addr & 3) * 8;
1718     newval &= ~(0xff << shift);
1719     newval |= val << shift;
1720     s->script_ram[addr >> 2] = newval;
1721 }
1722
1723 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1724 {
1725     LSIState *s = (LSIState *)opaque;
1726     uint32_t newval;
1727
1728     addr &= 0x1fff;
1729     newval = s->script_ram[addr >> 2];
1730     if (addr & 2) {
1731         newval = (newval & 0xffff) | (val << 16);
1732     } else {
1733         newval = (newval & 0xffff0000) | val;
1734     }
1735     s->script_ram[addr >> 2] = newval;
1736 }
1737
1738
1739 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1740 {
1741     LSIState *s = (LSIState *)opaque;
1742
1743     addr &= 0x1fff;
1744     s->script_ram[addr >> 2] = val;
1745 }
1746
1747 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1748 {
1749     LSIState *s = (LSIState *)opaque;
1750     uint32_t val;
1751
1752     addr &= 0x1fff;
1753     val = s->script_ram[addr >> 2];
1754     val >>= (addr & 3) * 8;
1755     return val & 0xff;
1756 }
1757
1758 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1759 {
1760     LSIState *s = (LSIState *)opaque;
1761     uint32_t val;
1762
1763     addr &= 0x1fff;
1764     val = s->script_ram[addr >> 2];
1765     if (addr & 2)
1766         val >>= 16;
1767     return le16_to_cpu(val);
1768 }
1769
1770 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1771 {
1772     LSIState *s = (LSIState *)opaque;
1773
1774     addr &= 0x1fff;
1775     return le32_to_cpu(s->script_ram[addr >> 2]);
1776 }
1777
1778 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1779     lsi_ram_readb,
1780     lsi_ram_readw,
1781     lsi_ram_readl,
1782 };
1783
1784 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1785     lsi_ram_writeb,
1786     lsi_ram_writew,
1787     lsi_ram_writel,
1788 };
1789
1790 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1791 {
1792     LSIState *s = (LSIState *)opaque;
1793     return lsi_reg_readb(s, addr & 0xff);
1794 }
1795
1796 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1797 {
1798     LSIState *s = (LSIState *)opaque;
1799     uint32_t val;
1800     addr &= 0xff;
1801     val = lsi_reg_readb(s, addr);
1802     val |= lsi_reg_readb(s, addr + 1) << 8;
1803     return val;
1804 }
1805
1806 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1807 {
1808     LSIState *s = (LSIState *)opaque;
1809     uint32_t val;
1810     addr &= 0xff;
1811     val = lsi_reg_readb(s, addr);
1812     val |= lsi_reg_readb(s, addr + 1) << 8;
1813     val |= lsi_reg_readb(s, addr + 2) << 16;
1814     val |= lsi_reg_readb(s, addr + 3) << 24;
1815     return val;
1816 }
1817
1818 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1819 {
1820     LSIState *s = (LSIState *)opaque;
1821     lsi_reg_writeb(s, addr & 0xff, val);
1822 }
1823
1824 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1825 {
1826     LSIState *s = (LSIState *)opaque;
1827     addr &= 0xff;
1828     lsi_reg_writeb(s, addr, val & 0xff);
1829     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1830 }
1831
1832 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1833 {
1834     LSIState *s = (LSIState *)opaque;
1835     addr &= 0xff;
1836     lsi_reg_writeb(s, addr, val & 0xff);
1837     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1838     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1839     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1840 }
1841
1842 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1843                            uint32_t addr, uint32_t size, int type)
1844 {
1845     LSIState *s = (LSIState *)pci_dev;
1846
1847     DPRINTF("Mapping IO at %08x\n", addr);
1848
1849     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1850     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1851     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1852     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1853     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1854     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1855 }
1856
1857 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1858                             uint32_t addr, uint32_t size, int type)
1859 {
1860     LSIState *s = (LSIState *)pci_dev;
1861
1862     DPRINTF("Mapping ram at %08x\n", addr);
1863     s->script_ram_base = addr;
1864     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1865 }
1866
1867 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1868                              uint32_t addr, uint32_t size, int type)
1869 {
1870     LSIState *s = (LSIState *)pci_dev;
1871
1872     DPRINTF("Mapping registers at %08x\n", addr);
1873     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1874 }
1875
1876 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1877 {
1878     LSIState *s = (LSIState *)opaque;
1879
1880     if (id < 0) {
1881         for (id = 0; id < LSI_MAX_DEVS; id++) {
1882             if (s->scsi_dev[id] == NULL)
1883                 break;
1884         }
1885     }
1886     if (id >= LSI_MAX_DEVS) {
1887         BADF("Bad Device ID %d\n", id);
1888         return;
1889     }
1890     if (s->scsi_dev[id]) {
1891         DPRINTF("Destroying device %d\n", id);
1892         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1893     }
1894     DPRINTF("Attaching block device %d\n", id);
1895     s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1896     if (s->scsi_dev[id] == NULL)
1897         s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1898 }
1899
1900 void *lsi_scsi_init(PCIBus *bus, int devfn)
1901 {
1902     LSIState *s;
1903
1904     s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1905                                         sizeof(*s), devfn, NULL, NULL);
1906     if (s == NULL) {
1907         fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1908         return NULL;
1909     }
1910
1911     /* PCI Vendor ID (word) */
1912     s->pci_dev.config[0x00] = 0x00;
1913     s->pci_dev.config[0x01] = 0x10;
1914     /* PCI device ID (word) */
1915     s->pci_dev.config[0x02] = 0x12;
1916     s->pci_dev.config[0x03] = 0x00;
1917     /* PCI base class code */
1918     s->pci_dev.config[0x0b] = 0x01;
1919     /* PCI subsystem ID */
1920     s->pci_dev.config[0x2e] = 0x00;
1921     s->pci_dev.config[0x2f] = 0x10;
1922     /* PCI latency timer = 255 */
1923     s->pci_dev.config[0x0d] = 0xff;
1924     /* Interrupt pin 1 */
1925     s->pci_dev.config[0x3d] = 0x01;
1926
1927     s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1928                                              lsi_mmio_writefn, s);
1929     s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1930                                             lsi_ram_writefn, s);
1931
1932     pci_register_io_region((struct PCIDevice *)s, 0, 256,
1933                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1934     pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1935                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1936     pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1937                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1938     s->queue = qemu_malloc(sizeof(lsi_queue));
1939     s->queue_len = 1;
1940     s->active_commands = 0;
1941
1942     lsi_soft_reset(s);
1943
1944     return s;
1945 }
1946