2 * QEMU generic PPC hardware System Emulator
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 /*****************************************************************************/
28 /* PPC time base and decrementer emulation */
32 /* Time base management */
33 int64_t tb_offset
; /* Compensation */
34 uint32_t tb_freq
; /* TB frequency */
35 /* Decrementer management */
36 uint64_t decr_next
; /* Tick for next decr interrupt */
37 struct QEMUTimer
*decr_timer
;
40 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t
*tb_env
)
42 /* TB time in tb periods */
43 return muldiv64(qemu_get_clock(vm_clock
) + tb_env
->tb_offset
,
44 tb_env
->tb_freq
, ticks_per_sec
);
47 uint32_t cpu_ppc_load_tbl (CPUState
*env
)
49 ppc_tb_t
*tb_env
= env
->tb_env
;
52 tb
= cpu_ppc_get_tb(tb_env
);
58 if (last_time
!= now
) {
60 printf("%s: tb=0x%016lx %d %08lx\n",
61 __func__
, tb
, now
, tb_env
->tb_offset
);
66 return tb
& 0xFFFFFFFF;
69 uint32_t cpu_ppc_load_tbu (CPUState
*env
)
71 ppc_tb_t
*tb_env
= env
->tb_env
;
74 tb
= cpu_ppc_get_tb(tb_env
);
76 printf("%s: tb=0x%016lx\n", __func__
, tb
);
81 static void cpu_ppc_store_tb (ppc_tb_t
*tb_env
, uint64_t value
)
83 tb_env
->tb_offset
= muldiv64(value
, ticks_per_sec
, tb_env
->tb_freq
)
84 - qemu_get_clock(vm_clock
);
86 printf("%s: tb=0x%016lx offset=%08x\n", __func__
, value
);
90 void cpu_ppc_store_tbu (CPUState
*env
, uint32_t value
)
92 ppc_tb_t
*tb_env
= env
->tb_env
;
94 cpu_ppc_store_tb(tb_env
,
95 ((uint64_t)value
<< 32) | cpu_ppc_load_tbl(env
));
98 void cpu_ppc_store_tbl (CPUState
*env
, uint32_t value
)
100 ppc_tb_t
*tb_env
= env
->tb_env
;
102 cpu_ppc_store_tb(tb_env
,
103 ((uint64_t)cpu_ppc_load_tbu(env
) << 32) | value
);
106 uint32_t cpu_ppc_load_decr (CPUState
*env
)
108 ppc_tb_t
*tb_env
= env
->tb_env
;
112 diff
= tb_env
->decr_next
- qemu_get_clock(vm_clock
);
114 decr
= muldiv64(diff
, tb_env
->tb_freq
, ticks_per_sec
);
116 decr
= -muldiv64(-diff
, tb_env
->tb_freq
, ticks_per_sec
);
117 #if defined(DEBUG_TB)
118 printf("%s: 0x%08x\n", __func__
, decr
);
123 /* When decrementer expires,
124 * all we need to do is generate or queue a CPU exception
126 static inline void cpu_ppc_decr_excp (CPUState
*env
)
130 printf("raise decrementer exception\n");
132 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
135 static void _cpu_ppc_store_decr (CPUState
*env
, uint32_t decr
,
136 uint32_t value
, int is_excp
)
138 ppc_tb_t
*tb_env
= env
->tb_env
;
142 printf("%s: 0x%08x => 0x%08x\n", __func__
, decr
, value
);
144 now
= qemu_get_clock(vm_clock
);
145 next
= now
+ muldiv64(value
, ticks_per_sec
, tb_env
->tb_freq
);
147 next
+= tb_env
->decr_next
- now
;
150 tb_env
->decr_next
= next
;
152 qemu_mod_timer(tb_env
->decr_timer
, next
);
153 /* If we set a negative value and the decrementer was positive,
154 * raise an exception.
156 if ((value
& 0x80000000) && !(decr
& 0x80000000))
157 cpu_ppc_decr_excp(env
);
160 void cpu_ppc_store_decr (CPUState
*env
, uint32_t value
)
162 _cpu_ppc_store_decr(env
, cpu_ppc_load_decr(env
), value
, 0);
165 static void cpu_ppc_decr_cb (void *opaque
)
167 _cpu_ppc_store_decr(opaque
, 0x00000000, 0xFFFFFFFF, 1);
170 /* Set up (once) timebase frequency (in Hz) */
171 ppc_tb_t
*cpu_ppc_tb_init (CPUState
*env
, uint32_t freq
)
175 tb_env
= qemu_mallocz(sizeof(ppc_tb_t
));
178 env
->tb_env
= tb_env
;
179 if (tb_env
->tb_freq
== 0 || 1) {
180 tb_env
->tb_freq
= freq
;
181 /* Create new timer */
183 qemu_new_timer(vm_clock
, &cpu_ppc_decr_cb
, env
);
184 /* There is a bug in 2.4 kernels:
185 * if a decrementer exception is pending when it enables msr_ee,
186 * it's not ready to handle it...
188 _cpu_ppc_store_decr(env
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
195 /*****************************************************************************/
196 /* Handle system reset (for now, just stop emulation) */
197 void cpu_ppc_reset (CPUState
*env
)
199 printf("Reset asked... Stop emulation\n");
204 static void PPC_io_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
206 cpu_outb(NULL
, addr
& 0xffff, value
);
209 static uint32_t PPC_io_readb (void *opaque
, target_phys_addr_t addr
)
211 uint32_t ret
= cpu_inb(NULL
, addr
& 0xffff);
215 static void PPC_io_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
217 #ifdef TARGET_WORDS_BIGENDIAN
218 value
= bswap16(value
);
220 cpu_outw(NULL
, addr
& 0xffff, value
);
223 static uint32_t PPC_io_readw (void *opaque
, target_phys_addr_t addr
)
225 uint32_t ret
= cpu_inw(NULL
, addr
& 0xffff);
226 #ifdef TARGET_WORDS_BIGENDIAN
232 static void PPC_io_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
234 #ifdef TARGET_WORDS_BIGENDIAN
235 value
= bswap32(value
);
237 cpu_outl(NULL
, addr
& 0xffff, value
);
240 static uint32_t PPC_io_readl (void *opaque
, target_phys_addr_t addr
)
242 uint32_t ret
= cpu_inl(NULL
, addr
& 0xffff);
244 #ifdef TARGET_WORDS_BIGENDIAN
250 CPUWriteMemoryFunc
*PPC_io_write
[] = {
256 CPUReadMemoryFunc
*PPC_io_read
[] = {
262 /*****************************************************************************/
264 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
276 printf("Set loglevel to %04x\n", val
);
277 cpu_set_log(val
| 0x100);
282 /*****************************************************************************/
284 void NVRAM_set_byte (m48t59_t
*nvram
, uint32_t addr
, uint8_t value
)
286 m48t59_write(nvram
, addr
, value
);
289 uint8_t NVRAM_get_byte (m48t59_t
*nvram
, uint32_t addr
)
291 return m48t59_read(nvram
, addr
);
294 void NVRAM_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
)
296 m48t59_write(nvram
, addr
, value
>> 8);
297 m48t59_write(nvram
, addr
+ 1, value
& 0xFF);
300 uint16_t NVRAM_get_word (m48t59_t
*nvram
, uint32_t addr
)
304 tmp
= m48t59_read(nvram
, addr
) << 8;
305 tmp
|= m48t59_read(nvram
, addr
+ 1);
309 void NVRAM_set_lword (m48t59_t
*nvram
, uint32_t addr
, uint32_t value
)
311 m48t59_write(nvram
, addr
, value
>> 24);
312 m48t59_write(nvram
, addr
+ 1, (value
>> 16) & 0xFF);
313 m48t59_write(nvram
, addr
+ 2, (value
>> 8) & 0xFF);
314 m48t59_write(nvram
, addr
+ 3, value
& 0xFF);
317 uint32_t NVRAM_get_lword (m48t59_t
*nvram
, uint32_t addr
)
321 tmp
= m48t59_read(nvram
, addr
) << 24;
322 tmp
|= m48t59_read(nvram
, addr
+ 1) << 16;
323 tmp
|= m48t59_read(nvram
, addr
+ 2) << 8;
324 tmp
|= m48t59_read(nvram
, addr
+ 3);
328 void NVRAM_set_string (m48t59_t
*nvram
, uint32_t addr
,
329 const unsigned char *str
, uint32_t max
)
333 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
334 m48t59_write(nvram
, addr
+ i
, str
[i
]);
336 m48t59_write(nvram
, addr
+ max
- 1, '\0');
339 int NVRAM_get_string (m48t59_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
)
344 for (i
= 0; i
< max
; i
++) {
345 dst
[i
] = NVRAM_get_byte(nvram
, addr
+ i
);
353 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
356 uint16_t pd
, pd1
, pd2
;
361 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
362 tmp
^= (pd1
<< 3) | (pd1
<< 8);
363 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
368 uint16_t NVRAM_compute_crc (m48t59_t
*nvram
, uint32_t start
, uint32_t count
)
371 uint16_t crc
= 0xFFFF;
376 for (i
= 0; i
!= count
; i
++) {
377 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
380 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
386 #define CMDLINE_ADDR 0x017ff000
388 int PPC_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
389 const unsigned char *arch
,
390 uint32_t RAM_size
, int boot_device
,
391 uint32_t kernel_image
, uint32_t kernel_size
,
393 uint32_t initrd_image
, uint32_t initrd_size
,
394 uint32_t NVRAM_image
,
395 int width
, int height
, int depth
)
399 /* Set parameters for Open Hack'Ware BIOS */
400 NVRAM_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
401 NVRAM_set_lword(nvram
, 0x10, 0x00000002); /* structure v2 */
402 NVRAM_set_word(nvram
, 0x14, NVRAM_size
);
403 NVRAM_set_string(nvram
, 0x20, arch
, 16);
404 NVRAM_set_lword(nvram
, 0x30, RAM_size
);
405 NVRAM_set_byte(nvram
, 0x34, boot_device
);
406 NVRAM_set_lword(nvram
, 0x38, kernel_image
);
407 NVRAM_set_lword(nvram
, 0x3C, kernel_size
);
409 /* XXX: put the cmdline in NVRAM too ? */
410 strcpy(phys_ram_base
+ CMDLINE_ADDR
, cmdline
);
411 NVRAM_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
412 NVRAM_set_lword(nvram
, 0x44, strlen(cmdline
));
414 NVRAM_set_lword(nvram
, 0x40, 0);
415 NVRAM_set_lword(nvram
, 0x44, 0);
417 NVRAM_set_lword(nvram
, 0x48, initrd_image
);
418 NVRAM_set_lword(nvram
, 0x4C, initrd_size
);
419 NVRAM_set_lword(nvram
, 0x50, NVRAM_image
);
421 NVRAM_set_word(nvram
, 0x54, width
);
422 NVRAM_set_word(nvram
, 0x56, height
);
423 NVRAM_set_word(nvram
, 0x58, depth
);
424 crc
= NVRAM_compute_crc(nvram
, 0x00, 0xF8);
425 NVRAM_set_word(nvram
, 0xFC, crc
);