hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35
  36 #define KERNEL_LOAD_ADDR     0x00404000
  37 #define CMDLINE_ADDR         0x003ff000
  38 #define INITRD_LOAD_ADDR     0x00300000
  39 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  40 #define PROM_ADDR            0x1fff0000000ULL
  41 #define PROM_VADDR           0x000ffd00000ULL
  42 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  43 #define APB_MEM_BASE         0x1ff00000000ULL
  44 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  45 #define PROM_FILENAME        "openbios-sparc64"
  46 #define NVRAM_SIZE           0x2000
  47 #define MAX_IDE_BUS          2
  48 #define BIOS_CFG_IOPORT      0x510
  49
  50 struct hwdef {
  51     const char * const default_cpu_model;
  52     uint16_t machine_id;
  53 };
  54
  55 int DMA_get_channel_mode (int nchan)
  56 {
  57     return 0;
  58 }
  59 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  60 {
  61     return 0;
  62 }
  63 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  64 {
  65     return 0;
  66 }
  67 void DMA_hold_DREQ (int nchan) {}
  68 void DMA_release_DREQ (int nchan) {}
  69 void DMA_schedule(int nchan) {}
  70 void DMA_run (void) {}
  71 void DMA_init (int high_page_enable) {}
  72 void DMA_register_channel (int nchan,
  73                            DMA_transfer_handler transfer_handler,
  74                            void *opaque)
  75 {
  76 }
  77
  78 static int nvram_boot_set(void *opaque, const char *boot_device)
  79 {
  80     unsigned int i;
  81     uint8_t image[sizeof(ohwcfg_v3_t)];
  82     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  83     m48t59_t *nvram = (m48t59_t *)opaque;
  84
  85     for (i = 0; i < sizeof(image); i++)
  86         image[i] = m48t59_read(nvram, i) & 0xff;
  87
  88     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
  89             boot_device);
  90     header->nboot_devices = strlen(boot_device) & 0xff;
  91     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
  92
  93     for (i = 0; i < sizeof(image); i++)
  94         m48t59_write(nvram, i, image[i]);
  95
  96     return 0;
  97 }
  98
  99 extern int nographic;
 100
 101 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 102                                    const char *arch,
 103                                    ram_addr_t RAM_size,
 104                                    const char *boot_devices,
 105                                    uint32_t kernel_image, uint32_t kernel_size,
 106                                    const char *cmdline,
 107                                    uint32_t initrd_image, uint32_t initrd_size,
 108                                    uint32_t NVRAM_image,
 109                                    int width, int height, int depth,
 110                                    const uint8_t *macaddr)
 111 {
 112     unsigned int i;
 113     uint32_t start, end;
 114     uint8_t image[0x1ff0];
 115     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 116     struct sparc_arch_cfg *sparc_header;
 117     struct OpenBIOS_nvpart_v1 *part_header;
 118
 119     memset(image, '\0', sizeof(image));
 120
 121     // Try to match PPC NVRAM
 122     pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
 123             "QEMU_BIOS");
 124     header->struct_version = cpu_to_be32(3); /* structure v3 */
 125
 126     header->nvram_size = cpu_to_be16(NVRAM_size);
 127     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 128     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 129     pstrcpy((char *)header->arch, sizeof(header->arch), arch);
 130     header->nb_cpus = smp_cpus & 0xff;
 131     header->RAM0_base = 0;
 132     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 133     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 134             boot_devices);
 135     header->nboot_devices = strlen(boot_devices) & 0xff;
 136     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 137     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 138     if (cmdline) {
 139         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 140         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 141         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 142     }
 143     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 144     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 145     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 146
 147     header->width = cpu_to_be16(width);
 148     header->height = cpu_to_be16(height);
 149     header->depth = cpu_to_be16(depth);
 150     if (nographic)
 151         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 152
 153     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 154
 155     // Architecture specific header
 156     start = sizeof(ohwcfg_v3_t);
 157     sparc_header = (struct sparc_arch_cfg *)&image[start];
 158     sparc_header->valid = 0;
 159     start += sizeof(struct sparc_arch_cfg);
 160
 161     // OpenBIOS nvram variables
 162     // Variable partition
 163     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 164     part_header->signature = OPENBIOS_PART_SYSTEM;
 165     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 166
 167     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 168     for (i = 0; i < nb_prom_envs; i++)
 169         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 170
 171     // End marker
 172     image[end++] = '\0';
 173
 174     end = start + ((end - start + 15) & ~15);
 175     OpenBIOS_finish_partition(part_header, end - start);
 176
 177     // free partition
 178     start = end;
 179     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 180     part_header->signature = OPENBIOS_PART_FREE;
 181     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 182
 183     end = 0x1fd0;
 184     OpenBIOS_finish_partition(part_header, end - start);
 185
 186     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 187
 188     for (i = 0; i < sizeof(image); i++)
 189         m48t59_write(nvram, i, image[i]);
 190
 191     qemu_register_boot_set(nvram_boot_set, nvram);
 192
 193     return 0;
 194 }
 195
 196 void pic_info(void)
 197 {
 198 }
 199
 200 void irq_info(void)
 201 {
 202 }
 203
 204 void qemu_system_powerdown(void)
 205 {
 206 }
 207
 208 static void main_cpu_reset(void *opaque)
 209 {
 210     CPUState *env = opaque;
 211
 212     cpu_reset(env);
 213     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 214     ptimer_run(env->tick, 0);
 215     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 216     ptimer_run(env->stick, 0);
 217     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 218     ptimer_run(env->hstick, 0);
 219 }
 220
 221 static void tick_irq(void *opaque)
 222 {
 223     CPUState *env = opaque;
 224
 225     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 226 }
 227
 228 static void stick_irq(void *opaque)
 229 {
 230     CPUState *env = opaque;
 231
 232     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 233 }
 234
 235 static void hstick_irq(void *opaque)
 236 {
 237     CPUState *env = opaque;
 238
 239     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 240 }
 241
 242 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 243 {
 244 }
 245
 246 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 247 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 248 static const int ide_irq[2] = { 14, 15 };
 249
 250 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 251 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 252
 253 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 254 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 255
 256 static fdctrl_t *floppy_controller;
 257
 258 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 259                         const char *boot_devices, DisplayState *ds,
 260                         const char *kernel_filename, const char *kernel_cmdline,
 261                         const char *initrd_filename, const char *cpu_model,
 262                         const struct hwdef *hwdef)
 263 {
 264     CPUState *env;
 265     char buf[1024];
 266     m48t59_t *nvram;
 267     int ret, linux_boot;
 268     unsigned int i;
 269     long prom_offset, initrd_size, kernel_size;
 270     PCIBus *pci_bus;
 271     QEMUBH *bh;
 272     qemu_irq *irq;
 273     int drive_index;
 274     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 275     BlockDriverState *fd[MAX_FD];
 276     void *fw_cfg;
 277
 278     linux_boot = (kernel_filename != NULL);
 279
 280     /* init CPUs */
 281     if (!cpu_model)
 282         cpu_model = hwdef->default_cpu_model;
 283
 284     env = cpu_init(cpu_model);
 285     if (!env) {
 286         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 287         exit(1);
 288     }
 289     bh = qemu_bh_new(tick_irq, env);
 290     env->tick = ptimer_init(bh);
 291     ptimer_set_period(env->tick, 1ULL);
 292
 293     bh = qemu_bh_new(stick_irq, env);
 294     env->stick = ptimer_init(bh);
 295     ptimer_set_period(env->stick, 1ULL);
 296
 297     bh = qemu_bh_new(hstick_irq, env);
 298     env->hstick = ptimer_init(bh);
 299     ptimer_set_period(env->hstick, 1ULL);
 300     qemu_register_reset(main_cpu_reset, env);
 301     main_cpu_reset(env);
 302
 303     /* allocate RAM */
 304     cpu_register_physical_memory(0, RAM_size, 0);
 305
 306     prom_offset = RAM_size + vga_ram_size;
 307     cpu_register_physical_memory(PROM_ADDR,
 308                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 309                                  TARGET_PAGE_MASK,
 310                                  prom_offset | IO_MEM_ROM);
 311
 312     if (bios_name == NULL)
 313         bios_name = PROM_FILENAME;
 314     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 315     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 316     if (ret < 0) {
 317         fprintf(stderr, "qemu: could not load prom '%s'\n",
 318                 buf);
 319         exit(1);
 320     }
 321
 322     kernel_size = 0;
 323     initrd_size = 0;
 324     if (linux_boot) {
 325         /* XXX: put correct offset */
 326         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 327         if (kernel_size < 0)
 328             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 329                                     ram_size - KERNEL_LOAD_ADDR);
 330         if (kernel_size < 0)
 331             kernel_size = load_image_targphys(kernel_filename,
 332                                               KERNEL_LOAD_ADDR,
 333                                               ram_size - KERNEL_LOAD_ADDR);
 334         if (kernel_size < 0) {
 335             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 336                     kernel_filename);
 337             exit(1);
 338         }
 339
 340         /* load initrd */
 341         if (initrd_filename) {
 342             initrd_size = load_image_targphys(initrd_filename,
 343                                               INITRD_LOAD_ADDR,
 344                                               ram_size - INITRD_LOAD_ADDR);
 345             if (initrd_size < 0) {
 346                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 347                         initrd_filename);
 348                 exit(1);
 349             }
 350         }
 351         if (initrd_size > 0) {
 352             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 353                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 354                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 355                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 356                     break;
 357                 }
 358             }
 359         }
 360     }
 361     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 362     isa_mem_base = VGA_BASE;
 363     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 364                         vga_ram_size);
 365
 366     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 367         if (serial_hds[i]) {
 368             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 369                         serial_hds[i]);
 370         }
 371     }
 372
 373     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 374         if (parallel_hds[i]) {
 375             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 376                           parallel_hds[i]);
 377         }
 378     }
 379
 380     for(i = 0; i < nb_nics; i++) {
 381         if (!nd_table[i].model)
 382             nd_table[i].model = "ne2k_pci";
 383         pci_nic_init(pci_bus, &nd_table[i], -1);
 384     }
 385
 386     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 387     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 388         fprintf(stderr, "qemu: too many IDE bus\n");
 389         exit(1);
 390     }
 391     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 392         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 393                                       i % MAX_IDE_DEVS);
 394        if (drive_index != -1)
 395            hd[i] = drives_table[drive_index].bdrv;
 396        else
 397            hd[i] = NULL;
 398     }
 399
 400     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 401     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 402     /* FIXME: wire up interrupts.  */
 403     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 404     for(i = 0; i < MAX_FD; i++) {
 405         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 406        if (drive_index != -1)
 407            fd[i] = drives_table[drive_index].bdrv;
 408        else
 409            fd[i] = NULL;
 410     }
 411     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 412     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 413     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 414                            KERNEL_LOAD_ADDR, kernel_size,
 415                            kernel_cmdline,
 416                            INITRD_LOAD_ADDR, initrd_size,
 417                            /* XXX: need an option to load a NVRAM image */
 418                            0,
 419                            graphic_width, graphic_height, graphic_depth,
 420                            (uint8_t *)&nd_table[0].macaddr);
 421
 422     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 423     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 424     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 425     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 426 }
 427
 428 enum {
 429     sun4u_id = 0,
 430     sun4v_id = 64,
 431 };
 432
 433 static const struct hwdef hwdefs[] = {
 434     /* Sun4u generic PC-like machine */
 435     {
 436         .default_cpu_model = "TI UltraSparc II",
 437         .machine_id = sun4u_id,
 438     },
 439     /* Sun4v generic PC-like machine */
 440     {
 441         .default_cpu_model = "Sun UltraSparc T1",
 442         .machine_id = sun4v_id,
 443     },
 444 };
 445
 446 /* Sun4u hardware initialisation */
 447 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 448                        const char *boot_devices, DisplayState *ds,
 449                        const char *kernel_filename, const char *kernel_cmdline,
 450                        const char *initrd_filename, const char *cpu_model)
 451 {
 452     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 453                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 454 }
 455
 456 /* Sun4v hardware initialisation */
 457 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 458                        const char *boot_devices, DisplayState *ds,
 459                        const char *kernel_filename, const char *kernel_cmdline,
 460                        const char *initrd_filename, const char *cpu_model)
 461 {
 462     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 463                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 464 }
 465
 466 QEMUMachine sun4u_machine = {
 467     .name = "sun4u",
 468     .desc = "Sun4u platform",
 469     .init = sun4u_init,
 470     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 471     .nodisk_ok = 1,
 472 };
 473
 474 QEMUMachine sun4v_machine = {
 475     .name = "sun4v",
 476     .desc = "Sun4v platform",
 477     .init = sun4v_init,
 478     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 479     .nodisk_ok = 1,
 480 };