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Fix building with 2.6.27 kernel headers (Kirill Shutemov).
[qemu/mini2440.git] / hw / sun4m.c
blobfcd0ace5e803079fcc22714bf9fbcc2d2b2615b9
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (512 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
100 long vram_size, nvram_size;
101 // IRQ numbers are not PIL ones, but master interrupt controller
102 // register bit numbers
103 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
104 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
105 uint8_t nvram_machine_id;
106 uint16_t machine_id;
107 uint32_t iommu_version;
108 uint32_t intbit_to_level[32];
109 uint64_t max_mem;
110 const char * const default_cpu_model;
111 };
112
113 #define MAX_IOUNITS 5
114
115 struct sun4d_hwdef {
116 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
117 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
118 target_phys_addr_t serial_base;
119 target_phys_addr_t espdma_base, esp_base;
120 target_phys_addr_t ledma_base, le_base;
121 target_phys_addr_t tcx_base;
122 target_phys_addr_t sbi_base;
123 unsigned long vram_size, nvram_size;
124 // IRQ numbers are not PIL ones, but SBI register bit numbers
125 int esp_irq, le_irq, clock_irq, clock1_irq;
126 int ser_irq, ms_kb_irq, me_irq;
127 uint8_t nvram_machine_id;
128 uint16_t machine_id;
129 uint32_t iounit_version;
130 uint64_t max_mem;
131 const char * const default_cpu_model;
132 };
133
134 int DMA_get_channel_mode (int nchan)
135 {
136 return 0;
137 }
138 int DMA_read_memory (int nchan, void *buf, int pos, int size)
139 {
140 return 0;
141 }
142 int DMA_write_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 void DMA_hold_DREQ (int nchan) {}
147 void DMA_release_DREQ (int nchan) {}
148 void DMA_schedule(int nchan) {}
149 void DMA_run (void) {}
150 void DMA_init (int high_page_enable) {}
151 void DMA_register_channel (int nchan,
152 DMA_transfer_handler transfer_handler,
153 void *opaque)
154 {
155 }
156
157 static int nvram_boot_set(void *opaque, const char *boot_device)
158 {
159 unsigned int i;
160 uint8_t image[sizeof(ohwcfg_v3_t)];
161 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
162 m48t59_t *nvram = (m48t59_t *)opaque;
163
164 for (i = 0; i < sizeof(image); i++)
165 image[i] = m48t59_read(nvram, i) & 0xff;
166
167 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
168 boot_device);
169 header->nboot_devices = strlen(boot_device) & 0xff;
170 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
171
172 for (i = 0; i < sizeof(image); i++)
173 m48t59_write(nvram, i, image[i]);
174
175 return 0;
176 }
177
178 extern int nographic;
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
190 struct sparc_arch_cfg *sparc_header;
191 struct OpenBIOS_nvpart_v1 *part_header;
192
193 memset(image, '\0', sizeof(image));
194
195 // Try to match PPC NVRAM
196 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
197 "QEMU_BIOS");
198 header->struct_version = cpu_to_be32(3); /* structure v3 */
199
200 header->nvram_size = cpu_to_be16(0x2000);
201 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
202 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
203 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
204 header->nb_cpus = smp_cpus & 0xff;
205 header->RAM0_base = 0;
206 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
207 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
208 boot_devices);
209 header->nboot_devices = strlen(boot_devices) & 0xff;
210 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
211 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
212 if (cmdline) {
213 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
214 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
215 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
216 }
217 // XXX add initrd_image, initrd_size
218 header->width = cpu_to_be16(width);
219 header->height = cpu_to_be16(height);
220 header->depth = cpu_to_be16(depth);
221 if (nographic)
222 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
223
224 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
225
226 // Architecture specific header
227 start = sizeof(ohwcfg_v3_t);
228 sparc_header = (struct sparc_arch_cfg *)&image[start];
229 sparc_header->valid = 0;
230 start += sizeof(struct sparc_arch_cfg);
231
232 // OpenBIOS nvram variables
233 // Variable partition
234 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
235 part_header->signature = OPENBIOS_PART_SYSTEM;
236 pstrcpy(part_header->name, sizeof(part_header->name), "system");
237
238 end = start + sizeof(struct OpenBIOS_nvpart_v1);
239 for (i = 0; i < nb_prom_envs; i++)
240 end = OpenBIOS_set_var(image, end, prom_envs[i]);
241
242 // End marker
243 image[end++] = '\0';
244
245 end = start + ((end - start + 15) & ~15);
246 OpenBIOS_finish_partition(part_header, end - start);
247
248 // free partition
249 start = end;
250 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
251 part_header->signature = OPENBIOS_PART_FREE;
252 pstrcpy(part_header->name, sizeof(part_header->name), "free");
253
254 end = 0x1fd0;
255 OpenBIOS_finish_partition(part_header, end - start);
256
257 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
258 nvram_machine_id);
259
260 for (i = 0; i < sizeof(image); i++)
261 m48t59_write(nvram, i, image[i]);
262
263 qemu_register_boot_set(nvram_boot_set, nvram);
264 }
265
266 static void *slavio_intctl;
267
268 void pic_info(void)
269 {
270 if (slavio_intctl)
271 slavio_pic_info(slavio_intctl);
272 }
273
274 void irq_info(void)
275 {
276 if (slavio_intctl)
277 slavio_irq_info(slavio_intctl);
278 }
279
280 void cpu_check_irqs(CPUState *env)
281 {
282 if (env->pil_in && (env->interrupt_index == 0 ||
283 (env->interrupt_index & ~15) == TT_EXTINT)) {
284 unsigned int i;
285
286 for (i = 15; i > 0; i--) {
287 if (env->pil_in & (1 << i)) {
288 int old_interrupt = env->interrupt_index;
289
290 env->interrupt_index = TT_EXTINT | i;
291 if (old_interrupt != env->interrupt_index) {
292 DPRINTF("Set CPU IRQ %d\n", i);
293 cpu_interrupt(env, CPU_INTERRUPT_HARD);
294 }
295 break;
296 }
297 }
298 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
299 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
300 env->interrupt_index = 0;
301 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
302 }
303 }
304
305 static void cpu_set_irq(void *opaque, int irq, int level)
306 {
307 CPUState *env = opaque;
308
309 if (level) {
310 DPRINTF("Raise CPU IRQ %d\n", irq);
311 env->halted = 0;
312 env->pil_in |= 1 << irq;
313 cpu_check_irqs(env);
314 } else {
315 DPRINTF("Lower CPU IRQ %d\n", irq);
316 env->pil_in &= ~(1 << irq);
317 cpu_check_irqs(env);
318 }
319 }
320
321 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
322 {
323 }
324
325 static void *slavio_misc;
326
327 void qemu_system_powerdown(void)
328 {
329 slavio_set_power_fail(slavio_misc, 1);
330 }
331
332 static void main_cpu_reset(void *opaque)
333 {
334 CPUState *env = opaque;
335
336 cpu_reset(env);
337 env->halted = 0;
338 }
339
340 static void secondary_cpu_reset(void *opaque)
341 {
342 CPUState *env = opaque;
343
344 cpu_reset(env);
345 env->halted = 1;
346 }
347
348 static unsigned long sun4m_load_kernel(const char *kernel_filename,
349 const char *initrd_filename,
350 ram_addr_t RAM_size)
351 {
352 int linux_boot;
353 unsigned int i;
354 long initrd_size, kernel_size;
355
356 linux_boot = (kernel_filename != NULL);
357
358 kernel_size = 0;
359 if (linux_boot) {
360 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
361 NULL);
362 if (kernel_size < 0)
363 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
364 RAM_size - KERNEL_LOAD_ADDR);
365 if (kernel_size < 0)
366 kernel_size = load_image_targphys(kernel_filename,
367 KERNEL_LOAD_ADDR,
368 RAM_size - KERNEL_LOAD_ADDR);
369 if (kernel_size < 0) {
370 fprintf(stderr, "qemu: could not load kernel '%s'\n",
371 kernel_filename);
372 exit(1);
373 }
374
375 /* load initrd */
376 initrd_size = 0;
377 if (initrd_filename) {
378 initrd_size = load_image_targphys(initrd_filename,
379 INITRD_LOAD_ADDR,
380 RAM_size - INITRD_LOAD_ADDR);
381 if (initrd_size < 0) {
382 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
383 initrd_filename);
384 exit(1);
385 }
386 }
387 if (initrd_size > 0) {
388 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
389 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
390 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
391 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
392 break;
393 }
394 }
395 }
396 }
397 return kernel_size;
398 }
399
400 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
401 const char *boot_device,
402 DisplayState *ds, const char *kernel_filename,
403 const char *kernel_cmdline,
404 const char *initrd_filename, const char *cpu_model)
405
406 {
407 CPUState *env, *envs[MAX_CPUS];
408 unsigned int i;
409 void *iommu, *espdma, *ledma, *main_esp, *nvram;
410 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
411 *espdma_irq, *ledma_irq;
412 qemu_irq *esp_reset, *le_reset;
413 qemu_irq *fdc_tc;
414 unsigned long prom_offset, kernel_size;
415 int ret;
416 char buf[1024];
417 BlockDriverState *fd[MAX_FD];
418 int drive_index;
419 void *fw_cfg;
420
421 /* init CPUs */
422 if (!cpu_model)
423 cpu_model = hwdef->default_cpu_model;
424
425 for(i = 0; i < smp_cpus; i++) {
426 env = cpu_init(cpu_model);
427 if (!env) {
428 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
429 exit(1);
430 }
431 cpu_sparc_set_id(env, i);
432 envs[i] = env;
433 if (i == 0) {
434 qemu_register_reset(main_cpu_reset, env);
435 } else {
436 qemu_register_reset(secondary_cpu_reset, env);
437 env->halted = 1;
438 }
439 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
440 env->prom_addr = hwdef->slavio_base;
441 }
442
443 for (i = smp_cpus; i < MAX_CPUS; i++)
444 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
445
446
447 /* allocate RAM */
448 if ((uint64_t)RAM_size > hwdef->max_mem) {
449 fprintf(stderr,
450 "qemu: Too much memory for this machine: %d, maximum %d\n",
451 (unsigned int)(RAM_size / (1024 * 1024)),
452 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
453 exit(1);
454 }
455 cpu_register_physical_memory(0, RAM_size, 0);
456
457 /* load boot prom */
458 prom_offset = RAM_size + hwdef->vram_size;
459 cpu_register_physical_memory(hwdef->slavio_base,
460 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
461 TARGET_PAGE_MASK,
462 prom_offset | IO_MEM_ROM);
463
464 if (bios_name == NULL)
465 bios_name = PROM_FILENAME;
466 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
467 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
468 if (ret < 0 || ret > PROM_SIZE_MAX)
469 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
470 if (ret < 0 || ret > PROM_SIZE_MAX) {
471 fprintf(stderr, "qemu: could not load prom '%s'\n",
472 buf);
473 exit(1);
474 }
475 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
476
477 /* set up devices */
478 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
479 hwdef->intctl_base + 0x10000ULL,
480 &hwdef->intbit_to_level[0],
481 &slavio_irq, &slavio_cpu_irq,
482 cpu_irqs,
483 hwdef->clock_irq);
484
485 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
486 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
487
488 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
489 prom_offset | IO_MEM_ROM);
490 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
491 sizeof(idreg_data));
492 }
493
494 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
495 slavio_irq[hwdef->me_irq]);
496
497 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
498 iommu, &espdma_irq, &esp_reset);
499
500 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
501 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
502 &le_reset);
503
504 if (graphic_depth != 8 && graphic_depth != 24) {
505 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
506 exit (1);
507 }
508 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
509 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
510
511 if (nd_table[0].model == NULL
512 || strcmp(nd_table[0].model, "lance") == 0) {
513 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
514 } else if (strcmp(nd_table[0].model, "?") == 0) {
515 fprintf(stderr, "qemu: Supported NICs: lance\n");
516 exit (1);
517 } else {
518 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
519 exit (1);
520 }
521
522 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
523 hwdef->nvram_size, 8);
524
525 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
526 slavio_cpu_irq, smp_cpus);
527
528 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
529 nographic);
530 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
531 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
532 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
533 serial_hds[1], serial_hds[0]);
534
535 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
536 hwdef->aux1_base, hwdef->aux2_base,
537 slavio_irq[hwdef->me_irq], envs[0],
538 &fdc_tc);
539
540 if (hwdef->fd_base != (target_phys_addr_t)-1) {
541 /* there is zero or one floppy drive */
542 memset(fd, 0, sizeof(fd));
543 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
544 if (drive_index != -1)
545 fd[0] = drives_table[drive_index].bdrv;
546
547 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
548 fdc_tc);
549 }
550
551 if (drive_get_max_bus(IF_SCSI) > 0) {
552 fprintf(stderr, "qemu: too many SCSI bus\n");
553 exit(1);
554 }
555
556 main_esp = esp_init(hwdef->esp_base, 2,
557 espdma_memory_read, espdma_memory_write,
558 espdma, *espdma_irq, esp_reset);
559
560 for (i = 0; i < ESP_MAX_DEVS; i++) {
561 drive_index = drive_get_index(IF_SCSI, 0, i);
562 if (drive_index == -1)
563 continue;
564 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
565 }
566
567 if (hwdef->cs_base != (target_phys_addr_t)-1)
568 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
569
570 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
571 RAM_size);
572
573 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
574 boot_device, RAM_size, kernel_size, graphic_width,
575 graphic_height, graphic_depth, hwdef->nvram_machine_id,
576 "Sun4m");
577
578 if (hwdef->ecc_base != (target_phys_addr_t)-1)
579 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
580 hwdef->ecc_version);
581
582 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
583 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
584 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
585 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
586 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
587 }
588
589 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
590 const char *boot_device,
591 DisplayState *ds, const char *kernel_filename,
592 const char *kernel_cmdline,
593 const char *initrd_filename, const char *cpu_model)
594 {
595 CPUState *env;
596 unsigned int i;
597 void *iommu, *espdma, *ledma, *main_esp, *nvram;
598 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
599 qemu_irq *esp_reset, *le_reset;
600 qemu_irq *fdc_tc;
601 unsigned long prom_offset, kernel_size;
602 int ret;
603 char buf[1024];
604 BlockDriverState *fd[MAX_FD];
605 int drive_index;
606 void *fw_cfg;
607
608 /* init CPU */
609 if (!cpu_model)
610 cpu_model = hwdef->default_cpu_model;
611
612 env = cpu_init(cpu_model);
613 if (!env) {
614 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
615 exit(1);
616 }
617
618 cpu_sparc_set_id(env, 0);
619
620 qemu_register_reset(main_cpu_reset, env);
621 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
622 env->prom_addr = hwdef->slavio_base;
623
624 /* allocate RAM */
625 if ((uint64_t)RAM_size > hwdef->max_mem) {
626 fprintf(stderr,
627 "qemu: Too much memory for this machine: %d, maximum %d\n",
628 (unsigned int)(RAM_size / (1024 * 1024)),
629 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
630 exit(1);
631 }
632 cpu_register_physical_memory(0, RAM_size, 0);
633
634 /* load boot prom */
635 prom_offset = RAM_size + hwdef->vram_size;
636 cpu_register_physical_memory(hwdef->slavio_base,
637 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
638 TARGET_PAGE_MASK,
639 prom_offset | IO_MEM_ROM);
640
641 if (bios_name == NULL)
642 bios_name = PROM_FILENAME;
643 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
644 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
645 if (ret < 0 || ret > PROM_SIZE_MAX)
646 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
647 if (ret < 0 || ret > PROM_SIZE_MAX) {
648 fprintf(stderr, "qemu: could not load prom '%s'\n",
649 buf);
650 exit(1);
651 }
652 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
653
654 /* set up devices */
655 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
656 &slavio_irq, cpu_irqs);
657
658 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
659 slavio_irq[hwdef->me_irq]);
660
661 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
662 iommu, &espdma_irq, &esp_reset);
663
664 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
665 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
666 &le_reset);
667
668 if (graphic_depth != 8 && graphic_depth != 24) {
669 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
670 exit (1);
671 }
672 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
673 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
674
675 if (nd_table[0].model == NULL
676 || strcmp(nd_table[0].model, "lance") == 0) {
677 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
678 } else if (strcmp(nd_table[0].model, "?") == 0) {
679 fprintf(stderr, "qemu: Supported NICs: lance\n");
680 exit (1);
681 } else {
682 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
683 exit (1);
684 }
685
686 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
687 hwdef->nvram_size, 2);
688
689 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
690 nographic);
691 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
692 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
693 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
694 serial_hds[1], serial_hds[0]);
695
696 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
697 hwdef->aux1_base, hwdef->aux2_base,
698 slavio_irq[hwdef->me_irq], env, &fdc_tc);
699
700 if (hwdef->fd_base != (target_phys_addr_t)-1) {
701 /* there is zero or one floppy drive */
702 fd[1] = fd[0] = NULL;
703 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
704 if (drive_index != -1)
705 fd[0] = drives_table[drive_index].bdrv;
706
707 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
708 fdc_tc);
709 }
710
711 if (drive_get_max_bus(IF_SCSI) > 0) {
712 fprintf(stderr, "qemu: too many SCSI bus\n");
713 exit(1);
714 }
715
716 main_esp = esp_init(hwdef->esp_base, 2,
717 espdma_memory_read, espdma_memory_write,
718 espdma, *espdma_irq, esp_reset);
719
720 for (i = 0; i < ESP_MAX_DEVS; i++) {
721 drive_index = drive_get_index(IF_SCSI, 0, i);
722 if (drive_index == -1)
723 continue;
724 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
725 }
726
727 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
728 RAM_size);
729
730 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
731 boot_device, RAM_size, kernel_size, graphic_width,
732 graphic_height, graphic_depth, hwdef->nvram_machine_id,
733 "Sun4c");
734
735 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
736 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
737 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
738 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
739 }
740
741 enum {
742 ss2_id = 0,
743 ss5_id = 32,
744 vger_id,
745 lx_id,
746 ss4_id,
747 scls_id,
748 sbook_id,
749 ss10_id = 64,
750 ss20_id,
751 ss600mp_id,
752 ss1000_id = 96,
753 ss2000_id,
754 };
755
756 static const struct hwdef hwdefs[] = {
757 /* SS-5 */
758 {
759 .iommu_base = 0x10000000,
760 .tcx_base = 0x50000000,
761 .cs_base = 0x6c000000,
762 .slavio_base = 0x70000000,
763 .ms_kb_base = 0x71000000,
764 .serial_base = 0x71100000,
765 .nvram_base = 0x71200000,
766 .fd_base = 0x71400000,
767 .counter_base = 0x71d00000,
768 .intctl_base = 0x71e00000,
769 .idreg_base = 0x78000000,
770 .dma_base = 0x78400000,
771 .esp_base = 0x78800000,
772 .le_base = 0x78c00000,
773 .apc_base = 0x6a000000,
774 .aux1_base = 0x71900000,
775 .aux2_base = 0x71910000,
776 .ecc_base = -1,
777 .sun4c_intctl_base = -1,
778 .sun4c_counter_base = -1,
779 .vram_size = 0x00100000,
780 .nvram_size = 0x2000,
781 .esp_irq = 18,
782 .le_irq = 16,
783 .clock_irq = 7,
784 .clock1_irq = 19,
785 .ms_kb_irq = 14,
786 .ser_irq = 15,
787 .fd_irq = 22,
788 .me_irq = 30,
789 .cs_irq = 5,
790 .nvram_machine_id = 0x80,
791 .machine_id = ss5_id,
792 .iommu_version = 0x05000000,
793 .intbit_to_level = {
794 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
795 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
796 },
797 .max_mem = 0x10000000,
798 .default_cpu_model = "Fujitsu MB86904",
799 },
800 /* SS-10 */
801 {
802 .iommu_base = 0xfe0000000ULL,
803 .tcx_base = 0xe20000000ULL,
804 .cs_base = -1,
805 .slavio_base = 0xff0000000ULL,
806 .ms_kb_base = 0xff1000000ULL,
807 .serial_base = 0xff1100000ULL,
808 .nvram_base = 0xff1200000ULL,
809 .fd_base = 0xff1700000ULL,
810 .counter_base = 0xff1300000ULL,
811 .intctl_base = 0xff1400000ULL,
812 .idreg_base = 0xef0000000ULL,
813 .dma_base = 0xef0400000ULL,
814 .esp_base = 0xef0800000ULL,
815 .le_base = 0xef0c00000ULL,
816 .apc_base = 0xefa000000ULL, // XXX should not exist
817 .aux1_base = 0xff1800000ULL,
818 .aux2_base = 0xff1a01000ULL,
819 .ecc_base = 0xf00000000ULL,
820 .ecc_version = 0x10000000, // version 0, implementation 1
821 .sun4c_intctl_base = -1,
822 .sun4c_counter_base = -1,
823 .vram_size = 0x00100000,
824 .nvram_size = 0x2000,
825 .esp_irq = 18,
826 .le_irq = 16,
827 .clock_irq = 7,
828 .clock1_irq = 19,
829 .ms_kb_irq = 14,
830 .ser_irq = 15,
831 .fd_irq = 22,
832 .me_irq = 30,
833 .cs_irq = -1,
834 .ecc_irq = 28,
835 .nvram_machine_id = 0x72,
836 .machine_id = ss10_id,
837 .iommu_version = 0x03000000,
838 .intbit_to_level = {
839 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
840 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
841 },
842 .max_mem = 0xf00000000ULL,
843 .default_cpu_model = "TI SuperSparc II",
844 },
845 /* SS-600MP */
846 {
847 .iommu_base = 0xfe0000000ULL,
848 .tcx_base = 0xe20000000ULL,
849 .cs_base = -1,
850 .slavio_base = 0xff0000000ULL,
851 .ms_kb_base = 0xff1000000ULL,
852 .serial_base = 0xff1100000ULL,
853 .nvram_base = 0xff1200000ULL,
854 .fd_base = -1,
855 .counter_base = 0xff1300000ULL,
856 .intctl_base = 0xff1400000ULL,
857 .idreg_base = -1,
858 .dma_base = 0xef0081000ULL,
859 .esp_base = 0xef0080000ULL,
860 .le_base = 0xef0060000ULL,
861 .apc_base = 0xefa000000ULL, // XXX should not exist
862 .aux1_base = 0xff1800000ULL,
863 .aux2_base = 0xff1a01000ULL, // XXX should not exist
864 .ecc_base = 0xf00000000ULL,
865 .ecc_version = 0x00000000, // version 0, implementation 0
866 .sun4c_intctl_base = -1,
867 .sun4c_counter_base = -1,
868 .vram_size = 0x00100000,
869 .nvram_size = 0x2000,
870 .esp_irq = 18,
871 .le_irq = 16,
872 .clock_irq = 7,
873 .clock1_irq = 19,
874 .ms_kb_irq = 14,
875 .ser_irq = 15,
876 .fd_irq = 22,
877 .me_irq = 30,
878 .cs_irq = -1,
879 .ecc_irq = 28,
880 .nvram_machine_id = 0x71,
881 .machine_id = ss600mp_id,
882 .iommu_version = 0x01000000,
883 .intbit_to_level = {
884 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
885 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
886 },
887 .max_mem = 0xf00000000ULL,
888 .default_cpu_model = "TI SuperSparc II",
889 },
890 /* SS-20 */
891 {
892 .iommu_base = 0xfe0000000ULL,
893 .tcx_base = 0xe20000000ULL,
894 .cs_base = -1,
895 .slavio_base = 0xff0000000ULL,
896 .ms_kb_base = 0xff1000000ULL,
897 .serial_base = 0xff1100000ULL,
898 .nvram_base = 0xff1200000ULL,
899 .fd_base = 0xff1700000ULL,
900 .counter_base = 0xff1300000ULL,
901 .intctl_base = 0xff1400000ULL,
902 .idreg_base = 0xef0000000ULL,
903 .dma_base = 0xef0400000ULL,
904 .esp_base = 0xef0800000ULL,
905 .le_base = 0xef0c00000ULL,
906 .apc_base = 0xefa000000ULL, // XXX should not exist
907 .aux1_base = 0xff1800000ULL,
908 .aux2_base = 0xff1a01000ULL,
909 .ecc_base = 0xf00000000ULL,
910 .ecc_version = 0x20000000, // version 0, implementation 2
911 .sun4c_intctl_base = -1,
912 .sun4c_counter_base = -1,
913 .vram_size = 0x00100000,
914 .nvram_size = 0x2000,
915 .esp_irq = 18,
916 .le_irq = 16,
917 .clock_irq = 7,
918 .clock1_irq = 19,
919 .ms_kb_irq = 14,
920 .ser_irq = 15,
921 .fd_irq = 22,
922 .me_irq = 30,
923 .cs_irq = -1,
924 .ecc_irq = 28,
925 .nvram_machine_id = 0x72,
926 .machine_id = ss20_id,
927 .iommu_version = 0x13000000,
928 .intbit_to_level = {
929 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
930 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
931 },
932 .max_mem = 0xf00000000ULL,
933 .default_cpu_model = "TI SuperSparc II",
934 },
935 /* SS-2 */
936 {
937 .iommu_base = 0xf8000000,
938 .tcx_base = 0xfe000000,
939 .cs_base = -1,
940 .slavio_base = 0xf6000000,
941 .ms_kb_base = 0xf0000000,
942 .serial_base = 0xf1000000,
943 .nvram_base = 0xf2000000,
944 .fd_base = 0xf7200000,
945 .counter_base = -1,
946 .intctl_base = -1,
947 .dma_base = 0xf8400000,
948 .esp_base = 0xf8800000,
949 .le_base = 0xf8c00000,
950 .apc_base = -1,
951 .aux1_base = 0xf7400003,
952 .aux2_base = -1,
953 .sun4c_intctl_base = 0xf5000000,
954 .sun4c_counter_base = 0xf3000000,
955 .vram_size = 0x00100000,
956 .nvram_size = 0x800,
957 .esp_irq = 2,
958 .le_irq = 3,
959 .clock_irq = 5,
960 .clock1_irq = 7,
961 .ms_kb_irq = 1,
962 .ser_irq = 1,
963 .fd_irq = 1,
964 .me_irq = 1,
965 .cs_irq = -1,
966 .nvram_machine_id = 0x55,
967 .machine_id = ss2_id,
968 .max_mem = 0x10000000,
969 .default_cpu_model = "Cypress CY7C601",
970 },
971 /* Voyager */
972 {
973 .iommu_base = 0x10000000,
974 .tcx_base = 0x50000000,
975 .cs_base = -1,
976 .slavio_base = 0x70000000,
977 .ms_kb_base = 0x71000000,
978 .serial_base = 0x71100000,
979 .nvram_base = 0x71200000,
980 .fd_base = 0x71400000,
981 .counter_base = 0x71d00000,
982 .intctl_base = 0x71e00000,
983 .idreg_base = 0x78000000,
984 .dma_base = 0x78400000,
985 .esp_base = 0x78800000,
986 .le_base = 0x78c00000,
987 .apc_base = 0x71300000, // pmc
988 .aux1_base = 0x71900000,
989 .aux2_base = 0x71910000,
990 .ecc_base = -1,
991 .sun4c_intctl_base = -1,
992 .sun4c_counter_base = -1,
993 .vram_size = 0x00100000,
994 .nvram_size = 0x2000,
995 .esp_irq = 18,
996 .le_irq = 16,
997 .clock_irq = 7,
998 .clock1_irq = 19,
999 .ms_kb_irq = 14,
1000 .ser_irq = 15,
1001 .fd_irq = 22,
1002 .me_irq = 30,
1003 .cs_irq = -1,
1004 .nvram_machine_id = 0x80,
1005 .machine_id = vger_id,
1006 .iommu_version = 0x05000000,
1007 .intbit_to_level = {
1008 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1009 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1010 },
1011 .max_mem = 0x10000000,
1012 .default_cpu_model = "Fujitsu MB86904",
1013 },
1014 /* LX */
1015 {
1016 .iommu_base = 0x10000000,
1017 .tcx_base = 0x50000000,
1018 .cs_base = -1,
1019 .slavio_base = 0x70000000,
1020 .ms_kb_base = 0x71000000,
1021 .serial_base = 0x71100000,
1022 .nvram_base = 0x71200000,
1023 .fd_base = 0x71400000,
1024 .counter_base = 0x71d00000,
1025 .intctl_base = 0x71e00000,
1026 .idreg_base = 0x78000000,
1027 .dma_base = 0x78400000,
1028 .esp_base = 0x78800000,
1029 .le_base = 0x78c00000,
1030 .apc_base = -1,
1031 .aux1_base = 0x71900000,
1032 .aux2_base = 0x71910000,
1033 .ecc_base = -1,
1034 .sun4c_intctl_base = -1,
1035 .sun4c_counter_base = -1,
1036 .vram_size = 0x00100000,
1037 .nvram_size = 0x2000,
1038 .esp_irq = 18,
1039 .le_irq = 16,
1040 .clock_irq = 7,
1041 .clock1_irq = 19,
1042 .ms_kb_irq = 14,
1043 .ser_irq = 15,
1044 .fd_irq = 22,
1045 .me_irq = 30,
1046 .cs_irq = -1,
1047 .nvram_machine_id = 0x80,
1048 .machine_id = lx_id,
1049 .iommu_version = 0x04000000,
1050 .intbit_to_level = {
1051 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1052 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1053 },
1054 .max_mem = 0x10000000,
1055 .default_cpu_model = "TI MicroSparc I",
1056 },
1057 /* SS-4 */
1058 {
1059 .iommu_base = 0x10000000,
1060 .tcx_base = 0x50000000,
1061 .cs_base = 0x6c000000,
1062 .slavio_base = 0x70000000,
1063 .ms_kb_base = 0x71000000,
1064 .serial_base = 0x71100000,
1065 .nvram_base = 0x71200000,
1066 .fd_base = 0x71400000,
1067 .counter_base = 0x71d00000,
1068 .intctl_base = 0x71e00000,
1069 .idreg_base = 0x78000000,
1070 .dma_base = 0x78400000,
1071 .esp_base = 0x78800000,
1072 .le_base = 0x78c00000,
1073 .apc_base = 0x6a000000,
1074 .aux1_base = 0x71900000,
1075 .aux2_base = 0x71910000,
1076 .ecc_base = -1,
1077 .sun4c_intctl_base = -1,
1078 .sun4c_counter_base = -1,
1079 .vram_size = 0x00100000,
1080 .nvram_size = 0x2000,
1081 .esp_irq = 18,
1082 .le_irq = 16,
1083 .clock_irq = 7,
1084 .clock1_irq = 19,
1085 .ms_kb_irq = 14,
1086 .ser_irq = 15,
1087 .fd_irq = 22,
1088 .me_irq = 30,
1089 .cs_irq = 5,
1090 .nvram_machine_id = 0x80,
1091 .machine_id = ss4_id,
1092 .iommu_version = 0x05000000,
1093 .intbit_to_level = {
1094 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1095 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1096 },
1097 .max_mem = 0x10000000,
1098 .default_cpu_model = "Fujitsu MB86904",
1099 },
1100 /* SPARCClassic */
1101 {
1102 .iommu_base = 0x10000000,
1103 .tcx_base = 0x50000000,
1104 .cs_base = -1,
1105 .slavio_base = 0x70000000,
1106 .ms_kb_base = 0x71000000,
1107 .serial_base = 0x71100000,
1108 .nvram_base = 0x71200000,
1109 .fd_base = 0x71400000,
1110 .counter_base = 0x71d00000,
1111 .intctl_base = 0x71e00000,
1112 .idreg_base = 0x78000000,
1113 .dma_base = 0x78400000,
1114 .esp_base = 0x78800000,
1115 .le_base = 0x78c00000,
1116 .apc_base = 0x6a000000,
1117 .aux1_base = 0x71900000,
1118 .aux2_base = 0x71910000,
1119 .ecc_base = -1,
1120 .sun4c_intctl_base = -1,
1121 .sun4c_counter_base = -1,
1122 .vram_size = 0x00100000,
1123 .nvram_size = 0x2000,
1124 .esp_irq = 18,
1125 .le_irq = 16,
1126 .clock_irq = 7,
1127 .clock1_irq = 19,
1128 .ms_kb_irq = 14,
1129 .ser_irq = 15,
1130 .fd_irq = 22,
1131 .me_irq = 30,
1132 .cs_irq = -1,
1133 .nvram_machine_id = 0x80,
1134 .machine_id = scls_id,
1135 .iommu_version = 0x05000000,
1136 .intbit_to_level = {
1137 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1138 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1139 },
1140 .max_mem = 0x10000000,
1141 .default_cpu_model = "TI MicroSparc I",
1142 },
1143 /* SPARCbook */
1144 {
1145 .iommu_base = 0x10000000,
1146 .tcx_base = 0x50000000, // XXX
1147 .cs_base = -1,
1148 .slavio_base = 0x70000000,
1149 .ms_kb_base = 0x71000000,
1150 .serial_base = 0x71100000,
1151 .nvram_base = 0x71200000,
1152 .fd_base = 0x71400000,
1153 .counter_base = 0x71d00000,
1154 .intctl_base = 0x71e00000,
1155 .idreg_base = 0x78000000,
1156 .dma_base = 0x78400000,
1157 .esp_base = 0x78800000,
1158 .le_base = 0x78c00000,
1159 .apc_base = 0x6a000000,
1160 .aux1_base = 0x71900000,
1161 .aux2_base = 0x71910000,
1162 .ecc_base = -1,
1163 .sun4c_intctl_base = -1,
1164 .sun4c_counter_base = -1,
1165 .vram_size = 0x00100000,
1166 .nvram_size = 0x2000,
1167 .esp_irq = 18,
1168 .le_irq = 16,
1169 .clock_irq = 7,
1170 .clock1_irq = 19,
1171 .ms_kb_irq = 14,
1172 .ser_irq = 15,
1173 .fd_irq = 22,
1174 .me_irq = 30,
1175 .cs_irq = -1,
1176 .nvram_machine_id = 0x80,
1177 .machine_id = sbook_id,
1178 .iommu_version = 0x05000000,
1179 .intbit_to_level = {
1180 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1181 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1182 },
1183 .max_mem = 0x10000000,
1184 .default_cpu_model = "TI MicroSparc I",
1185 },
1186 };
1187
1188 /* SPARCstation 5 hardware initialisation */
1189 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1190 const char *boot_device, DisplayState *ds,
1191 const char *kernel_filename, const char *kernel_cmdline,
1192 const char *initrd_filename, const char *cpu_model)
1193 {
1194 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1195 kernel_cmdline, initrd_filename, cpu_model);
1196 }
1197
1198 /* SPARCstation 10 hardware initialisation */
1199 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1200 const char *boot_device, DisplayState *ds,
1201 const char *kernel_filename, const char *kernel_cmdline,
1202 const char *initrd_filename, const char *cpu_model)
1203 {
1204 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1205 kernel_cmdline, initrd_filename, cpu_model);
1206 }
1207
1208 /* SPARCserver 600MP hardware initialisation */
1209 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1210 const char *boot_device, DisplayState *ds,
1211 const char *kernel_filename,
1212 const char *kernel_cmdline,
1213 const char *initrd_filename, const char *cpu_model)
1214 {
1215 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1216 kernel_cmdline, initrd_filename, cpu_model);
1217 }
1218
1219 /* SPARCstation 20 hardware initialisation */
1220 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1221 const char *boot_device, DisplayState *ds,
1222 const char *kernel_filename, const char *kernel_cmdline,
1223 const char *initrd_filename, const char *cpu_model)
1224 {
1225 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1226 kernel_cmdline, initrd_filename, cpu_model);
1227 }
1228
1229 /* SPARCstation 2 hardware initialisation */
1230 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1231 const char *boot_device, DisplayState *ds,
1232 const char *kernel_filename, const char *kernel_cmdline,
1233 const char *initrd_filename, const char *cpu_model)
1234 {
1235 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1236 kernel_cmdline, initrd_filename, cpu_model);
1237 }
1238
1239 /* SPARCstation Voyager hardware initialisation */
1240 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1241 const char *boot_device, DisplayState *ds,
1242 const char *kernel_filename, const char *kernel_cmdline,
1243 const char *initrd_filename, const char *cpu_model)
1244 {
1245 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1246 kernel_cmdline, initrd_filename, cpu_model);
1247 }
1248
1249 /* SPARCstation LX hardware initialisation */
1250 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1251 const char *boot_device, DisplayState *ds,
1252 const char *kernel_filename, const char *kernel_cmdline,
1253 const char *initrd_filename, const char *cpu_model)
1254 {
1255 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1256 kernel_cmdline, initrd_filename, cpu_model);
1257 }
1258
1259 /* SPARCstation 4 hardware initialisation */
1260 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1261 const char *boot_device, DisplayState *ds,
1262 const char *kernel_filename, const char *kernel_cmdline,
1263 const char *initrd_filename, const char *cpu_model)
1264 {
1265 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1266 kernel_cmdline, initrd_filename, cpu_model);
1267 }
1268
1269 /* SPARCClassic hardware initialisation */
1270 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1271 const char *boot_device, DisplayState *ds,
1272 const char *kernel_filename, const char *kernel_cmdline,
1273 const char *initrd_filename, const char *cpu_model)
1274 {
1275 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1276 kernel_cmdline, initrd_filename, cpu_model);
1277 }
1278
1279 /* SPARCbook hardware initialisation */
1280 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1281 const char *boot_device, DisplayState *ds,
1282 const char *kernel_filename, const char *kernel_cmdline,
1283 const char *initrd_filename, const char *cpu_model)
1284 {
1285 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1286 kernel_cmdline, initrd_filename, cpu_model);
1287 }
1288
1289 QEMUMachine ss5_machine = {
1290 .name = "SS-5",
1291 .desc = "Sun4m platform, SPARCstation 5",
1292 .init = ss5_init,
1293 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1294 .nodisk_ok = 1,
1295 };
1296
1297 QEMUMachine ss10_machine = {
1298 .name = "SS-10",
1299 .desc = "Sun4m platform, SPARCstation 10",
1300 .init = ss10_init,
1301 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1302 .nodisk_ok = 1,
1303 };
1304
1305 QEMUMachine ss600mp_machine = {
1306 .name = "SS-600MP",
1307 .desc = "Sun4m platform, SPARCserver 600MP",
1308 .init = ss600mp_init,
1309 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1310 .nodisk_ok = 1,
1311 };
1312
1313 QEMUMachine ss20_machine = {
1314 .name = "SS-20",
1315 .desc = "Sun4m platform, SPARCstation 20",
1316 .init = ss20_init,
1317 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1318 .nodisk_ok = 1,
1319 };
1320
1321 QEMUMachine ss2_machine = {
1322 .name = "SS-2",
1323 .desc = "Sun4c platform, SPARCstation 2",
1324 .init = ss2_init,
1325 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1326 .nodisk_ok = 1,
1327 };
1328
1329 QEMUMachine voyager_machine = {
1330 .name = "Voyager",
1331 .desc = "Sun4m platform, SPARCstation Voyager",
1332 .init = vger_init,
1333 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1334 .nodisk_ok = 1,
1335 };
1336
1337 QEMUMachine ss_lx_machine = {
1338 .name = "LX",
1339 .desc = "Sun4m platform, SPARCstation LX",
1340 .init = ss_lx_init,
1341 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1342 .nodisk_ok = 1,
1343 };
1344
1345 QEMUMachine ss4_machine = {
1346 .name = "SS-4",
1347 .desc = "Sun4m platform, SPARCstation 4",
1348 .init = ss4_init,
1349 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1350 .nodisk_ok = 1,
1351 };
1352
1353 QEMUMachine scls_machine = {
1354 .name = "SPARCClassic",
1355 .desc = "Sun4m platform, SPARCClassic",
1356 .init = scls_init,
1357 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1358 .nodisk_ok = 1,
1359 };
1360
1361 QEMUMachine sbook_machine = {
1362 .name = "SPARCbook",
1363 .desc = "Sun4m platform, SPARCbook",
1364 .init = sbook_init,
1365 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1366 .nodisk_ok = 1,
1367 };
1368
1369 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1370 /* SS-1000 */
1371 {
1372 .iounit_bases = {
1373 0xfe0200000ULL,
1374 0xfe1200000ULL,
1375 0xfe2200000ULL,
1376 0xfe3200000ULL,
1377 -1,
1378 },
1379 .tcx_base = 0x820000000ULL,
1380 .slavio_base = 0xf00000000ULL,
1381 .ms_kb_base = 0xf00240000ULL,
1382 .serial_base = 0xf00200000ULL,
1383 .nvram_base = 0xf00280000ULL,
1384 .counter_base = 0xf00300000ULL,
1385 .espdma_base = 0x800081000ULL,
1386 .esp_base = 0x800080000ULL,
1387 .ledma_base = 0x800040000ULL,
1388 .le_base = 0x800060000ULL,
1389 .sbi_base = 0xf02800000ULL,
1390 .vram_size = 0x00100000,
1391 .nvram_size = 0x2000,
1392 .esp_irq = 3,
1393 .le_irq = 4,
1394 .clock_irq = 14,
1395 .clock1_irq = 10,
1396 .ms_kb_irq = 12,
1397 .ser_irq = 12,
1398 .nvram_machine_id = 0x80,
1399 .machine_id = ss1000_id,
1400 .iounit_version = 0x03000000,
1401 .max_mem = 0xf00000000ULL,
1402 .default_cpu_model = "TI SuperSparc II",
1403 },
1404 /* SS-2000 */
1405 {
1406 .iounit_bases = {
1407 0xfe0200000ULL,
1408 0xfe1200000ULL,
1409 0xfe2200000ULL,
1410 0xfe3200000ULL,
1411 0xfe4200000ULL,
1412 },
1413 .tcx_base = 0x820000000ULL,
1414 .slavio_base = 0xf00000000ULL,
1415 .ms_kb_base = 0xf00240000ULL,
1416 .serial_base = 0xf00200000ULL,
1417 .nvram_base = 0xf00280000ULL,
1418 .counter_base = 0xf00300000ULL,
1419 .espdma_base = 0x800081000ULL,
1420 .esp_base = 0x800080000ULL,
1421 .ledma_base = 0x800040000ULL,
1422 .le_base = 0x800060000ULL,
1423 .sbi_base = 0xf02800000ULL,
1424 .vram_size = 0x00100000,
1425 .nvram_size = 0x2000,
1426 .esp_irq = 3,
1427 .le_irq = 4,
1428 .clock_irq = 14,
1429 .clock1_irq = 10,
1430 .ms_kb_irq = 12,
1431 .ser_irq = 12,
1432 .nvram_machine_id = 0x80,
1433 .machine_id = ss2000_id,
1434 .iounit_version = 0x03000000,
1435 .max_mem = 0xf00000000ULL,
1436 .default_cpu_model = "TI SuperSparc II",
1437 },
1438 };
1439
1440 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1441 const char *boot_device,
1442 DisplayState *ds, const char *kernel_filename,
1443 const char *kernel_cmdline,
1444 const char *initrd_filename, const char *cpu_model)
1445 {
1446 CPUState *env, *envs[MAX_CPUS];
1447 unsigned int i;
1448 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1449 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1450 *espdma_irq, *ledma_irq;
1451 qemu_irq *esp_reset, *le_reset;
1452 unsigned long prom_offset, kernel_size;
1453 int ret;
1454 char buf[1024];
1455 int drive_index;
1456 void *fw_cfg;
1457
1458 /* init CPUs */
1459 if (!cpu_model)
1460 cpu_model = hwdef->default_cpu_model;
1461
1462 for (i = 0; i < smp_cpus; i++) {
1463 env = cpu_init(cpu_model);
1464 if (!env) {
1465 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1466 exit(1);
1467 }
1468 cpu_sparc_set_id(env, i);
1469 envs[i] = env;
1470 if (i == 0) {
1471 qemu_register_reset(main_cpu_reset, env);
1472 } else {
1473 qemu_register_reset(secondary_cpu_reset, env);
1474 env->halted = 1;
1475 }
1476 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1477 env->prom_addr = hwdef->slavio_base;
1478 }
1479
1480 for (i = smp_cpus; i < MAX_CPUS; i++)
1481 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1482
1483 /* allocate RAM */
1484 if ((uint64_t)RAM_size > hwdef->max_mem) {
1485 fprintf(stderr,
1486 "qemu: Too much memory for this machine: %d, maximum %d\n",
1487 (unsigned int)(RAM_size / (1024 * 1024)),
1488 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1489 exit(1);
1490 }
1491 cpu_register_physical_memory(0, RAM_size, 0);
1492
1493 /* load boot prom */
1494 prom_offset = RAM_size + hwdef->vram_size;
1495 cpu_register_physical_memory(hwdef->slavio_base,
1496 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1497 TARGET_PAGE_MASK,
1498 prom_offset | IO_MEM_ROM);
1499
1500 if (bios_name == NULL)
1501 bios_name = PROM_FILENAME;
1502 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1503 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1504 if (ret < 0 || ret > PROM_SIZE_MAX)
1505 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1506 if (ret < 0 || ret > PROM_SIZE_MAX) {
1507 fprintf(stderr, "qemu: could not load prom '%s'\n",
1508 buf);
1509 exit(1);
1510 }
1511
1512 /* set up devices */
1513 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1514
1515 for (i = 0; i < MAX_IOUNITS; i++)
1516 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1517 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1518 hwdef->iounit_version,
1519 sbi_irq[hwdef->me_irq]);
1520
1521 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1522 iounits[0], &espdma_irq, &esp_reset);
1523
1524 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1525 iounits[0], &ledma_irq, &le_reset);
1526
1527 if (graphic_depth != 8 && graphic_depth != 24) {
1528 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1529 exit (1);
1530 }
1531 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1532 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1533
1534 if (nd_table[0].model == NULL
1535 || strcmp(nd_table[0].model, "lance") == 0) {
1536 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1537 } else if (strcmp(nd_table[0].model, "?") == 0) {
1538 fprintf(stderr, "qemu: Supported NICs: lance\n");
1539 exit (1);
1540 } else {
1541 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1542 exit (1);
1543 }
1544
1545 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1546 hwdef->nvram_size, 8);
1547
1548 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1549 sbi_cpu_irq, smp_cpus);
1550
1551 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1552 nographic);
1553 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1554 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1555 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1556 serial_hds[1], serial_hds[0]);
1557
1558 if (drive_get_max_bus(IF_SCSI) > 0) {
1559 fprintf(stderr, "qemu: too many SCSI bus\n");
1560 exit(1);
1561 }
1562
1563 main_esp = esp_init(hwdef->esp_base, 2,
1564 espdma_memory_read, espdma_memory_write,
1565 espdma, *espdma_irq, esp_reset);
1566
1567 for (i = 0; i < ESP_MAX_DEVS; i++) {
1568 drive_index = drive_get_index(IF_SCSI, 0, i);
1569 if (drive_index == -1)
1570 continue;
1571 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1572 }
1573
1574 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1575 RAM_size);
1576
1577 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1578 boot_device, RAM_size, kernel_size, graphic_width,
1579 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1580 "Sun4d");
1581
1582 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1583 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1584 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1585 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1586 }
1587
1588 /* SPARCserver 1000 hardware initialisation */
1589 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1590 const char *boot_device, DisplayState *ds,
1591 const char *kernel_filename, const char *kernel_cmdline,
1592 const char *initrd_filename, const char *cpu_model)
1593 {
1594 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1595 kernel_cmdline, initrd_filename, cpu_model);
1596 }
1597
1598 /* SPARCcenter 2000 hardware initialisation */
1599 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1600 const char *boot_device, DisplayState *ds,
1601 const char *kernel_filename, const char *kernel_cmdline,
1602 const char *initrd_filename, const char *cpu_model)
1603 {
1604 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1605 kernel_cmdline, initrd_filename, cpu_model);
1606 }
1607
1608 QEMUMachine ss1000_machine = {
1609 .name = "SS-1000",
1610 .desc = "Sun4d platform, SPARCserver 1000",
1611 .init = ss1000_init,
1612 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1613 .nodisk_ok = 1,
1614 };
1615
1616 QEMUMachine ss2000_machine = {
1617 .name = "SS-2000",
1618 .desc = "Sun4d platform, SPARCcenter 2000",
1619 .init = ss2000_init,
1620 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1621 .nodisk_ok = 1,
1622 };
Samsung s3c2440 and arm920t support for the mini2440 dev board