2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
27 #include "host-utils.h"
30 //#define PPC_DUMP_CPU
31 //#define PPC_DEBUG_SPR
32 //#define PPC_DUMP_SPR_ACCESSES
33 #if defined(CONFIG_USER_ONLY)
34 #define TODO_USER_ONLY 1
43 powerpc_mmu_t mmu_model
;
44 powerpc_excp_t excp_model
;
45 powerpc_input_t bus_model
;
48 void (*init_proc
)(CPUPPCState
*env
);
49 int (*check_pow
)(CPUPPCState
*env
);
52 /* For user-mode emulation, we don't emulate any IRQ controller */
53 #if defined(CONFIG_USER_ONLY)
54 #define PPC_IRQ_INIT_FN(name) \
55 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
59 #define PPC_IRQ_INIT_FN(name) \
60 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
68 * do nothing but store/retrieve spr value
70 static void spr_read_generic (void *opaque
, int gprn
, int sprn
)
72 gen_load_spr(cpu_gpr
[gprn
], sprn
);
73 #ifdef PPC_DUMP_SPR_ACCESSES
75 TCGv t0
= tcg_const_i32(sprn
);
76 gen_helper_load_dump_spr(t0
);
77 tcg_temp_free_i32(t0
);
82 static void spr_write_generic (void *opaque
, int sprn
, int gprn
)
84 gen_store_spr(sprn
, cpu_gpr
[gprn
]);
85 #ifdef PPC_DUMP_SPR_ACCESSES
87 TCGv t0
= tcg_const_i32(sprn
);
88 gen_helper_store_dump_spr(t0
);
89 tcg_temp_free_i32(t0
);
94 #if !defined(CONFIG_USER_ONLY)
95 static void spr_write_clear (void *opaque
, int sprn
, int gprn
)
97 TCGv t0
= tcg_temp_new();
98 TCGv t1
= tcg_temp_new();
99 gen_load_spr(t0
, sprn
);
100 tcg_gen_neg_tl(t1
, cpu_gpr
[gprn
]);
101 tcg_gen_and_tl(t0
, t0
, t1
);
102 gen_store_spr(sprn
, t0
);
108 /* SPR common to all PowerPC */
110 static void spr_read_xer (void *opaque
, int gprn
, int sprn
)
112 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_xer
);
115 static void spr_write_xer (void *opaque
, int sprn
, int gprn
)
117 tcg_gen_mov_tl(cpu_xer
, cpu_gpr
[gprn
]);
121 static void spr_read_lr (void *opaque
, int gprn
, int sprn
)
123 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_lr
);
126 static void spr_write_lr (void *opaque
, int sprn
, int gprn
)
128 tcg_gen_mov_tl(cpu_lr
, cpu_gpr
[gprn
]);
132 static void spr_read_ctr (void *opaque
, int gprn
, int sprn
)
134 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_ctr
);
137 static void spr_write_ctr (void *opaque
, int sprn
, int gprn
)
139 tcg_gen_mov_tl(cpu_ctr
, cpu_gpr
[gprn
]);
142 /* User read access to SPR */
148 static void spr_read_ureg (void *opaque
, int gprn
, int sprn
)
150 gen_load_spr(cpu_gpr
[gprn
], sprn
+ 0x10);
153 /* SPR common to all non-embedded PowerPC */
155 #if !defined(CONFIG_USER_ONLY)
156 static void spr_read_decr (void *opaque
, int gprn
, int sprn
)
158 gen_helper_load_decr(cpu_gpr
[gprn
]);
161 static void spr_write_decr (void *opaque
, int sprn
, int gprn
)
163 gen_helper_store_decr(cpu_gpr
[gprn
]);
167 /* SPR common to all non-embedded PowerPC, except 601 */
169 static void spr_read_tbl (void *opaque
, int gprn
, int sprn
)
171 gen_helper_load_tbl(cpu_gpr
[gprn
]);
174 static void spr_read_tbu (void *opaque
, int gprn
, int sprn
)
176 gen_helper_load_tbu(cpu_gpr
[gprn
]);
179 __attribute__ (( unused
))
180 static void spr_read_atbl (void *opaque
, int gprn
, int sprn
)
182 gen_helper_load_atbl(cpu_gpr
[gprn
]);
185 __attribute__ (( unused
))
186 static void spr_read_atbu (void *opaque
, int gprn
, int sprn
)
188 gen_helper_load_atbu(cpu_gpr
[gprn
]);
191 #if !defined(CONFIG_USER_ONLY)
192 static void spr_write_tbl (void *opaque
, int sprn
, int gprn
)
194 gen_helper_store_tbl(cpu_gpr
[gprn
]);
197 static void spr_write_tbu (void *opaque
, int sprn
, int gprn
)
199 gen_helper_store_tbu(cpu_gpr
[gprn
]);
202 __attribute__ (( unused
))
203 static void spr_write_atbl (void *opaque
, int sprn
, int gprn
)
205 gen_helper_store_atbl(cpu_gpr
[gprn
]);
208 __attribute__ (( unused
))
209 static void spr_write_atbu (void *opaque
, int sprn
, int gprn
)
211 gen_helper_store_atbu(cpu_gpr
[gprn
]);
215 #if !defined(CONFIG_USER_ONLY)
216 /* IBAT0U...IBAT0U */
217 /* IBAT0L...IBAT7L */
218 static void spr_read_ibat (void *opaque
, int gprn
, int sprn
)
220 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
223 static void spr_read_ibat_h (void *opaque
, int gprn
, int sprn
)
225 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT4U
) / 2]));
228 static void spr_write_ibatu (void *opaque
, int sprn
, int gprn
)
230 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
231 gen_helper_store_ibatu(t0
, cpu_gpr
[gprn
]);
232 tcg_temp_free_i32(t0
);
235 static void spr_write_ibatu_h (void *opaque
, int sprn
, int gprn
)
237 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT4U
) / 2);
238 gen_helper_store_ibatu(t0
, cpu_gpr
[gprn
]);
239 tcg_temp_free_i32(t0
);
242 static void spr_write_ibatl (void *opaque
, int sprn
, int gprn
)
244 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0L
) / 2);
245 gen_helper_store_ibatl(t0
, cpu_gpr
[gprn
]);
246 tcg_temp_free_i32(t0
);
249 static void spr_write_ibatl_h (void *opaque
, int sprn
, int gprn
)
251 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT4L
) / 2);
252 gen_helper_store_ibatl(t0
, cpu_gpr
[gprn
]);
253 tcg_temp_free_i32(t0
);
256 /* DBAT0U...DBAT7U */
257 /* DBAT0L...DBAT7L */
258 static void spr_read_dbat (void *opaque
, int gprn
, int sprn
)
260 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, DBAT
[sprn
& 1][(sprn
- SPR_DBAT0U
) / 2]));
263 static void spr_read_dbat_h (void *opaque
, int gprn
, int sprn
)
265 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, DBAT
[sprn
& 1][((sprn
- SPR_DBAT4U
) / 2) + 4]));
268 static void spr_write_dbatu (void *opaque
, int sprn
, int gprn
)
270 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0U
) / 2);
271 gen_helper_store_dbatu(t0
, cpu_gpr
[gprn
]);
272 tcg_temp_free_i32(t0
);
275 static void spr_write_dbatu_h (void *opaque
, int sprn
, int gprn
)
277 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4U
) / 2) + 4);
278 gen_helper_store_dbatu(t0
, cpu_gpr
[gprn
]);
279 tcg_temp_free_i32(t0
);
282 static void spr_write_dbatl (void *opaque
, int sprn
, int gprn
)
284 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0L
) / 2);
285 gen_helper_store_dbatl(t0
, cpu_gpr
[gprn
]);
286 tcg_temp_free_i32(t0
);
289 static void spr_write_dbatl_h (void *opaque
, int sprn
, int gprn
)
291 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4L
) / 2) + 4);
292 gen_helper_store_dbatl(t0
, cpu_gpr
[gprn
]);
293 tcg_temp_free_i32(t0
);
297 static void spr_read_sdr1 (void *opaque
, int gprn
, int sprn
)
299 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, sdr1
));
302 static void spr_write_sdr1 (void *opaque
, int sprn
, int gprn
)
304 gen_helper_store_sdr1(cpu_gpr
[gprn
]);
307 /* 64 bits PowerPC specific SPRs */
309 #if defined(TARGET_PPC64)
310 static void spr_read_asr (void *opaque
, int gprn
, int sprn
)
312 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, asr
));
315 static void spr_write_asr (void *opaque
, int sprn
, int gprn
)
317 gen_helper_store_asr(cpu_gpr
[gprn
]);
322 /* PowerPC 601 specific registers */
324 static void spr_read_601_rtcl (void *opaque
, int gprn
, int sprn
)
326 gen_helper_load_601_rtcl(cpu_gpr
[gprn
]);
329 static void spr_read_601_rtcu (void *opaque
, int gprn
, int sprn
)
331 gen_helper_load_601_rtcu(cpu_gpr
[gprn
]);
334 #if !defined(CONFIG_USER_ONLY)
335 static void spr_write_601_rtcu (void *opaque
, int sprn
, int gprn
)
337 gen_helper_store_601_rtcu(cpu_gpr
[gprn
]);
340 static void spr_write_601_rtcl (void *opaque
, int sprn
, int gprn
)
342 gen_helper_store_601_rtcl(cpu_gpr
[gprn
]);
345 static void spr_write_hid0_601 (void *opaque
, int sprn
, int gprn
)
347 DisasContext
*ctx
= opaque
;
349 gen_helper_store_hid0_601(cpu_gpr
[gprn
]);
350 /* Must stop the translation as endianness may have changed */
351 gen_stop_exception(ctx
);
356 #if !defined(CONFIG_USER_ONLY)
357 static void spr_read_601_ubat (void *opaque
, int gprn
, int sprn
)
359 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
362 static void spr_write_601_ubatu (void *opaque
, int sprn
, int gprn
)
364 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
365 gen_helper_store_601_batl(t0
, cpu_gpr
[gprn
]);
366 tcg_temp_free_i32(t0
);
369 static void spr_write_601_ubatl (void *opaque
, int sprn
, int gprn
)
371 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
372 gen_helper_store_601_batu(t0
, cpu_gpr
[gprn
]);
373 tcg_temp_free_i32(t0
);
377 /* PowerPC 40x specific registers */
378 #if !defined(CONFIG_USER_ONLY)
379 static void spr_read_40x_pit (void *opaque
, int gprn
, int sprn
)
381 gen_helper_load_40x_pit(cpu_gpr
[gprn
]);
384 static void spr_write_40x_pit (void *opaque
, int sprn
, int gprn
)
386 gen_helper_store_40x_pit(cpu_gpr
[gprn
]);
389 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
, int gprn
)
391 DisasContext
*ctx
= opaque
;
393 gen_helper_store_40x_dbcr0(cpu_gpr
[gprn
]);
394 /* We must stop translation as we may have rebooted */
395 gen_stop_exception(ctx
);
398 static void spr_write_40x_sler (void *opaque
, int sprn
, int gprn
)
400 gen_helper_store_40x_sler(cpu_gpr
[gprn
]);
403 static void spr_write_booke_tcr (void *opaque
, int sprn
, int gprn
)
405 gen_helper_store_booke_tcr(cpu_gpr
[gprn
]);
408 static void spr_write_booke_tsr (void *opaque
, int sprn
, int gprn
)
410 gen_helper_store_booke_tsr(cpu_gpr
[gprn
]);
414 /* PowerPC 403 specific registers */
415 /* PBL1 / PBU1 / PBL2 / PBU2 */
416 #if !defined(CONFIG_USER_ONLY)
417 static void spr_read_403_pbr (void *opaque
, int gprn
, int sprn
)
419 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUState
, pb
[sprn
- SPR_403_PBL1
]));
422 static void spr_write_403_pbr (void *opaque
, int sprn
, int gprn
)
424 TCGv_i32 t0
= tcg_const_i32(sprn
- SPR_403_PBL1
);
425 gen_helper_store_403_pbr(t0
, cpu_gpr
[gprn
]);
426 tcg_temp_free_i32(t0
);
429 static void spr_write_pir (void *opaque
, int sprn
, int gprn
)
431 TCGv t0
= tcg_temp_new();
432 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0xF);
433 gen_store_spr(SPR_PIR
, t0
);
438 #if !defined(CONFIG_USER_ONLY)
439 /* Callback used to write the exception vector base */
440 static void spr_write_excp_prefix (void *opaque
, int sprn
, int gprn
)
442 TCGv t0
= tcg_temp_new();
443 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivpr_mask
));
444 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
445 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_prefix
));
446 gen_store_spr(sprn
, t0
);
449 static void spr_write_excp_vector (void *opaque
, int sprn
, int gprn
)
451 DisasContext
*ctx
= opaque
;
453 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
454 TCGv t0
= tcg_temp_new();
455 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivor_mask
));
456 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
457 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_vectors
[sprn
- SPR_BOOKE_IVOR0
]));
458 gen_store_spr(sprn
, t0
);
460 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
461 TCGv t0
= tcg_temp_new();
462 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, ivor_mask
));
463 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
464 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, excp_vectors
[sprn
- SPR_BOOKE_IVOR32
+ 32]));
465 gen_store_spr(sprn
, t0
);
468 printf("Trying to write an unknown exception vector %d %03x\n",
470 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
475 static inline void vscr_init (CPUPPCState
*env
, uint32_t val
)
478 /* Altivec always uses round-to-nearest */
479 set_float_rounding_mode(float_round_nearest_even
, &env
->vec_status
);
480 set_flush_to_zero(vscr_nj
, &env
->vec_status
);
483 #if defined(CONFIG_USER_ONLY)
484 #define spr_register(env, num, name, uea_read, uea_write, \
485 oea_read, oea_write, initial_value) \
487 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
489 static inline void _spr_register (CPUPPCState
*env
, int num
,
491 void (*uea_read
)(void *opaque
, int gprn
, int sprn
),
492 void (*uea_write
)(void *opaque
, int sprn
, int gprn
),
493 target_ulong initial_value
)
495 static inline void spr_register (CPUPPCState
*env
, int num
,
497 void (*uea_read
)(void *opaque
, int gprn
, int sprn
),
498 void (*uea_write
)(void *opaque
, int sprn
, int gprn
),
499 void (*oea_read
)(void *opaque
, int gprn
, int sprn
),
500 void (*oea_write
)(void *opaque
, int sprn
, int gprn
),
501 target_ulong initial_value
)
506 spr
= &env
->spr_cb
[num
];
507 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
508 #if !defined(CONFIG_USER_ONLY)
509 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
511 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
512 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
515 #if defined(PPC_DEBUG_SPR)
516 printf("*** register spr %d (%03x) %s val " ADDRX
"\n", num
, num
, name
,
520 spr
->uea_read
= uea_read
;
521 spr
->uea_write
= uea_write
;
522 #if !defined(CONFIG_USER_ONLY)
523 spr
->oea_read
= oea_read
;
524 spr
->oea_write
= oea_write
;
526 env
->spr
[num
] = initial_value
;
529 /* Generic PowerPC SPRs */
530 static void gen_spr_generic (CPUPPCState
*env
)
532 /* Integer processing */
533 spr_register(env
, SPR_XER
, "XER",
534 &spr_read_xer
, &spr_write_xer
,
535 &spr_read_xer
, &spr_write_xer
,
538 spr_register(env
, SPR_LR
, "LR",
539 &spr_read_lr
, &spr_write_lr
,
540 &spr_read_lr
, &spr_write_lr
,
542 spr_register(env
, SPR_CTR
, "CTR",
543 &spr_read_ctr
, &spr_write_ctr
,
544 &spr_read_ctr
, &spr_write_ctr
,
546 /* Interrupt processing */
547 spr_register(env
, SPR_SRR0
, "SRR0",
548 SPR_NOACCESS
, SPR_NOACCESS
,
549 &spr_read_generic
, &spr_write_generic
,
551 spr_register(env
, SPR_SRR1
, "SRR1",
552 SPR_NOACCESS
, SPR_NOACCESS
,
553 &spr_read_generic
, &spr_write_generic
,
555 /* Processor control */
556 spr_register(env
, SPR_SPRG0
, "SPRG0",
557 SPR_NOACCESS
, SPR_NOACCESS
,
558 &spr_read_generic
, &spr_write_generic
,
560 spr_register(env
, SPR_SPRG1
, "SPRG1",
561 SPR_NOACCESS
, SPR_NOACCESS
,
562 &spr_read_generic
, &spr_write_generic
,
564 spr_register(env
, SPR_SPRG2
, "SPRG2",
565 SPR_NOACCESS
, SPR_NOACCESS
,
566 &spr_read_generic
, &spr_write_generic
,
568 spr_register(env
, SPR_SPRG3
, "SPRG3",
569 SPR_NOACCESS
, SPR_NOACCESS
,
570 &spr_read_generic
, &spr_write_generic
,
574 /* SPR common to all non-embedded PowerPC, including 601 */
575 static void gen_spr_ne_601 (CPUPPCState
*env
)
577 /* Exception processing */
578 spr_register(env
, SPR_DSISR
, "DSISR",
579 SPR_NOACCESS
, SPR_NOACCESS
,
580 &spr_read_generic
, &spr_write_generic
,
582 spr_register(env
, SPR_DAR
, "DAR",
583 SPR_NOACCESS
, SPR_NOACCESS
,
584 &spr_read_generic
, &spr_write_generic
,
587 spr_register(env
, SPR_DECR
, "DECR",
588 SPR_NOACCESS
, SPR_NOACCESS
,
589 &spr_read_decr
, &spr_write_decr
,
591 /* Memory management */
592 spr_register(env
, SPR_SDR1
, "SDR1",
593 SPR_NOACCESS
, SPR_NOACCESS
,
594 &spr_read_sdr1
, &spr_write_sdr1
,
599 static void gen_low_BATs (CPUPPCState
*env
)
601 #if !defined(CONFIG_USER_ONLY)
602 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
603 SPR_NOACCESS
, SPR_NOACCESS
,
604 &spr_read_ibat
, &spr_write_ibatu
,
606 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
607 SPR_NOACCESS
, SPR_NOACCESS
,
608 &spr_read_ibat
, &spr_write_ibatl
,
610 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
611 SPR_NOACCESS
, SPR_NOACCESS
,
612 &spr_read_ibat
, &spr_write_ibatu
,
614 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
615 SPR_NOACCESS
, SPR_NOACCESS
,
616 &spr_read_ibat
, &spr_write_ibatl
,
618 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
619 SPR_NOACCESS
, SPR_NOACCESS
,
620 &spr_read_ibat
, &spr_write_ibatu
,
622 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
623 SPR_NOACCESS
, SPR_NOACCESS
,
624 &spr_read_ibat
, &spr_write_ibatl
,
626 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
627 SPR_NOACCESS
, SPR_NOACCESS
,
628 &spr_read_ibat
, &spr_write_ibatu
,
630 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
631 SPR_NOACCESS
, SPR_NOACCESS
,
632 &spr_read_ibat
, &spr_write_ibatl
,
634 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
635 SPR_NOACCESS
, SPR_NOACCESS
,
636 &spr_read_dbat
, &spr_write_dbatu
,
638 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
639 SPR_NOACCESS
, SPR_NOACCESS
,
640 &spr_read_dbat
, &spr_write_dbatl
,
642 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
643 SPR_NOACCESS
, SPR_NOACCESS
,
644 &spr_read_dbat
, &spr_write_dbatu
,
646 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
647 SPR_NOACCESS
, SPR_NOACCESS
,
648 &spr_read_dbat
, &spr_write_dbatl
,
650 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
651 SPR_NOACCESS
, SPR_NOACCESS
,
652 &spr_read_dbat
, &spr_write_dbatu
,
654 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
655 SPR_NOACCESS
, SPR_NOACCESS
,
656 &spr_read_dbat
, &spr_write_dbatl
,
658 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
659 SPR_NOACCESS
, SPR_NOACCESS
,
660 &spr_read_dbat
, &spr_write_dbatu
,
662 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
663 SPR_NOACCESS
, SPR_NOACCESS
,
664 &spr_read_dbat
, &spr_write_dbatl
,
671 static void gen_high_BATs (CPUPPCState
*env
)
673 #if !defined(CONFIG_USER_ONLY)
674 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
675 SPR_NOACCESS
, SPR_NOACCESS
,
676 &spr_read_ibat_h
, &spr_write_ibatu_h
,
678 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
679 SPR_NOACCESS
, SPR_NOACCESS
,
680 &spr_read_ibat_h
, &spr_write_ibatl_h
,
682 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
683 SPR_NOACCESS
, SPR_NOACCESS
,
684 &spr_read_ibat_h
, &spr_write_ibatu_h
,
686 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
687 SPR_NOACCESS
, SPR_NOACCESS
,
688 &spr_read_ibat_h
, &spr_write_ibatl_h
,
690 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
691 SPR_NOACCESS
, SPR_NOACCESS
,
692 &spr_read_ibat_h
, &spr_write_ibatu_h
,
694 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
695 SPR_NOACCESS
, SPR_NOACCESS
,
696 &spr_read_ibat_h
, &spr_write_ibatl_h
,
698 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
699 SPR_NOACCESS
, SPR_NOACCESS
,
700 &spr_read_ibat_h
, &spr_write_ibatu_h
,
702 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
703 SPR_NOACCESS
, SPR_NOACCESS
,
704 &spr_read_ibat_h
, &spr_write_ibatl_h
,
706 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
707 SPR_NOACCESS
, SPR_NOACCESS
,
708 &spr_read_dbat_h
, &spr_write_dbatu_h
,
710 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
711 SPR_NOACCESS
, SPR_NOACCESS
,
712 &spr_read_dbat_h
, &spr_write_dbatl_h
,
714 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
715 SPR_NOACCESS
, SPR_NOACCESS
,
716 &spr_read_dbat_h
, &spr_write_dbatu_h
,
718 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
719 SPR_NOACCESS
, SPR_NOACCESS
,
720 &spr_read_dbat_h
, &spr_write_dbatl_h
,
722 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
723 SPR_NOACCESS
, SPR_NOACCESS
,
724 &spr_read_dbat_h
, &spr_write_dbatu_h
,
726 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
727 SPR_NOACCESS
, SPR_NOACCESS
,
728 &spr_read_dbat_h
, &spr_write_dbatl_h
,
730 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
731 SPR_NOACCESS
, SPR_NOACCESS
,
732 &spr_read_dbat_h
, &spr_write_dbatu_h
,
734 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
735 SPR_NOACCESS
, SPR_NOACCESS
,
736 &spr_read_dbat_h
, &spr_write_dbatl_h
,
742 /* Generic PowerPC time base */
743 static void gen_tbl (CPUPPCState
*env
)
745 spr_register(env
, SPR_VTBL
, "TBL",
746 &spr_read_tbl
, SPR_NOACCESS
,
747 &spr_read_tbl
, SPR_NOACCESS
,
749 spr_register(env
, SPR_TBL
, "TBL",
750 SPR_NOACCESS
, SPR_NOACCESS
,
751 SPR_NOACCESS
, &spr_write_tbl
,
753 spr_register(env
, SPR_VTBU
, "TBU",
754 &spr_read_tbu
, SPR_NOACCESS
,
755 &spr_read_tbu
, SPR_NOACCESS
,
757 spr_register(env
, SPR_TBU
, "TBU",
758 SPR_NOACCESS
, SPR_NOACCESS
,
759 SPR_NOACCESS
, &spr_write_tbu
,
763 /* Softare table search registers */
764 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
766 #if !defined(CONFIG_USER_ONLY)
767 env
->nb_tlb
= nb_tlbs
;
768 env
->nb_ways
= nb_ways
;
770 spr_register(env
, SPR_DMISS
, "DMISS",
771 SPR_NOACCESS
, SPR_NOACCESS
,
772 &spr_read_generic
, SPR_NOACCESS
,
774 spr_register(env
, SPR_DCMP
, "DCMP",
775 SPR_NOACCESS
, SPR_NOACCESS
,
776 &spr_read_generic
, SPR_NOACCESS
,
778 spr_register(env
, SPR_HASH1
, "HASH1",
779 SPR_NOACCESS
, SPR_NOACCESS
,
780 &spr_read_generic
, SPR_NOACCESS
,
782 spr_register(env
, SPR_HASH2
, "HASH2",
783 SPR_NOACCESS
, SPR_NOACCESS
,
784 &spr_read_generic
, SPR_NOACCESS
,
786 spr_register(env
, SPR_IMISS
, "IMISS",
787 SPR_NOACCESS
, SPR_NOACCESS
,
788 &spr_read_generic
, SPR_NOACCESS
,
790 spr_register(env
, SPR_ICMP
, "ICMP",
791 SPR_NOACCESS
, SPR_NOACCESS
,
792 &spr_read_generic
, SPR_NOACCESS
,
794 spr_register(env
, SPR_RPA
, "RPA",
795 SPR_NOACCESS
, SPR_NOACCESS
,
796 &spr_read_generic
, &spr_write_generic
,
801 /* SPR common to MPC755 and G2 */
802 static void gen_spr_G2_755 (CPUPPCState
*env
)
805 spr_register(env
, SPR_SPRG4
, "SPRG4",
806 SPR_NOACCESS
, SPR_NOACCESS
,
807 &spr_read_generic
, &spr_write_generic
,
809 spr_register(env
, SPR_SPRG5
, "SPRG5",
810 SPR_NOACCESS
, SPR_NOACCESS
,
811 &spr_read_generic
, &spr_write_generic
,
813 spr_register(env
, SPR_SPRG6
, "SPRG6",
814 SPR_NOACCESS
, SPR_NOACCESS
,
815 &spr_read_generic
, &spr_write_generic
,
817 spr_register(env
, SPR_SPRG7
, "SPRG7",
818 SPR_NOACCESS
, SPR_NOACCESS
,
819 &spr_read_generic
, &spr_write_generic
,
823 /* SPR common to all 7xx PowerPC implementations */
824 static void gen_spr_7xx (CPUPPCState
*env
)
827 /* XXX : not implemented */
828 spr_register(env
, SPR_DABR
, "DABR",
829 SPR_NOACCESS
, SPR_NOACCESS
,
830 &spr_read_generic
, &spr_write_generic
,
832 /* XXX : not implemented */
833 spr_register(env
, SPR_IABR
, "IABR",
834 SPR_NOACCESS
, SPR_NOACCESS
,
835 &spr_read_generic
, &spr_write_generic
,
837 /* Cache management */
838 /* XXX : not implemented */
839 spr_register(env
, SPR_ICTC
, "ICTC",
840 SPR_NOACCESS
, SPR_NOACCESS
,
841 &spr_read_generic
, &spr_write_generic
,
843 /* Performance monitors */
844 /* XXX : not implemented */
845 spr_register(env
, SPR_MMCR0
, "MMCR0",
846 SPR_NOACCESS
, SPR_NOACCESS
,
847 &spr_read_generic
, &spr_write_generic
,
849 /* XXX : not implemented */
850 spr_register(env
, SPR_MMCR1
, "MMCR1",
851 SPR_NOACCESS
, SPR_NOACCESS
,
852 &spr_read_generic
, &spr_write_generic
,
854 /* XXX : not implemented */
855 spr_register(env
, SPR_PMC1
, "PMC1",
856 SPR_NOACCESS
, SPR_NOACCESS
,
857 &spr_read_generic
, &spr_write_generic
,
859 /* XXX : not implemented */
860 spr_register(env
, SPR_PMC2
, "PMC2",
861 SPR_NOACCESS
, SPR_NOACCESS
,
862 &spr_read_generic
, &spr_write_generic
,
864 /* XXX : not implemented */
865 spr_register(env
, SPR_PMC3
, "PMC3",
866 SPR_NOACCESS
, SPR_NOACCESS
,
867 &spr_read_generic
, &spr_write_generic
,
869 /* XXX : not implemented */
870 spr_register(env
, SPR_PMC4
, "PMC4",
871 SPR_NOACCESS
, SPR_NOACCESS
,
872 &spr_read_generic
, &spr_write_generic
,
874 /* XXX : not implemented */
875 spr_register(env
, SPR_SIAR
, "SIAR",
876 SPR_NOACCESS
, SPR_NOACCESS
,
877 &spr_read_generic
, SPR_NOACCESS
,
879 /* XXX : not implemented */
880 spr_register(env
, SPR_UMMCR0
, "UMMCR0",
881 &spr_read_ureg
, SPR_NOACCESS
,
882 &spr_read_ureg
, SPR_NOACCESS
,
884 /* XXX : not implemented */
885 spr_register(env
, SPR_UMMCR1
, "UMMCR1",
886 &spr_read_ureg
, SPR_NOACCESS
,
887 &spr_read_ureg
, SPR_NOACCESS
,
889 /* XXX : not implemented */
890 spr_register(env
, SPR_UPMC1
, "UPMC1",
891 &spr_read_ureg
, SPR_NOACCESS
,
892 &spr_read_ureg
, SPR_NOACCESS
,
894 /* XXX : not implemented */
895 spr_register(env
, SPR_UPMC2
, "UPMC2",
896 &spr_read_ureg
, SPR_NOACCESS
,
897 &spr_read_ureg
, SPR_NOACCESS
,
899 /* XXX : not implemented */
900 spr_register(env
, SPR_UPMC3
, "UPMC3",
901 &spr_read_ureg
, SPR_NOACCESS
,
902 &spr_read_ureg
, SPR_NOACCESS
,
904 /* XXX : not implemented */
905 spr_register(env
, SPR_UPMC4
, "UPMC4",
906 &spr_read_ureg
, SPR_NOACCESS
,
907 &spr_read_ureg
, SPR_NOACCESS
,
909 /* XXX : not implemented */
910 spr_register(env
, SPR_USIAR
, "USIAR",
911 &spr_read_ureg
, SPR_NOACCESS
,
912 &spr_read_ureg
, SPR_NOACCESS
,
914 /* External access control */
915 /* XXX : not implemented */
916 spr_register(env
, SPR_EAR
, "EAR",
917 SPR_NOACCESS
, SPR_NOACCESS
,
918 &spr_read_generic
, &spr_write_generic
,
922 static void gen_spr_thrm (CPUPPCState
*env
)
924 /* Thermal management */
925 /* XXX : not implemented */
926 spr_register(env
, SPR_THRM1
, "THRM1",
927 SPR_NOACCESS
, SPR_NOACCESS
,
928 &spr_read_generic
, &spr_write_generic
,
930 /* XXX : not implemented */
931 spr_register(env
, SPR_THRM2
, "THRM2",
932 SPR_NOACCESS
, SPR_NOACCESS
,
933 &spr_read_generic
, &spr_write_generic
,
935 /* XXX : not implemented */
936 spr_register(env
, SPR_THRM3
, "THRM3",
937 SPR_NOACCESS
, SPR_NOACCESS
,
938 &spr_read_generic
, &spr_write_generic
,
942 /* SPR specific to PowerPC 604 implementation */
943 static void gen_spr_604 (CPUPPCState
*env
)
945 /* Processor identification */
946 spr_register(env
, SPR_PIR
, "PIR",
947 SPR_NOACCESS
, SPR_NOACCESS
,
948 &spr_read_generic
, &spr_write_pir
,
951 /* XXX : not implemented */
952 spr_register(env
, SPR_IABR
, "IABR",
953 SPR_NOACCESS
, SPR_NOACCESS
,
954 &spr_read_generic
, &spr_write_generic
,
956 /* XXX : not implemented */
957 spr_register(env
, SPR_DABR
, "DABR",
958 SPR_NOACCESS
, SPR_NOACCESS
,
959 &spr_read_generic
, &spr_write_generic
,
961 /* Performance counters */
962 /* XXX : not implemented */
963 spr_register(env
, SPR_MMCR0
, "MMCR0",
964 SPR_NOACCESS
, SPR_NOACCESS
,
965 &spr_read_generic
, &spr_write_generic
,
967 /* XXX : not implemented */
968 spr_register(env
, SPR_PMC1
, "PMC1",
969 SPR_NOACCESS
, SPR_NOACCESS
,
970 &spr_read_generic
, &spr_write_generic
,
972 /* XXX : not implemented */
973 spr_register(env
, SPR_PMC2
, "PMC2",
974 SPR_NOACCESS
, SPR_NOACCESS
,
975 &spr_read_generic
, &spr_write_generic
,
977 /* XXX : not implemented */
978 spr_register(env
, SPR_SIAR
, "SIAR",
979 SPR_NOACCESS
, SPR_NOACCESS
,
980 &spr_read_generic
, SPR_NOACCESS
,
982 /* XXX : not implemented */
983 spr_register(env
, SPR_SDA
, "SDA",
984 SPR_NOACCESS
, SPR_NOACCESS
,
985 &spr_read_generic
, SPR_NOACCESS
,
987 /* External access control */
988 /* XXX : not implemented */
989 spr_register(env
, SPR_EAR
, "EAR",
990 SPR_NOACCESS
, SPR_NOACCESS
,
991 &spr_read_generic
, &spr_write_generic
,
995 /* SPR specific to PowerPC 603 implementation */
996 static void gen_spr_603 (CPUPPCState
*env
)
998 /* External access control */
999 /* XXX : not implemented */
1000 spr_register(env
, SPR_EAR
, "EAR",
1001 SPR_NOACCESS
, SPR_NOACCESS
,
1002 &spr_read_generic
, &spr_write_generic
,
1006 /* SPR specific to PowerPC G2 implementation */
1007 static void gen_spr_G2 (CPUPPCState
*env
)
1009 /* Memory base address */
1011 /* XXX : not implemented */
1012 spr_register(env
, SPR_MBAR
, "MBAR",
1013 SPR_NOACCESS
, SPR_NOACCESS
,
1014 &spr_read_generic
, &spr_write_generic
,
1016 /* Exception processing */
1017 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1018 SPR_NOACCESS
, SPR_NOACCESS
,
1019 &spr_read_generic
, &spr_write_generic
,
1021 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1022 SPR_NOACCESS
, SPR_NOACCESS
,
1023 &spr_read_generic
, &spr_write_generic
,
1026 /* XXX : not implemented */
1027 spr_register(env
, SPR_DABR
, "DABR",
1028 SPR_NOACCESS
, SPR_NOACCESS
,
1029 &spr_read_generic
, &spr_write_generic
,
1031 /* XXX : not implemented */
1032 spr_register(env
, SPR_DABR2
, "DABR2",
1033 SPR_NOACCESS
, SPR_NOACCESS
,
1034 &spr_read_generic
, &spr_write_generic
,
1036 /* XXX : not implemented */
1037 spr_register(env
, SPR_IABR
, "IABR",
1038 SPR_NOACCESS
, SPR_NOACCESS
,
1039 &spr_read_generic
, &spr_write_generic
,
1041 /* XXX : not implemented */
1042 spr_register(env
, SPR_IABR2
, "IABR2",
1043 SPR_NOACCESS
, SPR_NOACCESS
,
1044 &spr_read_generic
, &spr_write_generic
,
1046 /* XXX : not implemented */
1047 spr_register(env
, SPR_IBCR
, "IBCR",
1048 SPR_NOACCESS
, SPR_NOACCESS
,
1049 &spr_read_generic
, &spr_write_generic
,
1051 /* XXX : not implemented */
1052 spr_register(env
, SPR_DBCR
, "DBCR",
1053 SPR_NOACCESS
, SPR_NOACCESS
,
1054 &spr_read_generic
, &spr_write_generic
,
1058 /* SPR specific to PowerPC 602 implementation */
1059 static void gen_spr_602 (CPUPPCState
*env
)
1062 /* XXX : not implemented */
1063 spr_register(env
, SPR_SER
, "SER",
1064 SPR_NOACCESS
, SPR_NOACCESS
,
1065 &spr_read_generic
, &spr_write_generic
,
1067 /* XXX : not implemented */
1068 spr_register(env
, SPR_SEBR
, "SEBR",
1069 SPR_NOACCESS
, SPR_NOACCESS
,
1070 &spr_read_generic
, &spr_write_generic
,
1072 /* XXX : not implemented */
1073 spr_register(env
, SPR_ESASRR
, "ESASRR",
1074 SPR_NOACCESS
, SPR_NOACCESS
,
1075 &spr_read_generic
, &spr_write_generic
,
1077 /* Floating point status */
1078 /* XXX : not implemented */
1079 spr_register(env
, SPR_SP
, "SP",
1080 SPR_NOACCESS
, SPR_NOACCESS
,
1081 &spr_read_generic
, &spr_write_generic
,
1083 /* XXX : not implemented */
1084 spr_register(env
, SPR_LT
, "LT",
1085 SPR_NOACCESS
, SPR_NOACCESS
,
1086 &spr_read_generic
, &spr_write_generic
,
1088 /* Watchdog timer */
1089 /* XXX : not implemented */
1090 spr_register(env
, SPR_TCR
, "TCR",
1091 SPR_NOACCESS
, SPR_NOACCESS
,
1092 &spr_read_generic
, &spr_write_generic
,
1094 /* Interrupt base */
1095 spr_register(env
, SPR_IBR
, "IBR",
1096 SPR_NOACCESS
, SPR_NOACCESS
,
1097 &spr_read_generic
, &spr_write_generic
,
1099 /* XXX : not implemented */
1100 spr_register(env
, SPR_IABR
, "IABR",
1101 SPR_NOACCESS
, SPR_NOACCESS
,
1102 &spr_read_generic
, &spr_write_generic
,
1106 /* SPR specific to PowerPC 601 implementation */
1107 static void gen_spr_601 (CPUPPCState
*env
)
1109 /* Multiplication/division register */
1111 spr_register(env
, SPR_MQ
, "MQ",
1112 &spr_read_generic
, &spr_write_generic
,
1113 &spr_read_generic
, &spr_write_generic
,
1116 spr_register(env
, SPR_601_RTCU
, "RTCU",
1117 SPR_NOACCESS
, SPR_NOACCESS
,
1118 SPR_NOACCESS
, &spr_write_601_rtcu
,
1120 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1121 &spr_read_601_rtcu
, SPR_NOACCESS
,
1122 &spr_read_601_rtcu
, SPR_NOACCESS
,
1124 spr_register(env
, SPR_601_RTCL
, "RTCL",
1125 SPR_NOACCESS
, SPR_NOACCESS
,
1126 SPR_NOACCESS
, &spr_write_601_rtcl
,
1128 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1129 &spr_read_601_rtcl
, SPR_NOACCESS
,
1130 &spr_read_601_rtcl
, SPR_NOACCESS
,
1134 spr_register(env
, SPR_601_UDECR
, "UDECR",
1135 &spr_read_decr
, SPR_NOACCESS
,
1136 &spr_read_decr
, SPR_NOACCESS
,
1139 /* External access control */
1140 /* XXX : not implemented */
1141 spr_register(env
, SPR_EAR
, "EAR",
1142 SPR_NOACCESS
, SPR_NOACCESS
,
1143 &spr_read_generic
, &spr_write_generic
,
1145 /* Memory management */
1146 #if !defined(CONFIG_USER_ONLY)
1147 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1148 SPR_NOACCESS
, SPR_NOACCESS
,
1149 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1151 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1152 SPR_NOACCESS
, SPR_NOACCESS
,
1153 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1155 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1156 SPR_NOACCESS
, SPR_NOACCESS
,
1157 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1159 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1160 SPR_NOACCESS
, SPR_NOACCESS
,
1161 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1163 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1164 SPR_NOACCESS
, SPR_NOACCESS
,
1165 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1167 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1168 SPR_NOACCESS
, SPR_NOACCESS
,
1169 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1171 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1172 SPR_NOACCESS
, SPR_NOACCESS
,
1173 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1175 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1176 SPR_NOACCESS
, SPR_NOACCESS
,
1177 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1183 static void gen_spr_74xx (CPUPPCState
*env
)
1185 /* Processor identification */
1186 spr_register(env
, SPR_PIR
, "PIR",
1187 SPR_NOACCESS
, SPR_NOACCESS
,
1188 &spr_read_generic
, &spr_write_pir
,
1190 /* XXX : not implemented */
1191 spr_register(env
, SPR_MMCR2
, "MMCR2",
1192 SPR_NOACCESS
, SPR_NOACCESS
,
1193 &spr_read_generic
, &spr_write_generic
,
1195 /* XXX : not implemented */
1196 spr_register(env
, SPR_UMMCR2
, "UMMCR2",
1197 &spr_read_ureg
, SPR_NOACCESS
,
1198 &spr_read_ureg
, SPR_NOACCESS
,
1200 /* XXX: not implemented */
1201 spr_register(env
, SPR_BAMR
, "BAMR",
1202 SPR_NOACCESS
, SPR_NOACCESS
,
1203 &spr_read_generic
, &spr_write_generic
,
1205 /* XXX : not implemented */
1206 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1207 SPR_NOACCESS
, SPR_NOACCESS
,
1208 &spr_read_generic
, &spr_write_generic
,
1210 /* Hardware implementation registers */
1211 /* XXX : not implemented */
1212 spr_register(env
, SPR_HID0
, "HID0",
1213 SPR_NOACCESS
, SPR_NOACCESS
,
1214 &spr_read_generic
, &spr_write_generic
,
1216 /* XXX : not implemented */
1217 spr_register(env
, SPR_HID1
, "HID1",
1218 SPR_NOACCESS
, SPR_NOACCESS
,
1219 &spr_read_generic
, &spr_write_generic
,
1222 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1223 &spr_read_generic
, &spr_write_generic
,
1224 &spr_read_generic
, &spr_write_generic
,
1226 /* XXX : not implemented */
1227 spr_register(env
, SPR_L2CR
, "L2CR",
1228 SPR_NOACCESS
, SPR_NOACCESS
,
1229 &spr_read_generic
, &spr_write_generic
,
1231 /* Not strictly an SPR */
1232 vscr_init(env
, 0x00010000);
1235 static void gen_l3_ctrl (CPUPPCState
*env
)
1238 /* XXX : not implemented */
1239 spr_register(env
, SPR_L3CR
, "L3CR",
1240 SPR_NOACCESS
, SPR_NOACCESS
,
1241 &spr_read_generic
, &spr_write_generic
,
1244 /* XXX : not implemented */
1245 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1246 SPR_NOACCESS
, SPR_NOACCESS
,
1247 &spr_read_generic
, &spr_write_generic
,
1250 /* XXX : not implemented */
1251 spr_register(env
, SPR_L3PM
, "L3PM",
1252 SPR_NOACCESS
, SPR_NOACCESS
,
1253 &spr_read_generic
, &spr_write_generic
,
1257 static void gen_74xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
1259 #if !defined(CONFIG_USER_ONLY)
1260 env
->nb_tlb
= nb_tlbs
;
1261 env
->nb_ways
= nb_ways
;
1263 /* XXX : not implemented */
1264 spr_register(env
, SPR_PTEHI
, "PTEHI",
1265 SPR_NOACCESS
, SPR_NOACCESS
,
1266 &spr_read_generic
, &spr_write_generic
,
1268 /* XXX : not implemented */
1269 spr_register(env
, SPR_PTELO
, "PTELO",
1270 SPR_NOACCESS
, SPR_NOACCESS
,
1271 &spr_read_generic
, &spr_write_generic
,
1273 /* XXX : not implemented */
1274 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1275 SPR_NOACCESS
, SPR_NOACCESS
,
1276 &spr_read_generic
, &spr_write_generic
,
1281 static void gen_spr_usprgh (CPUPPCState
*env
)
1283 spr_register(env
, SPR_USPRG4
, "USPRG4",
1284 &spr_read_ureg
, SPR_NOACCESS
,
1285 &spr_read_ureg
, SPR_NOACCESS
,
1287 spr_register(env
, SPR_USPRG5
, "USPRG5",
1288 &spr_read_ureg
, SPR_NOACCESS
,
1289 &spr_read_ureg
, SPR_NOACCESS
,
1291 spr_register(env
, SPR_USPRG6
, "USPRG6",
1292 &spr_read_ureg
, SPR_NOACCESS
,
1293 &spr_read_ureg
, SPR_NOACCESS
,
1295 spr_register(env
, SPR_USPRG7
, "USPRG7",
1296 &spr_read_ureg
, SPR_NOACCESS
,
1297 &spr_read_ureg
, SPR_NOACCESS
,
1301 /* PowerPC BookE SPR */
1302 static void gen_spr_BookE (CPUPPCState
*env
, uint64_t ivor_mask
)
1304 const char *ivor_names
[64] = {
1305 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1306 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1307 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1308 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1309 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1310 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1311 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1312 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1313 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1314 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1315 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1316 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1317 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1318 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1319 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1320 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1322 #define SPR_BOOKE_IVORxx (-1)
1323 int ivor_sprn
[64] = {
1324 SPR_BOOKE_IVOR0
, SPR_BOOKE_IVOR1
, SPR_BOOKE_IVOR2
, SPR_BOOKE_IVOR3
,
1325 SPR_BOOKE_IVOR4
, SPR_BOOKE_IVOR5
, SPR_BOOKE_IVOR6
, SPR_BOOKE_IVOR7
,
1326 SPR_BOOKE_IVOR8
, SPR_BOOKE_IVOR9
, SPR_BOOKE_IVOR10
, SPR_BOOKE_IVOR11
,
1327 SPR_BOOKE_IVOR12
, SPR_BOOKE_IVOR13
, SPR_BOOKE_IVOR14
, SPR_BOOKE_IVOR15
,
1328 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1329 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1330 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1331 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1332 SPR_BOOKE_IVOR32
, SPR_BOOKE_IVOR33
, SPR_BOOKE_IVOR34
, SPR_BOOKE_IVOR35
,
1333 SPR_BOOKE_IVOR36
, SPR_BOOKE_IVOR37
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1334 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1335 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1336 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1337 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1338 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1339 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1343 /* Interrupt processing */
1344 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1345 SPR_NOACCESS
, SPR_NOACCESS
,
1346 &spr_read_generic
, &spr_write_generic
,
1348 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1349 SPR_NOACCESS
, SPR_NOACCESS
,
1350 &spr_read_generic
, &spr_write_generic
,
1353 /* XXX : not implemented */
1354 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1355 SPR_NOACCESS
, SPR_NOACCESS
,
1356 &spr_read_generic
, &spr_write_generic
,
1358 /* XXX : not implemented */
1359 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1360 SPR_NOACCESS
, SPR_NOACCESS
,
1361 &spr_read_generic
, &spr_write_generic
,
1363 /* XXX : not implemented */
1364 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1365 SPR_NOACCESS
, SPR_NOACCESS
,
1366 &spr_read_generic
, &spr_write_generic
,
1368 /* XXX : not implemented */
1369 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1370 SPR_NOACCESS
, SPR_NOACCESS
,
1371 &spr_read_generic
, &spr_write_generic
,
1373 /* XXX : not implemented */
1374 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1375 SPR_NOACCESS
, SPR_NOACCESS
,
1376 &spr_read_generic
, &spr_write_generic
,
1378 /* XXX : not implemented */
1379 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1380 SPR_NOACCESS
, SPR_NOACCESS
,
1381 &spr_read_generic
, &spr_write_generic
,
1383 /* XXX : not implemented */
1384 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1385 SPR_NOACCESS
, SPR_NOACCESS
,
1386 &spr_read_generic
, &spr_write_generic
,
1388 /* XXX : not implemented */
1389 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1390 SPR_NOACCESS
, SPR_NOACCESS
,
1391 &spr_read_generic
, &spr_write_clear
,
1393 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1394 SPR_NOACCESS
, SPR_NOACCESS
,
1395 &spr_read_generic
, &spr_write_generic
,
1397 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1398 SPR_NOACCESS
, SPR_NOACCESS
,
1399 &spr_read_generic
, &spr_write_generic
,
1401 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1402 SPR_NOACCESS
, SPR_NOACCESS
,
1403 &spr_read_generic
, &spr_write_excp_prefix
,
1405 /* Exception vectors */
1406 for (i
= 0; i
< 64; i
++) {
1407 if (ivor_mask
& (1ULL << i
)) {
1408 if (ivor_sprn
[i
] == SPR_BOOKE_IVORxx
) {
1409 fprintf(stderr
, "ERROR: IVOR %d SPR is not defined\n", i
);
1412 spr_register(env
, ivor_sprn
[i
], ivor_names
[i
],
1413 SPR_NOACCESS
, SPR_NOACCESS
,
1414 &spr_read_generic
, &spr_write_excp_vector
,
1418 spr_register(env
, SPR_BOOKE_PID
, "PID",
1419 SPR_NOACCESS
, SPR_NOACCESS
,
1420 &spr_read_generic
, &spr_write_generic
,
1422 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1423 SPR_NOACCESS
, SPR_NOACCESS
,
1424 &spr_read_generic
, &spr_write_booke_tcr
,
1426 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1427 SPR_NOACCESS
, SPR_NOACCESS
,
1428 &spr_read_generic
, &spr_write_booke_tsr
,
1431 spr_register(env
, SPR_DECR
, "DECR",
1432 SPR_NOACCESS
, SPR_NOACCESS
,
1433 &spr_read_decr
, &spr_write_decr
,
1435 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1436 SPR_NOACCESS
, SPR_NOACCESS
,
1437 SPR_NOACCESS
, &spr_write_generic
,
1440 spr_register(env
, SPR_USPRG0
, "USPRG0",
1441 &spr_read_generic
, &spr_write_generic
,
1442 &spr_read_generic
, &spr_write_generic
,
1444 spr_register(env
, SPR_SPRG4
, "SPRG4",
1445 SPR_NOACCESS
, SPR_NOACCESS
,
1446 &spr_read_generic
, &spr_write_generic
,
1448 spr_register(env
, SPR_SPRG5
, "SPRG5",
1449 SPR_NOACCESS
, SPR_NOACCESS
,
1450 &spr_read_generic
, &spr_write_generic
,
1452 spr_register(env
, SPR_SPRG6
, "SPRG6",
1453 SPR_NOACCESS
, SPR_NOACCESS
,
1454 &spr_read_generic
, &spr_write_generic
,
1456 spr_register(env
, SPR_SPRG7
, "SPRG7",
1457 SPR_NOACCESS
, SPR_NOACCESS
,
1458 &spr_read_generic
, &spr_write_generic
,
1462 /* FSL storage control registers */
1463 static void gen_spr_BookE_FSL (CPUPPCState
*env
, uint32_t mas_mask
)
1465 #if !defined(CONFIG_USER_ONLY)
1466 const char *mas_names
[8] = {
1467 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1470 SPR_BOOKE_MAS0
, SPR_BOOKE_MAS1
, SPR_BOOKE_MAS2
, SPR_BOOKE_MAS3
,
1471 SPR_BOOKE_MAS4
, SPR_BOOKE_MAS5
, SPR_BOOKE_MAS6
, SPR_BOOKE_MAS7
,
1475 /* TLB assist registers */
1476 /* XXX : not implemented */
1477 for (i
= 0; i
< 8; i
++) {
1478 if (mas_mask
& (1 << i
)) {
1479 spr_register(env
, mas_sprn
[i
], mas_names
[i
],
1480 SPR_NOACCESS
, SPR_NOACCESS
,
1481 &spr_read_generic
, &spr_write_generic
,
1485 if (env
->nb_pids
> 1) {
1486 /* XXX : not implemented */
1487 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1488 SPR_NOACCESS
, SPR_NOACCESS
,
1489 &spr_read_generic
, &spr_write_generic
,
1492 if (env
->nb_pids
> 2) {
1493 /* XXX : not implemented */
1494 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1495 SPR_NOACCESS
, SPR_NOACCESS
,
1496 &spr_read_generic
, &spr_write_generic
,
1499 /* XXX : not implemented */
1500 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
1501 SPR_NOACCESS
, SPR_NOACCESS
,
1502 &spr_read_generic
, SPR_NOACCESS
,
1503 0x00000000); /* TOFIX */
1504 /* XXX : not implemented */
1505 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
1506 SPR_NOACCESS
, SPR_NOACCESS
,
1507 &spr_read_generic
, &spr_write_generic
,
1508 0x00000000); /* TOFIX */
1509 switch (env
->nb_ways
) {
1511 /* XXX : not implemented */
1512 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1513 SPR_NOACCESS
, SPR_NOACCESS
,
1514 &spr_read_generic
, SPR_NOACCESS
,
1515 0x00000000); /* TOFIX */
1518 /* XXX : not implemented */
1519 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1520 SPR_NOACCESS
, SPR_NOACCESS
,
1521 &spr_read_generic
, SPR_NOACCESS
,
1522 0x00000000); /* TOFIX */
1525 /* XXX : not implemented */
1526 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1527 SPR_NOACCESS
, SPR_NOACCESS
,
1528 &spr_read_generic
, SPR_NOACCESS
,
1529 0x00000000); /* TOFIX */
1532 /* XXX : not implemented */
1533 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1534 SPR_NOACCESS
, SPR_NOACCESS
,
1535 &spr_read_generic
, SPR_NOACCESS
,
1536 0x00000000); /* TOFIX */
1545 /* SPR specific to PowerPC 440 implementation */
1546 static void gen_spr_440 (CPUPPCState
*env
)
1549 /* XXX : not implemented */
1550 spr_register(env
, SPR_440_DNV0
, "DNV0",
1551 SPR_NOACCESS
, SPR_NOACCESS
,
1552 &spr_read_generic
, &spr_write_generic
,
1554 /* XXX : not implemented */
1555 spr_register(env
, SPR_440_DNV1
, "DNV1",
1556 SPR_NOACCESS
, SPR_NOACCESS
,
1557 &spr_read_generic
, &spr_write_generic
,
1559 /* XXX : not implemented */
1560 spr_register(env
, SPR_440_DNV2
, "DNV2",
1561 SPR_NOACCESS
, SPR_NOACCESS
,
1562 &spr_read_generic
, &spr_write_generic
,
1564 /* XXX : not implemented */
1565 spr_register(env
, SPR_440_DNV3
, "DNV3",
1566 SPR_NOACCESS
, SPR_NOACCESS
,
1567 &spr_read_generic
, &spr_write_generic
,
1569 /* XXX : not implemented */
1570 spr_register(env
, SPR_440_DTV0
, "DTV0",
1571 SPR_NOACCESS
, SPR_NOACCESS
,
1572 &spr_read_generic
, &spr_write_generic
,
1574 /* XXX : not implemented */
1575 spr_register(env
, SPR_440_DTV1
, "DTV1",
1576 SPR_NOACCESS
, SPR_NOACCESS
,
1577 &spr_read_generic
, &spr_write_generic
,
1579 /* XXX : not implemented */
1580 spr_register(env
, SPR_440_DTV2
, "DTV2",
1581 SPR_NOACCESS
, SPR_NOACCESS
,
1582 &spr_read_generic
, &spr_write_generic
,
1584 /* XXX : not implemented */
1585 spr_register(env
, SPR_440_DTV3
, "DTV3",
1586 SPR_NOACCESS
, SPR_NOACCESS
,
1587 &spr_read_generic
, &spr_write_generic
,
1589 /* XXX : not implemented */
1590 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1591 SPR_NOACCESS
, SPR_NOACCESS
,
1592 &spr_read_generic
, &spr_write_generic
,
1594 /* XXX : not implemented */
1595 spr_register(env
, SPR_440_INV0
, "INV0",
1596 SPR_NOACCESS
, SPR_NOACCESS
,
1597 &spr_read_generic
, &spr_write_generic
,
1599 /* XXX : not implemented */
1600 spr_register(env
, SPR_440_INV1
, "INV1",
1601 SPR_NOACCESS
, SPR_NOACCESS
,
1602 &spr_read_generic
, &spr_write_generic
,
1604 /* XXX : not implemented */
1605 spr_register(env
, SPR_440_INV2
, "INV2",
1606 SPR_NOACCESS
, SPR_NOACCESS
,
1607 &spr_read_generic
, &spr_write_generic
,
1609 /* XXX : not implemented */
1610 spr_register(env
, SPR_440_INV3
, "INV3",
1611 SPR_NOACCESS
, SPR_NOACCESS
,
1612 &spr_read_generic
, &spr_write_generic
,
1614 /* XXX : not implemented */
1615 spr_register(env
, SPR_440_ITV0
, "ITV0",
1616 SPR_NOACCESS
, SPR_NOACCESS
,
1617 &spr_read_generic
, &spr_write_generic
,
1619 /* XXX : not implemented */
1620 spr_register(env
, SPR_440_ITV1
, "ITV1",
1621 SPR_NOACCESS
, SPR_NOACCESS
,
1622 &spr_read_generic
, &spr_write_generic
,
1624 /* XXX : not implemented */
1625 spr_register(env
, SPR_440_ITV2
, "ITV2",
1626 SPR_NOACCESS
, SPR_NOACCESS
,
1627 &spr_read_generic
, &spr_write_generic
,
1629 /* XXX : not implemented */
1630 spr_register(env
, SPR_440_ITV3
, "ITV3",
1631 SPR_NOACCESS
, SPR_NOACCESS
,
1632 &spr_read_generic
, &spr_write_generic
,
1634 /* XXX : not implemented */
1635 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1636 SPR_NOACCESS
, SPR_NOACCESS
,
1637 &spr_read_generic
, &spr_write_generic
,
1640 /* XXX : not implemented */
1641 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1642 SPR_NOACCESS
, SPR_NOACCESS
,
1643 &spr_read_generic
, SPR_NOACCESS
,
1645 /* XXX : not implemented */
1646 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1647 SPR_NOACCESS
, SPR_NOACCESS
,
1648 &spr_read_generic
, SPR_NOACCESS
,
1650 /* XXX : not implemented */
1651 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1652 SPR_NOACCESS
, SPR_NOACCESS
,
1653 &spr_read_generic
, SPR_NOACCESS
,
1655 /* XXX : not implemented */
1656 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1657 SPR_NOACCESS
, SPR_NOACCESS
,
1658 &spr_read_generic
, SPR_NOACCESS
,
1660 /* XXX : not implemented */
1661 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1662 SPR_NOACCESS
, SPR_NOACCESS
,
1663 &spr_read_generic
, SPR_NOACCESS
,
1665 /* XXX : not implemented */
1666 spr_register(env
, SPR_440_DBDR
, "DBDR",
1667 SPR_NOACCESS
, SPR_NOACCESS
,
1668 &spr_read_generic
, &spr_write_generic
,
1670 /* Processor control */
1671 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1672 SPR_NOACCESS
, SPR_NOACCESS
,
1673 &spr_read_generic
, &spr_write_generic
,
1675 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1676 SPR_NOACCESS
, SPR_NOACCESS
,
1677 &spr_read_generic
, SPR_NOACCESS
,
1679 /* Storage control */
1680 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1681 SPR_NOACCESS
, SPR_NOACCESS
,
1682 &spr_read_generic
, &spr_write_generic
,
1686 /* SPR shared between PowerPC 40x implementations */
1687 static void gen_spr_40x (CPUPPCState
*env
)
1690 /* not emulated, as Qemu do not emulate caches */
1691 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1692 SPR_NOACCESS
, SPR_NOACCESS
,
1693 &spr_read_generic
, &spr_write_generic
,
1695 /* not emulated, as Qemu do not emulate caches */
1696 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1697 SPR_NOACCESS
, SPR_NOACCESS
,
1698 &spr_read_generic
, &spr_write_generic
,
1700 /* not emulated, as Qemu do not emulate caches */
1701 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1702 SPR_NOACCESS
, SPR_NOACCESS
,
1703 &spr_read_generic
, SPR_NOACCESS
,
1706 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1707 SPR_NOACCESS
, SPR_NOACCESS
,
1708 &spr_read_generic
, &spr_write_generic
,
1710 spr_register(env
, SPR_40x_ESR
, "ESR",
1711 SPR_NOACCESS
, SPR_NOACCESS
,
1712 &spr_read_generic
, &spr_write_generic
,
1714 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1715 SPR_NOACCESS
, SPR_NOACCESS
,
1716 &spr_read_generic
, &spr_write_excp_prefix
,
1718 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1719 &spr_read_generic
, &spr_write_generic
,
1720 &spr_read_generic
, &spr_write_generic
,
1722 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1723 &spr_read_generic
, &spr_write_generic
,
1724 &spr_read_generic
, &spr_write_generic
,
1727 spr_register(env
, SPR_40x_PIT
, "PIT",
1728 SPR_NOACCESS
, SPR_NOACCESS
,
1729 &spr_read_40x_pit
, &spr_write_40x_pit
,
1731 spr_register(env
, SPR_40x_TCR
, "TCR",
1732 SPR_NOACCESS
, SPR_NOACCESS
,
1733 &spr_read_generic
, &spr_write_booke_tcr
,
1735 spr_register(env
, SPR_40x_TSR
, "TSR",
1736 SPR_NOACCESS
, SPR_NOACCESS
,
1737 &spr_read_generic
, &spr_write_booke_tsr
,
1741 /* SPR specific to PowerPC 405 implementation */
1742 static void gen_spr_405 (CPUPPCState
*env
)
1745 spr_register(env
, SPR_40x_PID
, "PID",
1746 SPR_NOACCESS
, SPR_NOACCESS
,
1747 &spr_read_generic
, &spr_write_generic
,
1749 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1750 SPR_NOACCESS
, SPR_NOACCESS
,
1751 &spr_read_generic
, &spr_write_generic
,
1753 /* Debug interface */
1754 /* XXX : not implemented */
1755 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1756 SPR_NOACCESS
, SPR_NOACCESS
,
1757 &spr_read_generic
, &spr_write_40x_dbcr0
,
1759 /* XXX : not implemented */
1760 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1761 SPR_NOACCESS
, SPR_NOACCESS
,
1762 &spr_read_generic
, &spr_write_generic
,
1764 /* XXX : not implemented */
1765 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1766 SPR_NOACCESS
, SPR_NOACCESS
,
1767 &spr_read_generic
, &spr_write_clear
,
1768 /* Last reset was system reset */
1770 /* XXX : not implemented */
1771 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1772 SPR_NOACCESS
, SPR_NOACCESS
,
1773 &spr_read_generic
, &spr_write_generic
,
1775 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1776 SPR_NOACCESS
, SPR_NOACCESS
,
1777 &spr_read_generic
, &spr_write_generic
,
1779 /* XXX : not implemented */
1780 spr_register(env
, SPR_405_DVC1
, "DVC1",
1781 SPR_NOACCESS
, SPR_NOACCESS
,
1782 &spr_read_generic
, &spr_write_generic
,
1784 /* XXX : not implemented */
1785 spr_register(env
, SPR_405_DVC2
, "DVC2",
1786 SPR_NOACCESS
, SPR_NOACCESS
,
1787 &spr_read_generic
, &spr_write_generic
,
1789 /* XXX : not implemented */
1790 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1791 SPR_NOACCESS
, SPR_NOACCESS
,
1792 &spr_read_generic
, &spr_write_generic
,
1794 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1795 SPR_NOACCESS
, SPR_NOACCESS
,
1796 &spr_read_generic
, &spr_write_generic
,
1798 /* XXX : not implemented */
1799 spr_register(env
, SPR_405_IAC3
, "IAC3",
1800 SPR_NOACCESS
, SPR_NOACCESS
,
1801 &spr_read_generic
, &spr_write_generic
,
1803 /* XXX : not implemented */
1804 spr_register(env
, SPR_405_IAC4
, "IAC4",
1805 SPR_NOACCESS
, SPR_NOACCESS
,
1806 &spr_read_generic
, &spr_write_generic
,
1808 /* Storage control */
1809 /* XXX: TODO: not implemented */
1810 spr_register(env
, SPR_405_SLER
, "SLER",
1811 SPR_NOACCESS
, SPR_NOACCESS
,
1812 &spr_read_generic
, &spr_write_40x_sler
,
1814 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1815 SPR_NOACCESS
, SPR_NOACCESS
,
1816 &spr_read_generic
, &spr_write_generic
,
1818 /* XXX : not implemented */
1819 spr_register(env
, SPR_405_SU0R
, "SU0R",
1820 SPR_NOACCESS
, SPR_NOACCESS
,
1821 &spr_read_generic
, &spr_write_generic
,
1824 spr_register(env
, SPR_USPRG0
, "USPRG0",
1825 &spr_read_ureg
, SPR_NOACCESS
,
1826 &spr_read_ureg
, SPR_NOACCESS
,
1828 spr_register(env
, SPR_SPRG4
, "SPRG4",
1829 SPR_NOACCESS
, SPR_NOACCESS
,
1830 &spr_read_generic
, &spr_write_generic
,
1832 spr_register(env
, SPR_SPRG5
, "SPRG5",
1833 SPR_NOACCESS
, SPR_NOACCESS
,
1834 spr_read_generic
, &spr_write_generic
,
1836 spr_register(env
, SPR_SPRG6
, "SPRG6",
1837 SPR_NOACCESS
, SPR_NOACCESS
,
1838 spr_read_generic
, &spr_write_generic
,
1840 spr_register(env
, SPR_SPRG7
, "SPRG7",
1841 SPR_NOACCESS
, SPR_NOACCESS
,
1842 spr_read_generic
, &spr_write_generic
,
1844 gen_spr_usprgh(env
);
1847 /* SPR shared between PowerPC 401 & 403 implementations */
1848 static void gen_spr_401_403 (CPUPPCState
*env
)
1851 spr_register(env
, SPR_403_VTBL
, "TBL",
1852 &spr_read_tbl
, SPR_NOACCESS
,
1853 &spr_read_tbl
, SPR_NOACCESS
,
1855 spr_register(env
, SPR_403_TBL
, "TBL",
1856 SPR_NOACCESS
, SPR_NOACCESS
,
1857 SPR_NOACCESS
, &spr_write_tbl
,
1859 spr_register(env
, SPR_403_VTBU
, "TBU",
1860 &spr_read_tbu
, SPR_NOACCESS
,
1861 &spr_read_tbu
, SPR_NOACCESS
,
1863 spr_register(env
, SPR_403_TBU
, "TBU",
1864 SPR_NOACCESS
, SPR_NOACCESS
,
1865 SPR_NOACCESS
, &spr_write_tbu
,
1868 /* not emulated, as Qemu do not emulate caches */
1869 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
1870 SPR_NOACCESS
, SPR_NOACCESS
,
1871 &spr_read_generic
, &spr_write_generic
,
1875 /* SPR specific to PowerPC 401 implementation */
1876 static void gen_spr_401 (CPUPPCState
*env
)
1878 /* Debug interface */
1879 /* XXX : not implemented */
1880 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
1881 SPR_NOACCESS
, SPR_NOACCESS
,
1882 &spr_read_generic
, &spr_write_40x_dbcr0
,
1884 /* XXX : not implemented */
1885 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1886 SPR_NOACCESS
, SPR_NOACCESS
,
1887 &spr_read_generic
, &spr_write_clear
,
1888 /* Last reset was system reset */
1890 /* XXX : not implemented */
1891 spr_register(env
, SPR_40x_DAC1
, "DAC",
1892 SPR_NOACCESS
, SPR_NOACCESS
,
1893 &spr_read_generic
, &spr_write_generic
,
1895 /* XXX : not implemented */
1896 spr_register(env
, SPR_40x_IAC1
, "IAC",
1897 SPR_NOACCESS
, SPR_NOACCESS
,
1898 &spr_read_generic
, &spr_write_generic
,
1900 /* Storage control */
1901 /* XXX: TODO: not implemented */
1902 spr_register(env
, SPR_405_SLER
, "SLER",
1903 SPR_NOACCESS
, SPR_NOACCESS
,
1904 &spr_read_generic
, &spr_write_40x_sler
,
1906 /* not emulated, as Qemu never does speculative access */
1907 spr_register(env
, SPR_40x_SGR
, "SGR",
1908 SPR_NOACCESS
, SPR_NOACCESS
,
1909 &spr_read_generic
, &spr_write_generic
,
1911 /* not emulated, as Qemu do not emulate caches */
1912 spr_register(env
, SPR_40x_DCWR
, "DCWR",
1913 SPR_NOACCESS
, SPR_NOACCESS
,
1914 &spr_read_generic
, &spr_write_generic
,
1918 static void gen_spr_401x2 (CPUPPCState
*env
)
1921 spr_register(env
, SPR_40x_PID
, "PID",
1922 SPR_NOACCESS
, SPR_NOACCESS
,
1923 &spr_read_generic
, &spr_write_generic
,
1925 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1926 SPR_NOACCESS
, SPR_NOACCESS
,
1927 &spr_read_generic
, &spr_write_generic
,
1931 /* SPR specific to PowerPC 403 implementation */
1932 static void gen_spr_403 (CPUPPCState
*env
)
1934 /* Debug interface */
1935 /* XXX : not implemented */
1936 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1937 SPR_NOACCESS
, SPR_NOACCESS
,
1938 &spr_read_generic
, &spr_write_40x_dbcr0
,
1940 /* XXX : not implemented */
1941 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1942 SPR_NOACCESS
, SPR_NOACCESS
,
1943 &spr_read_generic
, &spr_write_clear
,
1944 /* Last reset was system reset */
1946 /* XXX : not implemented */
1947 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1948 SPR_NOACCESS
, SPR_NOACCESS
,
1949 &spr_read_generic
, &spr_write_generic
,
1951 /* XXX : not implemented */
1952 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1953 SPR_NOACCESS
, SPR_NOACCESS
,
1954 &spr_read_generic
, &spr_write_generic
,
1956 /* XXX : not implemented */
1957 spr_register(env
, SPR_40x_IAC1
, "IAC1",
1958 SPR_NOACCESS
, SPR_NOACCESS
,
1959 &spr_read_generic
, &spr_write_generic
,
1961 /* XXX : not implemented */
1962 spr_register(env
, SPR_40x_IAC2
, "IAC2",
1963 SPR_NOACCESS
, SPR_NOACCESS
,
1964 &spr_read_generic
, &spr_write_generic
,
1968 static void gen_spr_403_real (CPUPPCState
*env
)
1970 spr_register(env
, SPR_403_PBL1
, "PBL1",
1971 SPR_NOACCESS
, SPR_NOACCESS
,
1972 &spr_read_403_pbr
, &spr_write_403_pbr
,
1974 spr_register(env
, SPR_403_PBU1
, "PBU1",
1975 SPR_NOACCESS
, SPR_NOACCESS
,
1976 &spr_read_403_pbr
, &spr_write_403_pbr
,
1978 spr_register(env
, SPR_403_PBL2
, "PBL2",
1979 SPR_NOACCESS
, SPR_NOACCESS
,
1980 &spr_read_403_pbr
, &spr_write_403_pbr
,
1982 spr_register(env
, SPR_403_PBU2
, "PBU2",
1983 SPR_NOACCESS
, SPR_NOACCESS
,
1984 &spr_read_403_pbr
, &spr_write_403_pbr
,
1988 static void gen_spr_403_mmu (CPUPPCState
*env
)
1991 spr_register(env
, SPR_40x_PID
, "PID",
1992 SPR_NOACCESS
, SPR_NOACCESS
,
1993 &spr_read_generic
, &spr_write_generic
,
1995 spr_register(env
, SPR_40x_ZPR
, "ZPR",
1996 SPR_NOACCESS
, SPR_NOACCESS
,
1997 &spr_read_generic
, &spr_write_generic
,
2001 /* SPR specific to PowerPC compression coprocessor extension */
2002 static void gen_spr_compress (CPUPPCState
*env
)
2004 /* XXX : not implemented */
2005 spr_register(env
, SPR_401_SKR
, "SKR",
2006 SPR_NOACCESS
, SPR_NOACCESS
,
2007 &spr_read_generic
, &spr_write_generic
,
2011 #if defined (TARGET_PPC64)
2012 /* SPR specific to PowerPC 620 */
2013 static void gen_spr_620 (CPUPPCState
*env
)
2015 /* Processor identification */
2016 spr_register(env
, SPR_PIR
, "PIR",
2017 SPR_NOACCESS
, SPR_NOACCESS
,
2018 &spr_read_generic
, &spr_write_pir
,
2020 spr_register(env
, SPR_ASR
, "ASR",
2021 SPR_NOACCESS
, SPR_NOACCESS
,
2022 &spr_read_asr
, &spr_write_asr
,
2025 /* XXX : not implemented */
2026 spr_register(env
, SPR_IABR
, "IABR",
2027 SPR_NOACCESS
, SPR_NOACCESS
,
2028 &spr_read_generic
, &spr_write_generic
,
2030 /* XXX : not implemented */
2031 spr_register(env
, SPR_DABR
, "DABR",
2032 SPR_NOACCESS
, SPR_NOACCESS
,
2033 &spr_read_generic
, &spr_write_generic
,
2035 /* XXX : not implemented */
2036 spr_register(env
, SPR_SIAR
, "SIAR",
2037 SPR_NOACCESS
, SPR_NOACCESS
,
2038 &spr_read_generic
, SPR_NOACCESS
,
2040 /* XXX : not implemented */
2041 spr_register(env
, SPR_SDA
, "SDA",
2042 SPR_NOACCESS
, SPR_NOACCESS
,
2043 &spr_read_generic
, SPR_NOACCESS
,
2045 /* XXX : not implemented */
2046 spr_register(env
, SPR_620_PMC1R
, "PMC1",
2047 SPR_NOACCESS
, SPR_NOACCESS
,
2048 &spr_read_generic
, SPR_NOACCESS
,
2050 spr_register(env
, SPR_620_PMC1W
, "PMC1",
2051 SPR_NOACCESS
, SPR_NOACCESS
,
2052 SPR_NOACCESS
, &spr_write_generic
,
2054 /* XXX : not implemented */
2055 spr_register(env
, SPR_620_PMC2R
, "PMC2",
2056 SPR_NOACCESS
, SPR_NOACCESS
,
2057 &spr_read_generic
, SPR_NOACCESS
,
2059 spr_register(env
, SPR_620_PMC2W
, "PMC2",
2060 SPR_NOACCESS
, SPR_NOACCESS
,
2061 SPR_NOACCESS
, &spr_write_generic
,
2063 /* XXX : not implemented */
2064 spr_register(env
, SPR_620_MMCR0R
, "MMCR0",
2065 SPR_NOACCESS
, SPR_NOACCESS
,
2066 &spr_read_generic
, SPR_NOACCESS
,
2068 spr_register(env
, SPR_620_MMCR0W
, "MMCR0",
2069 SPR_NOACCESS
, SPR_NOACCESS
,
2070 SPR_NOACCESS
, &spr_write_generic
,
2072 /* External access control */
2073 /* XXX : not implemented */
2074 spr_register(env
, SPR_EAR
, "EAR",
2075 SPR_NOACCESS
, SPR_NOACCESS
,
2076 &spr_read_generic
, &spr_write_generic
,
2078 #if 0 // XXX: check this
2079 /* XXX : not implemented */
2080 spr_register(env
, SPR_620_PMR0
, "PMR0",
2081 SPR_NOACCESS
, SPR_NOACCESS
,
2082 &spr_read_generic
, &spr_write_generic
,
2084 /* XXX : not implemented */
2085 spr_register(env
, SPR_620_PMR1
, "PMR1",
2086 SPR_NOACCESS
, SPR_NOACCESS
,
2087 &spr_read_generic
, &spr_write_generic
,
2089 /* XXX : not implemented */
2090 spr_register(env
, SPR_620_PMR2
, "PMR2",
2091 SPR_NOACCESS
, SPR_NOACCESS
,
2092 &spr_read_generic
, &spr_write_generic
,
2094 /* XXX : not implemented */
2095 spr_register(env
, SPR_620_PMR3
, "PMR3",
2096 SPR_NOACCESS
, SPR_NOACCESS
,
2097 &spr_read_generic
, &spr_write_generic
,
2099 /* XXX : not implemented */
2100 spr_register(env
, SPR_620_PMR4
, "PMR4",
2101 SPR_NOACCESS
, SPR_NOACCESS
,
2102 &spr_read_generic
, &spr_write_generic
,
2104 /* XXX : not implemented */
2105 spr_register(env
, SPR_620_PMR5
, "PMR5",
2106 SPR_NOACCESS
, SPR_NOACCESS
,
2107 &spr_read_generic
, &spr_write_generic
,
2109 /* XXX : not implemented */
2110 spr_register(env
, SPR_620_PMR6
, "PMR6",
2111 SPR_NOACCESS
, SPR_NOACCESS
,
2112 &spr_read_generic
, &spr_write_generic
,
2114 /* XXX : not implemented */
2115 spr_register(env
, SPR_620_PMR7
, "PMR7",
2116 SPR_NOACCESS
, SPR_NOACCESS
,
2117 &spr_read_generic
, &spr_write_generic
,
2119 /* XXX : not implemented */
2120 spr_register(env
, SPR_620_PMR8
, "PMR8",
2121 SPR_NOACCESS
, SPR_NOACCESS
,
2122 &spr_read_generic
, &spr_write_generic
,
2124 /* XXX : not implemented */
2125 spr_register(env
, SPR_620_PMR9
, "PMR9",
2126 SPR_NOACCESS
, SPR_NOACCESS
,
2127 &spr_read_generic
, &spr_write_generic
,
2129 /* XXX : not implemented */
2130 spr_register(env
, SPR_620_PMRA
, "PMR10",
2131 SPR_NOACCESS
, SPR_NOACCESS
,
2132 &spr_read_generic
, &spr_write_generic
,
2134 /* XXX : not implemented */
2135 spr_register(env
, SPR_620_PMRB
, "PMR11",
2136 SPR_NOACCESS
, SPR_NOACCESS
,
2137 &spr_read_generic
, &spr_write_generic
,
2139 /* XXX : not implemented */
2140 spr_register(env
, SPR_620_PMRC
, "PMR12",
2141 SPR_NOACCESS
, SPR_NOACCESS
,
2142 &spr_read_generic
, &spr_write_generic
,
2144 /* XXX : not implemented */
2145 spr_register(env
, SPR_620_PMRD
, "PMR13",
2146 SPR_NOACCESS
, SPR_NOACCESS
,
2147 &spr_read_generic
, &spr_write_generic
,
2149 /* XXX : not implemented */
2150 spr_register(env
, SPR_620_PMRE
, "PMR14",
2151 SPR_NOACCESS
, SPR_NOACCESS
,
2152 &spr_read_generic
, &spr_write_generic
,
2154 /* XXX : not implemented */
2155 spr_register(env
, SPR_620_PMRF
, "PMR15",
2156 SPR_NOACCESS
, SPR_NOACCESS
,
2157 &spr_read_generic
, &spr_write_generic
,
2160 /* XXX : not implemented */
2161 spr_register(env
, SPR_620_BUSCSR
, "BUSCSR",
2162 SPR_NOACCESS
, SPR_NOACCESS
,
2163 &spr_read_generic
, &spr_write_generic
,
2165 /* XXX : not implemented */
2166 spr_register(env
, SPR_620_L2CR
, "L2CR",
2167 SPR_NOACCESS
, SPR_NOACCESS
,
2168 &spr_read_generic
, &spr_write_generic
,
2170 /* XXX : not implemented */
2171 spr_register(env
, SPR_620_L2SR
, "L2SR",
2172 SPR_NOACCESS
, SPR_NOACCESS
,
2173 &spr_read_generic
, &spr_write_generic
,
2176 #endif /* defined (TARGET_PPC64) */
2178 static void gen_spr_5xx_8xx (CPUPPCState
*env
)
2180 /* Exception processing */
2181 spr_register(env
, SPR_DSISR
, "DSISR",
2182 SPR_NOACCESS
, SPR_NOACCESS
,
2183 &spr_read_generic
, &spr_write_generic
,
2185 spr_register(env
, SPR_DAR
, "DAR",
2186 SPR_NOACCESS
, SPR_NOACCESS
,
2187 &spr_read_generic
, &spr_write_generic
,
2190 spr_register(env
, SPR_DECR
, "DECR",
2191 SPR_NOACCESS
, SPR_NOACCESS
,
2192 &spr_read_decr
, &spr_write_decr
,
2194 /* XXX : not implemented */
2195 spr_register(env
, SPR_MPC_EIE
, "EIE",
2196 SPR_NOACCESS
, SPR_NOACCESS
,
2197 &spr_read_generic
, &spr_write_generic
,
2199 /* XXX : not implemented */
2200 spr_register(env
, SPR_MPC_EID
, "EID",
2201 SPR_NOACCESS
, SPR_NOACCESS
,
2202 &spr_read_generic
, &spr_write_generic
,
2204 /* XXX : not implemented */
2205 spr_register(env
, SPR_MPC_NRI
, "NRI",
2206 SPR_NOACCESS
, SPR_NOACCESS
,
2207 &spr_read_generic
, &spr_write_generic
,
2209 /* XXX : not implemented */
2210 spr_register(env
, SPR_MPC_CMPA
, "CMPA",
2211 SPR_NOACCESS
, SPR_NOACCESS
,
2212 &spr_read_generic
, &spr_write_generic
,
2214 /* XXX : not implemented */
2215 spr_register(env
, SPR_MPC_CMPB
, "CMPB",
2216 SPR_NOACCESS
, SPR_NOACCESS
,
2217 &spr_read_generic
, &spr_write_generic
,
2219 /* XXX : not implemented */
2220 spr_register(env
, SPR_MPC_CMPC
, "CMPC",
2221 SPR_NOACCESS
, SPR_NOACCESS
,
2222 &spr_read_generic
, &spr_write_generic
,
2224 /* XXX : not implemented */
2225 spr_register(env
, SPR_MPC_CMPD
, "CMPD",
2226 SPR_NOACCESS
, SPR_NOACCESS
,
2227 &spr_read_generic
, &spr_write_generic
,
2229 /* XXX : not implemented */
2230 spr_register(env
, SPR_MPC_ECR
, "ECR",
2231 SPR_NOACCESS
, SPR_NOACCESS
,
2232 &spr_read_generic
, &spr_write_generic
,
2234 /* XXX : not implemented */
2235 spr_register(env
, SPR_MPC_DER
, "DER",
2236 SPR_NOACCESS
, SPR_NOACCESS
,
2237 &spr_read_generic
, &spr_write_generic
,
2239 /* XXX : not implemented */
2240 spr_register(env
, SPR_MPC_COUNTA
, "COUNTA",
2241 SPR_NOACCESS
, SPR_NOACCESS
,
2242 &spr_read_generic
, &spr_write_generic
,
2244 /* XXX : not implemented */
2245 spr_register(env
, SPR_MPC_COUNTB
, "COUNTB",
2246 SPR_NOACCESS
, SPR_NOACCESS
,
2247 &spr_read_generic
, &spr_write_generic
,
2249 /* XXX : not implemented */
2250 spr_register(env
, SPR_MPC_CMPE
, "CMPE",
2251 SPR_NOACCESS
, SPR_NOACCESS
,
2252 &spr_read_generic
, &spr_write_generic
,
2254 /* XXX : not implemented */
2255 spr_register(env
, SPR_MPC_CMPF
, "CMPF",
2256 SPR_NOACCESS
, SPR_NOACCESS
,
2257 &spr_read_generic
, &spr_write_generic
,
2259 /* XXX : not implemented */
2260 spr_register(env
, SPR_MPC_CMPG
, "CMPG",
2261 SPR_NOACCESS
, SPR_NOACCESS
,
2262 &spr_read_generic
, &spr_write_generic
,
2264 /* XXX : not implemented */
2265 spr_register(env
, SPR_MPC_CMPH
, "CMPH",
2266 SPR_NOACCESS
, SPR_NOACCESS
,
2267 &spr_read_generic
, &spr_write_generic
,
2269 /* XXX : not implemented */
2270 spr_register(env
, SPR_MPC_LCTRL1
, "LCTRL1",
2271 SPR_NOACCESS
, SPR_NOACCESS
,
2272 &spr_read_generic
, &spr_write_generic
,
2274 /* XXX : not implemented */
2275 spr_register(env
, SPR_MPC_LCTRL2
, "LCTRL2",
2276 SPR_NOACCESS
, SPR_NOACCESS
,
2277 &spr_read_generic
, &spr_write_generic
,
2279 /* XXX : not implemented */
2280 spr_register(env
, SPR_MPC_BAR
, "BAR",
2281 SPR_NOACCESS
, SPR_NOACCESS
,
2282 &spr_read_generic
, &spr_write_generic
,
2284 /* XXX : not implemented */
2285 spr_register(env
, SPR_MPC_DPDR
, "DPDR",
2286 SPR_NOACCESS
, SPR_NOACCESS
,
2287 &spr_read_generic
, &spr_write_generic
,
2289 /* XXX : not implemented */
2290 spr_register(env
, SPR_MPC_IMMR
, "IMMR",
2291 SPR_NOACCESS
, SPR_NOACCESS
,
2292 &spr_read_generic
, &spr_write_generic
,
2296 static void gen_spr_5xx (CPUPPCState
*env
)
2298 /* XXX : not implemented */
2299 spr_register(env
, SPR_RCPU_MI_GRA
, "MI_GRA",
2300 SPR_NOACCESS
, SPR_NOACCESS
,
2301 &spr_read_generic
, &spr_write_generic
,
2303 /* XXX : not implemented */
2304 spr_register(env
, SPR_RCPU_L2U_GRA
, "L2U_GRA",
2305 SPR_NOACCESS
, SPR_NOACCESS
,
2306 &spr_read_generic
, &spr_write_generic
,
2308 /* XXX : not implemented */
2309 spr_register(env
, SPR_RPCU_BBCMCR
, "L2U_BBCMCR",
2310 SPR_NOACCESS
, SPR_NOACCESS
,
2311 &spr_read_generic
, &spr_write_generic
,
2313 /* XXX : not implemented */
2314 spr_register(env
, SPR_RCPU_L2U_MCR
, "L2U_MCR",
2315 SPR_NOACCESS
, SPR_NOACCESS
,
2316 &spr_read_generic
, &spr_write_generic
,
2318 /* XXX : not implemented */
2319 spr_register(env
, SPR_RCPU_MI_RBA0
, "MI_RBA0",
2320 SPR_NOACCESS
, SPR_NOACCESS
,
2321 &spr_read_generic
, &spr_write_generic
,
2323 /* XXX : not implemented */
2324 spr_register(env
, SPR_RCPU_MI_RBA1
, "MI_RBA1",
2325 SPR_NOACCESS
, SPR_NOACCESS
,
2326 &spr_read_generic
, &spr_write_generic
,
2328 /* XXX : not implemented */
2329 spr_register(env
, SPR_RCPU_MI_RBA2
, "MI_RBA2",
2330 SPR_NOACCESS
, SPR_NOACCESS
,
2331 &spr_read_generic
, &spr_write_generic
,
2333 /* XXX : not implemented */
2334 spr_register(env
, SPR_RCPU_MI_RBA3
, "MI_RBA3",
2335 SPR_NOACCESS
, SPR_NOACCESS
,
2336 &spr_read_generic
, &spr_write_generic
,
2338 /* XXX : not implemented */
2339 spr_register(env
, SPR_RCPU_L2U_RBA0
, "L2U_RBA0",
2340 SPR_NOACCESS
, SPR_NOACCESS
,
2341 &spr_read_generic
, &spr_write_generic
,
2343 /* XXX : not implemented */
2344 spr_register(env
, SPR_RCPU_L2U_RBA1
, "L2U_RBA1",
2345 SPR_NOACCESS
, SPR_NOACCESS
,
2346 &spr_read_generic
, &spr_write_generic
,
2348 /* XXX : not implemented */
2349 spr_register(env
, SPR_RCPU_L2U_RBA2
, "L2U_RBA2",
2350 SPR_NOACCESS
, SPR_NOACCESS
,
2351 &spr_read_generic
, &spr_write_generic
,
2353 /* XXX : not implemented */
2354 spr_register(env
, SPR_RCPU_L2U_RBA3
, "L2U_RBA3",
2355 SPR_NOACCESS
, SPR_NOACCESS
,
2356 &spr_read_generic
, &spr_write_generic
,
2358 /* XXX : not implemented */
2359 spr_register(env
, SPR_RCPU_MI_RA0
, "MI_RA0",
2360 SPR_NOACCESS
, SPR_NOACCESS
,
2361 &spr_read_generic
, &spr_write_generic
,
2363 /* XXX : not implemented */
2364 spr_register(env
, SPR_RCPU_MI_RA1
, "MI_RA1",
2365 SPR_NOACCESS
, SPR_NOACCESS
,
2366 &spr_read_generic
, &spr_write_generic
,
2368 /* XXX : not implemented */
2369 spr_register(env
, SPR_RCPU_MI_RA2
, "MI_RA2",
2370 SPR_NOACCESS
, SPR_NOACCESS
,
2371 &spr_read_generic
, &spr_write_generic
,
2373 /* XXX : not implemented */
2374 spr_register(env
, SPR_RCPU_MI_RA3
, "MI_RA3",
2375 SPR_NOACCESS
, SPR_NOACCESS
,
2376 &spr_read_generic
, &spr_write_generic
,
2378 /* XXX : not implemented */
2379 spr_register(env
, SPR_RCPU_L2U_RA0
, "L2U_RA0",
2380 SPR_NOACCESS
, SPR_NOACCESS
,
2381 &spr_read_generic
, &spr_write_generic
,
2383 /* XXX : not implemented */
2384 spr_register(env
, SPR_RCPU_L2U_RA1
, "L2U_RA1",
2385 SPR_NOACCESS
, SPR_NOACCESS
,
2386 &spr_read_generic
, &spr_write_generic
,
2388 /* XXX : not implemented */
2389 spr_register(env
, SPR_RCPU_L2U_RA2
, "L2U_RA2",
2390 SPR_NOACCESS
, SPR_NOACCESS
,
2391 &spr_read_generic
, &spr_write_generic
,
2393 /* XXX : not implemented */
2394 spr_register(env
, SPR_RCPU_L2U_RA3
, "L2U_RA3",
2395 SPR_NOACCESS
, SPR_NOACCESS
,
2396 &spr_read_generic
, &spr_write_generic
,
2398 /* XXX : not implemented */
2399 spr_register(env
, SPR_RCPU_FPECR
, "FPECR",
2400 SPR_NOACCESS
, SPR_NOACCESS
,
2401 &spr_read_generic
, &spr_write_generic
,
2405 static void gen_spr_8xx (CPUPPCState
*env
)
2407 /* XXX : not implemented */
2408 spr_register(env
, SPR_MPC_IC_CST
, "IC_CST",
2409 SPR_NOACCESS
, SPR_NOACCESS
,
2410 &spr_read_generic
, &spr_write_generic
,
2412 /* XXX : not implemented */
2413 spr_register(env
, SPR_MPC_IC_ADR
, "IC_ADR",
2414 SPR_NOACCESS
, SPR_NOACCESS
,
2415 &spr_read_generic
, &spr_write_generic
,
2417 /* XXX : not implemented */
2418 spr_register(env
, SPR_MPC_IC_DAT
, "IC_DAT",
2419 SPR_NOACCESS
, SPR_NOACCESS
,
2420 &spr_read_generic
, &spr_write_generic
,
2422 /* XXX : not implemented */
2423 spr_register(env
, SPR_MPC_DC_CST
, "DC_CST",
2424 SPR_NOACCESS
, SPR_NOACCESS
,
2425 &spr_read_generic
, &spr_write_generic
,
2427 /* XXX : not implemented */
2428 spr_register(env
, SPR_MPC_DC_ADR
, "DC_ADR",
2429 SPR_NOACCESS
, SPR_NOACCESS
,
2430 &spr_read_generic
, &spr_write_generic
,
2432 /* XXX : not implemented */
2433 spr_register(env
, SPR_MPC_DC_DAT
, "DC_DAT",
2434 SPR_NOACCESS
, SPR_NOACCESS
,
2435 &spr_read_generic
, &spr_write_generic
,
2437 /* XXX : not implemented */
2438 spr_register(env
, SPR_MPC_MI_CTR
, "MI_CTR",
2439 SPR_NOACCESS
, SPR_NOACCESS
,
2440 &spr_read_generic
, &spr_write_generic
,
2442 /* XXX : not implemented */
2443 spr_register(env
, SPR_MPC_MI_AP
, "MI_AP",
2444 SPR_NOACCESS
, SPR_NOACCESS
,
2445 &spr_read_generic
, &spr_write_generic
,
2447 /* XXX : not implemented */
2448 spr_register(env
, SPR_MPC_MI_EPN
, "MI_EPN",
2449 SPR_NOACCESS
, SPR_NOACCESS
,
2450 &spr_read_generic
, &spr_write_generic
,
2452 /* XXX : not implemented */
2453 spr_register(env
, SPR_MPC_MI_TWC
, "MI_TWC",
2454 SPR_NOACCESS
, SPR_NOACCESS
,
2455 &spr_read_generic
, &spr_write_generic
,
2457 /* XXX : not implemented */
2458 spr_register(env
, SPR_MPC_MI_RPN
, "MI_RPN",
2459 SPR_NOACCESS
, SPR_NOACCESS
,
2460 &spr_read_generic
, &spr_write_generic
,
2462 /* XXX : not implemented */
2463 spr_register(env
, SPR_MPC_MI_DBCAM
, "MI_DBCAM",
2464 SPR_NOACCESS
, SPR_NOACCESS
,
2465 &spr_read_generic
, &spr_write_generic
,
2467 /* XXX : not implemented */
2468 spr_register(env
, SPR_MPC_MI_DBRAM0
, "MI_DBRAM0",
2469 SPR_NOACCESS
, SPR_NOACCESS
,
2470 &spr_read_generic
, &spr_write_generic
,
2472 /* XXX : not implemented */
2473 spr_register(env
, SPR_MPC_MI_DBRAM1
, "MI_DBRAM1",
2474 SPR_NOACCESS
, SPR_NOACCESS
,
2475 &spr_read_generic
, &spr_write_generic
,
2477 /* XXX : not implemented */
2478 spr_register(env
, SPR_MPC_MD_CTR
, "MD_CTR",
2479 SPR_NOACCESS
, SPR_NOACCESS
,
2480 &spr_read_generic
, &spr_write_generic
,
2482 /* XXX : not implemented */
2483 spr_register(env
, SPR_MPC_MD_CASID
, "MD_CASID",
2484 SPR_NOACCESS
, SPR_NOACCESS
,
2485 &spr_read_generic
, &spr_write_generic
,
2487 /* XXX : not implemented */
2488 spr_register(env
, SPR_MPC_MD_AP
, "MD_AP",
2489 SPR_NOACCESS
, SPR_NOACCESS
,
2490 &spr_read_generic
, &spr_write_generic
,
2492 /* XXX : not implemented */
2493 spr_register(env
, SPR_MPC_MD_EPN
, "MD_EPN",
2494 SPR_NOACCESS
, SPR_NOACCESS
,
2495 &spr_read_generic
, &spr_write_generic
,
2497 /* XXX : not implemented */
2498 spr_register(env
, SPR_MPC_MD_TWB
, "MD_TWB",
2499 SPR_NOACCESS
, SPR_NOACCESS
,
2500 &spr_read_generic
, &spr_write_generic
,
2502 /* XXX : not implemented */
2503 spr_register(env
, SPR_MPC_MD_TWC
, "MD_TWC",
2504 SPR_NOACCESS
, SPR_NOACCESS
,
2505 &spr_read_generic
, &spr_write_generic
,
2507 /* XXX : not implemented */
2508 spr_register(env
, SPR_MPC_MD_RPN
, "MD_RPN",
2509 SPR_NOACCESS
, SPR_NOACCESS
,
2510 &spr_read_generic
, &spr_write_generic
,
2512 /* XXX : not implemented */
2513 spr_register(env
, SPR_MPC_MD_TW
, "MD_TW",
2514 SPR_NOACCESS
, SPR_NOACCESS
,
2515 &spr_read_generic
, &spr_write_generic
,
2517 /* XXX : not implemented */
2518 spr_register(env
, SPR_MPC_MD_DBCAM
, "MD_DBCAM",
2519 SPR_NOACCESS
, SPR_NOACCESS
,
2520 &spr_read_generic
, &spr_write_generic
,
2522 /* XXX : not implemented */
2523 spr_register(env
, SPR_MPC_MD_DBRAM0
, "MD_DBRAM0",
2524 SPR_NOACCESS
, SPR_NOACCESS
,
2525 &spr_read_generic
, &spr_write_generic
,
2527 /* XXX : not implemented */
2528 spr_register(env
, SPR_MPC_MD_DBRAM1
, "MD_DBRAM1",
2529 SPR_NOACCESS
, SPR_NOACCESS
,
2530 &spr_read_generic
, &spr_write_generic
,
2536 * AMR => SPR 29 (Power 2.04)
2537 * CTRL => SPR 136 (Power 2.04)
2538 * CTRL => SPR 152 (Power 2.04)
2539 * SCOMC => SPR 276 (64 bits ?)
2540 * SCOMD => SPR 277 (64 bits ?)
2541 * TBU40 => SPR 286 (Power 2.04 hypv)
2542 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2543 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2544 * HDSISR => SPR 306 (Power 2.04 hypv)
2545 * HDAR => SPR 307 (Power 2.04 hypv)
2546 * PURR => SPR 309 (Power 2.04 hypv)
2547 * HDEC => SPR 310 (Power 2.04 hypv)
2548 * HIOR => SPR 311 (hypv)
2549 * RMOR => SPR 312 (970)
2550 * HRMOR => SPR 313 (Power 2.04 hypv)
2551 * HSRR0 => SPR 314 (Power 2.04 hypv)
2552 * HSRR1 => SPR 315 (Power 2.04 hypv)
2553 * LPCR => SPR 316 (970)
2554 * LPIDR => SPR 317 (970)
2555 * SPEFSCR => SPR 512 (Power 2.04 emb)
2556 * EPR => SPR 702 (Power 2.04 emb)
2557 * perf => 768-783 (Power 2.04)
2558 * perf => 784-799 (Power 2.04)
2559 * PPR => SPR 896 (Power 2.04)
2560 * EPLC => SPR 947 (Power 2.04 emb)
2561 * EPSC => SPR 948 (Power 2.04 emb)
2562 * DABRX => 1015 (Power 2.04 hypv)
2563 * FPECR => SPR 1022 (?)
2564 * ... and more (thermal management, performance counters, ...)
2567 /*****************************************************************************/
2568 /* Exception vectors models */
2569 static void init_excp_4xx_real (CPUPPCState
*env
)
2571 #if !defined(CONFIG_USER_ONLY)
2572 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2573 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2574 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2575 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2576 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2577 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2578 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2579 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2580 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2581 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2582 env
->excp_prefix
= 0x00000000UL
;
2583 env
->ivor_mask
= 0x0000FFF0UL
;
2584 env
->ivpr_mask
= 0xFFFF0000UL
;
2585 /* Hardware reset vector */
2586 env
->hreset_vector
= 0xFFFFFFFCUL
;
2590 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2592 #if !defined(CONFIG_USER_ONLY)
2593 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2594 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2595 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2596 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2597 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2598 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2599 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2600 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2601 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2602 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2603 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2604 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2605 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2606 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2607 env
->excp_prefix
= 0x00000000UL
;
2608 env
->ivor_mask
= 0x0000FFF0UL
;
2609 env
->ivpr_mask
= 0xFFFF0000UL
;
2610 /* Hardware reset vector */
2611 env
->hreset_vector
= 0xFFFFFFFCUL
;
2615 static void init_excp_MPC5xx (CPUPPCState
*env
)
2617 #if !defined(CONFIG_USER_ONLY)
2618 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2619 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2620 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2621 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2622 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2623 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2624 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2625 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2626 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2627 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2628 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2629 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2630 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2631 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2632 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2633 env
->excp_prefix
= 0x00000000UL
;
2634 env
->ivor_mask
= 0x0000FFF0UL
;
2635 env
->ivpr_mask
= 0xFFFF0000UL
;
2636 /* Hardware reset vector */
2637 env
->hreset_vector
= 0xFFFFFFFCUL
;
2641 static void init_excp_MPC8xx (CPUPPCState
*env
)
2643 #if !defined(CONFIG_USER_ONLY)
2644 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2645 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2646 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2647 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2648 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2649 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2650 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2651 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2652 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2653 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2654 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2655 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2656 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2657 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001100;
2658 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001200;
2659 env
->excp_vectors
[POWERPC_EXCP_ITLBE
] = 0x00001300;
2660 env
->excp_vectors
[POWERPC_EXCP_DTLBE
] = 0x00001400;
2661 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2662 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2663 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2664 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2665 env
->excp_prefix
= 0x00000000UL
;
2666 env
->ivor_mask
= 0x0000FFF0UL
;
2667 env
->ivpr_mask
= 0xFFFF0000UL
;
2668 /* Hardware reset vector */
2669 env
->hreset_vector
= 0xFFFFFFFCUL
;
2673 static void init_excp_G2 (CPUPPCState
*env
)
2675 #if !defined(CONFIG_USER_ONLY)
2676 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2677 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2678 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2679 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2680 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2681 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2682 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2683 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2684 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2685 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2686 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2687 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2688 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2689 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2690 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2691 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2692 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2693 env
->excp_prefix
= 0x00000000UL
;
2694 /* Hardware reset vector */
2695 env
->hreset_vector
= 0xFFFFFFFCUL
;
2699 static void init_excp_e200 (CPUPPCState
*env
)
2701 #if !defined(CONFIG_USER_ONLY)
2702 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000FFC;
2703 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2704 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2705 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2706 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2707 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2708 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2709 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2710 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2711 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2712 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2713 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2714 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2715 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2716 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2717 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2718 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2719 env
->excp_vectors
[POWERPC_EXCP_SPEU
] = 0x00000000;
2720 env
->excp_vectors
[POWERPC_EXCP_EFPDI
] = 0x00000000;
2721 env
->excp_vectors
[POWERPC_EXCP_EFPRI
] = 0x00000000;
2722 env
->excp_prefix
= 0x00000000UL
;
2723 env
->ivor_mask
= 0x0000FFF7UL
;
2724 env
->ivpr_mask
= 0xFFFF0000UL
;
2725 /* Hardware reset vector */
2726 env
->hreset_vector
= 0xFFFFFFFCUL
;
2730 static void init_excp_BookE (CPUPPCState
*env
)
2732 #if !defined(CONFIG_USER_ONLY)
2733 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2734 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2735 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2736 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2737 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2738 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2739 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2740 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2741 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2742 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2743 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2744 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2745 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2746 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2747 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2748 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2749 env
->excp_prefix
= 0x00000000UL
;
2750 env
->ivor_mask
= 0x0000FFE0UL
;
2751 env
->ivpr_mask
= 0xFFFF0000UL
;
2752 /* Hardware reset vector */
2753 env
->hreset_vector
= 0xFFFFFFFCUL
;
2757 static void init_excp_601 (CPUPPCState
*env
)
2759 #if !defined(CONFIG_USER_ONLY)
2760 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2761 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2762 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2763 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2764 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2765 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2766 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2767 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2768 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2769 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2770 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2771 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2772 env
->excp_prefix
= 0xFFF00000UL
;
2773 /* Hardware reset vector */
2774 env
->hreset_vector
= 0x00000100UL
;
2778 static void init_excp_602 (CPUPPCState
*env
)
2780 #if !defined(CONFIG_USER_ONLY)
2781 /* XXX: exception prefix has a special behavior on 602 */
2782 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2783 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2784 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2785 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2786 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2787 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2788 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2789 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2790 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2791 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2792 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2793 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2794 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2795 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2796 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2797 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2798 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2799 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2800 env
->excp_prefix
= 0xFFF00000UL
;
2801 /* Hardware reset vector */
2802 env
->hreset_vector
= 0xFFFFFFFCUL
;
2806 static void init_excp_603 (CPUPPCState
*env
)
2808 #if !defined(CONFIG_USER_ONLY)
2809 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2810 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2811 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2812 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2813 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2814 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2815 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2816 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2817 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2818 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2819 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2820 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2821 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2822 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2823 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2824 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2825 env
->excp_prefix
= 0x00000000UL
;
2826 /* Hardware reset vector */
2827 env
->hreset_vector
= 0xFFFFFFFCUL
;
2831 static void init_excp_604 (CPUPPCState
*env
)
2833 #if !defined(CONFIG_USER_ONLY)
2834 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2835 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2836 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2837 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2838 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2839 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2840 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2841 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2842 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2843 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2844 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2845 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2846 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2847 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2848 env
->excp_prefix
= 0x00000000UL
;
2849 /* Hardware reset vector */
2850 env
->hreset_vector
= 0xFFFFFFFCUL
;
2854 #if defined(TARGET_PPC64)
2855 static void init_excp_620 (CPUPPCState
*env
)
2857 #if !defined(CONFIG_USER_ONLY)
2858 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2859 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2860 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2861 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2862 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2863 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2864 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2865 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2866 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2867 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2868 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2869 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2870 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2871 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2872 env
->excp_prefix
= 0xFFF00000UL
;
2873 /* Hardware reset vector */
2874 env
->hreset_vector
= 0x0000000000000100ULL
;
2877 #endif /* defined(TARGET_PPC64) */
2879 static void init_excp_7x0 (CPUPPCState
*env
)
2881 #if !defined(CONFIG_USER_ONLY)
2882 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2883 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2884 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2885 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2886 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2887 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2888 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2889 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2890 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2891 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2892 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2893 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2894 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2895 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2896 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2897 env
->excp_prefix
= 0x00000000UL
;
2898 /* Hardware reset vector */
2899 env
->hreset_vector
= 0xFFFFFFFCUL
;
2903 static void init_excp_750cl (CPUPPCState
*env
)
2905 #if !defined(CONFIG_USER_ONLY)
2906 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2907 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2908 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2909 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2910 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2911 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2912 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2913 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2914 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2915 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2916 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2917 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2918 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2919 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2920 env
->excp_prefix
= 0x00000000UL
;
2921 /* Hardware reset vector */
2922 env
->hreset_vector
= 0xFFFFFFFCUL
;
2926 static void init_excp_750cx (CPUPPCState
*env
)
2928 #if !defined(CONFIG_USER_ONLY)
2929 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2930 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2931 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2932 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2933 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2934 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2935 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2936 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2937 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2938 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2939 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2940 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2941 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2942 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2943 env
->excp_prefix
= 0x00000000UL
;
2944 /* Hardware reset vector */
2945 env
->hreset_vector
= 0xFFFFFFFCUL
;
2949 /* XXX: Check if this is correct */
2950 static void init_excp_7x5 (CPUPPCState
*env
)
2952 #if !defined(CONFIG_USER_ONLY)
2953 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2954 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2955 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2956 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2957 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2958 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2959 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2960 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2961 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2962 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2963 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2964 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2965 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2966 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2967 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2968 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2969 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2970 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2971 env
->excp_prefix
= 0x00000000UL
;
2972 /* Hardware reset vector */
2973 env
->hreset_vector
= 0xFFFFFFFCUL
;
2977 static void init_excp_7400 (CPUPPCState
*env
)
2979 #if !defined(CONFIG_USER_ONLY)
2980 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2981 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2982 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2983 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2984 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2985 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2986 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2987 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2988 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2989 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2990 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2991 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2992 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2993 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2994 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2995 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
2996 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2997 env
->excp_prefix
= 0x00000000UL
;
2998 /* Hardware reset vector */
2999 env
->hreset_vector
= 0xFFFFFFFCUL
;
3003 static void init_excp_7450 (CPUPPCState
*env
)
3005 #if !defined(CONFIG_USER_ONLY)
3006 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3007 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3008 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3009 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3010 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3011 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3012 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3013 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3014 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3015 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3016 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3017 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3018 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3019 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
3020 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
3021 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
3022 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3023 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3024 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
3025 env
->excp_prefix
= 0x00000000UL
;
3026 /* Hardware reset vector */
3027 env
->hreset_vector
= 0xFFFFFFFCUL
;
3031 #if defined (TARGET_PPC64)
3032 static void init_excp_970 (CPUPPCState
*env
)
3034 #if !defined(CONFIG_USER_ONLY)
3035 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3036 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3037 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3038 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
3039 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3040 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
3041 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3042 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3043 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3044 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3045 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3046 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
3047 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3048 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3049 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3050 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3051 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3052 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
3053 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
3054 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
3055 env
->excp_prefix
= 0x00000000FFF00000ULL
;
3056 /* Hardware reset vector */
3057 env
->hreset_vector
= 0x0000000000000100ULL
;
3062 /*****************************************************************************/
3063 /* Power management enable checks */
3064 static int check_pow_none (CPUPPCState
*env
)
3069 static int check_pow_nocheck (CPUPPCState
*env
)
3074 static int check_pow_hid0 (CPUPPCState
*env
)
3076 if (env
->spr
[SPR_HID0
] & 0x00E00000)
3082 static int check_pow_hid0_74xx (CPUPPCState
*env
)
3084 if (env
->spr
[SPR_HID0
] & 0x00600000)
3090 /*****************************************************************************/
3091 /* PowerPC implementations definitions */
3094 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3095 PPC_WRTEE | PPC_DCR | \
3096 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3098 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3099 PPC_4xx_COMMON | PPC_40x_EXCP)
3100 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3101 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3102 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3103 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3104 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3105 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3106 POWERPC_FLAG_BUS_CLK)
3107 #define check_pow_401 check_pow_nocheck
3109 static void init_proc_401 (CPUPPCState
*env
)
3112 gen_spr_401_403(env
);
3114 init_excp_4xx_real(env
);
3115 env
->dcache_line_size
= 32;
3116 env
->icache_line_size
= 32;
3117 /* Allocate hardware IRQ controller */
3118 ppc40x_irq_init(env
);
3122 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3123 PPC_DCR | PPC_WRTEE | \
3124 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3125 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3126 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3127 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3128 PPC_4xx_COMMON | PPC_40x_EXCP)
3129 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3130 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3131 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3132 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3133 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3134 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3135 POWERPC_FLAG_BUS_CLK)
3136 #define check_pow_401x2 check_pow_nocheck
3138 static void init_proc_401x2 (CPUPPCState
*env
)
3141 gen_spr_401_403(env
);
3143 gen_spr_compress(env
);
3144 /* Memory management */
3145 #if !defined(CONFIG_USER_ONLY)
3150 init_excp_4xx_softmmu(env
);
3151 env
->dcache_line_size
= 32;
3152 env
->icache_line_size
= 32;
3153 /* Allocate hardware IRQ controller */
3154 ppc40x_irq_init(env
);
3158 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3159 PPC_DCR | PPC_WRTEE | \
3160 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3161 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3162 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3163 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3164 PPC_4xx_COMMON | PPC_40x_EXCP)
3165 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3166 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3167 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3168 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3169 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3170 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3171 POWERPC_FLAG_BUS_CLK)
3172 #define check_pow_401x3 check_pow_nocheck
3174 __attribute__ (( unused
))
3175 static void init_proc_401x3 (CPUPPCState
*env
)
3178 gen_spr_401_403(env
);
3181 gen_spr_compress(env
);
3182 init_excp_4xx_softmmu(env
);
3183 env
->dcache_line_size
= 32;
3184 env
->icache_line_size
= 32;
3185 /* Allocate hardware IRQ controller */
3186 ppc40x_irq_init(env
);
3190 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3191 PPC_DCR | PPC_WRTEE | \
3192 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3193 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3194 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3195 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3196 PPC_4xx_COMMON | PPC_40x_EXCP)
3197 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3198 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3199 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3200 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3201 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3202 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3203 POWERPC_FLAG_BUS_CLK)
3204 #define check_pow_IOP480 check_pow_nocheck
3206 static void init_proc_IOP480 (CPUPPCState
*env
)
3209 gen_spr_401_403(env
);
3211 gen_spr_compress(env
);
3212 /* Memory management */
3213 #if !defined(CONFIG_USER_ONLY)
3218 init_excp_4xx_softmmu(env
);
3219 env
->dcache_line_size
= 32;
3220 env
->icache_line_size
= 32;
3221 /* Allocate hardware IRQ controller */
3222 ppc40x_irq_init(env
);
3226 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3227 PPC_DCR | PPC_WRTEE | \
3228 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3230 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3231 PPC_4xx_COMMON | PPC_40x_EXCP)
3232 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3233 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3234 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3235 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3236 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3237 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3238 POWERPC_FLAG_BUS_CLK)
3239 #define check_pow_403 check_pow_nocheck
3241 static void init_proc_403 (CPUPPCState
*env
)
3244 gen_spr_401_403(env
);
3246 gen_spr_403_real(env
);
3247 init_excp_4xx_real(env
);
3248 env
->dcache_line_size
= 32;
3249 env
->icache_line_size
= 32;
3250 /* Allocate hardware IRQ controller */
3251 ppc40x_irq_init(env
);
3254 /* PowerPC 403 GCX */
3255 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3256 PPC_DCR | PPC_WRTEE | \
3257 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3259 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3260 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3261 PPC_4xx_COMMON | PPC_40x_EXCP)
3262 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3263 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3264 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3265 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3266 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3267 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3268 POWERPC_FLAG_BUS_CLK)
3269 #define check_pow_403GCX check_pow_nocheck
3271 static void init_proc_403GCX (CPUPPCState
*env
)
3274 gen_spr_401_403(env
);
3276 gen_spr_403_real(env
);
3277 gen_spr_403_mmu(env
);
3278 /* Bus access control */
3279 /* not emulated, as Qemu never does speculative access */
3280 spr_register(env
, SPR_40x_SGR
, "SGR",
3281 SPR_NOACCESS
, SPR_NOACCESS
,
3282 &spr_read_generic
, &spr_write_generic
,
3284 /* not emulated, as Qemu do not emulate caches */
3285 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3286 SPR_NOACCESS
, SPR_NOACCESS
,
3287 &spr_read_generic
, &spr_write_generic
,
3289 /* Memory management */
3290 #if !defined(CONFIG_USER_ONLY)
3295 init_excp_4xx_softmmu(env
);
3296 env
->dcache_line_size
= 32;
3297 env
->icache_line_size
= 32;
3298 /* Allocate hardware IRQ controller */
3299 ppc40x_irq_init(env
);
3303 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3304 PPC_DCR | PPC_WRTEE | \
3305 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3306 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3307 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3308 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3309 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3310 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3311 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3312 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3313 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3314 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3315 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3316 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3317 #define check_pow_405 check_pow_nocheck
3319 static void init_proc_405 (CPUPPCState
*env
)
3325 /* Bus access control */
3326 /* not emulated, as Qemu never does speculative access */
3327 spr_register(env
, SPR_40x_SGR
, "SGR",
3328 SPR_NOACCESS
, SPR_NOACCESS
,
3329 &spr_read_generic
, &spr_write_generic
,
3331 /* not emulated, as Qemu do not emulate caches */
3332 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3333 SPR_NOACCESS
, SPR_NOACCESS
,
3334 &spr_read_generic
, &spr_write_generic
,
3336 /* Memory management */
3337 #if !defined(CONFIG_USER_ONLY)
3342 init_excp_4xx_softmmu(env
);
3343 env
->dcache_line_size
= 32;
3344 env
->icache_line_size
= 32;
3345 /* Allocate hardware IRQ controller */
3346 ppc40x_irq_init(env
);
3349 /* PowerPC 440 EP */
3350 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3351 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3352 PPC_CACHE | PPC_CACHE_ICBI | \
3353 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3355 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3357 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3358 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3359 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3360 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3361 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3362 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3363 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3364 #define check_pow_440EP check_pow_nocheck
3366 __attribute__ (( unused
))
3367 static void init_proc_440EP (CPUPPCState
*env
)
3371 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3373 gen_spr_usprgh(env
);
3374 /* Processor identification */
3375 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3376 SPR_NOACCESS
, SPR_NOACCESS
,
3377 &spr_read_generic
, &spr_write_pir
,
3379 /* XXX : not implemented */
3380 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3381 SPR_NOACCESS
, SPR_NOACCESS
,
3382 &spr_read_generic
, &spr_write_generic
,
3384 /* XXX : not implemented */
3385 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3386 SPR_NOACCESS
, SPR_NOACCESS
,
3387 &spr_read_generic
, &spr_write_generic
,
3389 /* XXX : not implemented */
3390 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3391 SPR_NOACCESS
, SPR_NOACCESS
,
3392 &spr_read_generic
, &spr_write_generic
,
3394 /* XXX : not implemented */
3395 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3396 SPR_NOACCESS
, SPR_NOACCESS
,
3397 &spr_read_generic
, &spr_write_generic
,
3399 /* XXX : not implemented */
3400 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3401 SPR_NOACCESS
, SPR_NOACCESS
,
3402 &spr_read_generic
, &spr_write_generic
,
3404 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3405 SPR_NOACCESS
, SPR_NOACCESS
,
3406 &spr_read_generic
, &spr_write_generic
,
3408 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3409 SPR_NOACCESS
, SPR_NOACCESS
,
3410 &spr_read_generic
, &spr_write_generic
,
3412 /* XXX : not implemented */
3413 spr_register(env
, SPR_440_CCR1
, "CCR1",
3414 SPR_NOACCESS
, SPR_NOACCESS
,
3415 &spr_read_generic
, &spr_write_generic
,
3417 /* Memory management */
3418 #if !defined(CONFIG_USER_ONLY)
3423 init_excp_BookE(env
);
3424 env
->dcache_line_size
= 32;
3425 env
->icache_line_size
= 32;
3426 /* XXX: TODO: allocate internal IRQ controller */
3429 /* PowerPC 440 GP */
3430 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3431 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3432 PPC_CACHE | PPC_CACHE_ICBI | \
3433 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3434 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3435 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3437 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3438 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3439 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3440 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3441 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3442 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3443 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3444 #define check_pow_440GP check_pow_nocheck
3446 __attribute__ (( unused
))
3447 static void init_proc_440GP (CPUPPCState
*env
)
3451 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3453 gen_spr_usprgh(env
);
3454 /* Processor identification */
3455 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3456 SPR_NOACCESS
, SPR_NOACCESS
,
3457 &spr_read_generic
, &spr_write_pir
,
3459 /* XXX : not implemented */
3460 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3461 SPR_NOACCESS
, SPR_NOACCESS
,
3462 &spr_read_generic
, &spr_write_generic
,
3464 /* XXX : not implemented */
3465 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3466 SPR_NOACCESS
, SPR_NOACCESS
,
3467 &spr_read_generic
, &spr_write_generic
,
3469 /* XXX : not implemented */
3470 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3471 SPR_NOACCESS
, SPR_NOACCESS
,
3472 &spr_read_generic
, &spr_write_generic
,
3474 /* XXX : not implemented */
3475 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3476 SPR_NOACCESS
, SPR_NOACCESS
,
3477 &spr_read_generic
, &spr_write_generic
,
3479 /* Memory management */
3480 #if !defined(CONFIG_USER_ONLY)
3485 init_excp_BookE(env
);
3486 env
->dcache_line_size
= 32;
3487 env
->icache_line_size
= 32;
3488 /* XXX: TODO: allocate internal IRQ controller */
3492 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3493 PPC_DCR | PPC_WRTEE | \
3494 PPC_CACHE | PPC_CACHE_ICBI | \
3495 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3497 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3499 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3500 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3501 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3502 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3503 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3504 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3505 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3506 #define check_pow_440x4 check_pow_nocheck
3508 __attribute__ (( unused
))
3509 static void init_proc_440x4 (CPUPPCState
*env
)
3513 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3515 gen_spr_usprgh(env
);
3516 /* Processor identification */
3517 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3518 SPR_NOACCESS
, SPR_NOACCESS
,
3519 &spr_read_generic
, &spr_write_pir
,
3521 /* XXX : not implemented */
3522 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3523 SPR_NOACCESS
, SPR_NOACCESS
,
3524 &spr_read_generic
, &spr_write_generic
,
3526 /* XXX : not implemented */
3527 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3528 SPR_NOACCESS
, SPR_NOACCESS
,
3529 &spr_read_generic
, &spr_write_generic
,
3531 /* XXX : not implemented */
3532 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3533 SPR_NOACCESS
, SPR_NOACCESS
,
3534 &spr_read_generic
, &spr_write_generic
,
3536 /* XXX : not implemented */
3537 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3538 SPR_NOACCESS
, SPR_NOACCESS
,
3539 &spr_read_generic
, &spr_write_generic
,
3541 /* Memory management */
3542 #if !defined(CONFIG_USER_ONLY)
3547 init_excp_BookE(env
);
3548 env
->dcache_line_size
= 32;
3549 env
->icache_line_size
= 32;
3550 /* XXX: TODO: allocate internal IRQ controller */
3554 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3555 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3556 PPC_CACHE | PPC_CACHE_ICBI | \
3557 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3559 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3561 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3562 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3563 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3564 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3565 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3566 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3567 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3568 #define check_pow_440x5 check_pow_nocheck
3570 __attribute__ (( unused
))
3571 static void init_proc_440x5 (CPUPPCState
*env
)
3575 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3577 gen_spr_usprgh(env
);
3578 /* Processor identification */
3579 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3580 SPR_NOACCESS
, SPR_NOACCESS
,
3581 &spr_read_generic
, &spr_write_pir
,
3583 /* XXX : not implemented */
3584 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3585 SPR_NOACCESS
, SPR_NOACCESS
,
3586 &spr_read_generic
, &spr_write_generic
,
3588 /* XXX : not implemented */
3589 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3590 SPR_NOACCESS
, SPR_NOACCESS
,
3591 &spr_read_generic
, &spr_write_generic
,
3593 /* XXX : not implemented */
3594 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3595 SPR_NOACCESS
, SPR_NOACCESS
,
3596 &spr_read_generic
, &spr_write_generic
,
3598 /* XXX : not implemented */
3599 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3600 SPR_NOACCESS
, SPR_NOACCESS
,
3601 &spr_read_generic
, &spr_write_generic
,
3603 /* XXX : not implemented */
3604 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3605 SPR_NOACCESS
, SPR_NOACCESS
,
3606 &spr_read_generic
, &spr_write_generic
,
3608 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3609 SPR_NOACCESS
, SPR_NOACCESS
,
3610 &spr_read_generic
, &spr_write_generic
,
3612 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3613 SPR_NOACCESS
, SPR_NOACCESS
,
3614 &spr_read_generic
, &spr_write_generic
,
3616 /* XXX : not implemented */
3617 spr_register(env
, SPR_440_CCR1
, "CCR1",
3618 SPR_NOACCESS
, SPR_NOACCESS
,
3619 &spr_read_generic
, &spr_write_generic
,
3621 /* Memory management */
3622 #if !defined(CONFIG_USER_ONLY)
3627 init_excp_BookE(env
);
3628 env
->dcache_line_size
= 32;
3629 env
->icache_line_size
= 32;
3630 /* XXX: TODO: allocate internal IRQ controller */
3633 /* PowerPC 460 (guessed) */
3634 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3635 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3636 PPC_WRTEE | PPC_MFAPIDI | \
3637 PPC_CACHE | PPC_CACHE_ICBI | \
3638 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3639 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3640 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3642 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3643 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3644 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3645 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3646 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3647 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3648 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3649 #define check_pow_460 check_pow_nocheck
3651 __attribute__ (( unused
))
3652 static void init_proc_460 (CPUPPCState
*env
)
3656 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3658 gen_spr_usprgh(env
);
3659 /* Processor identification */
3660 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3661 SPR_NOACCESS
, SPR_NOACCESS
,
3662 &spr_read_generic
, &spr_write_pir
,
3664 /* XXX : not implemented */
3665 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3666 SPR_NOACCESS
, SPR_NOACCESS
,
3667 &spr_read_generic
, &spr_write_generic
,
3669 /* XXX : not implemented */
3670 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3671 SPR_NOACCESS
, SPR_NOACCESS
,
3672 &spr_read_generic
, &spr_write_generic
,
3674 /* XXX : not implemented */
3675 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3676 SPR_NOACCESS
, SPR_NOACCESS
,
3677 &spr_read_generic
, &spr_write_generic
,
3679 /* XXX : not implemented */
3680 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3681 SPR_NOACCESS
, SPR_NOACCESS
,
3682 &spr_read_generic
, &spr_write_generic
,
3684 /* XXX : not implemented */
3685 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3686 SPR_NOACCESS
, SPR_NOACCESS
,
3687 &spr_read_generic
, &spr_write_generic
,
3689 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3690 SPR_NOACCESS
, SPR_NOACCESS
,
3691 &spr_read_generic
, &spr_write_generic
,
3693 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3694 SPR_NOACCESS
, SPR_NOACCESS
,
3695 &spr_read_generic
, &spr_write_generic
,
3697 /* XXX : not implemented */
3698 spr_register(env
, SPR_440_CCR1
, "CCR1",
3699 SPR_NOACCESS
, SPR_NOACCESS
,
3700 &spr_read_generic
, &spr_write_generic
,
3702 /* XXX : not implemented */
3703 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3704 &spr_read_generic
, &spr_write_generic
,
3705 &spr_read_generic
, &spr_write_generic
,
3707 /* Memory management */
3708 #if !defined(CONFIG_USER_ONLY)
3713 init_excp_BookE(env
);
3714 env
->dcache_line_size
= 32;
3715 env
->icache_line_size
= 32;
3716 /* XXX: TODO: allocate internal IRQ controller */
3719 /* PowerPC 460F (guessed) */
3720 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3721 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3722 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3723 PPC_FLOAT_STFIWX | \
3724 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3725 PPC_WRTEE | PPC_MFAPIDI | \
3726 PPC_CACHE | PPC_CACHE_ICBI | \
3727 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3728 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3729 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3731 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3732 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3733 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3734 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3735 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3736 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3737 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3738 #define check_pow_460F check_pow_nocheck
3740 __attribute__ (( unused
))
3741 static void init_proc_460F (CPUPPCState
*env
)
3745 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3747 gen_spr_usprgh(env
);
3748 /* Processor identification */
3749 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3750 SPR_NOACCESS
, SPR_NOACCESS
,
3751 &spr_read_generic
, &spr_write_pir
,
3753 /* XXX : not implemented */
3754 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3755 SPR_NOACCESS
, SPR_NOACCESS
,
3756 &spr_read_generic
, &spr_write_generic
,
3758 /* XXX : not implemented */
3759 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3760 SPR_NOACCESS
, SPR_NOACCESS
,
3761 &spr_read_generic
, &spr_write_generic
,
3763 /* XXX : not implemented */
3764 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3765 SPR_NOACCESS
, SPR_NOACCESS
,
3766 &spr_read_generic
, &spr_write_generic
,
3768 /* XXX : not implemented */
3769 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3770 SPR_NOACCESS
, SPR_NOACCESS
,
3771 &spr_read_generic
, &spr_write_generic
,
3773 /* XXX : not implemented */
3774 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3775 SPR_NOACCESS
, SPR_NOACCESS
,
3776 &spr_read_generic
, &spr_write_generic
,
3778 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3779 SPR_NOACCESS
, SPR_NOACCESS
,
3780 &spr_read_generic
, &spr_write_generic
,
3782 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3783 SPR_NOACCESS
, SPR_NOACCESS
,
3784 &spr_read_generic
, &spr_write_generic
,
3786 /* XXX : not implemented */
3787 spr_register(env
, SPR_440_CCR1
, "CCR1",
3788 SPR_NOACCESS
, SPR_NOACCESS
,
3789 &spr_read_generic
, &spr_write_generic
,
3791 /* XXX : not implemented */
3792 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3793 &spr_read_generic
, &spr_write_generic
,
3794 &spr_read_generic
, &spr_write_generic
,
3796 /* Memory management */
3797 #if !defined(CONFIG_USER_ONLY)
3802 init_excp_BookE(env
);
3803 env
->dcache_line_size
= 32;
3804 env
->icache_line_size
= 32;
3805 /* XXX: TODO: allocate internal IRQ controller */
3808 /* Freescale 5xx cores (aka RCPU) */
3809 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3810 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3811 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3813 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3814 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3815 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3816 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3817 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3818 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3819 POWERPC_FLAG_BUS_CLK)
3820 #define check_pow_MPC5xx check_pow_none
3822 __attribute__ (( unused
))
3823 static void init_proc_MPC5xx (CPUPPCState
*env
)
3827 gen_spr_5xx_8xx(env
);
3829 init_excp_MPC5xx(env
);
3830 env
->dcache_line_size
= 32;
3831 env
->icache_line_size
= 32;
3832 /* XXX: TODO: allocate internal IRQ controller */
3835 /* Freescale 8xx cores (aka PowerQUICC) */
3836 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3837 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3838 PPC_CACHE_ICBI | PPC_MFTB)
3839 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3840 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3841 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3842 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3843 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
3844 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3845 POWERPC_FLAG_BUS_CLK)
3846 #define check_pow_MPC8xx check_pow_none
3848 __attribute__ (( unused
))
3849 static void init_proc_MPC8xx (CPUPPCState
*env
)
3853 gen_spr_5xx_8xx(env
);
3855 init_excp_MPC8xx(env
);
3856 env
->dcache_line_size
= 32;
3857 env
->icache_line_size
= 32;
3858 /* XXX: TODO: allocate internal IRQ controller */
3861 /* Freescale 82xx cores (aka PowerQUICC-II) */
3863 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3864 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3865 PPC_FLOAT_STFIWX | \
3866 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3867 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3868 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3869 PPC_SEGMENT | PPC_EXTERN)
3870 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3871 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3872 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3873 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3874 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3875 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3876 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3877 #define check_pow_G2 check_pow_hid0
3879 static void init_proc_G2 (CPUPPCState
*env
)
3881 gen_spr_ne_601(env
);
3882 gen_spr_G2_755(env
);
3886 /* External access control */
3887 /* XXX : not implemented */
3888 spr_register(env
, SPR_EAR
, "EAR",
3889 SPR_NOACCESS
, SPR_NOACCESS
,
3890 &spr_read_generic
, &spr_write_generic
,
3892 /* Hardware implementation register */
3893 /* XXX : not implemented */
3894 spr_register(env
, SPR_HID0
, "HID0",
3895 SPR_NOACCESS
, SPR_NOACCESS
,
3896 &spr_read_generic
, &spr_write_generic
,
3898 /* XXX : not implemented */
3899 spr_register(env
, SPR_HID1
, "HID1",
3900 SPR_NOACCESS
, SPR_NOACCESS
,
3901 &spr_read_generic
, &spr_write_generic
,
3903 /* XXX : not implemented */
3904 spr_register(env
, SPR_HID2
, "HID2",
3905 SPR_NOACCESS
, SPR_NOACCESS
,
3906 &spr_read_generic
, &spr_write_generic
,
3908 /* Memory management */
3911 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3913 env
->dcache_line_size
= 32;
3914 env
->icache_line_size
= 32;
3915 /* Allocate hardware IRQ controller */
3916 ppc6xx_irq_init(env
);
3920 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3921 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3922 PPC_FLOAT_STFIWX | \
3923 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3924 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3925 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3926 PPC_SEGMENT | PPC_EXTERN)
3927 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3928 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3929 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3930 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3931 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3932 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3933 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3934 #define check_pow_G2LE check_pow_hid0
3936 static void init_proc_G2LE (CPUPPCState
*env
)
3938 gen_spr_ne_601(env
);
3939 gen_spr_G2_755(env
);
3943 /* External access control */
3944 /* XXX : not implemented */
3945 spr_register(env
, SPR_EAR
, "EAR",
3946 SPR_NOACCESS
, SPR_NOACCESS
,
3947 &spr_read_generic
, &spr_write_generic
,
3949 /* Hardware implementation register */
3950 /* XXX : not implemented */
3951 spr_register(env
, SPR_HID0
, "HID0",
3952 SPR_NOACCESS
, SPR_NOACCESS
,
3953 &spr_read_generic
, &spr_write_generic
,
3955 /* XXX : not implemented */
3956 spr_register(env
, SPR_HID1
, "HID1",
3957 SPR_NOACCESS
, SPR_NOACCESS
,
3958 &spr_read_generic
, &spr_write_generic
,
3960 /* XXX : not implemented */
3961 spr_register(env
, SPR_HID2
, "HID2",
3962 SPR_NOACCESS
, SPR_NOACCESS
,
3963 &spr_read_generic
, &spr_write_generic
,
3965 /* Memory management */
3968 gen_6xx_7xx_soft_tlb(env
, 64, 2);
3970 env
->dcache_line_size
= 32;
3971 env
->icache_line_size
= 32;
3972 /* Allocate hardware IRQ controller */
3973 ppc6xx_irq_init(env
);
3977 /* XXX: unimplemented instructions:
3984 * all SPE multiply-accumulate instructions
3986 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
3987 PPC_SPE | PPC_SPE_SINGLE | \
3988 PPC_WRTEE | PPC_RFDI | \
3989 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
3990 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3991 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3993 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3994 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3995 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3996 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3997 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3998 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3999 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4000 POWERPC_FLAG_BUS_CLK)
4001 #define check_pow_e200 check_pow_hid0
4003 __attribute__ (( unused
))
4004 static void init_proc_e200 (CPUPPCState
*env
)
4008 gen_spr_BookE(env
, 0x000000070000FFFFULL
);
4009 /* XXX : not implemented */
4010 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4011 SPR_NOACCESS
, SPR_NOACCESS
,
4012 &spr_read_generic
, &spr_write_generic
,
4014 /* Memory management */
4015 gen_spr_BookE_FSL(env
, 0x0000005D);
4016 /* XXX : not implemented */
4017 spr_register(env
, SPR_HID0
, "HID0",
4018 SPR_NOACCESS
, SPR_NOACCESS
,
4019 &spr_read_generic
, &spr_write_generic
,
4021 /* XXX : not implemented */
4022 spr_register(env
, SPR_HID1
, "HID1",
4023 SPR_NOACCESS
, SPR_NOACCESS
,
4024 &spr_read_generic
, &spr_write_generic
,
4026 /* XXX : not implemented */
4027 spr_register(env
, SPR_Exxx_ALTCTXCR
, "ALTCTXCR",
4028 SPR_NOACCESS
, SPR_NOACCESS
,
4029 &spr_read_generic
, &spr_write_generic
,
4031 /* XXX : not implemented */
4032 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4033 SPR_NOACCESS
, SPR_NOACCESS
,
4034 &spr_read_generic
, &spr_write_generic
,
4036 /* XXX : not implemented */
4037 spr_register(env
, SPR_Exxx_CTXCR
, "CTXCR",
4038 SPR_NOACCESS
, SPR_NOACCESS
,
4039 &spr_read_generic
, &spr_write_generic
,
4041 /* XXX : not implemented */
4042 spr_register(env
, SPR_Exxx_DBCNT
, "DBCNT",
4043 SPR_NOACCESS
, SPR_NOACCESS
,
4044 &spr_read_generic
, &spr_write_generic
,
4046 /* XXX : not implemented */
4047 spr_register(env
, SPR_Exxx_DBCR3
, "DBCR3",
4048 SPR_NOACCESS
, SPR_NOACCESS
,
4049 &spr_read_generic
, &spr_write_generic
,
4051 /* XXX : not implemented */
4052 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4053 SPR_NOACCESS
, SPR_NOACCESS
,
4054 &spr_read_generic
, &spr_write_generic
,
4056 /* XXX : not implemented */
4057 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4058 SPR_NOACCESS
, SPR_NOACCESS
,
4059 &spr_read_generic
, &spr_write_generic
,
4061 /* XXX : not implemented */
4062 spr_register(env
, SPR_Exxx_L1FINV0
, "L1FINV0",
4063 SPR_NOACCESS
, SPR_NOACCESS
,
4064 &spr_read_generic
, &spr_write_generic
,
4066 /* XXX : not implemented */
4067 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
4068 SPR_NOACCESS
, SPR_NOACCESS
,
4069 &spr_read_generic
, &spr_write_generic
,
4071 /* XXX : not implemented */
4072 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
4073 SPR_NOACCESS
, SPR_NOACCESS
,
4074 &spr_read_generic
, &spr_write_generic
,
4076 /* XXX : not implemented */
4077 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
4078 SPR_NOACCESS
, SPR_NOACCESS
,
4079 &spr_read_generic
, &spr_write_generic
,
4081 /* XXX : not implemented */
4082 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
4083 SPR_NOACCESS
, SPR_NOACCESS
,
4084 &spr_read_generic
, &spr_write_generic
,
4086 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
4087 SPR_NOACCESS
, SPR_NOACCESS
,
4088 &spr_read_generic
, &spr_write_generic
,
4090 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
4091 SPR_NOACCESS
, SPR_NOACCESS
,
4092 &spr_read_generic
, &spr_write_generic
,
4094 #if !defined(CONFIG_USER_ONLY)
4099 init_excp_e200(env
);
4100 env
->dcache_line_size
= 32;
4101 env
->icache_line_size
= 32;
4102 /* XXX: TODO: allocate internal IRQ controller */
4106 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4107 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4108 PPC_FLOAT_STFIWX | \
4109 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4110 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4111 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4112 PPC_SEGMENT | PPC_EXTERN)
4113 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4114 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4115 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4116 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4117 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4118 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4119 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4120 #define check_pow_e300 check_pow_hid0
4122 __attribute__ (( unused
))
4123 static void init_proc_e300 (CPUPPCState
*env
)
4125 gen_spr_ne_601(env
);
4129 /* hardware implementation registers */
4130 /* XXX : not implemented */
4131 spr_register(env
, SPR_HID0
, "HID0",
4132 SPR_NOACCESS
, SPR_NOACCESS
,
4133 &spr_read_generic
, &spr_write_generic
,
4135 /* XXX : not implemented */
4136 spr_register(env
, SPR_HID1
, "HID1",
4137 SPR_NOACCESS
, SPR_NOACCESS
,
4138 &spr_read_generic
, &spr_write_generic
,
4140 /* Memory management */
4142 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4144 env
->dcache_line_size
= 32;
4145 env
->icache_line_size
= 32;
4146 /* Allocate hardware IRQ controller */
4147 ppc6xx_irq_init(env
);
4151 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4152 PPC_SPE | PPC_SPE_SINGLE | \
4153 PPC_WRTEE | PPC_RFDI | \
4154 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4155 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4156 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4158 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4159 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4160 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4161 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4162 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4163 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4164 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4165 POWERPC_FLAG_BUS_CLK)
4166 #define check_pow_e500v1 check_pow_hid0
4167 #define init_proc_e500v1 init_proc_e500
4170 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4171 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4172 PPC_WRTEE | PPC_RFDI | \
4173 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4174 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4175 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4177 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4178 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4179 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4180 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4181 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4182 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4183 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4184 POWERPC_FLAG_BUS_CLK)
4185 #define check_pow_e500v2 check_pow_hid0
4186 #define init_proc_e500v2 init_proc_e500
4188 __attribute__ (( unused
))
4189 static void init_proc_e500 (CPUPPCState
*env
)
4193 gen_spr_BookE(env
, 0x0000000F0000FD7FULL
);
4194 /* Processor identification */
4195 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
4196 SPR_NOACCESS
, SPR_NOACCESS
,
4197 &spr_read_generic
, &spr_write_pir
,
4199 /* XXX : not implemented */
4200 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4201 SPR_NOACCESS
, SPR_NOACCESS
,
4202 &spr_read_generic
, &spr_write_generic
,
4204 /* Memory management */
4205 #if !defined(CONFIG_USER_ONLY)
4208 gen_spr_BookE_FSL(env
, 0x0000005F);
4209 /* XXX : not implemented */
4210 spr_register(env
, SPR_HID0
, "HID0",
4211 SPR_NOACCESS
, SPR_NOACCESS
,
4212 &spr_read_generic
, &spr_write_generic
,
4214 /* XXX : not implemented */
4215 spr_register(env
, SPR_HID1
, "HID1",
4216 SPR_NOACCESS
, SPR_NOACCESS
,
4217 &spr_read_generic
, &spr_write_generic
,
4219 /* XXX : not implemented */
4220 spr_register(env
, SPR_Exxx_BBEAR
, "BBEAR",
4221 SPR_NOACCESS
, SPR_NOACCESS
,
4222 &spr_read_generic
, &spr_write_generic
,
4224 /* XXX : not implemented */
4225 spr_register(env
, SPR_Exxx_BBTAR
, "BBTAR",
4226 SPR_NOACCESS
, SPR_NOACCESS
,
4227 &spr_read_generic
, &spr_write_generic
,
4229 /* XXX : not implemented */
4230 spr_register(env
, SPR_Exxx_MCAR
, "MCAR",
4231 SPR_NOACCESS
, SPR_NOACCESS
,
4232 &spr_read_generic
, &spr_write_generic
,
4234 /* XXX : not implemented */
4235 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
4236 SPR_NOACCESS
, SPR_NOACCESS
,
4237 &spr_read_generic
, &spr_write_generic
,
4239 /* XXX : not implemented */
4240 spr_register(env
, SPR_Exxx_NPIDR
, "NPIDR",
4241 SPR_NOACCESS
, SPR_NOACCESS
,
4242 &spr_read_generic
, &spr_write_generic
,
4244 /* XXX : not implemented */
4245 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4246 SPR_NOACCESS
, SPR_NOACCESS
,
4247 &spr_read_generic
, &spr_write_generic
,
4249 /* XXX : not implemented */
4250 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4251 SPR_NOACCESS
, SPR_NOACCESS
,
4252 &spr_read_generic
, &spr_write_generic
,
4254 /* XXX : not implemented */
4255 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4256 SPR_NOACCESS
, SPR_NOACCESS
,
4257 &spr_read_generic
, &spr_write_generic
,
4259 /* XXX : not implemented */
4260 spr_register(env
, SPR_Exxx_L1CSR1
, "L1CSR1",
4261 SPR_NOACCESS
, SPR_NOACCESS
,
4262 &spr_read_generic
, &spr_write_generic
,
4264 /* XXX : not implemented */
4265 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
4266 SPR_NOACCESS
, SPR_NOACCESS
,
4267 &spr_read_generic
, &spr_write_generic
,
4269 /* XXX : not implemented */
4270 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
4271 SPR_NOACCESS
, SPR_NOACCESS
,
4272 &spr_read_generic
, &spr_write_generic
,
4274 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
4275 SPR_NOACCESS
, SPR_NOACCESS
,
4276 &spr_read_generic
, &spr_write_generic
,
4278 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
4279 SPR_NOACCESS
, SPR_NOACCESS
,
4280 &spr_read_generic
, &spr_write_generic
,
4282 #if !defined(CONFIG_USER_ONLY)
4287 init_excp_e200(env
);
4288 env
->dcache_line_size
= 32;
4289 env
->icache_line_size
= 32;
4290 /* XXX: TODO: allocate internal IRQ controller */
4293 /* Non-embedded PowerPC */
4295 /* POWER : same as 601, without mfmsr, mfsr */
4297 #define POWERPC_INSNS_POWER (XXX_TODO)
4298 /* POWER RSC (from RAD6000) */
4299 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4303 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4306 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4307 PPC_SEGMENT | PPC_EXTERN)
4308 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4309 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4310 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4311 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4312 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4313 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4314 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4315 #define check_pow_601 check_pow_none
4317 static void init_proc_601 (CPUPPCState
*env
)
4319 gen_spr_ne_601(env
);
4321 /* Hardware implementation registers */
4322 /* XXX : not implemented */
4323 spr_register(env
, SPR_HID0
, "HID0",
4324 SPR_NOACCESS
, SPR_NOACCESS
,
4325 &spr_read_generic
, &spr_write_hid0_601
,
4327 /* XXX : not implemented */
4328 spr_register(env
, SPR_HID1
, "HID1",
4329 SPR_NOACCESS
, SPR_NOACCESS
,
4330 &spr_read_generic
, &spr_write_generic
,
4332 /* XXX : not implemented */
4333 spr_register(env
, SPR_601_HID2
, "HID2",
4334 SPR_NOACCESS
, SPR_NOACCESS
,
4335 &spr_read_generic
, &spr_write_generic
,
4337 /* XXX : not implemented */
4338 spr_register(env
, SPR_601_HID5
, "HID5",
4339 SPR_NOACCESS
, SPR_NOACCESS
,
4340 &spr_read_generic
, &spr_write_generic
,
4342 /* Memory management */
4344 /* XXX: beware that dcache line size is 64
4345 * but dcbz uses 32 bytes "sectors"
4346 * XXX: this breaks clcs instruction !
4348 env
->dcache_line_size
= 32;
4349 env
->icache_line_size
= 64;
4350 /* Allocate hardware IRQ controller */
4351 ppc6xx_irq_init(env
);
4355 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4357 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4358 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4359 PPC_SEGMENT | PPC_EXTERN)
4360 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4361 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4362 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4363 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4364 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4365 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4366 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4367 #define check_pow_601v check_pow_none
4369 static void init_proc_601v (CPUPPCState
*env
)
4372 /* XXX : not implemented */
4373 spr_register(env
, SPR_601_HID15
, "HID15",
4374 SPR_NOACCESS
, SPR_NOACCESS
,
4375 &spr_read_generic
, &spr_write_generic
,
4380 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4382 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4384 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4385 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4386 PPC_SEGMENT | PPC_602_SPEC)
4387 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4388 /* XXX: 602 MMU is quite specific. Should add a special case */
4389 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4390 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4391 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4392 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4393 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4394 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4395 #define check_pow_602 check_pow_hid0
4397 static void init_proc_602 (CPUPPCState
*env
)
4399 gen_spr_ne_601(env
);
4403 /* hardware implementation registers */
4404 /* XXX : not implemented */
4405 spr_register(env
, SPR_HID0
, "HID0",
4406 SPR_NOACCESS
, SPR_NOACCESS
,
4407 &spr_read_generic
, &spr_write_generic
,
4409 /* XXX : not implemented */
4410 spr_register(env
, SPR_HID1
, "HID1",
4411 SPR_NOACCESS
, SPR_NOACCESS
,
4412 &spr_read_generic
, &spr_write_generic
,
4414 /* Memory management */
4416 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4418 env
->dcache_line_size
= 32;
4419 env
->icache_line_size
= 32;
4420 /* Allocate hardware IRQ controller */
4421 ppc6xx_irq_init(env
);
4425 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4426 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4427 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4428 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4429 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4430 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4431 PPC_SEGMENT | PPC_EXTERN)
4432 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4433 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4434 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4435 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4436 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4437 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4438 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4439 #define check_pow_603 check_pow_hid0
4441 static void init_proc_603 (CPUPPCState
*env
)
4443 gen_spr_ne_601(env
);
4447 /* hardware implementation registers */
4448 /* XXX : not implemented */
4449 spr_register(env
, SPR_HID0
, "HID0",
4450 SPR_NOACCESS
, SPR_NOACCESS
,
4451 &spr_read_generic
, &spr_write_generic
,
4453 /* XXX : not implemented */
4454 spr_register(env
, SPR_HID1
, "HID1",
4455 SPR_NOACCESS
, SPR_NOACCESS
,
4456 &spr_read_generic
, &spr_write_generic
,
4458 /* Memory management */
4460 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4462 env
->dcache_line_size
= 32;
4463 env
->icache_line_size
= 32;
4464 /* Allocate hardware IRQ controller */
4465 ppc6xx_irq_init(env
);
4469 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4470 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4471 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4472 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4473 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4474 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4475 PPC_SEGMENT | PPC_EXTERN)
4476 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4477 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4478 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4479 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4480 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4481 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4482 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4483 #define check_pow_603E check_pow_hid0
4485 static void init_proc_603E (CPUPPCState
*env
)
4487 gen_spr_ne_601(env
);
4491 /* hardware implementation registers */
4492 /* XXX : not implemented */
4493 spr_register(env
, SPR_HID0
, "HID0",
4494 SPR_NOACCESS
, SPR_NOACCESS
,
4495 &spr_read_generic
, &spr_write_generic
,
4497 /* XXX : not implemented */
4498 spr_register(env
, SPR_HID1
, "HID1",
4499 SPR_NOACCESS
, SPR_NOACCESS
,
4500 &spr_read_generic
, &spr_write_generic
,
4502 /* XXX : not implemented */
4503 spr_register(env
, SPR_IABR
, "IABR",
4504 SPR_NOACCESS
, SPR_NOACCESS
,
4505 &spr_read_generic
, &spr_write_generic
,
4507 /* Memory management */
4509 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4511 env
->dcache_line_size
= 32;
4512 env
->icache_line_size
= 32;
4513 /* Allocate hardware IRQ controller */
4514 ppc6xx_irq_init(env
);
4518 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4520 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4521 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4522 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4523 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4524 PPC_SEGMENT | PPC_EXTERN)
4525 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4526 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4527 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4528 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4529 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4530 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4531 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4532 #define check_pow_604 check_pow_nocheck
4534 static void init_proc_604 (CPUPPCState
*env
)
4536 gen_spr_ne_601(env
);
4540 /* Hardware implementation registers */
4541 /* XXX : not implemented */
4542 spr_register(env
, SPR_HID0
, "HID0",
4543 SPR_NOACCESS
, SPR_NOACCESS
,
4544 &spr_read_generic
, &spr_write_generic
,
4546 /* Memory management */
4549 env
->dcache_line_size
= 32;
4550 env
->icache_line_size
= 32;
4551 /* Allocate hardware IRQ controller */
4552 ppc6xx_irq_init(env
);
4556 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4557 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4558 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4559 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4560 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4561 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4562 PPC_SEGMENT | PPC_EXTERN)
4563 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4564 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4565 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4566 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4567 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4568 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4569 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4570 #define check_pow_604E check_pow_nocheck
4572 static void init_proc_604E (CPUPPCState
*env
)
4574 gen_spr_ne_601(env
);
4576 /* XXX : not implemented */
4577 spr_register(env
, SPR_MMCR1
, "MMCR1",
4578 SPR_NOACCESS
, SPR_NOACCESS
,
4579 &spr_read_generic
, &spr_write_generic
,
4581 /* XXX : not implemented */
4582 spr_register(env
, SPR_PMC3
, "PMC3",
4583 SPR_NOACCESS
, SPR_NOACCESS
,
4584 &spr_read_generic
, &spr_write_generic
,
4586 /* XXX : not implemented */
4587 spr_register(env
, SPR_PMC4
, "PMC4",
4588 SPR_NOACCESS
, SPR_NOACCESS
,
4589 &spr_read_generic
, &spr_write_generic
,
4593 /* Hardware implementation registers */
4594 /* XXX : not implemented */
4595 spr_register(env
, SPR_HID0
, "HID0",
4596 SPR_NOACCESS
, SPR_NOACCESS
,
4597 &spr_read_generic
, &spr_write_generic
,
4599 /* XXX : not implemented */
4600 spr_register(env
, SPR_HID1
, "HID1",
4601 SPR_NOACCESS
, SPR_NOACCESS
,
4602 &spr_read_generic
, &spr_write_generic
,
4604 /* Memory management */
4607 env
->dcache_line_size
= 32;
4608 env
->icache_line_size
= 32;
4609 /* Allocate hardware IRQ controller */
4610 ppc6xx_irq_init(env
);
4614 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4616 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4618 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4620 PPC_SEGMENT | PPC_EXTERN)
4621 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4622 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4623 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4624 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4625 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4626 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4627 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4628 #define check_pow_740 check_pow_hid0
4630 static void init_proc_740 (CPUPPCState
*env
)
4632 gen_spr_ne_601(env
);
4636 /* Thermal management */
4638 /* Hardware implementation registers */
4639 /* XXX : not implemented */
4640 spr_register(env
, SPR_HID0
, "HID0",
4641 SPR_NOACCESS
, SPR_NOACCESS
,
4642 &spr_read_generic
, &spr_write_generic
,
4644 /* XXX : not implemented */
4645 spr_register(env
, SPR_HID1
, "HID1",
4646 SPR_NOACCESS
, SPR_NOACCESS
,
4647 &spr_read_generic
, &spr_write_generic
,
4649 /* Memory management */
4652 env
->dcache_line_size
= 32;
4653 env
->icache_line_size
= 32;
4654 /* Allocate hardware IRQ controller */
4655 ppc6xx_irq_init(env
);
4659 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4660 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4661 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4662 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4663 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4664 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4665 PPC_SEGMENT | PPC_EXTERN)
4666 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4667 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4668 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4669 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4670 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4671 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4672 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4673 #define check_pow_750 check_pow_hid0
4675 static void init_proc_750 (CPUPPCState
*env
)
4677 gen_spr_ne_601(env
);
4679 /* XXX : not implemented */
4680 spr_register(env
, SPR_L2CR
, "L2CR",
4681 SPR_NOACCESS
, SPR_NOACCESS
,
4682 &spr_read_generic
, &spr_write_generic
,
4686 /* Thermal management */
4688 /* Hardware implementation registers */
4689 /* XXX : not implemented */
4690 spr_register(env
, SPR_HID0
, "HID0",
4691 SPR_NOACCESS
, SPR_NOACCESS
,
4692 &spr_read_generic
, &spr_write_generic
,
4694 /* XXX : not implemented */
4695 spr_register(env
, SPR_HID1
, "HID1",
4696 SPR_NOACCESS
, SPR_NOACCESS
,
4697 &spr_read_generic
, &spr_write_generic
,
4699 /* Memory management */
4701 /* XXX: high BATs are also present but are known to be bugged on
4705 env
->dcache_line_size
= 32;
4706 env
->icache_line_size
= 32;
4707 /* Allocate hardware IRQ controller */
4708 ppc6xx_irq_init(env
);
4711 /* PowerPC 750 CL */
4712 /* XXX: not implemented:
4713 * cache lock instructions:
4715 * floating point paired instructions
4750 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4751 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4752 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4753 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4754 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4755 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4756 PPC_SEGMENT | PPC_EXTERN)
4757 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4758 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4759 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4760 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4761 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4762 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4763 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4764 #define check_pow_750cl check_pow_hid0
4766 static void init_proc_750cl (CPUPPCState
*env
)
4768 gen_spr_ne_601(env
);
4770 /* XXX : not implemented */
4771 spr_register(env
, SPR_L2CR
, "L2CR",
4772 SPR_NOACCESS
, SPR_NOACCESS
,
4773 &spr_read_generic
, &spr_write_generic
,
4777 /* Thermal management */
4778 /* Those registers are fake on 750CL */
4779 spr_register(env
, SPR_THRM1
, "THRM1",
4780 SPR_NOACCESS
, SPR_NOACCESS
,
4781 &spr_read_generic
, &spr_write_generic
,
4783 spr_register(env
, SPR_THRM2
, "THRM2",
4784 SPR_NOACCESS
, SPR_NOACCESS
,
4785 &spr_read_generic
, &spr_write_generic
,
4787 spr_register(env
, SPR_THRM3
, "THRM3",
4788 SPR_NOACCESS
, SPR_NOACCESS
,
4789 &spr_read_generic
, &spr_write_generic
,
4791 /* XXX: not implemented */
4792 spr_register(env
, SPR_750_TDCL
, "TDCL",
4793 SPR_NOACCESS
, SPR_NOACCESS
,
4794 &spr_read_generic
, &spr_write_generic
,
4796 spr_register(env
, SPR_750_TDCH
, "TDCH",
4797 SPR_NOACCESS
, SPR_NOACCESS
,
4798 &spr_read_generic
, &spr_write_generic
,
4801 /* XXX : not implemented */
4802 spr_register(env
, SPR_750_WPAR
, "WPAR",
4803 SPR_NOACCESS
, SPR_NOACCESS
,
4804 &spr_read_generic
, &spr_write_generic
,
4806 spr_register(env
, SPR_750_DMAL
, "DMAL",
4807 SPR_NOACCESS
, SPR_NOACCESS
,
4808 &spr_read_generic
, &spr_write_generic
,
4810 spr_register(env
, SPR_750_DMAU
, "DMAU",
4811 SPR_NOACCESS
, SPR_NOACCESS
,
4812 &spr_read_generic
, &spr_write_generic
,
4814 /* Hardware implementation registers */
4815 /* XXX : not implemented */
4816 spr_register(env
, SPR_HID0
, "HID0",
4817 SPR_NOACCESS
, SPR_NOACCESS
,
4818 &spr_read_generic
, &spr_write_generic
,
4820 /* XXX : not implemented */
4821 spr_register(env
, SPR_HID1
, "HID1",
4822 SPR_NOACCESS
, SPR_NOACCESS
,
4823 &spr_read_generic
, &spr_write_generic
,
4825 /* XXX : not implemented */
4826 spr_register(env
, SPR_750CL_HID2
, "HID2",
4827 SPR_NOACCESS
, SPR_NOACCESS
,
4828 &spr_read_generic
, &spr_write_generic
,
4830 /* XXX : not implemented */
4831 spr_register(env
, SPR_750CL_HID4
, "HID4",
4832 SPR_NOACCESS
, SPR_NOACCESS
,
4833 &spr_read_generic
, &spr_write_generic
,
4835 /* Quantization registers */
4836 /* XXX : not implemented */
4837 spr_register(env
, SPR_750_GQR0
, "GQR0",
4838 SPR_NOACCESS
, SPR_NOACCESS
,
4839 &spr_read_generic
, &spr_write_generic
,
4841 /* XXX : not implemented */
4842 spr_register(env
, SPR_750_GQR1
, "GQR1",
4843 SPR_NOACCESS
, SPR_NOACCESS
,
4844 &spr_read_generic
, &spr_write_generic
,
4846 /* XXX : not implemented */
4847 spr_register(env
, SPR_750_GQR2
, "GQR2",
4848 SPR_NOACCESS
, SPR_NOACCESS
,
4849 &spr_read_generic
, &spr_write_generic
,
4851 /* XXX : not implemented */
4852 spr_register(env
, SPR_750_GQR3
, "GQR3",
4853 SPR_NOACCESS
, SPR_NOACCESS
,
4854 &spr_read_generic
, &spr_write_generic
,
4856 /* XXX : not implemented */
4857 spr_register(env
, SPR_750_GQR4
, "GQR4",
4858 SPR_NOACCESS
, SPR_NOACCESS
,
4859 &spr_read_generic
, &spr_write_generic
,
4861 /* XXX : not implemented */
4862 spr_register(env
, SPR_750_GQR5
, "GQR5",
4863 SPR_NOACCESS
, SPR_NOACCESS
,
4864 &spr_read_generic
, &spr_write_generic
,
4866 /* XXX : not implemented */
4867 spr_register(env
, SPR_750_GQR6
, "GQR6",
4868 SPR_NOACCESS
, SPR_NOACCESS
,
4869 &spr_read_generic
, &spr_write_generic
,
4871 /* XXX : not implemented */
4872 spr_register(env
, SPR_750_GQR7
, "GQR7",
4873 SPR_NOACCESS
, SPR_NOACCESS
,
4874 &spr_read_generic
, &spr_write_generic
,
4876 /* Memory management */
4878 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4880 init_excp_750cl(env
);
4881 env
->dcache_line_size
= 32;
4882 env
->icache_line_size
= 32;
4883 /* Allocate hardware IRQ controller */
4884 ppc6xx_irq_init(env
);
4888 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4890 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4891 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4892 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4893 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4894 PPC_SEGMENT | PPC_EXTERN)
4895 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4896 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4897 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4898 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4899 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4900 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4901 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4902 #define check_pow_750cx check_pow_hid0
4904 static void init_proc_750cx (CPUPPCState
*env
)
4906 gen_spr_ne_601(env
);
4908 /* XXX : not implemented */
4909 spr_register(env
, SPR_L2CR
, "L2CR",
4910 SPR_NOACCESS
, SPR_NOACCESS
,
4911 &spr_read_generic
, &spr_write_generic
,
4915 /* Thermal management */
4917 /* This register is not implemented but is present for compatibility */
4918 spr_register(env
, SPR_SDA
, "SDA",
4919 SPR_NOACCESS
, SPR_NOACCESS
,
4920 &spr_read_generic
, &spr_write_generic
,
4922 /* Hardware implementation registers */
4923 /* XXX : not implemented */
4924 spr_register(env
, SPR_HID0
, "HID0",
4925 SPR_NOACCESS
, SPR_NOACCESS
,
4926 &spr_read_generic
, &spr_write_generic
,
4928 /* XXX : not implemented */
4929 spr_register(env
, SPR_HID1
, "HID1",
4930 SPR_NOACCESS
, SPR_NOACCESS
,
4931 &spr_read_generic
, &spr_write_generic
,
4933 /* Memory management */
4935 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4937 init_excp_750cx(env
);
4938 env
->dcache_line_size
= 32;
4939 env
->icache_line_size
= 32;
4940 /* Allocate hardware IRQ controller */
4941 ppc6xx_irq_init(env
);
4945 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4946 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4947 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4948 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4949 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4950 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4951 PPC_SEGMENT | PPC_EXTERN)
4952 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
4953 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4954 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4955 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
4956 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
4957 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4958 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4959 #define check_pow_750fx check_pow_hid0
4961 static void init_proc_750fx (CPUPPCState
*env
)
4963 gen_spr_ne_601(env
);
4965 /* XXX : not implemented */
4966 spr_register(env
, SPR_L2CR
, "L2CR",
4967 SPR_NOACCESS
, SPR_NOACCESS
,
4968 &spr_read_generic
, &spr_write_generic
,
4972 /* Thermal management */
4974 /* XXX : not implemented */
4975 spr_register(env
, SPR_750_THRM4
, "THRM4",
4976 SPR_NOACCESS
, SPR_NOACCESS
,
4977 &spr_read_generic
, &spr_write_generic
,
4979 /* Hardware implementation registers */
4980 /* XXX : not implemented */
4981 spr_register(env
, SPR_HID0
, "HID0",
4982 SPR_NOACCESS
, SPR_NOACCESS
,
4983 &spr_read_generic
, &spr_write_generic
,
4985 /* XXX : not implemented */
4986 spr_register(env
, SPR_HID1
, "HID1",
4987 SPR_NOACCESS
, SPR_NOACCESS
,
4988 &spr_read_generic
, &spr_write_generic
,
4990 /* XXX : not implemented */
4991 spr_register(env
, SPR_750FX_HID2
, "HID2",
4992 SPR_NOACCESS
, SPR_NOACCESS
,
4993 &spr_read_generic
, &spr_write_generic
,
4995 /* Memory management */
4997 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5000 env
->dcache_line_size
= 32;
5001 env
->icache_line_size
= 32;
5002 /* Allocate hardware IRQ controller */
5003 ppc6xx_irq_init(env
);
5007 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5009 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5011 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5013 PPC_SEGMENT | PPC_EXTERN)
5014 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5015 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5016 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5017 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5018 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5019 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5020 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5021 #define check_pow_750gx check_pow_hid0
5023 static void init_proc_750gx (CPUPPCState
*env
)
5025 gen_spr_ne_601(env
);
5027 /* XXX : not implemented (XXX: different from 750fx) */
5028 spr_register(env
, SPR_L2CR
, "L2CR",
5029 SPR_NOACCESS
, SPR_NOACCESS
,
5030 &spr_read_generic
, &spr_write_generic
,
5034 /* Thermal management */
5036 /* XXX : not implemented */
5037 spr_register(env
, SPR_750_THRM4
, "THRM4",
5038 SPR_NOACCESS
, SPR_NOACCESS
,
5039 &spr_read_generic
, &spr_write_generic
,
5041 /* Hardware implementation registers */
5042 /* XXX : not implemented (XXX: different from 750fx) */
5043 spr_register(env
, SPR_HID0
, "HID0",
5044 SPR_NOACCESS
, SPR_NOACCESS
,
5045 &spr_read_generic
, &spr_write_generic
,
5047 /* XXX : not implemented */
5048 spr_register(env
, SPR_HID1
, "HID1",
5049 SPR_NOACCESS
, SPR_NOACCESS
,
5050 &spr_read_generic
, &spr_write_generic
,
5052 /* XXX : not implemented (XXX: different from 750fx) */
5053 spr_register(env
, SPR_750FX_HID2
, "HID2",
5054 SPR_NOACCESS
, SPR_NOACCESS
,
5055 &spr_read_generic
, &spr_write_generic
,
5057 /* Memory management */
5059 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5062 env
->dcache_line_size
= 32;
5063 env
->icache_line_size
= 32;
5064 /* Allocate hardware IRQ controller */
5065 ppc6xx_irq_init(env
);
5069 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5070 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5071 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5072 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5073 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5074 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5075 PPC_SEGMENT | PPC_EXTERN)
5076 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5077 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5078 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5079 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5080 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5081 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5082 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5083 #define check_pow_745 check_pow_hid0
5085 static void init_proc_745 (CPUPPCState
*env
)
5087 gen_spr_ne_601(env
);
5089 gen_spr_G2_755(env
);
5092 /* Thermal management */
5094 /* Hardware implementation registers */
5095 /* XXX : not implemented */
5096 spr_register(env
, SPR_HID0
, "HID0",
5097 SPR_NOACCESS
, SPR_NOACCESS
,
5098 &spr_read_generic
, &spr_write_generic
,
5100 /* XXX : not implemented */
5101 spr_register(env
, SPR_HID1
, "HID1",
5102 SPR_NOACCESS
, SPR_NOACCESS
,
5103 &spr_read_generic
, &spr_write_generic
,
5105 /* XXX : not implemented */
5106 spr_register(env
, SPR_HID2
, "HID2",
5107 SPR_NOACCESS
, SPR_NOACCESS
,
5108 &spr_read_generic
, &spr_write_generic
,
5110 /* Memory management */
5113 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5115 env
->dcache_line_size
= 32;
5116 env
->icache_line_size
= 32;
5117 /* Allocate hardware IRQ controller */
5118 ppc6xx_irq_init(env
);
5122 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5123 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5124 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5125 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5126 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5127 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5128 PPC_SEGMENT | PPC_EXTERN)
5129 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5130 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5131 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5132 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5133 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5134 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5135 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5136 #define check_pow_755 check_pow_hid0
5138 static void init_proc_755 (CPUPPCState
*env
)
5140 gen_spr_ne_601(env
);
5142 gen_spr_G2_755(env
);
5145 /* L2 cache control */
5146 /* XXX : not implemented */
5147 spr_register(env
, SPR_L2CR
, "L2CR",
5148 SPR_NOACCESS
, SPR_NOACCESS
,
5149 &spr_read_generic
, &spr_write_generic
,
5151 /* XXX : not implemented */
5152 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
5153 SPR_NOACCESS
, SPR_NOACCESS
,
5154 &spr_read_generic
, &spr_write_generic
,
5156 /* Thermal management */
5158 /* Hardware implementation registers */
5159 /* XXX : not implemented */
5160 spr_register(env
, SPR_HID0
, "HID0",
5161 SPR_NOACCESS
, SPR_NOACCESS
,
5162 &spr_read_generic
, &spr_write_generic
,
5164 /* XXX : not implemented */
5165 spr_register(env
, SPR_HID1
, "HID1",
5166 SPR_NOACCESS
, SPR_NOACCESS
,
5167 &spr_read_generic
, &spr_write_generic
,
5169 /* XXX : not implemented */
5170 spr_register(env
, SPR_HID2
, "HID2",
5171 SPR_NOACCESS
, SPR_NOACCESS
,
5172 &spr_read_generic
, &spr_write_generic
,
5174 /* Memory management */
5177 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5179 env
->dcache_line_size
= 32;
5180 env
->icache_line_size
= 32;
5181 /* Allocate hardware IRQ controller */
5182 ppc6xx_irq_init(env
);
5185 /* PowerPC 7400 (aka G4) */
5186 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5187 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5188 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5189 PPC_FLOAT_STFIWX | \
5190 PPC_CACHE | PPC_CACHE_ICBI | \
5191 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5192 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5193 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5195 PPC_SEGMENT | PPC_EXTERN | \
5197 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5198 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5199 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5200 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5201 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5202 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5203 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5204 POWERPC_FLAG_BUS_CLK)
5205 #define check_pow_7400 check_pow_hid0_74xx
5207 static void init_proc_7400 (CPUPPCState
*env
)
5209 gen_spr_ne_601(env
);
5213 /* 74xx specific SPR */
5215 /* XXX : not implemented */
5216 spr_register(env
, SPR_UBAMR
, "UBAMR",
5217 &spr_read_ureg
, SPR_NOACCESS
,
5218 &spr_read_ureg
, SPR_NOACCESS
,
5220 /* XXX: this seems not implemented on all revisions. */
5221 /* XXX : not implemented */
5222 spr_register(env
, SPR_MSSCR1
, "MSSCR1",
5223 SPR_NOACCESS
, SPR_NOACCESS
,
5224 &spr_read_generic
, &spr_write_generic
,
5226 /* Thermal management */
5228 /* Memory management */
5230 init_excp_7400(env
);
5231 env
->dcache_line_size
= 32;
5232 env
->icache_line_size
= 32;
5233 /* Allocate hardware IRQ controller */
5234 ppc6xx_irq_init(env
);
5237 /* PowerPC 7410 (aka G4) */
5238 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5239 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5240 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5241 PPC_FLOAT_STFIWX | \
5242 PPC_CACHE | PPC_CACHE_ICBI | \
5243 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5244 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5247 PPC_SEGMENT | PPC_EXTERN | \
5249 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5250 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5251 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5252 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5253 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5254 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5255 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5256 POWERPC_FLAG_BUS_CLK)
5257 #define check_pow_7410 check_pow_hid0_74xx
5259 static void init_proc_7410 (CPUPPCState
*env
)
5261 gen_spr_ne_601(env
);
5265 /* 74xx specific SPR */
5267 /* XXX : not implemented */
5268 spr_register(env
, SPR_UBAMR
, "UBAMR",
5269 &spr_read_ureg
, SPR_NOACCESS
,
5270 &spr_read_ureg
, SPR_NOACCESS
,
5272 /* Thermal management */
5275 /* XXX : not implemented */
5276 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
5277 SPR_NOACCESS
, SPR_NOACCESS
,
5278 &spr_read_generic
, &spr_write_generic
,
5281 /* XXX : not implemented */
5282 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
5283 SPR_NOACCESS
, SPR_NOACCESS
,
5284 &spr_read_generic
, &spr_write_generic
,
5286 /* Memory management */
5288 init_excp_7400(env
);
5289 env
->dcache_line_size
= 32;
5290 env
->icache_line_size
= 32;
5291 /* Allocate hardware IRQ controller */
5292 ppc6xx_irq_init(env
);
5295 /* PowerPC 7440 (aka G4) */
5296 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5298 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5299 PPC_FLOAT_STFIWX | \
5300 PPC_CACHE | PPC_CACHE_ICBI | \
5301 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5302 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5303 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5304 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5305 PPC_SEGMENT | PPC_EXTERN | \
5307 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5308 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5309 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5310 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5311 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5312 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5313 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5314 POWERPC_FLAG_BUS_CLK)
5315 #define check_pow_7440 check_pow_hid0_74xx
5317 __attribute__ (( unused
))
5318 static void init_proc_7440 (CPUPPCState
*env
)
5320 gen_spr_ne_601(env
);
5324 /* 74xx specific SPR */
5326 /* XXX : not implemented */
5327 spr_register(env
, SPR_UBAMR
, "UBAMR",
5328 &spr_read_ureg
, SPR_NOACCESS
,
5329 &spr_read_ureg
, SPR_NOACCESS
,
5332 /* XXX : not implemented */
5333 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5334 SPR_NOACCESS
, SPR_NOACCESS
,
5335 &spr_read_generic
, &spr_write_generic
,
5338 /* XXX : not implemented */
5339 spr_register(env
, SPR_ICTRL
, "ICTRL",
5340 SPR_NOACCESS
, SPR_NOACCESS
,
5341 &spr_read_generic
, &spr_write_generic
,
5344 /* XXX : not implemented */
5345 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5346 SPR_NOACCESS
, SPR_NOACCESS
,
5347 &spr_read_generic
, &spr_write_generic
,
5350 /* XXX : not implemented */
5351 spr_register(env
, SPR_PMC5
, "PMC5",
5352 SPR_NOACCESS
, SPR_NOACCESS
,
5353 &spr_read_generic
, &spr_write_generic
,
5355 /* XXX : not implemented */
5356 spr_register(env
, SPR_UPMC5
, "UPMC5",
5357 &spr_read_ureg
, SPR_NOACCESS
,
5358 &spr_read_ureg
, SPR_NOACCESS
,
5360 /* XXX : not implemented */
5361 spr_register(env
, SPR_PMC6
, "PMC6",
5362 SPR_NOACCESS
, SPR_NOACCESS
,
5363 &spr_read_generic
, &spr_write_generic
,
5365 /* XXX : not implemented */
5366 spr_register(env
, SPR_UPMC6
, "UPMC6",
5367 &spr_read_ureg
, SPR_NOACCESS
,
5368 &spr_read_ureg
, SPR_NOACCESS
,
5370 /* Memory management */
5372 gen_74xx_soft_tlb(env
, 128, 2);
5373 init_excp_7450(env
);
5374 env
->dcache_line_size
= 32;
5375 env
->icache_line_size
= 32;
5376 /* Allocate hardware IRQ controller */
5377 ppc6xx_irq_init(env
);
5380 /* PowerPC 7450 (aka G4) */
5381 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5382 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5383 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5384 PPC_FLOAT_STFIWX | \
5385 PPC_CACHE | PPC_CACHE_ICBI | \
5386 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5387 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5388 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5389 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5390 PPC_SEGMENT | PPC_EXTERN | \
5392 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5393 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5394 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5395 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5396 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5397 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5398 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5399 POWERPC_FLAG_BUS_CLK)
5400 #define check_pow_7450 check_pow_hid0_74xx
5402 __attribute__ (( unused
))
5403 static void init_proc_7450 (CPUPPCState
*env
)
5405 gen_spr_ne_601(env
);
5409 /* 74xx specific SPR */
5411 /* Level 3 cache control */
5414 /* XXX : not implemented */
5415 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
5416 SPR_NOACCESS
, SPR_NOACCESS
,
5417 &spr_read_generic
, &spr_write_generic
,
5420 /* XXX : not implemented */
5421 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
5422 SPR_NOACCESS
, SPR_NOACCESS
,
5423 &spr_read_generic
, &spr_write_generic
,
5426 /* XXX : not implemented */
5427 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
5428 SPR_NOACCESS
, SPR_NOACCESS
,
5429 &spr_read_generic
, &spr_write_generic
,
5432 /* XXX : not implemented */
5433 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
5434 SPR_NOACCESS
, SPR_NOACCESS
,
5435 &spr_read_generic
, &spr_write_generic
,
5437 /* XXX : not implemented */
5438 spr_register(env
, SPR_UBAMR
, "UBAMR",
5439 &spr_read_ureg
, SPR_NOACCESS
,
5440 &spr_read_ureg
, SPR_NOACCESS
,
5443 /* XXX : not implemented */
5444 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5445 SPR_NOACCESS
, SPR_NOACCESS
,
5446 &spr_read_generic
, &spr_write_generic
,
5449 /* XXX : not implemented */
5450 spr_register(env
, SPR_ICTRL
, "ICTRL",
5451 SPR_NOACCESS
, SPR_NOACCESS
,
5452 &spr_read_generic
, &spr_write_generic
,
5455 /* XXX : not implemented */
5456 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5457 SPR_NOACCESS
, SPR_NOACCESS
,
5458 &spr_read_generic
, &spr_write_generic
,
5461 /* XXX : not implemented */
5462 spr_register(env
, SPR_PMC5
, "PMC5",
5463 SPR_NOACCESS
, SPR_NOACCESS
,
5464 &spr_read_generic
, &spr_write_generic
,
5466 /* XXX : not implemented */
5467 spr_register(env
, SPR_UPMC5
, "UPMC5",
5468 &spr_read_ureg
, SPR_NOACCESS
,
5469 &spr_read_ureg
, SPR_NOACCESS
,
5471 /* XXX : not implemented */
5472 spr_register(env
, SPR_PMC6
, "PMC6",
5473 SPR_NOACCESS
, SPR_NOACCESS
,
5474 &spr_read_generic
, &spr_write_generic
,
5476 /* XXX : not implemented */
5477 spr_register(env
, SPR_UPMC6
, "UPMC6",
5478 &spr_read_ureg
, SPR_NOACCESS
,
5479 &spr_read_ureg
, SPR_NOACCESS
,
5481 /* Memory management */
5483 gen_74xx_soft_tlb(env
, 128, 2);
5484 init_excp_7450(env
);
5485 env
->dcache_line_size
= 32;
5486 env
->icache_line_size
= 32;
5487 /* Allocate hardware IRQ controller */
5488 ppc6xx_irq_init(env
);
5491 /* PowerPC 7445 (aka G4) */
5492 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5495 PPC_FLOAT_STFIWX | \
5496 PPC_CACHE | PPC_CACHE_ICBI | \
5497 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5498 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5500 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5501 PPC_SEGMENT | PPC_EXTERN | \
5503 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5504 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5505 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5506 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5507 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5508 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5509 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5510 POWERPC_FLAG_BUS_CLK)
5511 #define check_pow_7445 check_pow_hid0_74xx
5513 __attribute__ (( unused
))
5514 static void init_proc_7445 (CPUPPCState
*env
)
5516 gen_spr_ne_601(env
);
5520 /* 74xx specific SPR */
5523 /* XXX : not implemented */
5524 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5525 SPR_NOACCESS
, SPR_NOACCESS
,
5526 &spr_read_generic
, &spr_write_generic
,
5529 /* XXX : not implemented */
5530 spr_register(env
, SPR_ICTRL
, "ICTRL",
5531 SPR_NOACCESS
, SPR_NOACCESS
,
5532 &spr_read_generic
, &spr_write_generic
,
5535 /* XXX : not implemented */
5536 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5537 SPR_NOACCESS
, SPR_NOACCESS
,
5538 &spr_read_generic
, &spr_write_generic
,
5541 /* XXX : not implemented */
5542 spr_register(env
, SPR_PMC5
, "PMC5",
5543 SPR_NOACCESS
, SPR_NOACCESS
,
5544 &spr_read_generic
, &spr_write_generic
,
5546 /* XXX : not implemented */
5547 spr_register(env
, SPR_UPMC5
, "UPMC5",
5548 &spr_read_ureg
, SPR_NOACCESS
,
5549 &spr_read_ureg
, SPR_NOACCESS
,
5551 /* XXX : not implemented */
5552 spr_register(env
, SPR_PMC6
, "PMC6",
5553 SPR_NOACCESS
, SPR_NOACCESS
,
5554 &spr_read_generic
, &spr_write_generic
,
5556 /* XXX : not implemented */
5557 spr_register(env
, SPR_UPMC6
, "UPMC6",
5558 &spr_read_ureg
, SPR_NOACCESS
,
5559 &spr_read_ureg
, SPR_NOACCESS
,
5562 spr_register(env
, SPR_SPRG4
, "SPRG4",
5563 SPR_NOACCESS
, SPR_NOACCESS
,
5564 &spr_read_generic
, &spr_write_generic
,
5566 spr_register(env
, SPR_USPRG4
, "USPRG4",
5567 &spr_read_ureg
, SPR_NOACCESS
,
5568 &spr_read_ureg
, SPR_NOACCESS
,
5570 spr_register(env
, SPR_SPRG5
, "SPRG5",
5571 SPR_NOACCESS
, SPR_NOACCESS
,
5572 &spr_read_generic
, &spr_write_generic
,
5574 spr_register(env
, SPR_USPRG5
, "USPRG5",
5575 &spr_read_ureg
, SPR_NOACCESS
,
5576 &spr_read_ureg
, SPR_NOACCESS
,
5578 spr_register(env
, SPR_SPRG6
, "SPRG6",
5579 SPR_NOACCESS
, SPR_NOACCESS
,
5580 &spr_read_generic
, &spr_write_generic
,
5582 spr_register(env
, SPR_USPRG6
, "USPRG6",
5583 &spr_read_ureg
, SPR_NOACCESS
,
5584 &spr_read_ureg
, SPR_NOACCESS
,
5586 spr_register(env
, SPR_SPRG7
, "SPRG7",
5587 SPR_NOACCESS
, SPR_NOACCESS
,
5588 &spr_read_generic
, &spr_write_generic
,
5590 spr_register(env
, SPR_USPRG7
, "USPRG7",
5591 &spr_read_ureg
, SPR_NOACCESS
,
5592 &spr_read_ureg
, SPR_NOACCESS
,
5594 /* Memory management */
5597 gen_74xx_soft_tlb(env
, 128, 2);
5598 init_excp_7450(env
);
5599 env
->dcache_line_size
= 32;
5600 env
->icache_line_size
= 32;
5601 /* Allocate hardware IRQ controller */
5602 ppc6xx_irq_init(env
);
5605 /* PowerPC 7455 (aka G4) */
5606 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5608 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5609 PPC_FLOAT_STFIWX | \
5610 PPC_CACHE | PPC_CACHE_ICBI | \
5611 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5612 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5614 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5615 PPC_SEGMENT | PPC_EXTERN | \
5617 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5618 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5619 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5620 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5621 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5622 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5623 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5624 POWERPC_FLAG_BUS_CLK)
5625 #define check_pow_7455 check_pow_hid0_74xx
5627 __attribute__ (( unused
))
5628 static void init_proc_7455 (CPUPPCState
*env
)
5630 gen_spr_ne_601(env
);
5634 /* 74xx specific SPR */
5636 /* Level 3 cache control */
5639 /* XXX : not implemented */
5640 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5641 SPR_NOACCESS
, SPR_NOACCESS
,
5642 &spr_read_generic
, &spr_write_generic
,
5645 /* XXX : not implemented */
5646 spr_register(env
, SPR_ICTRL
, "ICTRL",
5647 SPR_NOACCESS
, SPR_NOACCESS
,
5648 &spr_read_generic
, &spr_write_generic
,
5651 /* XXX : not implemented */
5652 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5653 SPR_NOACCESS
, SPR_NOACCESS
,
5654 &spr_read_generic
, &spr_write_generic
,
5657 /* XXX : not implemented */
5658 spr_register(env
, SPR_PMC5
, "PMC5",
5659 SPR_NOACCESS
, SPR_NOACCESS
,
5660 &spr_read_generic
, &spr_write_generic
,
5662 /* XXX : not implemented */
5663 spr_register(env
, SPR_UPMC5
, "UPMC5",
5664 &spr_read_ureg
, SPR_NOACCESS
,
5665 &spr_read_ureg
, SPR_NOACCESS
,
5667 /* XXX : not implemented */
5668 spr_register(env
, SPR_PMC6
, "PMC6",
5669 SPR_NOACCESS
, SPR_NOACCESS
,
5670 &spr_read_generic
, &spr_write_generic
,
5672 /* XXX : not implemented */
5673 spr_register(env
, SPR_UPMC6
, "UPMC6",
5674 &spr_read_ureg
, SPR_NOACCESS
,
5675 &spr_read_ureg
, SPR_NOACCESS
,
5678 spr_register(env
, SPR_SPRG4
, "SPRG4",
5679 SPR_NOACCESS
, SPR_NOACCESS
,
5680 &spr_read_generic
, &spr_write_generic
,
5682 spr_register(env
, SPR_USPRG4
, "USPRG4",
5683 &spr_read_ureg
, SPR_NOACCESS
,
5684 &spr_read_ureg
, SPR_NOACCESS
,
5686 spr_register(env
, SPR_SPRG5
, "SPRG5",
5687 SPR_NOACCESS
, SPR_NOACCESS
,
5688 &spr_read_generic
, &spr_write_generic
,
5690 spr_register(env
, SPR_USPRG5
, "USPRG5",
5691 &spr_read_ureg
, SPR_NOACCESS
,
5692 &spr_read_ureg
, SPR_NOACCESS
,
5694 spr_register(env
, SPR_SPRG6
, "SPRG6",
5695 SPR_NOACCESS
, SPR_NOACCESS
,
5696 &spr_read_generic
, &spr_write_generic
,
5698 spr_register(env
, SPR_USPRG6
, "USPRG6",
5699 &spr_read_ureg
, SPR_NOACCESS
,
5700 &spr_read_ureg
, SPR_NOACCESS
,
5702 spr_register(env
, SPR_SPRG7
, "SPRG7",
5703 SPR_NOACCESS
, SPR_NOACCESS
,
5704 &spr_read_generic
, &spr_write_generic
,
5706 spr_register(env
, SPR_USPRG7
, "USPRG7",
5707 &spr_read_ureg
, SPR_NOACCESS
,
5708 &spr_read_ureg
, SPR_NOACCESS
,
5710 /* Memory management */
5713 gen_74xx_soft_tlb(env
, 128, 2);
5714 init_excp_7450(env
);
5715 env
->dcache_line_size
= 32;
5716 env
->icache_line_size
= 32;
5717 /* Allocate hardware IRQ controller */
5718 ppc6xx_irq_init(env
);
5721 /* PowerPC 7457 (aka G4) */
5722 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5723 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5724 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5725 PPC_FLOAT_STFIWX | \
5726 PPC_CACHE | PPC_CACHE_ICBI | \
5727 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5728 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5729 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5730 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5731 PPC_SEGMENT | PPC_EXTERN | \
5733 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5734 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5735 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5736 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5737 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5738 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5739 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5740 POWERPC_FLAG_BUS_CLK)
5741 #define check_pow_7457 check_pow_hid0_74xx
5743 __attribute__ (( unused
))
5744 static void init_proc_7457 (CPUPPCState
*env
)
5746 gen_spr_ne_601(env
);
5750 /* 74xx specific SPR */
5752 /* Level 3 cache control */
5755 /* XXX : not implemented */
5756 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
5757 SPR_NOACCESS
, SPR_NOACCESS
,
5758 &spr_read_generic
, &spr_write_generic
,
5761 /* XXX : not implemented */
5762 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
5763 SPR_NOACCESS
, SPR_NOACCESS
,
5764 &spr_read_generic
, &spr_write_generic
,
5767 /* XXX : not implemented */
5768 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
5769 SPR_NOACCESS
, SPR_NOACCESS
,
5770 &spr_read_generic
, &spr_write_generic
,
5773 /* XXX : not implemented */
5774 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
5775 SPR_NOACCESS
, SPR_NOACCESS
,
5776 &spr_read_generic
, &spr_write_generic
,
5779 /* XXX : not implemented */
5780 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
5781 SPR_NOACCESS
, SPR_NOACCESS
,
5782 &spr_read_generic
, &spr_write_generic
,
5785 /* XXX : not implemented */
5786 spr_register(env
, SPR_ICTRL
, "ICTRL",
5787 SPR_NOACCESS
, SPR_NOACCESS
,
5788 &spr_read_generic
, &spr_write_generic
,
5791 /* XXX : not implemented */
5792 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
5793 SPR_NOACCESS
, SPR_NOACCESS
,
5794 &spr_read_generic
, &spr_write_generic
,
5797 /* XXX : not implemented */
5798 spr_register(env
, SPR_PMC5
, "PMC5",
5799 SPR_NOACCESS
, SPR_NOACCESS
,
5800 &spr_read_generic
, &spr_write_generic
,
5802 /* XXX : not implemented */
5803 spr_register(env
, SPR_UPMC5
, "UPMC5",
5804 &spr_read_ureg
, SPR_NOACCESS
,
5805 &spr_read_ureg
, SPR_NOACCESS
,
5807 /* XXX : not implemented */
5808 spr_register(env
, SPR_PMC6
, "PMC6",
5809 SPR_NOACCESS
, SPR_NOACCESS
,
5810 &spr_read_generic
, &spr_write_generic
,
5812 /* XXX : not implemented */
5813 spr_register(env
, SPR_UPMC6
, "UPMC6",
5814 &spr_read_ureg
, SPR_NOACCESS
,
5815 &spr_read_ureg
, SPR_NOACCESS
,
5818 spr_register(env
, SPR_SPRG4
, "SPRG4",
5819 SPR_NOACCESS
, SPR_NOACCESS
,
5820 &spr_read_generic
, &spr_write_generic
,
5822 spr_register(env
, SPR_USPRG4
, "USPRG4",
5823 &spr_read_ureg
, SPR_NOACCESS
,
5824 &spr_read_ureg
, SPR_NOACCESS
,
5826 spr_register(env
, SPR_SPRG5
, "SPRG5",
5827 SPR_NOACCESS
, SPR_NOACCESS
,
5828 &spr_read_generic
, &spr_write_generic
,
5830 spr_register(env
, SPR_USPRG5
, "USPRG5",
5831 &spr_read_ureg
, SPR_NOACCESS
,
5832 &spr_read_ureg
, SPR_NOACCESS
,
5834 spr_register(env
, SPR_SPRG6
, "SPRG6",
5835 SPR_NOACCESS
, SPR_NOACCESS
,
5836 &spr_read_generic
, &spr_write_generic
,
5838 spr_register(env
, SPR_USPRG6
, "USPRG6",
5839 &spr_read_ureg
, SPR_NOACCESS
,
5840 &spr_read_ureg
, SPR_NOACCESS
,
5842 spr_register(env
, SPR_SPRG7
, "SPRG7",
5843 SPR_NOACCESS
, SPR_NOACCESS
,
5844 &spr_read_generic
, &spr_write_generic
,
5846 spr_register(env
, SPR_USPRG7
, "USPRG7",
5847 &spr_read_ureg
, SPR_NOACCESS
,
5848 &spr_read_ureg
, SPR_NOACCESS
,
5850 /* Memory management */
5853 gen_74xx_soft_tlb(env
, 128, 2);
5854 init_excp_7450(env
);
5855 env
->dcache_line_size
= 32;
5856 env
->icache_line_size
= 32;
5857 /* Allocate hardware IRQ controller */
5858 ppc6xx_irq_init(env
);
5861 #if defined (TARGET_PPC64)
5863 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5864 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5865 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5866 PPC_FLOAT_STFIWX | \
5867 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5868 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5869 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5870 PPC_64B | PPC_ALTIVEC | \
5871 PPC_SEGMENT_64B | PPC_SLBI)
5872 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
5873 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
5874 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5875 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
5876 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
5877 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5878 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5879 POWERPC_FLAG_BUS_CLK)
5881 #if defined(CONFIG_USER_ONLY)
5882 #define POWERPC970_HID5_INIT 0x00000080
5884 #define POWERPC970_HID5_INIT 0x00000000
5887 static int check_pow_970 (CPUPPCState
*env
)
5889 if (env
->spr
[SPR_HID0
] & 0x00600000)
5895 static void init_proc_970 (CPUPPCState
*env
)
5897 gen_spr_ne_601(env
);
5901 /* Hardware implementation registers */
5902 /* XXX : not implemented */
5903 spr_register(env
, SPR_HID0
, "HID0",
5904 SPR_NOACCESS
, SPR_NOACCESS
,
5905 &spr_read_generic
, &spr_write_clear
,
5907 /* XXX : not implemented */
5908 spr_register(env
, SPR_HID1
, "HID1",
5909 SPR_NOACCESS
, SPR_NOACCESS
,
5910 &spr_read_generic
, &spr_write_generic
,
5912 /* XXX : not implemented */
5913 spr_register(env
, SPR_750FX_HID2
, "HID2",
5914 SPR_NOACCESS
, SPR_NOACCESS
,
5915 &spr_read_generic
, &spr_write_generic
,
5917 /* XXX : not implemented */
5918 spr_register(env
, SPR_970_HID5
, "HID5",
5919 SPR_NOACCESS
, SPR_NOACCESS
,
5920 &spr_read_generic
, &spr_write_generic
,
5921 POWERPC970_HID5_INIT
);
5922 /* XXX : not implemented */
5923 spr_register(env
, SPR_L2CR
, "L2CR",
5924 SPR_NOACCESS
, SPR_NOACCESS
,
5925 &spr_read_generic
, &spr_write_generic
,
5927 /* Memory management */
5928 /* XXX: not correct */
5930 /* XXX : not implemented */
5931 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
5932 SPR_NOACCESS
, SPR_NOACCESS
,
5933 &spr_read_generic
, SPR_NOACCESS
,
5934 0x00000000); /* TOFIX */
5935 /* XXX : not implemented */
5936 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
5937 SPR_NOACCESS
, SPR_NOACCESS
,
5938 &spr_read_generic
, &spr_write_generic
,
5939 0x00000000); /* TOFIX */
5940 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
5941 SPR_NOACCESS
, SPR_NOACCESS
,
5942 &spr_read_generic
, &spr_write_generic
,
5943 0xFFF00000); /* XXX: This is a hack */
5944 #if !defined(CONFIG_USER_ONLY)
5948 env
->dcache_line_size
= 128;
5949 env
->icache_line_size
= 128;
5950 /* Allocate hardware IRQ controller */
5951 ppc970_irq_init(env
);
5952 /* Can't find information on what this should be on reset. This
5953 * value is the one used by 74xx processors. */
5954 vscr_init(env
, 0x00010000);
5957 /* PowerPC 970FX (aka G5) */
5958 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5960 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5961 PPC_FLOAT_STFIWX | \
5962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5963 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5965 PPC_64B | PPC_ALTIVEC | \
5966 PPC_SEGMENT_64B | PPC_SLBI)
5967 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
5968 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
5969 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5970 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
5971 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
5972 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5973 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5974 POWERPC_FLAG_BUS_CLK)
5976 static int check_pow_970FX (CPUPPCState
*env
)
5978 if (env
->spr
[SPR_HID0
] & 0x00600000)
5984 static void init_proc_970FX (CPUPPCState
*env
)
5986 gen_spr_ne_601(env
);
5990 /* Hardware implementation registers */
5991 /* XXX : not implemented */
5992 spr_register(env
, SPR_HID0
, "HID0",
5993 SPR_NOACCESS
, SPR_NOACCESS
,
5994 &spr_read_generic
, &spr_write_clear
,
5996 /* XXX : not implemented */
5997 spr_register(env
, SPR_HID1
, "HID1",
5998 SPR_NOACCESS
, SPR_NOACCESS
,
5999 &spr_read_generic
, &spr_write_generic
,
6001 /* XXX : not implemented */
6002 spr_register(env
, SPR_750FX_HID2
, "HID2",
6003 SPR_NOACCESS
, SPR_NOACCESS
,
6004 &spr_read_generic
, &spr_write_generic
,
6006 /* XXX : not implemented */
6007 spr_register(env
, SPR_970_HID5
, "HID5",
6008 SPR_NOACCESS
, SPR_NOACCESS
,
6009 &spr_read_generic
, &spr_write_generic
,
6010 POWERPC970_HID5_INIT
);
6011 /* XXX : not implemented */
6012 spr_register(env
, SPR_L2CR
, "L2CR",
6013 SPR_NOACCESS
, SPR_NOACCESS
,
6014 &spr_read_generic
, &spr_write_generic
,
6016 /* Memory management */
6017 /* XXX: not correct */
6019 /* XXX : not implemented */
6020 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6021 SPR_NOACCESS
, SPR_NOACCESS
,
6022 &spr_read_generic
, SPR_NOACCESS
,
6023 0x00000000); /* TOFIX */
6024 /* XXX : not implemented */
6025 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6026 SPR_NOACCESS
, SPR_NOACCESS
,
6027 &spr_read_generic
, &spr_write_generic
,
6028 0x00000000); /* TOFIX */
6029 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6030 SPR_NOACCESS
, SPR_NOACCESS
,
6031 &spr_read_generic
, &spr_write_generic
,
6032 0xFFF00000); /* XXX: This is a hack */
6033 #if !defined(CONFIG_USER_ONLY)
6037 env
->dcache_line_size
= 128;
6038 env
->icache_line_size
= 128;
6039 /* Allocate hardware IRQ controller */
6040 ppc970_irq_init(env
);
6041 /* Can't find information on what this should be on reset. This
6042 * value is the one used by 74xx processors. */
6043 vscr_init(env
, 0x00010000);
6046 /* PowerPC 970 GX */
6047 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6048 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6049 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6050 PPC_FLOAT_STFIWX | \
6051 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6052 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6053 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6054 PPC_64B | PPC_ALTIVEC | \
6055 PPC_SEGMENT_64B | PPC_SLBI)
6056 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6057 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6058 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6059 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6060 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6061 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6062 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6063 POWERPC_FLAG_BUS_CLK)
6065 static int check_pow_970GX (CPUPPCState
*env
)
6067 if (env
->spr
[SPR_HID0
] & 0x00600000)
6073 static void init_proc_970GX (CPUPPCState
*env
)
6075 gen_spr_ne_601(env
);
6079 /* Hardware implementation registers */
6080 /* XXX : not implemented */
6081 spr_register(env
, SPR_HID0
, "HID0",
6082 SPR_NOACCESS
, SPR_NOACCESS
,
6083 &spr_read_generic
, &spr_write_clear
,
6085 /* XXX : not implemented */
6086 spr_register(env
, SPR_HID1
, "HID1",
6087 SPR_NOACCESS
, SPR_NOACCESS
,
6088 &spr_read_generic
, &spr_write_generic
,
6090 /* XXX : not implemented */
6091 spr_register(env
, SPR_750FX_HID2
, "HID2",
6092 SPR_NOACCESS
, SPR_NOACCESS
,
6093 &spr_read_generic
, &spr_write_generic
,
6095 /* XXX : not implemented */
6096 spr_register(env
, SPR_970_HID5
, "HID5",
6097 SPR_NOACCESS
, SPR_NOACCESS
,
6098 &spr_read_generic
, &spr_write_generic
,
6099 POWERPC970_HID5_INIT
);
6100 /* XXX : not implemented */
6101 spr_register(env
, SPR_L2CR
, "L2CR",
6102 SPR_NOACCESS
, SPR_NOACCESS
,
6103 &spr_read_generic
, &spr_write_generic
,
6105 /* Memory management */
6106 /* XXX: not correct */
6108 /* XXX : not implemented */
6109 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6110 SPR_NOACCESS
, SPR_NOACCESS
,
6111 &spr_read_generic
, SPR_NOACCESS
,
6112 0x00000000); /* TOFIX */
6113 /* XXX : not implemented */
6114 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6115 SPR_NOACCESS
, SPR_NOACCESS
,
6116 &spr_read_generic
, &spr_write_generic
,
6117 0x00000000); /* TOFIX */
6118 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6119 SPR_NOACCESS
, SPR_NOACCESS
,
6120 &spr_read_generic
, &spr_write_generic
,
6121 0xFFF00000); /* XXX: This is a hack */
6122 #if !defined(CONFIG_USER_ONLY)
6126 env
->dcache_line_size
= 128;
6127 env
->icache_line_size
= 128;
6128 /* Allocate hardware IRQ controller */
6129 ppc970_irq_init(env
);
6130 /* Can't find information on what this should be on reset. This
6131 * value is the one used by 74xx processors. */
6132 vscr_init(env
, 0x00010000);
6135 /* PowerPC 970 MP */
6136 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6137 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6138 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6139 PPC_FLOAT_STFIWX | \
6140 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6141 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6142 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6143 PPC_64B | PPC_ALTIVEC | \
6144 PPC_SEGMENT_64B | PPC_SLBI)
6145 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6146 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6147 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6148 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6149 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6150 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6151 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6152 POWERPC_FLAG_BUS_CLK)
6154 static int check_pow_970MP (CPUPPCState
*env
)
6156 if (env
->spr
[SPR_HID0
] & 0x01C00000)
6162 static void init_proc_970MP (CPUPPCState
*env
)
6164 gen_spr_ne_601(env
);
6168 /* Hardware implementation registers */
6169 /* XXX : not implemented */
6170 spr_register(env
, SPR_HID0
, "HID0",
6171 SPR_NOACCESS
, SPR_NOACCESS
,
6172 &spr_read_generic
, &spr_write_clear
,
6174 /* XXX : not implemented */
6175 spr_register(env
, SPR_HID1
, "HID1",
6176 SPR_NOACCESS
, SPR_NOACCESS
,
6177 &spr_read_generic
, &spr_write_generic
,
6179 /* XXX : not implemented */
6180 spr_register(env
, SPR_750FX_HID2
, "HID2",
6181 SPR_NOACCESS
, SPR_NOACCESS
,
6182 &spr_read_generic
, &spr_write_generic
,
6184 /* XXX : not implemented */
6185 spr_register(env
, SPR_970_HID5
, "HID5",
6186 SPR_NOACCESS
, SPR_NOACCESS
,
6187 &spr_read_generic
, &spr_write_generic
,
6188 POWERPC970_HID5_INIT
);
6189 /* XXX : not implemented */
6190 spr_register(env
, SPR_L2CR
, "L2CR",
6191 SPR_NOACCESS
, SPR_NOACCESS
,
6192 &spr_read_generic
, &spr_write_generic
,
6194 /* Memory management */
6195 /* XXX: not correct */
6197 /* XXX : not implemented */
6198 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
6199 SPR_NOACCESS
, SPR_NOACCESS
,
6200 &spr_read_generic
, SPR_NOACCESS
,
6201 0x00000000); /* TOFIX */
6202 /* XXX : not implemented */
6203 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
6204 SPR_NOACCESS
, SPR_NOACCESS
,
6205 &spr_read_generic
, &spr_write_generic
,
6206 0x00000000); /* TOFIX */
6207 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
6208 SPR_NOACCESS
, SPR_NOACCESS
,
6209 &spr_read_generic
, &spr_write_generic
,
6210 0xFFF00000); /* XXX: This is a hack */
6211 #if !defined(CONFIG_USER_ONLY)
6215 env
->dcache_line_size
= 128;
6216 env
->icache_line_size
= 128;
6217 /* Allocate hardware IRQ controller */
6218 ppc970_irq_init(env
);
6219 /* Can't find information on what this should be on reset. This
6220 * value is the one used by 74xx processors. */
6221 vscr_init(env
, 0x00010000);
6225 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6226 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6227 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6228 PPC_FLOAT_STFIWX | \
6229 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6230 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6232 PPC_SEGMENT | PPC_EXTERN | \
6234 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6235 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6236 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6237 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6238 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6239 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6240 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6241 #define check_pow_620 check_pow_nocheck /* Check this */
6243 __attribute__ (( unused
))
6244 static void init_proc_620 (CPUPPCState
*env
)
6246 gen_spr_ne_601(env
);
6250 /* Hardware implementation registers */
6251 /* XXX : not implemented */
6252 spr_register(env
, SPR_HID0
, "HID0",
6253 SPR_NOACCESS
, SPR_NOACCESS
,
6254 &spr_read_generic
, &spr_write_generic
,
6256 /* Memory management */
6259 env
->dcache_line_size
= 64;
6260 env
->icache_line_size
= 64;
6261 /* Allocate hardware IRQ controller */
6262 ppc6xx_irq_init(env
);
6264 #endif /* defined (TARGET_PPC64) */
6266 /* Default 32 bits PowerPC target will be 604 */
6267 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6268 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6269 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6270 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6271 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6272 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6273 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6274 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6275 #define check_pow_PPC32 check_pow_604
6276 #define init_proc_PPC32 init_proc_604
6278 /* Default 64 bits PowerPC target will be 970 FX */
6279 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6280 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6281 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6282 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6283 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6284 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6285 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6286 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6287 #define check_pow_PPC64 check_pow_970FX
6288 #define init_proc_PPC64 init_proc_970FX
6290 /* Default PowerPC target will be PowerPC 32 */
6291 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6292 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6293 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6294 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6295 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6296 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6297 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6298 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6299 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6300 #define check_pow_DEFAULT check_pow_PPC64
6301 #define init_proc_DEFAULT init_proc_PPC64
6303 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6304 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6305 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6306 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6307 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6308 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6309 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6310 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6311 #define check_pow_DEFAULT check_pow_PPC32
6312 #define init_proc_DEFAULT init_proc_PPC32
6315 /*****************************************************************************/
6316 /* PVR definitions for most known PowerPC */
6318 /* PowerPC 401 family */
6319 /* Generic PowerPC 401 */
6320 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6321 /* PowerPC 401 cores */
6322 CPU_POWERPC_401A1
= 0x00210000,
6323 CPU_POWERPC_401B2
= 0x00220000,
6325 CPU_POWERPC_401B3
= xxx
,
6327 CPU_POWERPC_401C2
= 0x00230000,
6328 CPU_POWERPC_401D2
= 0x00240000,
6329 CPU_POWERPC_401E2
= 0x00250000,
6330 CPU_POWERPC_401F2
= 0x00260000,
6331 CPU_POWERPC_401G2
= 0x00270000,
6332 /* PowerPC 401 microcontrolers */
6334 CPU_POWERPC_401GF
= xxx
,
6336 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6337 /* IBM Processor for Network Resources */
6338 CPU_POWERPC_COBRA
= 0x10100000, /* XXX: 405 ? */
6340 CPU_POWERPC_XIPCHIP
= xxx
,
6342 /* PowerPC 403 family */
6343 /* Generic PowerPC 403 */
6344 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6345 /* PowerPC 403 microcontrollers */
6346 CPU_POWERPC_403GA
= 0x00200011,
6347 CPU_POWERPC_403GB
= 0x00200100,
6348 CPU_POWERPC_403GC
= 0x00200200,
6349 CPU_POWERPC_403GCX
= 0x00201400,
6351 CPU_POWERPC_403GP
= xxx
,
6353 /* PowerPC 405 family */
6354 /* Generic PowerPC 405 */
6355 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6356 /* PowerPC 405 cores */
6358 CPU_POWERPC_405A3
= xxx
,
6361 CPU_POWERPC_405A4
= xxx
,
6364 CPU_POWERPC_405B3
= xxx
,
6367 CPU_POWERPC_405B4
= xxx
,
6370 CPU_POWERPC_405C3
= xxx
,
6373 CPU_POWERPC_405C4
= xxx
,
6375 CPU_POWERPC_405D2
= 0x20010000,
6377 CPU_POWERPC_405D3
= xxx
,
6379 CPU_POWERPC_405D4
= 0x41810000,
6381 CPU_POWERPC_405D5
= xxx
,
6384 CPU_POWERPC_405E4
= xxx
,
6387 CPU_POWERPC_405F4
= xxx
,
6390 CPU_POWERPC_405F5
= xxx
,
6393 CPU_POWERPC_405F6
= xxx
,
6395 /* PowerPC 405 microcontrolers */
6396 /* XXX: missing 0x200108a0 */
6397 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6398 CPU_POWERPC_405CRa
= 0x40110041,
6399 CPU_POWERPC_405CRb
= 0x401100C5,
6400 CPU_POWERPC_405CRc
= 0x40110145,
6401 CPU_POWERPC_405EP
= 0x51210950,
6403 CPU_POWERPC_405EXr
= xxx
,
6405 CPU_POWERPC_405EZ
= 0x41511460, /* 0x51210950 ? */
6407 CPU_POWERPC_405FX
= xxx
,
6409 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6410 CPU_POWERPC_405GPa
= 0x40110000,
6411 CPU_POWERPC_405GPb
= 0x40110040,
6412 CPU_POWERPC_405GPc
= 0x40110082,
6413 CPU_POWERPC_405GPd
= 0x401100C4,
6414 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6415 CPU_POWERPC_405GPR
= 0x50910951,
6417 CPU_POWERPC_405H
= xxx
,
6420 CPU_POWERPC_405L
= xxx
,
6422 CPU_POWERPC_405LP
= 0x41F10000,
6424 CPU_POWERPC_405PM
= xxx
,
6427 CPU_POWERPC_405PS
= xxx
,
6430 CPU_POWERPC_405S
= xxx
,
6432 /* IBM network processors */
6433 CPU_POWERPC_NPE405H
= 0x414100C0,
6434 CPU_POWERPC_NPE405H2
= 0x41410140,
6435 CPU_POWERPC_NPE405L
= 0x416100C0,
6436 CPU_POWERPC_NPE4GS3
= 0x40B10000,
6438 CPU_POWERPC_NPCxx1
= xxx
,
6441 CPU_POWERPC_NPR161
= xxx
,
6444 CPU_POWERPC_LC77700
= xxx
,
6446 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6448 CPU_POWERPC_STB01000
= xxx
,
6451 CPU_POWERPC_STB01010
= xxx
,
6454 CPU_POWERPC_STB0210
= xxx
, /* 401B3 */
6456 CPU_POWERPC_STB03
= 0x40310000, /* 0x40130000 ? */
6458 CPU_POWERPC_STB043
= xxx
,
6461 CPU_POWERPC_STB045
= xxx
,
6463 CPU_POWERPC_STB04
= 0x41810000,
6464 CPU_POWERPC_STB25
= 0x51510950,
6466 CPU_POWERPC_STB130
= xxx
,
6469 CPU_POWERPC_X2VP4
= 0x20010820,
6470 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6471 CPU_POWERPC_X2VP20
= 0x20010860,
6472 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6474 CPU_POWERPC_ZL10310
= xxx
,
6477 CPU_POWERPC_ZL10311
= xxx
,
6480 CPU_POWERPC_ZL10320
= xxx
,
6483 CPU_POWERPC_ZL10321
= xxx
,
6485 /* PowerPC 440 family */
6486 /* Generic PowerPC 440 */
6487 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6488 /* PowerPC 440 cores */
6490 CPU_POWERPC_440A4
= xxx
,
6493 CPU_POWERPC_440A5
= xxx
,
6496 CPU_POWERPC_440B4
= xxx
,
6499 CPU_POWERPC_440F5
= xxx
,
6502 CPU_POWERPC_440G5
= xxx
,
6505 CPU_POWERPC_440H4
= xxx
,
6508 CPU_POWERPC_440H6
= xxx
,
6510 /* PowerPC 440 microcontrolers */
6511 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6512 CPU_POWERPC_440EPa
= 0x42221850,
6513 CPU_POWERPC_440EPb
= 0x422218D3,
6514 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6515 CPU_POWERPC_440GPb
= 0x40120440,
6516 CPU_POWERPC_440GPc
= 0x40120481,
6517 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6518 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6519 CPU_POWERPC_440GRX
= 0x200008D0,
6520 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6521 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6522 CPU_POWERPC_440GXa
= 0x51B21850,
6523 CPU_POWERPC_440GXb
= 0x51B21851,
6524 CPU_POWERPC_440GXc
= 0x51B21892,
6525 CPU_POWERPC_440GXf
= 0x51B21894,
6527 CPU_POWERPC_440S
= xxx
,
6529 CPU_POWERPC_440SP
= 0x53221850,
6530 CPU_POWERPC_440SP2
= 0x53221891,
6531 CPU_POWERPC_440SPE
= 0x53421890,
6532 /* PowerPC 460 family */
6534 /* Generic PowerPC 464 */
6535 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6537 /* PowerPC 464 microcontrolers */
6539 CPU_POWERPC_464H90
= xxx
,
6542 CPU_POWERPC_464H90FP
= xxx
,
6544 /* Freescale embedded PowerPC cores */
6545 /* PowerPC MPC 5xx cores (aka RCPU) */
6546 CPU_POWERPC_MPC5xx
= 0x00020020,
6547 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6548 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6549 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6550 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6551 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6552 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6553 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6554 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6555 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6556 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6557 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6558 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6559 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6560 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6561 CPU_POWERPC_MPC8xx
= 0x00500000,
6562 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6563 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6564 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6565 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6566 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6567 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6568 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6569 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6570 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6571 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6572 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6573 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6574 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6575 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6576 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6577 /* G2 cores (aka PowerQUICC-II) */
6578 CPU_POWERPC_G2
= 0x00810011,
6579 CPU_POWERPC_G2H4
= 0x80811010,
6580 CPU_POWERPC_G2gp
= 0x80821010,
6581 CPU_POWERPC_G2ls
= 0x90810010,
6582 CPU_POWERPC_MPC603
= 0x00810100,
6583 CPU_POWERPC_G2_HIP3
= 0x00810101,
6584 CPU_POWERPC_G2_HIP4
= 0x80811014,
6585 /* G2_LE core (aka PowerQUICC-II) */
6586 CPU_POWERPC_G2LE
= 0x80820010,
6587 CPU_POWERPC_G2LEgp
= 0x80822010,
6588 CPU_POWERPC_G2LEls
= 0xA0822010,
6589 CPU_POWERPC_G2LEgp1
= 0x80822011,
6590 CPU_POWERPC_G2LEgp3
= 0x80822013,
6591 /* MPC52xx microcontrollers */
6592 /* XXX: MPC 5121 ? */
6593 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6594 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6595 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6596 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6597 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6598 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6599 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6600 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6601 /* MPC82xx microcontrollers */
6602 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6603 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6604 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6605 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6606 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6607 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6608 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6609 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6610 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6611 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6612 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6613 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6614 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6615 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6616 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6617 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6618 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6619 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6620 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6621 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6622 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6623 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6624 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6625 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6626 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6627 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6628 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6629 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6630 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
6633 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
6635 CPU_POWERPC_e200z0
= xxx
,
6638 CPU_POWERPC_e200z1
= xxx
,
6641 CPU_POWERPC_e200z3
= 0x81120000,
6643 CPU_POWERPC_e200z5
= 0x81000000,
6644 CPU_POWERPC_e200z6
= 0x81120000,
6645 /* MPC55xx microcontrollers */
6646 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6648 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6649 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6650 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6651 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6652 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6653 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6654 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6655 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6656 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6657 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6658 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6659 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6660 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6661 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6664 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6665 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6667 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6668 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6669 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6670 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6671 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6672 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
6675 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6676 CPU_POWERPC_e300c1
= 0x00830010,
6677 CPU_POWERPC_e300c2
= 0x00840010,
6678 CPU_POWERPC_e300c3
= 0x00850010,
6679 CPU_POWERPC_e300c4
= 0x00860010,
6680 /* MPC83xx microcontrollers */
6681 #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6682 #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6683 #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6684 #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6685 #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6686 #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6687 #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6688 #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6689 #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6690 #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6691 #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6692 #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6693 #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6694 #define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6695 #define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6696 #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6697 #define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6698 #define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6699 #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6700 #define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6701 #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6702 #define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6703 #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6704 #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6705 #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6706 #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6707 #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6708 #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6709 #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6710 #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
6713 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
6714 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
6715 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
6716 CPU_POWERPC_e500v1_v10
= 0x80200010,
6717 CPU_POWERPC_e500v1_v20
= 0x80200020,
6718 CPU_POWERPC_e500v2_v10
= 0x80210010,
6719 CPU_POWERPC_e500v2_v11
= 0x80210011,
6720 CPU_POWERPC_e500v2_v20
= 0x80210020,
6721 CPU_POWERPC_e500v2_v21
= 0x80210021,
6722 CPU_POWERPC_e500v2_v22
= 0x80210022,
6723 CPU_POWERPC_e500v2_v30
= 0x80210030,
6724 /* MPC85xx microcontrollers */
6725 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6726 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6727 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6728 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6729 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6730 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6731 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
6732 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6733 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6734 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
6735 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
6736 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6737 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
6738 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
6739 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6740 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
6741 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6742 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6743 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6744 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6745 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6746 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6747 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6748 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6749 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6750 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6751 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6752 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6753 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6754 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6755 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6756 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6757 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6758 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6759 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6760 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6761 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6762 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6763 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6764 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6765 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6766 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6767 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6768 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6769 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6770 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6771 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6772 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6773 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6774 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6775 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6776 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6777 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6778 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6779 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6780 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6781 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6782 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6783 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6784 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6785 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6786 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6787 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6788 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6789 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6790 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6791 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6792 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6793 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6794 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
6797 CPU_POWERPC_e600
= 0x80040010,
6798 /* MPC86xx microcontrollers */
6799 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6800 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6801 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
6802 /* PowerPC 6xx cores */
6803 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
6804 CPU_POWERPC_601_v0
= 0x00010001,
6805 CPU_POWERPC_601_v1
= 0x00010001,
6806 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
6807 CPU_POWERPC_601_v2
= 0x00010002,
6808 CPU_POWERPC_602
= 0x00050100,
6809 CPU_POWERPC_603
= 0x00030100,
6810 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6811 CPU_POWERPC_603E_v11
= 0x00060101,
6812 CPU_POWERPC_603E_v12
= 0x00060102,
6813 CPU_POWERPC_603E_v13
= 0x00060103,
6814 CPU_POWERPC_603E_v14
= 0x00060104,
6815 CPU_POWERPC_603E_v22
= 0x00060202,
6816 CPU_POWERPC_603E_v3
= 0x00060300,
6817 CPU_POWERPC_603E_v4
= 0x00060400,
6818 CPU_POWERPC_603E_v41
= 0x00060401,
6819 CPU_POWERPC_603E7t
= 0x00071201,
6820 CPU_POWERPC_603E7v
= 0x00070100,
6821 CPU_POWERPC_603E7v1
= 0x00070101,
6822 CPU_POWERPC_603E7v2
= 0x00070201,
6823 CPU_POWERPC_603E7
= 0x00070200,
6824 CPU_POWERPC_603P
= 0x00070000,
6825 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
6826 /* XXX: missing 0x00040303 (604) */
6827 CPU_POWERPC_604
= 0x00040103,
6828 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
6829 /* XXX: missing 0x00091203 */
6830 /* XXX: missing 0x00092110 */
6831 /* XXX: missing 0x00092120 */
6832 CPU_POWERPC_604E_v10
= 0x00090100,
6833 CPU_POWERPC_604E_v22
= 0x00090202,
6834 CPU_POWERPC_604E_v24
= 0x00090204,
6835 /* XXX: missing 0x000a0100 */
6836 /* XXX: missing 0x00093102 */
6837 CPU_POWERPC_604R
= 0x000a0101,
6839 CPU_POWERPC_604EV
= xxx
, /* XXX: same as 604R ? */
6841 /* PowerPC 740/750 cores (aka G3) */
6842 /* XXX: missing 0x00084202 */
6843 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
6844 CPU_POWERPC_7x0_v10
= 0x00080100,
6845 CPU_POWERPC_7x0_v20
= 0x00080200,
6846 CPU_POWERPC_7x0_v21
= 0x00080201,
6847 CPU_POWERPC_7x0_v22
= 0x00080202,
6848 CPU_POWERPC_7x0_v30
= 0x00080300,
6849 CPU_POWERPC_7x0_v31
= 0x00080301,
6850 CPU_POWERPC_740E
= 0x00080100,
6851 CPU_POWERPC_750E
= 0x00080200,
6852 CPU_POWERPC_7x0P
= 0x10080000,
6853 /* XXX: missing 0x00087010 (CL ?) */
6854 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6855 CPU_POWERPC_750CL_v10
= 0x00087200,
6856 CPU_POWERPC_750CL_v20
= 0x00087210, /* aka rev E */
6857 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
6858 CPU_POWERPC_750CX_v10
= 0x00082100,
6859 CPU_POWERPC_750CX_v20
= 0x00082200,
6860 CPU_POWERPC_750CX_v21
= 0x00082201,
6861 CPU_POWERPC_750CX_v22
= 0x00082202,
6862 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6863 CPU_POWERPC_750CXE_v21
= 0x00082211,
6864 CPU_POWERPC_750CXE_v22
= 0x00082212,
6865 CPU_POWERPC_750CXE_v23
= 0x00082213,
6866 CPU_POWERPC_750CXE_v24
= 0x00082214,
6867 CPU_POWERPC_750CXE_v24b
= 0x00083214,
6868 CPU_POWERPC_750CXE_v30
= 0x00082310,
6869 CPU_POWERPC_750CXE_v31
= 0x00082311,
6870 CPU_POWERPC_750CXE_v31b
= 0x00083311,
6871 CPU_POWERPC_750CXR
= 0x00083410,
6872 CPU_POWERPC_750FL
= 0x70000203,
6873 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6874 CPU_POWERPC_750FX_v10
= 0x70000100,
6875 CPU_POWERPC_750FX_v20
= 0x70000200,
6876 CPU_POWERPC_750FX_v21
= 0x70000201,
6877 CPU_POWERPC_750FX_v22
= 0x70000202,
6878 CPU_POWERPC_750FX_v23
= 0x70000203,
6879 CPU_POWERPC_750GL
= 0x70020102,
6880 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6881 CPU_POWERPC_750GX_v10
= 0x70020100,
6882 CPU_POWERPC_750GX_v11
= 0x70020101,
6883 CPU_POWERPC_750GX_v12
= 0x70020102,
6884 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
6885 CPU_POWERPC_750L_v20
= 0x00088200,
6886 CPU_POWERPC_750L_v21
= 0x00088201,
6887 CPU_POWERPC_750L_v22
= 0x00088202,
6888 CPU_POWERPC_750L_v30
= 0x00088300,
6889 CPU_POWERPC_750L_v32
= 0x00088302,
6890 /* PowerPC 745/755 cores */
6891 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6892 CPU_POWERPC_7x5_v10
= 0x00083100,
6893 CPU_POWERPC_7x5_v11
= 0x00083101,
6894 CPU_POWERPC_7x5_v20
= 0x00083200,
6895 CPU_POWERPC_7x5_v21
= 0x00083201,
6896 CPU_POWERPC_7x5_v22
= 0x00083202, /* aka D */
6897 CPU_POWERPC_7x5_v23
= 0x00083203, /* aka E */
6898 CPU_POWERPC_7x5_v24
= 0x00083204,
6899 CPU_POWERPC_7x5_v25
= 0x00083205,
6900 CPU_POWERPC_7x5_v26
= 0x00083206,
6901 CPU_POWERPC_7x5_v27
= 0x00083207,
6902 CPU_POWERPC_7x5_v28
= 0x00083208,
6904 CPU_POWERPC_7x5P
= xxx
,
6906 /* PowerPC 74xx cores (aka G4) */
6907 /* XXX: missing 0x000C1101 */
6908 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6909 CPU_POWERPC_7400_v10
= 0x000C0100,
6910 CPU_POWERPC_7400_v11
= 0x000C0101,
6911 CPU_POWERPC_7400_v20
= 0x000C0200,
6912 CPU_POWERPC_7400_v21
= 0x000C0201,
6913 CPU_POWERPC_7400_v22
= 0x000C0202,
6914 CPU_POWERPC_7400_v26
= 0x000C0206,
6915 CPU_POWERPC_7400_v27
= 0x000C0207,
6916 CPU_POWERPC_7400_v28
= 0x000C0208,
6917 CPU_POWERPC_7400_v29
= 0x000C0209,
6918 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6919 CPU_POWERPC_7410_v10
= 0x800C1100,
6920 CPU_POWERPC_7410_v11
= 0x800C1101,
6921 CPU_POWERPC_7410_v12
= 0x800C1102, /* aka C */
6922 CPU_POWERPC_7410_v13
= 0x800C1103, /* aka D */
6923 CPU_POWERPC_7410_v14
= 0x800C1104, /* aka E */
6924 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6925 CPU_POWERPC_7448_v10
= 0x80040100,
6926 CPU_POWERPC_7448_v11
= 0x80040101,
6927 CPU_POWERPC_7448_v20
= 0x80040200,
6928 CPU_POWERPC_7448_v21
= 0x80040201,
6929 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6930 CPU_POWERPC_7450_v10
= 0x80000100,
6931 CPU_POWERPC_7450_v11
= 0x80000101,
6932 CPU_POWERPC_7450_v12
= 0x80000102,
6933 CPU_POWERPC_7450_v20
= 0x80000200, /* aka A, B, C, D: 2.04 */
6934 CPU_POWERPC_7450_v21
= 0x80000201, /* aka E */
6935 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6936 CPU_POWERPC_74x1_v23
= 0x80000203, /* aka G: 2.3 */
6937 /* XXX: this entry might be a bug in some documentation */
6938 CPU_POWERPC_74x1_v210
= 0x80000210, /* aka G: 2.3 ? */
6939 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6940 CPU_POWERPC_74x5_v10
= 0x80010100,
6941 /* XXX: missing 0x80010200 */
6942 CPU_POWERPC_74x5_v21
= 0x80010201, /* aka C: 2.1 */
6943 CPU_POWERPC_74x5_v32
= 0x80010302,
6944 CPU_POWERPC_74x5_v33
= 0x80010303, /* aka F: 3.3 */
6945 CPU_POWERPC_74x5_v34
= 0x80010304, /* aka G: 3.4 */
6946 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
6947 CPU_POWERPC_74x7_v10
= 0x80020100, /* aka A: 1.0 */
6948 CPU_POWERPC_74x7_v11
= 0x80020101, /* aka B: 1.1 */
6949 CPU_POWERPC_74x7_v12
= 0x80020102, /* aka C: 1.2 */
6950 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6951 CPU_POWERPC_74x7A_v10
= 0x80030100, /* aka A: 1.0 */
6952 CPU_POWERPC_74x7A_v11
= 0x80030101, /* aka B: 1.1 */
6953 CPU_POWERPC_74x7A_v12
= 0x80030102, /* aka C: 1.2 */
6954 /* 64 bits PowerPC */
6955 #if defined(TARGET_PPC64)
6956 CPU_POWERPC_620
= 0x00140000,
6957 CPU_POWERPC_630
= 0x00400000,
6958 CPU_POWERPC_631
= 0x00410104,
6959 CPU_POWERPC_POWER4
= 0x00350000,
6960 CPU_POWERPC_POWER4P
= 0x00380000,
6961 /* XXX: missing 0x003A0201 */
6962 CPU_POWERPC_POWER5
= 0x003A0203,
6963 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6964 CPU_POWERPC_POWER5P
= 0x003B0000,
6965 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6966 CPU_POWERPC_POWER6
= 0x003E0000,
6967 CPU_POWERPC_POWER6_5
= 0x0F000001, /* POWER6 in POWER5 mode */
6968 CPU_POWERPC_POWER6A
= 0x0F000002,
6969 CPU_POWERPC_970
= 0x00390202,
6970 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6971 CPU_POWERPC_970FX_v10
= 0x00391100,
6972 CPU_POWERPC_970FX_v20
= 0x003C0200,
6973 CPU_POWERPC_970FX_v21
= 0x003C0201,
6974 CPU_POWERPC_970FX_v30
= 0x003C0300,
6975 CPU_POWERPC_970FX_v31
= 0x003C0301,
6976 CPU_POWERPC_970GX
= 0x00450000,
6977 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6978 CPU_POWERPC_970MP_v10
= 0x00440100,
6979 CPU_POWERPC_970MP_v11
= 0x00440101,
6980 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6981 CPU_POWERPC_CELL_v10
= 0x00700100,
6982 CPU_POWERPC_CELL_v20
= 0x00700400,
6983 CPU_POWERPC_CELL_v30
= 0x00700500,
6984 CPU_POWERPC_CELL_v31
= 0x00700501,
6985 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6986 CPU_POWERPC_RS64
= 0x00330000,
6987 CPU_POWERPC_RS64II
= 0x00340000,
6988 CPU_POWERPC_RS64III
= 0x00360000,
6989 CPU_POWERPC_RS64IV
= 0x00370000,
6990 #endif /* defined(TARGET_PPC64) */
6991 /* Original POWER */
6992 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6993 * POWER2 (RIOS2) & RSC2 (P2SC) here
6996 CPU_POWER
= xxx
, /* 0x20000 ? 0x30000 for RSC ? */
6999 CPU_POWER2
= xxx
, /* 0x40000 ? */
7002 CPU_POWERPC_PA6T
= 0x00900000,
7005 /* System version register (used on MPC 8xxx) */
7007 POWERPC_SVR_NONE
= 0x00000000,
7008 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7009 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7010 POWERPC_SVR_5200_v10
= 0x80110010,
7011 POWERPC_SVR_5200_v11
= 0x80110011,
7012 POWERPC_SVR_5200_v12
= 0x80110012,
7013 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7014 POWERPC_SVR_5200B_v20
= 0x80110020,
7015 POWERPC_SVR_5200B_v21
= 0x80110021,
7016 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7018 POWERPC_SVR_5533
= xxx
,
7021 POWERPC_SVR_5534
= xxx
,
7024 POWERPC_SVR_5553
= xxx
,
7027 POWERPC_SVR_5554
= xxx
,
7030 POWERPC_SVR_5561
= xxx
,
7033 POWERPC_SVR_5565
= xxx
,
7036 POWERPC_SVR_5566
= xxx
,
7039 POWERPC_SVR_5567
= xxx
,
7042 POWERPC_SVR_8313
= xxx
,
7045 POWERPC_SVR_8313E
= xxx
,
7048 POWERPC_SVR_8314
= xxx
,
7051 POWERPC_SVR_8314E
= xxx
,
7054 POWERPC_SVR_8315
= xxx
,
7057 POWERPC_SVR_8315E
= xxx
,
7060 POWERPC_SVR_8321
= xxx
,
7063 POWERPC_SVR_8321E
= xxx
,
7066 POWERPC_SVR_8323
= xxx
,
7069 POWERPC_SVR_8323E
= xxx
,
7071 POWERPC_SVR_8343A
= 0x80570030,
7072 POWERPC_SVR_8343EA
= 0x80560030,
7073 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7074 POWERPC_SVR_8347AP
= 0x80550030, /* PBGA package */
7075 POWERPC_SVR_8347AT
= 0x80530030, /* TBGA package */
7076 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7077 POWERPC_SVR_8347EAP
= 0x80540030, /* PBGA package */
7078 POWERPC_SVR_8347EAT
= 0x80520030, /* TBGA package */
7079 POWERPC_SVR_8349
= 0x80510010,
7080 POWERPC_SVR_8349A
= 0x80510030,
7081 POWERPC_SVR_8349E
= 0x80500010,
7082 POWERPC_SVR_8349EA
= 0x80500030,
7084 POWERPC_SVR_8358E
= xxx
,
7087 POWERPC_SVR_8360E
= xxx
,
7089 #define POWERPC_SVR_E500 0x40000000
7090 POWERPC_SVR_8377
= 0x80C70010 | POWERPC_SVR_E500
,
7091 POWERPC_SVR_8377E
= 0x80C60010 | POWERPC_SVR_E500
,
7092 POWERPC_SVR_8378
= 0x80C50010 | POWERPC_SVR_E500
,
7093 POWERPC_SVR_8378E
= 0x80C40010 | POWERPC_SVR_E500
,
7094 POWERPC_SVR_8379
= 0x80C30010 | POWERPC_SVR_E500
,
7095 POWERPC_SVR_8379E
= 0x80C00010 | POWERPC_SVR_E500
,
7096 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7097 POWERPC_SVR_8533_v10
= 0x80340010 | POWERPC_SVR_E500
,
7098 POWERPC_SVR_8533_v11
= 0x80340011 | POWERPC_SVR_E500
,
7099 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7100 POWERPC_SVR_8533E_v10
= 0x803C0010 | POWERPC_SVR_E500
,
7101 POWERPC_SVR_8533E_v11
= 0x803C0011 | POWERPC_SVR_E500
,
7102 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7103 POWERPC_SVR_8540_v10
= 0x80300010 | POWERPC_SVR_E500
,
7104 POWERPC_SVR_8540_v20
= 0x80300020 | POWERPC_SVR_E500
,
7105 POWERPC_SVR_8540_v21
= 0x80300021 | POWERPC_SVR_E500
,
7106 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7107 POWERPC_SVR_8541_v10
= 0x80720010 | POWERPC_SVR_E500
,
7108 POWERPC_SVR_8541_v11
= 0x80720011 | POWERPC_SVR_E500
,
7109 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7110 POWERPC_SVR_8541E_v10
= 0x807A0010 | POWERPC_SVR_E500
,
7111 POWERPC_SVR_8541E_v11
= 0x807A0011 | POWERPC_SVR_E500
,
7112 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7113 POWERPC_SVR_8543_v10
= 0x80320010 | POWERPC_SVR_E500
,
7114 POWERPC_SVR_8543_v11
= 0x80320011 | POWERPC_SVR_E500
,
7115 POWERPC_SVR_8543_v20
= 0x80320020 | POWERPC_SVR_E500
,
7116 POWERPC_SVR_8543_v21
= 0x80320021 | POWERPC_SVR_E500
,
7117 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7118 POWERPC_SVR_8543E_v10
= 0x803A0010 | POWERPC_SVR_E500
,
7119 POWERPC_SVR_8543E_v11
= 0x803A0011 | POWERPC_SVR_E500
,
7120 POWERPC_SVR_8543E_v20
= 0x803A0020 | POWERPC_SVR_E500
,
7121 POWERPC_SVR_8543E_v21
= 0x803A0021 | POWERPC_SVR_E500
,
7122 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7123 POWERPC_SVR_8544_v10
= 0x80340110 | POWERPC_SVR_E500
,
7124 POWERPC_SVR_8544_v11
= 0x80340111 | POWERPC_SVR_E500
,
7125 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7126 POWERPC_SVR_8544E_v10
= 0x803C0110 | POWERPC_SVR_E500
,
7127 POWERPC_SVR_8544E_v11
= 0x803C0111 | POWERPC_SVR_E500
,
7128 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7129 POWERPC_SVR_8545_v20
= 0x80310220 | POWERPC_SVR_E500
,
7130 POWERPC_SVR_8545_v21
= 0x80310221 | POWERPC_SVR_E500
,
7131 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7132 POWERPC_SVR_8545E_v20
= 0x80390220 | POWERPC_SVR_E500
,
7133 POWERPC_SVR_8545E_v21
= 0x80390221 | POWERPC_SVR_E500
,
7134 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7135 POWERPC_SVR_8547E_v20
= 0x80390120 | POWERPC_SVR_E500
,
7136 POWERPC_SVR_8547E_v21
= 0x80390121 | POWERPC_SVR_E500
,
7137 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7138 POWERPC_SVR_8548_v10
= 0x80310010 | POWERPC_SVR_E500
,
7139 POWERPC_SVR_8548_v11
= 0x80310011 | POWERPC_SVR_E500
,
7140 POWERPC_SVR_8548_v20
= 0x80310020 | POWERPC_SVR_E500
,
7141 POWERPC_SVR_8548_v21
= 0x80310021 | POWERPC_SVR_E500
,
7142 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7143 POWERPC_SVR_8548E_v10
= 0x80390010 | POWERPC_SVR_E500
,
7144 POWERPC_SVR_8548E_v11
= 0x80390011 | POWERPC_SVR_E500
,
7145 POWERPC_SVR_8548E_v20
= 0x80390020 | POWERPC_SVR_E500
,
7146 POWERPC_SVR_8548E_v21
= 0x80390021 | POWERPC_SVR_E500
,
7147 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7148 POWERPC_SVR_8555_v10
= 0x80710010 | POWERPC_SVR_E500
,
7149 POWERPC_SVR_8555_v11
= 0x80710011 | POWERPC_SVR_E500
,
7150 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7151 POWERPC_SVR_8555E_v10
= 0x80790010 | POWERPC_SVR_E500
,
7152 POWERPC_SVR_8555E_v11
= 0x80790011 | POWERPC_SVR_E500
,
7153 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7154 POWERPC_SVR_8560_v10
= 0x80700010 | POWERPC_SVR_E500
,
7155 POWERPC_SVR_8560_v20
= 0x80700020 | POWERPC_SVR_E500
,
7156 POWERPC_SVR_8560_v21
= 0x80700021 | POWERPC_SVR_E500
,
7157 POWERPC_SVR_8567
= 0x80750111 | POWERPC_SVR_E500
,
7158 POWERPC_SVR_8567E
= 0x807D0111 | POWERPC_SVR_E500
,
7159 POWERPC_SVR_8568
= 0x80750011 | POWERPC_SVR_E500
,
7160 POWERPC_SVR_8568E
= 0x807D0011 | POWERPC_SVR_E500
,
7161 POWERPC_SVR_8572
= 0x80E00010 | POWERPC_SVR_E500
,
7162 POWERPC_SVR_8572E
= 0x80E80010 | POWERPC_SVR_E500
,
7164 POWERPC_SVR_8610
= xxx
,
7166 POWERPC_SVR_8641
= 0x80900021,
7167 POWERPC_SVR_8641D
= 0x80900121,
7170 /*****************************************************************************/
7171 /* PowerPC CPU definitions */
7172 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7177 .insns_flags = glue(POWERPC_INSNS_,_type), \
7178 .msr_mask = glue(POWERPC_MSRM_,_type), \
7179 .mmu_model = glue(POWERPC_MMU_,_type), \
7180 .excp_model = glue(POWERPC_EXCP_,_type), \
7181 .bus_model = glue(POWERPC_INPUT_,_type), \
7182 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7183 .flags = glue(POWERPC_FLAG_,_type), \
7184 .init_proc = &glue(init_proc_,_type), \
7185 .check_pow = &glue(check_pow_,_type), \
7187 #define POWERPC_DEF(_name, _pvr, _type) \
7188 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7190 static const ppc_def_t ppc_defs
[] = {
7191 /* Embedded PowerPC */
7192 /* PowerPC 401 family */
7193 /* Generic PowerPC 401 */
7194 POWERPC_DEF("401", CPU_POWERPC_401
, 401),
7195 /* PowerPC 401 cores */
7197 POWERPC_DEF("401A1", CPU_POWERPC_401A1
, 401),
7199 POWERPC_DEF("401B2", CPU_POWERPC_401B2
, 401x2
),
7202 POWERPC_DEF("401B3", CPU_POWERPC_401B3
, 401x3
),
7205 POWERPC_DEF("401C2", CPU_POWERPC_401C2
, 401x2
),
7207 POWERPC_DEF("401D2", CPU_POWERPC_401D2
, 401x2
),
7209 POWERPC_DEF("401E2", CPU_POWERPC_401E2
, 401x2
),
7211 POWERPC_DEF("401F2", CPU_POWERPC_401F2
, 401x2
),
7213 /* XXX: to be checked */
7214 POWERPC_DEF("401G2", CPU_POWERPC_401G2
, 401x2
),
7215 /* PowerPC 401 microcontrolers */
7218 POWERPC_DEF("401GF", CPU_POWERPC_401GF
, 401),
7220 /* IOP480 (401 microcontroler) */
7221 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480
, IOP480
),
7222 /* IBM Processor for Network Resources */
7223 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA
, 401),
7225 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP
, 401),
7227 /* PowerPC 403 family */
7228 /* Generic PowerPC 403 */
7229 POWERPC_DEF("403", CPU_POWERPC_403
, 403),
7230 /* PowerPC 403 microcontrolers */
7231 /* PowerPC 403 GA */
7232 POWERPC_DEF("403GA", CPU_POWERPC_403GA
, 403),
7233 /* PowerPC 403 GB */
7234 POWERPC_DEF("403GB", CPU_POWERPC_403GB
, 403),
7235 /* PowerPC 403 GC */
7236 POWERPC_DEF("403GC", CPU_POWERPC_403GC
, 403),
7237 /* PowerPC 403 GCX */
7238 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX
, 403GCX
),
7240 /* PowerPC 403 GP */
7241 POWERPC_DEF("403GP", CPU_POWERPC_403GP
, 403),
7243 /* PowerPC 405 family */
7244 /* Generic PowerPC 405 */
7245 POWERPC_DEF("405", CPU_POWERPC_405
, 405),
7246 /* PowerPC 405 cores */
7248 /* PowerPC 405 A3 */
7249 POWERPC_DEF("405A3", CPU_POWERPC_405A3
, 405),
7252 /* PowerPC 405 A4 */
7253 POWERPC_DEF("405A4", CPU_POWERPC_405A4
, 405),
7256 /* PowerPC 405 B3 */
7257 POWERPC_DEF("405B3", CPU_POWERPC_405B3
, 405),
7260 /* PowerPC 405 B4 */
7261 POWERPC_DEF("405B4", CPU_POWERPC_405B4
, 405),
7264 /* PowerPC 405 C3 */
7265 POWERPC_DEF("405C3", CPU_POWERPC_405C3
, 405),
7268 /* PowerPC 405 C4 */
7269 POWERPC_DEF("405C4", CPU_POWERPC_405C4
, 405),
7271 /* PowerPC 405 D2 */
7272 POWERPC_DEF("405D2", CPU_POWERPC_405D2
, 405),
7274 /* PowerPC 405 D3 */
7275 POWERPC_DEF("405D3", CPU_POWERPC_405D3
, 405),
7277 /* PowerPC 405 D4 */
7278 POWERPC_DEF("405D4", CPU_POWERPC_405D4
, 405),
7280 /* PowerPC 405 D5 */
7281 POWERPC_DEF("405D5", CPU_POWERPC_405D5
, 405),
7284 /* PowerPC 405 E4 */
7285 POWERPC_DEF("405E4", CPU_POWERPC_405E4
, 405),
7288 /* PowerPC 405 F4 */
7289 POWERPC_DEF("405F4", CPU_POWERPC_405F4
, 405),
7292 /* PowerPC 405 F5 */
7293 POWERPC_DEF("405F5", CPU_POWERPC_405F5
, 405),
7296 /* PowerPC 405 F6 */
7297 POWERPC_DEF("405F6", CPU_POWERPC_405F6
, 405),
7299 /* PowerPC 405 microcontrolers */
7300 /* PowerPC 405 CR */
7301 POWERPC_DEF("405CR", CPU_POWERPC_405CR
, 405),
7302 /* PowerPC 405 CRa */
7303 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa
, 405),
7304 /* PowerPC 405 CRb */
7305 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb
, 405),
7306 /* PowerPC 405 CRc */
7307 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc
, 405),
7308 /* PowerPC 405 EP */
7309 POWERPC_DEF("405EP", CPU_POWERPC_405EP
, 405),
7311 /* PowerPC 405 EXr */
7312 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr
, 405),
7314 /* PowerPC 405 EZ */
7315 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ
, 405),
7317 /* PowerPC 405 FX */
7318 POWERPC_DEF("405FX", CPU_POWERPC_405FX
, 405),
7320 /* PowerPC 405 GP */
7321 POWERPC_DEF("405GP", CPU_POWERPC_405GP
, 405),
7322 /* PowerPC 405 GPa */
7323 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa
, 405),
7324 /* PowerPC 405 GPb */
7325 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb
, 405),
7326 /* PowerPC 405 GPc */
7327 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc
, 405),
7328 /* PowerPC 405 GPd */
7329 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd
, 405),
7330 /* PowerPC 405 GPe */
7331 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe
, 405),
7332 /* PowerPC 405 GPR */
7333 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR
, 405),
7336 POWERPC_DEF("405H", CPU_POWERPC_405H
, 405),
7340 POWERPC_DEF("405L", CPU_POWERPC_405L
, 405),
7342 /* PowerPC 405 LP */
7343 POWERPC_DEF("405LP", CPU_POWERPC_405LP
, 405),
7345 /* PowerPC 405 PM */
7346 POWERPC_DEF("405PM", CPU_POWERPC_405PM
, 405),
7349 /* PowerPC 405 PS */
7350 POWERPC_DEF("405PS", CPU_POWERPC_405PS
, 405),
7354 POWERPC_DEF("405S", CPU_POWERPC_405S
, 405),
7357 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H
, 405),
7359 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2
, 405),
7361 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L
, 405),
7363 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3
, 405),
7365 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1
, 405),
7368 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161
, 405),
7371 /* PowerPC LC77700 (Sanyo) */
7372 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700
, 405),
7374 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7377 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000
, 401x2
),
7381 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010
, 401x2
),
7385 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210
, 401x3
),
7388 POWERPC_DEF("STB03", CPU_POWERPC_STB03
, 405),
7391 POWERPC_DEF("STB043", CPU_POWERPC_STB043
, 405),
7395 POWERPC_DEF("STB045", CPU_POWERPC_STB045
, 405),
7398 POWERPC_DEF("STB04", CPU_POWERPC_STB04
, 405),
7400 POWERPC_DEF("STB25", CPU_POWERPC_STB25
, 405),
7403 POWERPC_DEF("STB130", CPU_POWERPC_STB130
, 405),
7405 /* Xilinx PowerPC 405 cores */
7406 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4
, 405),
7407 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7
, 405),
7408 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20
, 405),
7409 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50
, 405),
7411 /* Zarlink ZL10310 */
7412 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310
, 405),
7415 /* Zarlink ZL10311 */
7416 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311
, 405),
7419 /* Zarlink ZL10320 */
7420 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320
, 405),
7423 /* Zarlink ZL10321 */
7424 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321
, 405),
7426 /* PowerPC 440 family */
7427 #if defined(TODO_USER_ONLY)
7428 /* Generic PowerPC 440 */
7429 POWERPC_DEF("440", CPU_POWERPC_440
, 440GP
),
7431 /* PowerPC 440 cores */
7433 /* PowerPC 440 A4 */
7434 POWERPC_DEF("440A4", CPU_POWERPC_440A4
, 440x4
),
7437 /* PowerPC 440 A5 */
7438 POWERPC_DEF("440A5", CPU_POWERPC_440A5
, 440x5
),
7441 /* PowerPC 440 B4 */
7442 POWERPC_DEF("440B4", CPU_POWERPC_440B4
, 440x4
),
7445 /* PowerPC 440 G4 */
7446 POWERPC_DEF("440G4", CPU_POWERPC_440G4
, 440x4
),
7449 /* PowerPC 440 F5 */
7450 POWERPC_DEF("440F5", CPU_POWERPC_440F5
, 440x5
),
7453 /* PowerPC 440 G5 */
7454 POWERPC_DEF("440G5", CPU_POWERPC_440G5
, 440x5
),
7458 POWERPC_DEF("440H4", CPU_POWERPC_440H4
, 440x4
),
7462 POWERPC_DEF("440H6", CPU_POWERPC_440H6
, 440Gx5
),
7464 /* PowerPC 440 microcontrolers */
7465 #if defined(TODO_USER_ONLY)
7466 /* PowerPC 440 EP */
7467 POWERPC_DEF("440EP", CPU_POWERPC_440EP
, 440EP
),
7469 #if defined(TODO_USER_ONLY)
7470 /* PowerPC 440 EPa */
7471 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa
, 440EP
),
7473 #if defined(TODO_USER_ONLY)
7474 /* PowerPC 440 EPb */
7475 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb
, 440EP
),
7477 #if defined(TODO_USER_ONLY)
7478 /* PowerPC 440 EPX */
7479 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX
, 440EP
),
7481 #if defined(TODO_USER_ONLY)
7482 /* PowerPC 440 GP */
7483 POWERPC_DEF("440GP", CPU_POWERPC_440GP
, 440GP
),
7485 #if defined(TODO_USER_ONLY)
7486 /* PowerPC 440 GPb */
7487 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb
, 440GP
),
7489 #if defined(TODO_USER_ONLY)
7490 /* PowerPC 440 GPc */
7491 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc
, 440GP
),
7493 #if defined(TODO_USER_ONLY)
7494 /* PowerPC 440 GR */
7495 POWERPC_DEF("440GR", CPU_POWERPC_440GR
, 440x5
),
7497 #if defined(TODO_USER_ONLY)
7498 /* PowerPC 440 GRa */
7499 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa
, 440x5
),
7501 #if defined(TODO_USER_ONLY)
7502 /* PowerPC 440 GRX */
7503 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX
, 440x5
),
7505 #if defined(TODO_USER_ONLY)
7506 /* PowerPC 440 GX */
7507 POWERPC_DEF("440GX", CPU_POWERPC_440GX
, 440EP
),
7509 #if defined(TODO_USER_ONLY)
7510 /* PowerPC 440 GXa */
7511 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa
, 440EP
),
7513 #if defined(TODO_USER_ONLY)
7514 /* PowerPC 440 GXb */
7515 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb
, 440EP
),
7517 #if defined(TODO_USER_ONLY)
7518 /* PowerPC 440 GXc */
7519 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc
, 440EP
),
7521 #if defined(TODO_USER_ONLY)
7522 /* PowerPC 440 GXf */
7523 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf
, 440EP
),
7527 POWERPC_DEF("440S", CPU_POWERPC_440S
, 440),
7529 #if defined(TODO_USER_ONLY)
7530 /* PowerPC 440 SP */
7531 POWERPC_DEF("440SP", CPU_POWERPC_440SP
, 440EP
),
7533 #if defined(TODO_USER_ONLY)
7534 /* PowerPC 440 SP2 */
7535 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2
, 440EP
),
7537 #if defined(TODO_USER_ONLY)
7538 /* PowerPC 440 SPE */
7539 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE
, 440EP
),
7541 /* PowerPC 460 family */
7543 /* Generic PowerPC 464 */
7544 POWERPC_DEF("464", CPU_POWERPC_464
, 460),
7546 /* PowerPC 464 microcontrolers */
7548 /* PowerPC 464H90 */
7549 POWERPC_DEF("464H90", CPU_POWERPC_464H90
, 460),
7552 /* PowerPC 464H90F */
7553 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F
, 460F
),
7555 /* Freescale embedded PowerPC cores */
7556 /* MPC5xx family (aka RCPU) */
7557 #if defined(TODO_USER_ONLY)
7558 /* Generic MPC5xx core */
7559 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx
, MPC5xx
),
7561 #if defined(TODO_USER_ONLY)
7562 /* Codename for MPC5xx core */
7563 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx
, MPC5xx
),
7565 /* MPC5xx microcontrollers */
7566 #if defined(TODO_USER_ONLY)
7568 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560
, MPC5xx
),
7570 #if defined(TODO_USER_ONLY)
7572 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509
, MPC5xx
),
7574 #if defined(TODO_USER_ONLY)
7576 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533
, MPC5xx
),
7578 #if defined(TODO_USER_ONLY)
7580 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534
, MPC5xx
),
7582 #if defined(TODO_USER_ONLY)
7584 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555
, MPC5xx
),
7586 #if defined(TODO_USER_ONLY)
7588 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556
, MPC5xx
),
7590 #if defined(TODO_USER_ONLY)
7592 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560
, MPC5xx
),
7594 #if defined(TODO_USER_ONLY)
7596 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561
, MPC5xx
),
7598 #if defined(TODO_USER_ONLY)
7600 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562
, MPC5xx
),
7602 #if defined(TODO_USER_ONLY)
7604 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563
, MPC5xx
),
7606 #if defined(TODO_USER_ONLY)
7608 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564
, MPC5xx
),
7610 #if defined(TODO_USER_ONLY)
7612 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565
, MPC5xx
),
7614 #if defined(TODO_USER_ONLY)
7616 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566
, MPC5xx
),
7618 /* MPC8xx family (aka PowerQUICC) */
7619 #if defined(TODO_USER_ONLY)
7620 /* Generic MPC8xx core */
7621 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx
, MPC8xx
),
7623 #if defined(TODO_USER_ONLY)
7624 /* Codename for MPC8xx core */
7625 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx
, MPC8xx
),
7627 /* MPC8xx microcontrollers */
7628 #if defined(TODO_USER_ONLY)
7630 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823
, MPC8xx
),
7632 #if defined(TODO_USER_ONLY)
7634 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821
, MPC8xx
),
7636 #if defined(TODO_USER_ONLY)
7638 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823
, MPC8xx
),
7640 #if defined(TODO_USER_ONLY)
7642 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850
, MPC8xx
),
7644 #if defined(TODO_USER_ONLY)
7646 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T
, MPC8xx
),
7648 #if defined(TODO_USER_ONLY)
7650 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T
, MPC8xx
),
7652 #if defined(TODO_USER_ONLY)
7654 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857
, MPC8xx
),
7656 #if defined(TODO_USER_ONLY)
7658 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859
, MPC8xx
),
7660 #if defined(TODO_USER_ONLY)
7662 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860
, MPC8xx
),
7664 #if defined(TODO_USER_ONLY)
7666 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862
, MPC8xx
),
7668 #if defined(TODO_USER_ONLY)
7670 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866
, MPC8xx
),
7672 #if defined(TODO_USER_ONLY)
7674 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870
, MPC8xx
),
7676 #if defined(TODO_USER_ONLY)
7678 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875
, MPC8xx
),
7680 #if defined(TODO_USER_ONLY)
7682 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880
, MPC8xx
),
7684 #if defined(TODO_USER_ONLY)
7686 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885
, MPC8xx
),
7688 /* MPC82xx family (aka PowerQUICC-II) */
7689 /* Generic MPC52xx core */
7690 POWERPC_DEF_SVR("MPC52xx",
7691 CPU_POWERPC_MPC52xx
, POWERPC_SVR_52xx
, G2LE
),
7692 /* Generic MPC82xx core */
7693 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx
, G2
),
7694 /* Codename for MPC82xx */
7695 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx
, G2
),
7696 /* PowerPC G2 core */
7697 POWERPC_DEF("G2", CPU_POWERPC_G2
, G2
),
7698 /* PowerPC G2 H4 core */
7699 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4
, G2
),
7700 /* PowerPC G2 GP core */
7701 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp
, G2
),
7702 /* PowerPC G2 LS core */
7703 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls
, G2
),
7704 /* PowerPC G2 HiP3 core */
7705 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3
, G2
),
7706 /* PowerPC G2 HiP4 core */
7707 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4
, G2
),
7708 /* PowerPC MPC603 core */
7709 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603
, 603E
),
7710 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7711 POWERPC_DEF("G2le", CPU_POWERPC_G2LE
, G2LE
),
7712 /* PowerPC G2LE GP core */
7713 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp
, G2LE
),
7714 /* PowerPC G2LE LS core */
7715 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls
, G2LE
),
7716 /* PowerPC G2LE GP1 core */
7717 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1
, G2LE
),
7718 /* PowerPC G2LE GP3 core */
7719 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1
, G2LE
),
7720 /* PowerPC MPC603 microcontrollers */
7722 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240
, 603E
),
7723 /* PowerPC G2 microcontrollers */
7726 POWERPC_DEF_SVR("MPC5121",
7727 CPU_POWERPC_MPC5121
, POWERPC_SVR_5121
, G2LE
),
7730 POWERPC_DEF_SVR("MPC5200",
7731 CPU_POWERPC_MPC5200
, POWERPC_SVR_5200
, G2LE
),
7733 POWERPC_DEF_SVR("MPC5200_v10",
7734 CPU_POWERPC_MPC5200_v10
, POWERPC_SVR_5200_v10
, G2LE
),
7736 POWERPC_DEF_SVR("MPC5200_v11",
7737 CPU_POWERPC_MPC5200_v11
, POWERPC_SVR_5200_v11
, G2LE
),
7739 POWERPC_DEF_SVR("MPC5200_v12",
7740 CPU_POWERPC_MPC5200_v12
, POWERPC_SVR_5200_v12
, G2LE
),
7742 POWERPC_DEF_SVR("MPC5200B",
7743 CPU_POWERPC_MPC5200B
, POWERPC_SVR_5200B
, G2LE
),
7745 POWERPC_DEF_SVR("MPC5200B_v20",
7746 CPU_POWERPC_MPC5200B_v20
, POWERPC_SVR_5200B_v20
, G2LE
),
7748 POWERPC_DEF_SVR("MPC5200B_v21",
7749 CPU_POWERPC_MPC5200B_v21
, POWERPC_SVR_5200B_v21
, G2LE
),
7751 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241
, G2
),
7753 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245
, G2
),
7755 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247
, G2LE
),
7757 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248
, G2LE
),
7759 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250
, G2
),
7761 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3
, G2
),
7763 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4
, G2
),
7765 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255
, G2
),
7767 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3
, G2
),
7769 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4
, G2
),
7771 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260
, G2
),
7773 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3
, G2
),
7775 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4
, G2
),
7777 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264
, G2
),
7779 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3
, G2
),
7781 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4
, G2
),
7783 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265
, G2
),
7785 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3
, G2
),
7787 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4
, G2
),
7789 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266
, G2
),
7791 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3
, G2
),
7793 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4
, G2
),
7795 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270
, G2LE
),
7797 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271
, G2LE
),
7799 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272
, G2LE
),
7801 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275
, G2LE
),
7803 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280
, G2LE
),
7805 /* Generic PowerPC e200 core */
7806 POWERPC_DEF("e200", CPU_POWERPC_e200
, e200
),
7807 /* Generic MPC55xx core */
7809 POWERPC_DEF_SVR("MPC55xx",
7810 CPU_POWERPC_MPC55xx
, POWERPC_SVR_55xx
, e200
),
7813 /* PowerPC e200z0 core */
7814 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0
, e200
),
7817 /* PowerPC e200z1 core */
7818 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1
, e200
),
7821 /* PowerPC e200z3 core */
7822 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3
, e200
),
7824 /* PowerPC e200z5 core */
7825 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5
, e200
),
7826 /* PowerPC e200z6 core */
7827 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6
, e200
),
7828 /* PowerPC e200 microcontrollers */
7831 POWERPC_DEF_SVR("MPC5514E",
7832 CPU_POWERPC_MPC5514E
, POWERPC_SVR_5514E
, e200
),
7836 POWERPC_DEF_SVR("MPC5514E_v0",
7837 CPU_POWERPC_MPC5514E_v0
, POWERPC_SVR_5514E_v0
, e200
),
7841 POWERPC_DEF_SVR("MPC5514E_v1",
7842 CPU_POWERPC_MPC5514E_v1
, POWERPC_SVR_5514E_v1
, e200
),
7846 POWERPC_DEF_SVR("MPC5514G",
7847 CPU_POWERPC_MPC5514G
, POWERPC_SVR_5514G
, e200
),
7851 POWERPC_DEF_SVR("MPC5514G_v0",
7852 CPU_POWERPC_MPC5514G_v0
, POWERPC_SVR_5514G_v0
, e200
),
7856 POWERPC_DEF_SVR("MPC5514G_v1",
7857 CPU_POWERPC_MPC5514G_v1
, POWERPC_SVR_5514G_v1
, e200
),
7861 POWERPC_DEF_SVR("MPC5515S",
7862 CPU_POWERPC_MPC5515S
, POWERPC_SVR_5515S
, e200
),
7866 POWERPC_DEF_SVR("MPC5516E",
7867 CPU_POWERPC_MPC5516E
, POWERPC_SVR_5516E
, e200
),
7871 POWERPC_DEF_SVR("MPC5516E_v0",
7872 CPU_POWERPC_MPC5516E_v0
, POWERPC_SVR_5516E_v0
, e200
),
7876 POWERPC_DEF_SVR("MPC5516E_v1",
7877 CPU_POWERPC_MPC5516E_v1
, POWERPC_SVR_5516E_v1
, e200
),
7881 POWERPC_DEF_SVR("MPC5516G",
7882 CPU_POWERPC_MPC5516G
, POWERPC_SVR_5516G
, e200
),
7886 POWERPC_DEF_SVR("MPC5516G_v0",
7887 CPU_POWERPC_MPC5516G_v0
, POWERPC_SVR_5516G_v0
, e200
),
7891 POWERPC_DEF_SVR("MPC5516G_v1",
7892 CPU_POWERPC_MPC5516G_v1
, POWERPC_SVR_5516G_v1
, e200
),
7896 POWERPC_DEF_SVR("MPC5516S",
7897 CPU_POWERPC_MPC5516S
, POWERPC_SVR_5516S
, e200
),
7901 POWERPC_DEF_SVR("MPC5533",
7902 CPU_POWERPC_MPC5533
, POWERPC_SVR_5533
, e200
),
7906 POWERPC_DEF_SVR("MPC5534",
7907 CPU_POWERPC_MPC5534
, POWERPC_SVR_5534
, e200
),
7911 POWERPC_DEF_SVR("MPC5553",
7912 CPU_POWERPC_MPC5553
, POWERPC_SVR_5553
, e200
),
7916 POWERPC_DEF_SVR("MPC5554",
7917 CPU_POWERPC_MPC5554
, POWERPC_SVR_5554
, e200
),
7921 POWERPC_DEF_SVR("MPC5561",
7922 CPU_POWERPC_MPC5561
, POWERPC_SVR_5561
, e200
),
7926 POWERPC_DEF_SVR("MPC5565",
7927 CPU_POWERPC_MPC5565
, POWERPC_SVR_5565
, e200
),
7931 POWERPC_DEF_SVR("MPC5566",
7932 CPU_POWERPC_MPC5566
, POWERPC_SVR_5566
, e200
),
7936 POWERPC_DEF_SVR("MPC5567",
7937 CPU_POWERPC_MPC5567
, POWERPC_SVR_5567
, e200
),
7940 /* Generic PowerPC e300 core */
7941 POWERPC_DEF("e300", CPU_POWERPC_e300
, e300
),
7942 /* PowerPC e300c1 core */
7943 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1
, e300
),
7944 /* PowerPC e300c2 core */
7945 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2
, e300
),
7946 /* PowerPC e300c3 core */
7947 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3
, e300
),
7948 /* PowerPC e300c4 core */
7949 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4
, e300
),
7950 /* PowerPC e300 microcontrollers */
7953 POWERPC_DEF_SVR("MPC8313",
7954 CPU_POWERPC_MPC8313
, POWERPC_SVR_8313
, e300
),
7958 POWERPC_DEF_SVR("MPC8313E",
7959 CPU_POWERPC_MPC8313E
, POWERPC_SVR_8313E
, e300
),
7963 POWERPC_DEF_SVR("MPC8314",
7964 CPU_POWERPC_MPC8314
, POWERPC_SVR_8314
, e300
),
7968 POWERPC_DEF_SVR("MPC8314E",
7969 CPU_POWERPC_MPC8314E
, POWERPC_SVR_8314E
, e300
),
7973 POWERPC_DEF_SVR("MPC8315",
7974 CPU_POWERPC_MPC8315
, POWERPC_SVR_8315
, e300
),
7978 POWERPC_DEF_SVR("MPC8315E",
7979 CPU_POWERPC_MPC8315E
, POWERPC_SVR_8315E
, e300
),
7983 POWERPC_DEF_SVR("MPC8321",
7984 CPU_POWERPC_MPC8321
, POWERPC_SVR_8321
, e300
),
7988 POWERPC_DEF_SVR("MPC8321E",
7989 CPU_POWERPC_MPC8321E
, POWERPC_SVR_8321E
, e300
),
7993 POWERPC_DEF_SVR("MPC8323",
7994 CPU_POWERPC_MPC8323
, POWERPC_SVR_8323
, e300
),
7998 POWERPC_DEF_SVR("MPC8323E",
7999 CPU_POWERPC_MPC8323E
, POWERPC_SVR_8323E
, e300
),
8002 POWERPC_DEF_SVR("MPC8343A",
8003 CPU_POWERPC_MPC8343A
, POWERPC_SVR_8343A
, e300
),
8005 POWERPC_DEF_SVR("MPC8343EA",
8006 CPU_POWERPC_MPC8343EA
, POWERPC_SVR_8343EA
, e300
),
8008 POWERPC_DEF_SVR("MPC8347A",
8009 CPU_POWERPC_MPC8347A
, POWERPC_SVR_8347A
, e300
),
8011 POWERPC_DEF_SVR("MPC8347AT",
8012 CPU_POWERPC_MPC8347AT
, POWERPC_SVR_8347AT
, e300
),
8014 POWERPC_DEF_SVR("MPC8347AP",
8015 CPU_POWERPC_MPC8347AP
, POWERPC_SVR_8347AP
, e300
),
8017 POWERPC_DEF_SVR("MPC8347EA",
8018 CPU_POWERPC_MPC8347EA
, POWERPC_SVR_8347EA
, e300
),
8020 POWERPC_DEF_SVR("MPC8347EAT",
8021 CPU_POWERPC_MPC8347EAT
, POWERPC_SVR_8347EAT
, e300
),
8023 POWERPC_DEF_SVR("MPC8347EAP",
8024 CPU_POWERPC_MPC8347EAP
, POWERPC_SVR_8347EAP
, e300
),
8026 POWERPC_DEF_SVR("MPC8349",
8027 CPU_POWERPC_MPC8349
, POWERPC_SVR_8349
, e300
),
8029 POWERPC_DEF_SVR("MPC8349A",
8030 CPU_POWERPC_MPC8349A
, POWERPC_SVR_8349A
, e300
),
8032 POWERPC_DEF_SVR("MPC8349E",
8033 CPU_POWERPC_MPC8349E
, POWERPC_SVR_8349E
, e300
),
8035 POWERPC_DEF_SVR("MPC8349EA",
8036 CPU_POWERPC_MPC8349EA
, POWERPC_SVR_8349EA
, e300
),
8039 POWERPC_DEF_SVR("MPC8358E",
8040 CPU_POWERPC_MPC8358E
, POWERPC_SVR_8358E
, e300
),
8044 POWERPC_DEF_SVR("MPC8360E",
8045 CPU_POWERPC_MPC8360E
, POWERPC_SVR_8360E
, e300
),
8048 POWERPC_DEF_SVR("MPC8377",
8049 CPU_POWERPC_MPC8377
, POWERPC_SVR_8377
, e300
),
8051 POWERPC_DEF_SVR("MPC8377E",
8052 CPU_POWERPC_MPC8377E
, POWERPC_SVR_8377E
, e300
),
8054 POWERPC_DEF_SVR("MPC8378",
8055 CPU_POWERPC_MPC8378
, POWERPC_SVR_8378
, e300
),
8057 POWERPC_DEF_SVR("MPC8378E",
8058 CPU_POWERPC_MPC8378E
, POWERPC_SVR_8378E
, e300
),
8060 POWERPC_DEF_SVR("MPC8379",
8061 CPU_POWERPC_MPC8379
, POWERPC_SVR_8379
, e300
),
8063 POWERPC_DEF_SVR("MPC8379E",
8064 CPU_POWERPC_MPC8379E
, POWERPC_SVR_8379E
, e300
),
8066 /* PowerPC e500 core */
8067 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22
, e500v2
),
8068 /* PowerPC e500v1 core */
8069 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1
, e500v1
),
8070 /* PowerPC e500 v1.0 core */
8071 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10
, e500v1
),
8072 /* PowerPC e500 v2.0 core */
8073 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20
, e500v1
),
8074 /* PowerPC e500v2 core */
8075 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2
, e500v2
),
8076 /* PowerPC e500v2 v1.0 core */
8077 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10
, e500v2
),
8078 /* PowerPC e500v2 v2.0 core */
8079 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20
, e500v2
),
8080 /* PowerPC e500v2 v2.1 core */
8081 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21
, e500v2
),
8082 /* PowerPC e500v2 v2.2 core */
8083 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22
, e500v2
),
8084 /* PowerPC e500v2 v3.0 core */
8085 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30
, e500v2
),
8086 /* PowerPC e500 microcontrollers */
8088 POWERPC_DEF_SVR("MPC8533",
8089 CPU_POWERPC_MPC8533
, POWERPC_SVR_8533
, e500v2
),
8091 POWERPC_DEF_SVR("MPC8533_v10",
8092 CPU_POWERPC_MPC8533_v10
, POWERPC_SVR_8533_v10
, e500v2
),
8094 POWERPC_DEF_SVR("MPC8533_v11",
8095 CPU_POWERPC_MPC8533_v11
, POWERPC_SVR_8533_v11
, e500v2
),
8097 POWERPC_DEF_SVR("MPC8533E",
8098 CPU_POWERPC_MPC8533E
, POWERPC_SVR_8533E
, e500v2
),
8100 POWERPC_DEF_SVR("MPC8533E_v10",
8101 CPU_POWERPC_MPC8533E_v10
, POWERPC_SVR_8533E_v10
, e500v2
),
8102 POWERPC_DEF_SVR("MPC8533E_v11",
8103 CPU_POWERPC_MPC8533E_v11
, POWERPC_SVR_8533E_v11
, e500v2
),
8105 POWERPC_DEF_SVR("MPC8540",
8106 CPU_POWERPC_MPC8540
, POWERPC_SVR_8540
, e500v1
),
8108 POWERPC_DEF_SVR("MPC8540_v10",
8109 CPU_POWERPC_MPC8540_v10
, POWERPC_SVR_8540_v10
, e500v1
),
8111 POWERPC_DEF_SVR("MPC8540_v20",
8112 CPU_POWERPC_MPC8540_v20
, POWERPC_SVR_8540_v20
, e500v1
),
8114 POWERPC_DEF_SVR("MPC8540_v21",
8115 CPU_POWERPC_MPC8540_v21
, POWERPC_SVR_8540_v21
, e500v1
),
8117 POWERPC_DEF_SVR("MPC8541",
8118 CPU_POWERPC_MPC8541
, POWERPC_SVR_8541
, e500v1
),
8120 POWERPC_DEF_SVR("MPC8541_v10",
8121 CPU_POWERPC_MPC8541_v10
, POWERPC_SVR_8541_v10
, e500v1
),
8123 POWERPC_DEF_SVR("MPC8541_v11",
8124 CPU_POWERPC_MPC8541_v11
, POWERPC_SVR_8541_v11
, e500v1
),
8126 POWERPC_DEF_SVR("MPC8541E",
8127 CPU_POWERPC_MPC8541E
, POWERPC_SVR_8541E
, e500v1
),
8129 POWERPC_DEF_SVR("MPC8541E_v10",
8130 CPU_POWERPC_MPC8541E_v10
, POWERPC_SVR_8541E_v10
, e500v1
),
8132 POWERPC_DEF_SVR("MPC8541E_v11",
8133 CPU_POWERPC_MPC8541E_v11
, POWERPC_SVR_8541E_v11
, e500v1
),
8135 POWERPC_DEF_SVR("MPC8543",
8136 CPU_POWERPC_MPC8543
, POWERPC_SVR_8543
, e500v2
),
8138 POWERPC_DEF_SVR("MPC8543_v10",
8139 CPU_POWERPC_MPC8543_v10
, POWERPC_SVR_8543_v10
, e500v2
),
8141 POWERPC_DEF_SVR("MPC8543_v11",
8142 CPU_POWERPC_MPC8543_v11
, POWERPC_SVR_8543_v11
, e500v2
),
8144 POWERPC_DEF_SVR("MPC8543_v20",
8145 CPU_POWERPC_MPC8543_v20
, POWERPC_SVR_8543_v20
, e500v2
),
8147 POWERPC_DEF_SVR("MPC8543_v21",
8148 CPU_POWERPC_MPC8543_v21
, POWERPC_SVR_8543_v21
, e500v2
),
8150 POWERPC_DEF_SVR("MPC8543E",
8151 CPU_POWERPC_MPC8543E
, POWERPC_SVR_8543E
, e500v2
),
8153 POWERPC_DEF_SVR("MPC8543E_v10",
8154 CPU_POWERPC_MPC8543E_v10
, POWERPC_SVR_8543E_v10
, e500v2
),
8156 POWERPC_DEF_SVR("MPC8543E_v11",
8157 CPU_POWERPC_MPC8543E_v11
, POWERPC_SVR_8543E_v11
, e500v2
),
8159 POWERPC_DEF_SVR("MPC8543E_v20",
8160 CPU_POWERPC_MPC8543E_v20
, POWERPC_SVR_8543E_v20
, e500v2
),
8162 POWERPC_DEF_SVR("MPC8543E_v21",
8163 CPU_POWERPC_MPC8543E_v21
, POWERPC_SVR_8543E_v21
, e500v2
),
8165 POWERPC_DEF_SVR("MPC8544",
8166 CPU_POWERPC_MPC8544
, POWERPC_SVR_8544
, e500v2
),
8168 POWERPC_DEF_SVR("MPC8544_v10",
8169 CPU_POWERPC_MPC8544_v10
, POWERPC_SVR_8544_v10
, e500v2
),
8171 POWERPC_DEF_SVR("MPC8544_v11",
8172 CPU_POWERPC_MPC8544_v11
, POWERPC_SVR_8544_v11
, e500v2
),
8174 POWERPC_DEF_SVR("MPC8544E",
8175 CPU_POWERPC_MPC8544E
, POWERPC_SVR_8544E
, e500v2
),
8177 POWERPC_DEF_SVR("MPC8544E_v10",
8178 CPU_POWERPC_MPC8544E_v10
, POWERPC_SVR_8544E_v10
, e500v2
),
8180 POWERPC_DEF_SVR("MPC8544E_v11",
8181 CPU_POWERPC_MPC8544E_v11
, POWERPC_SVR_8544E_v11
, e500v2
),
8183 POWERPC_DEF_SVR("MPC8545",
8184 CPU_POWERPC_MPC8545
, POWERPC_SVR_8545
, e500v2
),
8186 POWERPC_DEF_SVR("MPC8545_v20",
8187 CPU_POWERPC_MPC8545_v20
, POWERPC_SVR_8545_v20
, e500v2
),
8189 POWERPC_DEF_SVR("MPC8545_v21",
8190 CPU_POWERPC_MPC8545_v21
, POWERPC_SVR_8545_v21
, e500v2
),
8192 POWERPC_DEF_SVR("MPC8545E",
8193 CPU_POWERPC_MPC8545E
, POWERPC_SVR_8545E
, e500v2
),
8195 POWERPC_DEF_SVR("MPC8545E_v20",
8196 CPU_POWERPC_MPC8545E_v20
, POWERPC_SVR_8545E_v20
, e500v2
),
8198 POWERPC_DEF_SVR("MPC8545E_v21",
8199 CPU_POWERPC_MPC8545E_v21
, POWERPC_SVR_8545E_v21
, e500v2
),
8201 POWERPC_DEF_SVR("MPC8547E",
8202 CPU_POWERPC_MPC8547E
, POWERPC_SVR_8547E
, e500v2
),
8204 POWERPC_DEF_SVR("MPC8547E_v20",
8205 CPU_POWERPC_MPC8547E_v20
, POWERPC_SVR_8547E_v20
, e500v2
),
8207 POWERPC_DEF_SVR("MPC8547E_v21",
8208 CPU_POWERPC_MPC8547E_v21
, POWERPC_SVR_8547E_v21
, e500v2
),
8210 POWERPC_DEF_SVR("MPC8548",
8211 CPU_POWERPC_MPC8548
, POWERPC_SVR_8548
, e500v2
),
8213 POWERPC_DEF_SVR("MPC8548_v10",
8214 CPU_POWERPC_MPC8548_v10
, POWERPC_SVR_8548_v10
, e500v2
),
8216 POWERPC_DEF_SVR("MPC8548_v11",
8217 CPU_POWERPC_MPC8548_v11
, POWERPC_SVR_8548_v11
, e500v2
),
8219 POWERPC_DEF_SVR("MPC8548_v20",
8220 CPU_POWERPC_MPC8548_v20
, POWERPC_SVR_8548_v20
, e500v2
),
8222 POWERPC_DEF_SVR("MPC8548_v21",
8223 CPU_POWERPC_MPC8548_v21
, POWERPC_SVR_8548_v21
, e500v2
),
8225 POWERPC_DEF_SVR("MPC8548E",
8226 CPU_POWERPC_MPC8548E
, POWERPC_SVR_8548E
, e500v2
),
8228 POWERPC_DEF_SVR("MPC8548E_v10",
8229 CPU_POWERPC_MPC8548E_v10
, POWERPC_SVR_8548E_v10
, e500v2
),
8231 POWERPC_DEF_SVR("MPC8548E_v11",
8232 CPU_POWERPC_MPC8548E_v11
, POWERPC_SVR_8548E_v11
, e500v2
),
8234 POWERPC_DEF_SVR("MPC8548E_v20",
8235 CPU_POWERPC_MPC8548E_v20
, POWERPC_SVR_8548E_v20
, e500v2
),
8237 POWERPC_DEF_SVR("MPC8548E_v21",
8238 CPU_POWERPC_MPC8548E_v21
, POWERPC_SVR_8548E_v21
, e500v2
),
8240 POWERPC_DEF_SVR("MPC8555",
8241 CPU_POWERPC_MPC8555
, POWERPC_SVR_8555
, e500v2
),
8243 POWERPC_DEF_SVR("MPC8555_v10",
8244 CPU_POWERPC_MPC8555_v10
, POWERPC_SVR_8555_v10
, e500v2
),
8246 POWERPC_DEF_SVR("MPC8555_v11",
8247 CPU_POWERPC_MPC8555_v11
, POWERPC_SVR_8555_v11
, e500v2
),
8249 POWERPC_DEF_SVR("MPC8555E",
8250 CPU_POWERPC_MPC8555E
, POWERPC_SVR_8555E
, e500v2
),
8252 POWERPC_DEF_SVR("MPC8555E_v10",
8253 CPU_POWERPC_MPC8555E_v10
, POWERPC_SVR_8555E_v10
, e500v2
),
8255 POWERPC_DEF_SVR("MPC8555E_v11",
8256 CPU_POWERPC_MPC8555E_v11
, POWERPC_SVR_8555E_v11
, e500v2
),
8258 POWERPC_DEF_SVR("MPC8560",
8259 CPU_POWERPC_MPC8560
, POWERPC_SVR_8560
, e500v2
),
8261 POWERPC_DEF_SVR("MPC8560_v10",
8262 CPU_POWERPC_MPC8560_v10
, POWERPC_SVR_8560_v10
, e500v2
),
8264 POWERPC_DEF_SVR("MPC8560_v20",
8265 CPU_POWERPC_MPC8560_v20
, POWERPC_SVR_8560_v20
, e500v2
),
8267 POWERPC_DEF_SVR("MPC8560_v21",
8268 CPU_POWERPC_MPC8560_v21
, POWERPC_SVR_8560_v21
, e500v2
),
8270 POWERPC_DEF_SVR("MPC8567",
8271 CPU_POWERPC_MPC8567
, POWERPC_SVR_8567
, e500v2
),
8273 POWERPC_DEF_SVR("MPC8567E",
8274 CPU_POWERPC_MPC8567E
, POWERPC_SVR_8567E
, e500v2
),
8276 POWERPC_DEF_SVR("MPC8568",
8277 CPU_POWERPC_MPC8568
, POWERPC_SVR_8568
, e500v2
),
8279 POWERPC_DEF_SVR("MPC8568E",
8280 CPU_POWERPC_MPC8568E
, POWERPC_SVR_8568E
, e500v2
),
8282 POWERPC_DEF_SVR("MPC8572",
8283 CPU_POWERPC_MPC8572
, POWERPC_SVR_8572
, e500v2
),
8285 POWERPC_DEF_SVR("MPC8572E",
8286 CPU_POWERPC_MPC8572E
, POWERPC_SVR_8572E
, e500v2
),
8288 /* PowerPC e600 core */
8289 POWERPC_DEF("e600", CPU_POWERPC_e600
, 7400),
8290 /* PowerPC e600 microcontrollers */
8293 POWERPC_DEF_SVR("MPC8610",
8294 CPU_POWERPC_MPC8610
, POWERPC_SVR_8610
, 7400),
8297 POWERPC_DEF_SVR("MPC8641",
8298 CPU_POWERPC_MPC8641
, POWERPC_SVR_8641
, 7400),
8300 POWERPC_DEF_SVR("MPC8641D",
8301 CPU_POWERPC_MPC8641D
, POWERPC_SVR_8641D
, 7400),
8302 /* 32 bits "classic" PowerPC */
8303 /* PowerPC 6xx family */
8305 POWERPC_DEF("601", CPU_POWERPC_601
, 601v
),
8307 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0
, 601),
8309 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1
, 601),
8311 POWERPC_DEF("601v", CPU_POWERPC_601v
, 601v
),
8313 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2
, 601v
),
8315 POWERPC_DEF("602", CPU_POWERPC_602
, 602),
8317 POWERPC_DEF("603", CPU_POWERPC_603
, 603),
8318 /* Code name for PowerPC 603 */
8319 POWERPC_DEF("Vanilla", CPU_POWERPC_603
, 603),
8320 /* PowerPC 603e (aka PID6) */
8321 POWERPC_DEF("603e", CPU_POWERPC_603E
, 603E
),
8322 /* Code name for PowerPC 603e */
8323 POWERPC_DEF("Stretch", CPU_POWERPC_603E
, 603E
),
8324 /* PowerPC 603e v1.1 */
8325 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11
, 603E
),
8326 /* PowerPC 603e v1.2 */
8327 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12
, 603E
),
8328 /* PowerPC 603e v1.3 */
8329 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13
, 603E
),
8330 /* PowerPC 603e v1.4 */
8331 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14
, 603E
),
8332 /* PowerPC 603e v2.2 */
8333 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22
, 603E
),
8334 /* PowerPC 603e v3 */
8335 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3
, 603E
),
8336 /* PowerPC 603e v4 */
8337 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4
, 603E
),
8338 /* PowerPC 603e v4.1 */
8339 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41
, 603E
),
8340 /* PowerPC 603e (aka PID7) */
8341 POWERPC_DEF("603e7", CPU_POWERPC_603E7
, 603E
),
8342 /* PowerPC 603e7t */
8343 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t
, 603E
),
8344 /* PowerPC 603e7v */
8345 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v
, 603E
),
8346 /* Code name for PowerPC 603ev */
8347 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v
, 603E
),
8348 /* PowerPC 603e7v1 */
8349 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1
, 603E
),
8350 /* PowerPC 603e7v2 */
8351 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2
, 603E
),
8352 /* PowerPC 603p (aka PID7v) */
8353 POWERPC_DEF("603p", CPU_POWERPC_603P
, 603E
),
8354 /* PowerPC 603r (aka PID7t) */
8355 POWERPC_DEF("603r", CPU_POWERPC_603R
, 603E
),
8356 /* Code name for PowerPC 603r */
8357 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R
, 603E
),
8359 POWERPC_DEF("604", CPU_POWERPC_604
, 604),
8360 /* PowerPC 604e (aka PID9) */
8361 POWERPC_DEF("604e", CPU_POWERPC_604E
, 604E
),
8362 /* Code name for PowerPC 604e */
8363 POWERPC_DEF("Sirocco", CPU_POWERPC_604E
, 604E
),
8364 /* PowerPC 604e v1.0 */
8365 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10
, 604E
),
8366 /* PowerPC 604e v2.2 */
8367 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22
, 604E
),
8368 /* PowerPC 604e v2.4 */
8369 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24
, 604E
),
8370 /* PowerPC 604r (aka PIDA) */
8371 POWERPC_DEF("604r", CPU_POWERPC_604R
, 604E
),
8372 /* Code name for PowerPC 604r */
8373 POWERPC_DEF("Mach5", CPU_POWERPC_604R
, 604E
),
8376 POWERPC_DEF("604ev", CPU_POWERPC_604EV
, 604E
),
8378 /* PowerPC 7xx family */
8379 /* Generic PowerPC 740 (G3) */
8380 POWERPC_DEF("740", CPU_POWERPC_7x0
, 740),
8381 /* Code name for PowerPC 740 */
8382 POWERPC_DEF("Arthur", CPU_POWERPC_7x0
, 740),
8383 /* Generic PowerPC 750 (G3) */
8384 POWERPC_DEF("750", CPU_POWERPC_7x0
, 750),
8385 /* Code name for PowerPC 750 */
8386 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0
, 750),
8387 /* PowerPC 740/750 is also known as G3 */
8388 POWERPC_DEF("G3", CPU_POWERPC_7x0
, 750),
8389 /* PowerPC 740 v1.0 (G3) */
8390 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10
, 740),
8391 /* PowerPC 750 v1.0 (G3) */
8392 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10
, 750),
8393 /* PowerPC 740 v2.0 (G3) */
8394 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20
, 740),
8395 /* PowerPC 750 v2.0 (G3) */
8396 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20
, 750),
8397 /* PowerPC 740 v2.1 (G3) */
8398 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21
, 740),
8399 /* PowerPC 750 v2.1 (G3) */
8400 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21
, 750),
8401 /* PowerPC 740 v2.2 (G3) */
8402 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22
, 740),
8403 /* PowerPC 750 v2.2 (G3) */
8404 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22
, 750),
8405 /* PowerPC 740 v3.0 (G3) */
8406 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30
, 740),
8407 /* PowerPC 750 v3.0 (G3) */
8408 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30
, 750),
8409 /* PowerPC 740 v3.1 (G3) */
8410 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31
, 740),
8411 /* PowerPC 750 v3.1 (G3) */
8412 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31
, 750),
8413 /* PowerPC 740E (G3) */
8414 POWERPC_DEF("740e", CPU_POWERPC_740E
, 740),
8415 /* PowerPC 750E (G3) */
8416 POWERPC_DEF("750e", CPU_POWERPC_750E
, 750),
8417 /* PowerPC 740P (G3) */
8418 POWERPC_DEF("740p", CPU_POWERPC_7x0P
, 740),
8419 /* PowerPC 750P (G3) */
8420 POWERPC_DEF("750p", CPU_POWERPC_7x0P
, 750),
8421 /* Code name for PowerPC 740P/750P (G3) */
8422 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P
, 750),
8423 /* PowerPC 750CL (G3 embedded) */
8424 POWERPC_DEF("750cl", CPU_POWERPC_750CL
, 750cl
),
8425 /* PowerPC 750CL v1.0 */
8426 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10
, 750cl
),
8427 /* PowerPC 750CL v2.0 */
8428 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20
, 750cl
),
8429 /* PowerPC 750CX (G3 embedded) */
8430 POWERPC_DEF("750cx", CPU_POWERPC_750CX
, 750cx
),
8431 /* PowerPC 750CX v1.0 (G3 embedded) */
8432 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10
, 750cx
),
8433 /* PowerPC 750CX v2.1 (G3 embedded) */
8434 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20
, 750cx
),
8435 /* PowerPC 750CX v2.1 (G3 embedded) */
8436 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21
, 750cx
),
8437 /* PowerPC 750CX v2.2 (G3 embedded) */
8438 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22
, 750cx
),
8439 /* PowerPC 750CXe (G3 embedded) */
8440 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE
, 750cx
),
8441 /* PowerPC 750CXe v2.1 (G3 embedded) */
8442 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21
, 750cx
),
8443 /* PowerPC 750CXe v2.2 (G3 embedded) */
8444 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22
, 750cx
),
8445 /* PowerPC 750CXe v2.3 (G3 embedded) */
8446 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23
, 750cx
),
8447 /* PowerPC 750CXe v2.4 (G3 embedded) */
8448 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24
, 750cx
),
8449 /* PowerPC 750CXe v2.4b (G3 embedded) */
8450 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b
, 750cx
),
8451 /* PowerPC 750CXe v3.0 (G3 embedded) */
8452 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30
, 750cx
),
8453 /* PowerPC 750CXe v3.1 (G3 embedded) */
8454 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31
, 750cx
),
8455 /* PowerPC 750CXe v3.1b (G3 embedded) */
8456 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b
, 750cx
),
8457 /* PowerPC 750CXr (G3 embedded) */
8458 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR
, 750cx
),
8459 /* PowerPC 750FL (G3 embedded) */
8460 POWERPC_DEF("750fl", CPU_POWERPC_750FL
, 750fx
),
8461 /* PowerPC 750FX (G3 embedded) */
8462 POWERPC_DEF("750fx", CPU_POWERPC_750FX
, 750fx
),
8463 /* PowerPC 750FX v1.0 (G3 embedded) */
8464 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10
, 750fx
),
8465 /* PowerPC 750FX v2.0 (G3 embedded) */
8466 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20
, 750fx
),
8467 /* PowerPC 750FX v2.1 (G3 embedded) */
8468 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21
, 750fx
),
8469 /* PowerPC 750FX v2.2 (G3 embedded) */
8470 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22
, 750fx
),
8471 /* PowerPC 750FX v2.3 (G3 embedded) */
8472 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23
, 750fx
),
8473 /* PowerPC 750GL (G3 embedded) */
8474 POWERPC_DEF("750gl", CPU_POWERPC_750GL
, 750gx
),
8475 /* PowerPC 750GX (G3 embedded) */
8476 POWERPC_DEF("750gx", CPU_POWERPC_750GX
, 750gx
),
8477 /* PowerPC 750GX v1.0 (G3 embedded) */
8478 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10
, 750gx
),
8479 /* PowerPC 750GX v1.1 (G3 embedded) */
8480 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11
, 750gx
),
8481 /* PowerPC 750GX v1.2 (G3 embedded) */
8482 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12
, 750gx
),
8483 /* PowerPC 750L (G3 embedded) */
8484 POWERPC_DEF("750l", CPU_POWERPC_750L
, 750),
8485 /* Code name for PowerPC 750L (G3 embedded) */
8486 POWERPC_DEF("LoneStar", CPU_POWERPC_750L
, 750),
8487 /* PowerPC 750L v2.0 (G3 embedded) */
8488 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20
, 750),
8489 /* PowerPC 750L v2.1 (G3 embedded) */
8490 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21
, 750),
8491 /* PowerPC 750L v2.2 (G3 embedded) */
8492 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22
, 750),
8493 /* PowerPC 750L v3.0 (G3 embedded) */
8494 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30
, 750),
8495 /* PowerPC 750L v3.2 (G3 embedded) */
8496 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32
, 750),
8497 /* Generic PowerPC 745 */
8498 POWERPC_DEF("745", CPU_POWERPC_7x5
, 745),
8499 /* Generic PowerPC 755 */
8500 POWERPC_DEF("755", CPU_POWERPC_7x5
, 755),
8501 /* Code name for PowerPC 745/755 */
8502 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5
, 755),
8503 /* PowerPC 745 v1.0 */
8504 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10
, 745),
8505 /* PowerPC 755 v1.0 */
8506 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10
, 755),
8507 /* PowerPC 745 v1.1 */
8508 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11
, 745),
8509 /* PowerPC 755 v1.1 */
8510 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11
, 755),
8511 /* PowerPC 745 v2.0 */
8512 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20
, 745),
8513 /* PowerPC 755 v2.0 */
8514 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20
, 755),
8515 /* PowerPC 745 v2.1 */
8516 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21
, 745),
8517 /* PowerPC 755 v2.1 */
8518 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21
, 755),
8519 /* PowerPC 745 v2.2 */
8520 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22
, 745),
8521 /* PowerPC 755 v2.2 */
8522 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22
, 755),
8523 /* PowerPC 745 v2.3 */
8524 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23
, 745),
8525 /* PowerPC 755 v2.3 */
8526 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23
, 755),
8527 /* PowerPC 745 v2.4 */
8528 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24
, 745),
8529 /* PowerPC 755 v2.4 */
8530 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24
, 755),
8531 /* PowerPC 745 v2.5 */
8532 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25
, 745),
8533 /* PowerPC 755 v2.5 */
8534 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25
, 755),
8535 /* PowerPC 745 v2.6 */
8536 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26
, 745),
8537 /* PowerPC 755 v2.6 */
8538 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26
, 755),
8539 /* PowerPC 745 v2.7 */
8540 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27
, 745),
8541 /* PowerPC 755 v2.7 */
8542 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27
, 755),
8543 /* PowerPC 745 v2.8 */
8544 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28
, 745),
8545 /* PowerPC 755 v2.8 */
8546 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28
, 755),
8548 /* PowerPC 745P (G3) */
8549 POWERPC_DEF("745p", CPU_POWERPC_7x5P
, 745),
8550 /* PowerPC 755P (G3) */
8551 POWERPC_DEF("755p", CPU_POWERPC_7x5P
, 755),
8553 /* PowerPC 74xx family */
8554 /* PowerPC 7400 (G4) */
8555 POWERPC_DEF("7400", CPU_POWERPC_7400
, 7400),
8556 /* Code name for PowerPC 7400 */
8557 POWERPC_DEF("Max", CPU_POWERPC_7400
, 7400),
8558 /* PowerPC 74xx is also well known as G4 */
8559 POWERPC_DEF("G4", CPU_POWERPC_7400
, 7400),
8560 /* PowerPC 7400 v1.0 (G4) */
8561 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10
, 7400),
8562 /* PowerPC 7400 v1.1 (G4) */
8563 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11
, 7400),
8564 /* PowerPC 7400 v2.0 (G4) */
8565 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20
, 7400),
8566 /* PowerPC 7400 v2.1 (G4) */
8567 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21
, 7400),
8568 /* PowerPC 7400 v2.2 (G4) */
8569 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22
, 7400),
8570 /* PowerPC 7400 v2.6 (G4) */
8571 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26
, 7400),
8572 /* PowerPC 7400 v2.7 (G4) */
8573 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27
, 7400),
8574 /* PowerPC 7400 v2.8 (G4) */
8575 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28
, 7400),
8576 /* PowerPC 7400 v2.9 (G4) */
8577 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29
, 7400),
8578 /* PowerPC 7410 (G4) */
8579 POWERPC_DEF("7410", CPU_POWERPC_7410
, 7410),
8580 /* Code name for PowerPC 7410 */
8581 POWERPC_DEF("Nitro", CPU_POWERPC_7410
, 7410),
8582 /* PowerPC 7410 v1.0 (G4) */
8583 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10
, 7410),
8584 /* PowerPC 7410 v1.1 (G4) */
8585 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11
, 7410),
8586 /* PowerPC 7410 v1.2 (G4) */
8587 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12
, 7410),
8588 /* PowerPC 7410 v1.3 (G4) */
8589 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13
, 7410),
8590 /* PowerPC 7410 v1.4 (G4) */
8591 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14
, 7410),
8592 /* PowerPC 7448 (G4) */
8593 POWERPC_DEF("7448", CPU_POWERPC_7448
, 7400),
8594 /* PowerPC 7448 v1.0 (G4) */
8595 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10
, 7400),
8596 /* PowerPC 7448 v1.1 (G4) */
8597 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11
, 7400),
8598 /* PowerPC 7448 v2.0 (G4) */
8599 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20
, 7400),
8600 /* PowerPC 7448 v2.1 (G4) */
8601 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21
, 7400),
8602 /* PowerPC 7450 (G4) */
8603 POWERPC_DEF("7450", CPU_POWERPC_7450
, 7450),
8604 /* Code name for PowerPC 7450 */
8605 POWERPC_DEF("Vger", CPU_POWERPC_7450
, 7450),
8606 /* PowerPC 7450 v1.0 (G4) */
8607 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10
, 7450),
8608 /* PowerPC 7450 v1.1 (G4) */
8609 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11
, 7450),
8610 /* PowerPC 7450 v1.2 (G4) */
8611 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12
, 7450),
8612 /* PowerPC 7450 v2.0 (G4) */
8613 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20
, 7450),
8614 /* PowerPC 7450 v2.1 (G4) */
8615 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21
, 7450),
8616 /* PowerPC 7441 (G4) */
8617 POWERPC_DEF("7441", CPU_POWERPC_74x1
, 7440),
8618 /* PowerPC 7451 (G4) */
8619 POWERPC_DEF("7451", CPU_POWERPC_74x1
, 7450),
8620 /* PowerPC 7441 v2.1 (G4) */
8621 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21
, 7440),
8622 /* PowerPC 7441 v2.3 (G4) */
8623 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23
, 7440),
8624 /* PowerPC 7451 v2.3 (G4) */
8625 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23
, 7450),
8626 /* PowerPC 7441 v2.10 (G4) */
8627 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210
, 7440),
8628 /* PowerPC 7451 v2.10 (G4) */
8629 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210
, 7450),
8630 /* PowerPC 7445 (G4) */
8631 POWERPC_DEF("7445", CPU_POWERPC_74x5
, 7445),
8632 /* PowerPC 7455 (G4) */
8633 POWERPC_DEF("7455", CPU_POWERPC_74x5
, 7455),
8634 /* Code name for PowerPC 7445/7455 */
8635 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5
, 7455),
8636 /* PowerPC 7445 v1.0 (G4) */
8637 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10
, 7445),
8638 /* PowerPC 7455 v1.0 (G4) */
8639 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10
, 7455),
8640 /* PowerPC 7445 v2.1 (G4) */
8641 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21
, 7445),
8642 /* PowerPC 7455 v2.1 (G4) */
8643 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21
, 7455),
8644 /* PowerPC 7445 v3.2 (G4) */
8645 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32
, 7445),
8646 /* PowerPC 7455 v3.2 (G4) */
8647 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32
, 7455),
8648 /* PowerPC 7445 v3.3 (G4) */
8649 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33
, 7445),
8650 /* PowerPC 7455 v3.3 (G4) */
8651 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33
, 7455),
8652 /* PowerPC 7445 v3.4 (G4) */
8653 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34
, 7445),
8654 /* PowerPC 7455 v3.4 (G4) */
8655 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34
, 7455),
8656 /* PowerPC 7447 (G4) */
8657 POWERPC_DEF("7447", CPU_POWERPC_74x7
, 7445),
8658 /* PowerPC 7457 (G4) */
8659 POWERPC_DEF("7457", CPU_POWERPC_74x7
, 7455),
8660 /* Code name for PowerPC 7447/7457 */
8661 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7
, 7455),
8662 /* PowerPC 7447 v1.0 (G4) */
8663 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10
, 7445),
8664 /* PowerPC 7457 v1.0 (G4) */
8665 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10
, 7455),
8666 /* PowerPC 7447 v1.1 (G4) */
8667 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11
, 7445),
8668 /* PowerPC 7457 v1.1 (G4) */
8669 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11
, 7455),
8670 /* PowerPC 7457 v1.2 (G4) */
8671 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12
, 7455),
8672 /* PowerPC 7447A (G4) */
8673 POWERPC_DEF("7447A", CPU_POWERPC_74x7A
, 7445),
8674 /* PowerPC 7457A (G4) */
8675 POWERPC_DEF("7457A", CPU_POWERPC_74x7A
, 7455),
8676 /* PowerPC 7447A v1.0 (G4) */
8677 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10
, 7445),
8678 /* PowerPC 7457A v1.0 (G4) */
8679 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10
, 7455),
8680 /* Code name for PowerPC 7447A/7457A */
8681 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10
, 7455),
8682 /* PowerPC 7447A v1.1 (G4) */
8683 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11
, 7445),
8684 /* PowerPC 7457A v1.1 (G4) */
8685 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11
, 7455),
8686 /* PowerPC 7447A v1.2 (G4) */
8687 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12
, 7445),
8688 /* PowerPC 7457A v1.2 (G4) */
8689 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12
, 7455),
8690 /* 64 bits PowerPC */
8691 #if defined (TARGET_PPC64)
8693 POWERPC_DEF("620", CPU_POWERPC_620
, 620),
8694 /* Code name for PowerPC 620 */
8695 POWERPC_DEF("Trident", CPU_POWERPC_620
, 620),
8697 /* PowerPC 630 (POWER3) */
8698 POWERPC_DEF("630", CPU_POWERPC_630
, 630),
8699 POWERPC_DEF("POWER3", CPU_POWERPC_630
, 630),
8700 /* Code names for POWER3 */
8701 POWERPC_DEF("Boxer", CPU_POWERPC_630
, 630),
8702 POWERPC_DEF("Dino", CPU_POWERPC_630
, 630),
8705 /* PowerPC 631 (Power 3+) */
8706 POWERPC_DEF("631", CPU_POWERPC_631
, 631),
8707 POWERPC_DEF("POWER3+", CPU_POWERPC_631
, 631),
8711 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4
, POWER4
),
8715 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P
, POWER4P
),
8719 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5
, POWER5
),
8721 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR
, POWER5
),
8725 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P
, POWER5P
),
8727 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS
, POWER5P
),
8731 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6
, POWER6
),
8732 /* POWER6 running in POWER5 mode */
8733 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5
, POWER5
),
8735 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A
, POWER6
),
8738 POWERPC_DEF("970", CPU_POWERPC_970
, 970),
8739 /* PowerPC 970FX (G5) */
8740 POWERPC_DEF("970fx", CPU_POWERPC_970FX
, 970FX
),
8741 /* PowerPC 970FX v1.0 (G5) */
8742 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10
, 970FX
),
8743 /* PowerPC 970FX v2.0 (G5) */
8744 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20
, 970FX
),
8745 /* PowerPC 970FX v2.1 (G5) */
8746 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21
, 970FX
),
8747 /* PowerPC 970FX v3.0 (G5) */
8748 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30
, 970FX
),
8749 /* PowerPC 970FX v3.1 (G5) */
8750 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31
, 970FX
),
8751 /* PowerPC 970GX (G5) */
8752 POWERPC_DEF("970gx", CPU_POWERPC_970GX
, 970GX
),
8754 POWERPC_DEF("970mp", CPU_POWERPC_970MP
, 970MP
),
8755 /* PowerPC 970MP v1.0 */
8756 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10
, 970MP
),
8757 /* PowerPC 970MP v1.1 */
8758 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11
, 970MP
),
8761 POWERPC_DEF("Cell", CPU_POWERPC_CELL
, 970),
8764 /* PowerPC Cell v1.0 */
8765 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10
, 970),
8768 /* PowerPC Cell v2.0 */
8769 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20
, 970),
8772 /* PowerPC Cell v3.0 */
8773 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30
, 970),
8776 /* PowerPC Cell v3.1 */
8777 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31
, 970),
8780 /* PowerPC Cell v3.2 */
8781 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32
, 970),
8784 /* RS64 (Apache/A35) */
8785 /* This one seems to support the whole POWER2 instruction set
8786 * and the PowerPC 64 one.
8788 /* What about A10 & A30 ? */
8789 POWERPC_DEF("RS64", CPU_POWERPC_RS64
, RS64
),
8790 POWERPC_DEF("Apache", CPU_POWERPC_RS64
, RS64
),
8791 POWERPC_DEF("A35", CPU_POWERPC_RS64
, RS64
),
8794 /* RS64-II (NorthStar/A50) */
8795 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II
, RS64
),
8796 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II
, RS64
),
8797 POWERPC_DEF("A50", CPU_POWERPC_RS64II
, RS64
),
8800 /* RS64-III (Pulsar) */
8801 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III
, RS64
),
8802 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III
, RS64
),
8805 /* RS64-IV (IceStar/IStar/SStar) */
8806 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV
, RS64
),
8807 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV
, RS64
),
8808 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV
, RS64
),
8809 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV
, RS64
),
8811 #endif /* defined (TARGET_PPC64) */
8814 /* Original POWER */
8815 POWERPC_DEF("POWER", CPU_POWERPC_POWER
, POWER
),
8816 POWERPC_DEF("RIOS", CPU_POWERPC_POWER
, POWER
),
8817 POWERPC_DEF("RSC", CPU_POWERPC_POWER
, POWER
),
8818 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER
, POWER
),
8819 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER
, POWER
),
8823 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2
, POWER
),
8824 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2
, POWER
),
8825 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2
, POWER
),
8830 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T
, PA6T
),
8832 /* Generic PowerPCs */
8833 #if defined (TARGET_PPC64)
8834 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64
, PPC64
),
8836 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32
, PPC32
),
8837 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT
, DEFAULT
),
8839 POWERPC_DEF("default", CPU_POWERPC_DEFAULT
, DEFAULT
),
8842 /*****************************************************************************/
8843 /* Generic CPU instanciation routine */
8844 static void init_ppc_proc (CPUPPCState
*env
, const ppc_def_t
*def
)
8846 #if !defined(CONFIG_USER_ONLY)
8849 env
->irq_inputs
= NULL
;
8850 /* Set all exception vectors to an invalid address */
8851 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
8852 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
8853 env
->excp_prefix
= 0x00000000;
8854 env
->ivor_mask
= 0x00000000;
8855 env
->ivpr_mask
= 0x00000000;
8856 /* Default MMU definitions */
8861 /* Register SPR common to all PowerPC implementations */
8862 gen_spr_generic(env
);
8863 spr_register(env
, SPR_PVR
, "PVR",
8864 SPR_NOACCESS
, SPR_NOACCESS
,
8865 &spr_read_generic
, SPR_NOACCESS
,
8867 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8868 if (def
->svr
!= POWERPC_SVR_NONE
) {
8869 if (def
->svr
& POWERPC_SVR_E500
) {
8870 spr_register(env
, SPR_E500_SVR
, "SVR",
8871 SPR_NOACCESS
, SPR_NOACCESS
,
8872 &spr_read_generic
, SPR_NOACCESS
,
8873 def
->svr
& ~POWERPC_SVR_E500
);
8875 spr_register(env
, SPR_SVR
, "SVR",
8876 SPR_NOACCESS
, SPR_NOACCESS
,
8877 &spr_read_generic
, SPR_NOACCESS
,
8881 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8882 (*def
->init_proc
)(env
);
8883 /* MSR bits & flags consistency checks */
8884 if (env
->msr_mask
& (1 << 25)) {
8885 switch (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
8886 case POWERPC_FLAG_SPE
:
8887 case POWERPC_FLAG_VRE
:
8890 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8891 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8894 } else if (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
8895 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8896 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8899 if (env
->msr_mask
& (1 << 17)) {
8900 switch (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
8901 case POWERPC_FLAG_TGPR
:
8902 case POWERPC_FLAG_CE
:
8905 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8906 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8909 } else if (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
8910 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8911 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8914 if (env
->msr_mask
& (1 << 10)) {
8915 switch (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
8916 POWERPC_FLAG_UBLE
)) {
8917 case POWERPC_FLAG_SE
:
8918 case POWERPC_FLAG_DWE
:
8919 case POWERPC_FLAG_UBLE
:
8922 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8923 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8924 "POWERPC_FLAG_UBLE\n");
8927 } else if (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
8928 POWERPC_FLAG_UBLE
)) {
8929 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8930 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8931 "POWERPC_FLAG_UBLE\n");
8934 if (env
->msr_mask
& (1 << 9)) {
8935 switch (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
8936 case POWERPC_FLAG_BE
:
8937 case POWERPC_FLAG_DE
:
8940 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8941 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8944 } else if (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
8945 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8946 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8949 if (env
->msr_mask
& (1 << 2)) {
8950 switch (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
8951 case POWERPC_FLAG_PX
:
8952 case POWERPC_FLAG_PMM
:
8955 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8956 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8959 } else if (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
8960 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8961 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8964 if ((env
->flags
& (POWERPC_FLAG_RTC_CLK
| POWERPC_FLAG_BUS_CLK
)) == 0) {
8965 fprintf(stderr
, "PowerPC flags inconsistency\n"
8966 "Should define the time-base and decrementer clock source\n");
8969 /* Allocate TLBs buffer when needed */
8970 #if !defined(CONFIG_USER_ONLY)
8971 if (env
->nb_tlb
!= 0) {
8972 int nb_tlb
= env
->nb_tlb
;
8973 if (env
->id_tlbs
!= 0)
8975 env
->tlb
= qemu_mallocz(nb_tlb
* sizeof(ppc_tlb_t
));
8976 /* Pre-compute some useful values */
8977 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
8979 if (env
->irq_inputs
== NULL
) {
8980 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
8981 " Attempt Qemu to crash very soon !\n");
8984 if (env
->check_pow
== NULL
) {
8985 fprintf(stderr
, "WARNING: no power management check handler "
8987 " Attempt Qemu to crash very soon !\n");
8991 #if defined(PPC_DUMP_CPU)
8992 static void dump_ppc_sprs (CPUPPCState
*env
)
8995 #if !defined(CONFIG_USER_ONLY)
9001 printf("Special purpose registers:\n");
9002 for (i
= 0; i
< 32; i
++) {
9003 for (j
= 0; j
< 32; j
++) {
9005 spr
= &env
->spr_cb
[n
];
9006 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
9007 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
9008 #if !defined(CONFIG_USER_ONLY)
9009 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
9010 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
9011 if (sw
|| sr
|| uw
|| ur
) {
9012 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9013 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
9014 sw
? 'w' : '-', sr
? 'r' : '-',
9015 uw
? 'w' : '-', ur
? 'r' : '-');
9019 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9020 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
9021 uw
? 'w' : '-', ur
? 'r' : '-');
9031 /*****************************************************************************/
9037 PPC_DIRECT
= 0, /* Opcode routine */
9038 PPC_INDIRECT
= 1, /* Indirect opcode table */
9041 static inline int is_indirect_opcode (void *handler
)
9043 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
9046 static inline opc_handler_t
**ind_table(void *handler
)
9048 return (opc_handler_t
**)((unsigned long)handler
& ~3);
9051 /* Instruction table creation */
9052 /* Opcodes tables creation */
9053 static void fill_new_table (opc_handler_t
**table
, int len
)
9057 for (i
= 0; i
< len
; i
++)
9058 table
[i
] = &invalid_handler
;
9061 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
9063 opc_handler_t
**tmp
;
9065 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
9066 fill_new_table(tmp
, 0x20);
9067 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
9072 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
9073 opc_handler_t
*handler
)
9075 if (table
[idx
] != &invalid_handler
)
9077 table
[idx
] = handler
;
9082 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
9083 unsigned char idx
, opc_handler_t
*handler
)
9085 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
9086 printf("*** ERROR: opcode %02x already assigned in main "
9087 "opcode table\n", idx
);
9088 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9089 printf(" Registered handler '%s' - new handler '%s'\n",
9090 ppc_opcodes
[idx
]->oname
, handler
->oname
);
9098 static int register_ind_in_table (opc_handler_t
**table
,
9099 unsigned char idx1
, unsigned char idx2
,
9100 opc_handler_t
*handler
)
9102 if (table
[idx1
] == &invalid_handler
) {
9103 if (create_new_table(table
, idx1
) < 0) {
9104 printf("*** ERROR: unable to create indirect table "
9105 "idx=%02x\n", idx1
);
9109 if (!is_indirect_opcode(table
[idx1
])) {
9110 printf("*** ERROR: idx %02x already assigned to a direct "
9112 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9113 printf(" Registered handler '%s' - new handler '%s'\n",
9114 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
9119 if (handler
!= NULL
&&
9120 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
9121 printf("*** ERROR: opcode %02x already assigned in "
9122 "opcode table %02x\n", idx2
, idx1
);
9123 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9124 printf(" Registered handler '%s' - new handler '%s'\n",
9125 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
9133 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
9134 unsigned char idx1
, unsigned char idx2
,
9135 opc_handler_t
*handler
)
9139 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
9144 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
9145 unsigned char idx1
, unsigned char idx2
,
9146 unsigned char idx3
, opc_handler_t
*handler
)
9148 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
9149 printf("*** ERROR: unable to join indirect table idx "
9150 "[%02x-%02x]\n", idx1
, idx2
);
9153 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
9155 printf("*** ERROR: unable to insert opcode "
9156 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
9163 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
9165 if (insn
->opc2
!= 0xFF) {
9166 if (insn
->opc3
!= 0xFF) {
9167 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
9168 insn
->opc3
, &insn
->handler
) < 0)
9171 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
9172 insn
->opc2
, &insn
->handler
) < 0)
9176 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
9183 static int test_opcode_table (opc_handler_t
**table
, int len
)
9187 for (i
= 0, count
= 0; i
< len
; i
++) {
9188 /* Consistency fixup */
9189 if (table
[i
] == NULL
)
9190 table
[i
] = &invalid_handler
;
9191 if (table
[i
] != &invalid_handler
) {
9192 if (is_indirect_opcode(table
[i
])) {
9193 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
9196 table
[i
] = &invalid_handler
;
9209 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
9211 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
9212 printf("*** WARNING: no opcode defined !\n");
9215 /*****************************************************************************/
9216 static int create_ppc_opcodes (CPUPPCState
*env
, const ppc_def_t
*def
)
9218 opcode_t
*opc
, *start
, *end
;
9220 fill_new_table(env
->opcodes
, 0x40);
9221 if (&opc_start
< &opc_end
) {
9228 for (opc
= start
+ 1; opc
!= end
; opc
++) {
9229 if ((opc
->handler
.type
& def
->insns_flags
) != 0) {
9230 if (register_insn(env
->opcodes
, opc
) < 0) {
9231 printf("*** ERROR initializing PowerPC instruction "
9232 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
9238 fix_opcode_tables(env
->opcodes
);
9245 #if defined(PPC_DUMP_CPU)
9246 static void dump_ppc_insns (CPUPPCState
*env
)
9248 opc_handler_t
**table
, *handler
;
9250 uint8_t opc1
, opc2
, opc3
;
9252 printf("Instructions set:\n");
9253 /* opc1 is 6 bits long */
9254 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
9255 table
= env
->opcodes
;
9256 handler
= table
[opc1
];
9257 if (is_indirect_opcode(handler
)) {
9258 /* opc2 is 5 bits long */
9259 for (opc2
= 0; opc2
< 0x20; opc2
++) {
9260 table
= env
->opcodes
;
9261 handler
= env
->opcodes
[opc1
];
9262 table
= ind_table(handler
);
9263 handler
= table
[opc2
];
9264 if (is_indirect_opcode(handler
)) {
9265 table
= ind_table(handler
);
9266 /* opc3 is 5 bits long */
9267 for (opc3
= 0; opc3
< 0x20; opc3
++) {
9268 handler
= table
[opc3
];
9269 if (handler
->handler
!= &gen_invalid
) {
9270 /* Special hack to properly dump SPE insns */
9271 p
= strchr(handler
->oname
, '_');
9273 printf("INSN: %02x %02x %02x (%02d %04d) : "
9275 opc1
, opc2
, opc3
, opc1
,
9280 if ((p
- handler
->oname
) != strlen(q
) ||
9281 memcmp(handler
->oname
, q
, strlen(q
)) != 0) {
9282 /* First instruction */
9283 printf("INSN: %02x %02x %02x (%02d %04d) : "
9285 opc1
, opc2
<< 1, opc3
, opc1
,
9286 (opc3
<< 6) | (opc2
<< 1),
9287 (int)(p
- handler
->oname
),
9290 if (strcmp(p
+ 1, q
) != 0) {
9291 /* Second instruction */
9292 printf("INSN: %02x %02x %02x (%02d %04d) : "
9294 opc1
, (opc2
<< 1) | 1, opc3
, opc1
,
9295 (opc3
<< 6) | (opc2
<< 1) | 1,
9302 if (handler
->handler
!= &gen_invalid
) {
9303 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9304 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
9309 if (handler
->handler
!= &gen_invalid
) {
9310 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9311 opc1
, opc1
, handler
->oname
);
9318 static int gdb_get_float_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9321 stfq_p(mem_buf
, env
->fpr
[n
]);
9325 /* FPSCR not implemented */
9326 memset(mem_buf
, 0, 4);
9332 static int gdb_set_float_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9335 env
->fpr
[n
] = ldfq_p(mem_buf
);
9339 /* FPSCR not implemented */
9345 static int gdb_get_avr_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9348 #ifdef WORDS_BIGENDIAN
9349 stq_p(mem_buf
, env
->avr
[n
].u64
[0]);
9350 stq_p(mem_buf
+8, env
->avr
[n
].u64
[1]);
9352 stq_p(mem_buf
, env
->avr
[n
].u64
[1]);
9353 stq_p(mem_buf
+8, env
->avr
[n
].u64
[0]);
9358 stl_p(mem_buf
, env
->vscr
);
9362 stl_p(mem_buf
, (uint32_t)env
->spr
[SPR_VRSAVE
]);
9368 static int gdb_set_avr_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9371 #ifdef WORDS_BIGENDIAN
9372 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
);
9373 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
+8);
9375 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
);
9376 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
+8);
9381 env
->vscr
= ldl_p(mem_buf
);
9385 env
->spr
[SPR_VRSAVE
] = (target_ulong
)ldl_p(mem_buf
);
9391 static int gdb_get_spe_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9394 #if defined(TARGET_PPC64)
9395 stl_p(mem_buf
, env
->gpr
[n
] >> 32);
9397 stl_p(mem_buf
, env
->gprh
[n
]);
9402 stq_p(mem_buf
, env
->spe_acc
);
9406 /* SPEFSCR not implemented */
9407 memset(mem_buf
, 0, 4);
9413 static int gdb_set_spe_reg(CPUState
*env
, uint8_t *mem_buf
, int n
)
9416 #if defined(TARGET_PPC64)
9417 target_ulong lo
= (uint32_t)env
->gpr
[n
];
9418 target_ulong hi
= (target_ulong
)ldl_p(mem_buf
) << 32;
9419 env
->gpr
[n
] = lo
| hi
;
9421 env
->gprh
[n
] = ldl_p(mem_buf
);
9426 env
->spe_acc
= ldq_p(mem_buf
);
9430 /* SPEFSCR not implemented */
9436 int cpu_ppc_register_internal (CPUPPCState
*env
, const ppc_def_t
*def
)
9438 env
->msr_mask
= def
->msr_mask
;
9439 env
->mmu_model
= def
->mmu_model
;
9440 env
->excp_model
= def
->excp_model
;
9441 env
->bus_model
= def
->bus_model
;
9442 env
->flags
= def
->flags
;
9443 env
->bfd_mach
= def
->bfd_mach
;
9444 env
->check_pow
= def
->check_pow
;
9445 if (create_ppc_opcodes(env
, def
) < 0)
9447 init_ppc_proc(env
, def
);
9449 if (def
->insns_flags
& PPC_FLOAT
) {
9450 gdb_register_coprocessor(env
, gdb_get_float_reg
, gdb_set_float_reg
,
9451 33, "power-fpu.xml", 0);
9453 if (def
->insns_flags
& PPC_ALTIVEC
) {
9454 gdb_register_coprocessor(env
, gdb_get_avr_reg
, gdb_set_avr_reg
,
9455 34, "power-altivec.xml", 0);
9457 if (def
->insns_flags
& PPC_SPE
) {
9458 gdb_register_coprocessor(env
, gdb_get_spe_reg
, gdb_set_spe_reg
,
9459 34, "power-spe.xml", 0);
9462 #if defined(PPC_DUMP_CPU)
9464 const char *mmu_model
, *excp_model
, *bus_model
;
9465 switch (env
->mmu_model
) {
9466 case POWERPC_MMU_32B
:
9467 mmu_model
= "PowerPC 32";
9469 case POWERPC_MMU_SOFT_6xx
:
9470 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
9472 case POWERPC_MMU_SOFT_74xx
:
9473 mmu_model
= "PowerPC 74xx with software driven TLBs";
9475 case POWERPC_MMU_SOFT_4xx
:
9476 mmu_model
= "PowerPC 4xx with software driven TLBs";
9478 case POWERPC_MMU_SOFT_4xx_Z
:
9479 mmu_model
= "PowerPC 4xx with software driven TLBs "
9480 "and zones protections";
9482 case POWERPC_MMU_REAL
:
9483 mmu_model
= "PowerPC real mode only";
9485 case POWERPC_MMU_MPC8xx
:
9486 mmu_model
= "PowerPC MPC8xx";
9488 case POWERPC_MMU_BOOKE
:
9489 mmu_model
= "PowerPC BookE";
9491 case POWERPC_MMU_BOOKE_FSL
:
9492 mmu_model
= "PowerPC BookE FSL";
9494 case POWERPC_MMU_601
:
9495 mmu_model
= "PowerPC 601";
9497 #if defined (TARGET_PPC64)
9498 case POWERPC_MMU_64B
:
9499 mmu_model
= "PowerPC 64";
9501 case POWERPC_MMU_620
:
9502 mmu_model
= "PowerPC 620";
9506 mmu_model
= "Unknown or invalid";
9509 switch (env
->excp_model
) {
9510 case POWERPC_EXCP_STD
:
9511 excp_model
= "PowerPC";
9513 case POWERPC_EXCP_40x
:
9514 excp_model
= "PowerPC 40x";
9516 case POWERPC_EXCP_601
:
9517 excp_model
= "PowerPC 601";
9519 case POWERPC_EXCP_602
:
9520 excp_model
= "PowerPC 602";
9522 case POWERPC_EXCP_603
:
9523 excp_model
= "PowerPC 603";
9525 case POWERPC_EXCP_603E
:
9526 excp_model
= "PowerPC 603e";
9528 case POWERPC_EXCP_604
:
9529 excp_model
= "PowerPC 604";
9531 case POWERPC_EXCP_7x0
:
9532 excp_model
= "PowerPC 740/750";
9534 case POWERPC_EXCP_7x5
:
9535 excp_model
= "PowerPC 745/755";
9537 case POWERPC_EXCP_74xx
:
9538 excp_model
= "PowerPC 74xx";
9540 case POWERPC_EXCP_BOOKE
:
9541 excp_model
= "PowerPC BookE";
9543 #if defined (TARGET_PPC64)
9544 case POWERPC_EXCP_970
:
9545 excp_model
= "PowerPC 970";
9549 excp_model
= "Unknown or invalid";
9552 switch (env
->bus_model
) {
9553 case PPC_FLAGS_INPUT_6xx
:
9554 bus_model
= "PowerPC 6xx";
9556 case PPC_FLAGS_INPUT_BookE
:
9557 bus_model
= "PowerPC BookE";
9559 case PPC_FLAGS_INPUT_405
:
9560 bus_model
= "PowerPC 405";
9562 case PPC_FLAGS_INPUT_401
:
9563 bus_model
= "PowerPC 401/403";
9565 case PPC_FLAGS_INPUT_RCPU
:
9566 bus_model
= "RCPU / MPC8xx";
9568 #if defined (TARGET_PPC64)
9569 case PPC_FLAGS_INPUT_970
:
9570 bus_model
= "PowerPC 970";
9574 bus_model
= "Unknown or invalid";
9577 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
9578 " MMU model : %s\n",
9579 def
->name
, def
->pvr
, def
->msr_mask
, mmu_model
);
9580 #if !defined(CONFIG_USER_ONLY)
9581 if (env
->tlb
!= NULL
) {
9582 printf(" %d %s TLB in %d ways\n",
9583 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
9587 printf(" Exceptions model : %s\n"
9588 " Bus model : %s\n",
9589 excp_model
, bus_model
);
9590 printf(" MSR features :\n");
9591 if (env
->flags
& POWERPC_FLAG_SPE
)
9592 printf(" signal processing engine enable"
9594 else if (env
->flags
& POWERPC_FLAG_VRE
)
9595 printf(" vector processor enable\n");
9596 if (env
->flags
& POWERPC_FLAG_TGPR
)
9597 printf(" temporary GPRs\n");
9598 else if (env
->flags
& POWERPC_FLAG_CE
)
9599 printf(" critical input enable\n");
9600 if (env
->flags
& POWERPC_FLAG_SE
)
9601 printf(" single-step trace mode\n");
9602 else if (env
->flags
& POWERPC_FLAG_DWE
)
9603 printf(" debug wait enable\n");
9604 else if (env
->flags
& POWERPC_FLAG_UBLE
)
9605 printf(" user BTB lock enable\n");
9606 if (env
->flags
& POWERPC_FLAG_BE
)
9607 printf(" branch-step trace mode\n");
9608 else if (env
->flags
& POWERPC_FLAG_DE
)
9609 printf(" debug interrupt enable\n");
9610 if (env
->flags
& POWERPC_FLAG_PX
)
9611 printf(" inclusive protection\n");
9612 else if (env
->flags
& POWERPC_FLAG_PMM
)
9613 printf(" performance monitor mark\n");
9614 if (env
->flags
== POWERPC_FLAG_NONE
)
9616 printf(" Time-base/decrementer clock source: %s\n",
9617 env
->flags
& POWERPC_FLAG_RTC_CLK
? "RTC clock" : "bus clock");
9619 dump_ppc_insns(env
);
9627 static const ppc_def_t
*ppc_find_by_pvr (uint32_t pvr
)
9629 const ppc_def_t
*ret
;
9631 int i
, best
, match
, best_match
, max
;
9634 max
= ARRAY_SIZE(ppc_defs
);
9636 pvr_rev
= pvr
& 0xFFFF;
9637 /* We want all specified bits to match */
9638 best_match
= 32 - ctz32(pvr_rev
);
9639 for (i
= 0; i
< max
; i
++) {
9640 /* We check that the 16 higher bits are the same to ensure the CPU
9641 * model will be the choosen one.
9643 if (((pvr
^ ppc_defs
[i
].pvr
) >> 16) == 0) {
9644 /* We want as much as possible of the low-level 16 bits
9645 * to be the same but we allow inexact matches.
9647 match
= clz32(pvr_rev
^ (ppc_defs
[i
].pvr
& 0xFFFF));
9648 /* We check '>=' instead of '>' because the PPC_defs table
9649 * is ordered by increasing revision.
9650 * Then, we will match the higher revision compatible
9651 * with the requested PVR
9653 if (match
>= best_match
) {
9660 ret
= &ppc_defs
[best
];
9667 const ppc_def_t
*cpu_ppc_find_by_name (const char *name
)
9669 const ppc_def_t
*ret
;
9673 /* Check if the given name is a PVR */
9675 if (len
== 10 && name
[0] == '0' && name
[1] == 'x') {
9678 } else if (len
== 8) {
9681 for (i
= 0; i
< 8; i
++) {
9682 if (!qemu_isxdigit(*p
++))
9686 return ppc_find_by_pvr(strtoul(name
, NULL
, 16));
9689 max
= ARRAY_SIZE(ppc_defs
);
9690 for (i
= 0; i
< max
; i
++) {
9691 if (strcasecmp(name
, ppc_defs
[i
].name
) == 0) {
9700 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
9704 max
= ARRAY_SIZE(ppc_defs
);
9705 for (i
= 0; i
< max
; i
++) {
9706 (*cpu_fprintf
)(f
, "PowerPC %-16s PVR %08x\n",
9707 ppc_defs
[i
].name
, ppc_defs
[i
].pvr
);