?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Unbreak SDL on Mac OS X
[qemu/mini2440.git] / target-ppc / translate.c
blob0999f4c24542bb46829e61d7cb45eab823741ff0
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_ptr cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
58 #endif
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh[32];
65 #endif
66 static TCGv_i64 cpu_fpr[32];
67 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68 static TCGv_i32 cpu_crf[8];
69 static TCGv cpu_nip;
70 static TCGv cpu_msr;
71 static TCGv cpu_ctr;
72 static TCGv cpu_lr;
73 static TCGv cpu_xer;
74 static TCGv cpu_reserve;
75 static TCGv_i32 cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92
93 for (i = 0; i < 8; i++) {
94 sprintf(p, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUState, crf[i]), p);
97 p += 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 sprintf(p, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 sprintf(p, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 #endif
111
112 sprintf(p, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116
117 sprintf(p, "avr%dH", i);
118 #ifdef WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
123 offsetof(CPUState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126
127 sprintf(p, "avr%dL", i);
128 #ifdef WORDS_BIGENDIAN
129 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
130 offsetof(CPUState, avr[i].u64[1]), p);
131 #else
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUState, avr[i].u64[0]), p);
134 #endif
135 p += (i < 10) ? 6 : 7;
136 }
137
138 cpu_nip = tcg_global_mem_new(TCG_AREG0,
139 offsetof(CPUState, nip), "nip");
140
141 cpu_msr = tcg_global_mem_new(TCG_AREG0,
142 offsetof(CPUState, msr), "msr");
143
144 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
145 offsetof(CPUState, ctr), "ctr");
146
147 cpu_lr = tcg_global_mem_new(TCG_AREG0,
148 offsetof(CPUState, lr), "lr");
149
150 cpu_xer = tcg_global_mem_new(TCG_AREG0,
151 offsetof(CPUState, xer), "xer");
152
153 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUState, reserve), "reserve");
155
156 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
157 offsetof(CPUState, fpscr), "fpscr");
158
159 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
160 offsetof(CPUState, access_type), "access_type");
161
162 /* register helpers */
163 #define GEN_HELPER 2
164 #include "helper.h"
165
166 done_init = 1;
167 }
168
169 /* internal defines */
170 typedef struct DisasContext {
171 struct TranslationBlock *tb;
172 target_ulong nip;
173 uint32_t opcode;
174 uint32_t exception;
175 /* Routine used to access memory */
176 int mem_idx;
177 int access_type;
178 /* Translation flags */
179 int le_mode;
180 #if defined(TARGET_PPC64)
181 int sf_mode;
182 #endif
183 int fpu_enabled;
184 int altivec_enabled;
185 int spe_enabled;
186 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
187 int singlestep_enabled;
188 } DisasContext;
189
190 struct opc_handler_t {
191 /* invalid bits */
192 uint32_t inval;
193 /* instruction type */
194 uint64_t type;
195 /* handler */
196 void (*handler)(DisasContext *ctx);
197 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
198 const char *oname;
199 #endif
200 #if defined(DO_PPC_STATISTICS)
201 uint64_t count;
202 #endif
203 };
204
205 static always_inline void gen_reset_fpstatus (void)
206 {
207 #ifdef CONFIG_SOFTFLOAT
208 gen_helper_reset_fpstatus();
209 #endif
210 }
211
212 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
213 {
214 TCGv_i32 t0 = tcg_temp_new_i32();
215
216 if (set_fprf != 0) {
217 /* This case might be optimized later */
218 tcg_gen_movi_i32(t0, 1);
219 gen_helper_compute_fprf(t0, arg, t0);
220 if (unlikely(set_rc)) {
221 tcg_gen_mov_i32(cpu_crf[1], t0);
222 }
223 gen_helper_float_check_status();
224 } else if (unlikely(set_rc)) {
225 /* We always need to compute fpcc */
226 tcg_gen_movi_i32(t0, 0);
227 gen_helper_compute_fprf(t0, arg, t0);
228 tcg_gen_mov_i32(cpu_crf[1], t0);
229 }
230
231 tcg_temp_free_i32(t0);
232 }
233
234 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
235 {
236 if (ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
240 }
241
242 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
243 {
244 #if defined(TARGET_PPC64)
245 if (ctx->sf_mode)
246 tcg_gen_movi_tl(cpu_nip, nip);
247 else
248 #endif
249 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
250 }
251
252 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
253 {
254 TCGv_i32 t0, t1;
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->nip);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264 }
265
266 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
267 {
268 TCGv_i32 t0;
269 if (ctx->exception == POWERPC_EXCP_NONE) {
270 gen_update_nip(ctx, ctx->nip);
271 }
272 t0 = tcg_const_i32(excp);
273 gen_helper_raise_exception(t0);
274 tcg_temp_free_i32(t0);
275 ctx->exception = (excp);
276 }
277
278 static always_inline void gen_debug_exception (DisasContext *ctx)
279 {
280 TCGv_i32 t0;
281 gen_update_nip(ctx, ctx->nip);
282 t0 = tcg_const_i32(EXCP_DEBUG);
283 gen_helper_raise_exception(t0);
284 tcg_temp_free_i32(t0);
285 }
286
287 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
288 {
289 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
290 }
291
292 /* Stop translation */
293 static always_inline void gen_stop_exception (DisasContext *ctx)
294 {
295 gen_update_nip(ctx, ctx->nip);
296 ctx->exception = POWERPC_EXCP_STOP;
297 }
298
299 /* No need to update nip here, as execution flow will change */
300 static always_inline void gen_sync_exception (DisasContext *ctx)
301 {
302 ctx->exception = POWERPC_EXCP_SYNC;
303 }
304
305 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
306 static void gen_##name (DisasContext *ctx); \
307 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
308 static void gen_##name (DisasContext *ctx)
309
310 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
311 static void gen_##name (DisasContext *ctx); \
312 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
313 static void gen_##name (DisasContext *ctx)
314
315 typedef struct opcode_t {
316 unsigned char opc1, opc2, opc3;
317 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
318 unsigned char pad[5];
319 #else
320 unsigned char pad[1];
321 #endif
322 opc_handler_t handler;
323 const char *oname;
324 } opcode_t;
325
326 /*****************************************************************************/
327 /*** Instruction decoding ***/
328 #define EXTRACT_HELPER(name, shift, nb) \
329 static always_inline uint32_t name (uint32_t opcode) \
330 { \
331 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
332 }
333
334 #define EXTRACT_SHELPER(name, shift, nb) \
335 static always_inline int32_t name (uint32_t opcode) \
336 { \
337 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
338 }
339
340 /* Opcode part 1 */
341 EXTRACT_HELPER(opc1, 26, 6);
342 /* Opcode part 2 */
343 EXTRACT_HELPER(opc2, 1, 5);
344 /* Opcode part 3 */
345 EXTRACT_HELPER(opc3, 6, 5);
346 /* Update Cr0 flags */
347 EXTRACT_HELPER(Rc, 0, 1);
348 /* Destination */
349 EXTRACT_HELPER(rD, 21, 5);
350 /* Source */
351 EXTRACT_HELPER(rS, 21, 5);
352 /* First operand */
353 EXTRACT_HELPER(rA, 16, 5);
354 /* Second operand */
355 EXTRACT_HELPER(rB, 11, 5);
356 /* Third operand */
357 EXTRACT_HELPER(rC, 6, 5);
358 /*** Get CRn ***/
359 EXTRACT_HELPER(crfD, 23, 3);
360 EXTRACT_HELPER(crfS, 18, 3);
361 EXTRACT_HELPER(crbD, 21, 5);
362 EXTRACT_HELPER(crbA, 16, 5);
363 EXTRACT_HELPER(crbB, 11, 5);
364 /* SPR / TBL */
365 EXTRACT_HELPER(_SPR, 11, 10);
366 static always_inline uint32_t SPR (uint32_t opcode)
367 {
368 uint32_t sprn = _SPR(opcode);
369
370 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
371 }
372 /*** Get constants ***/
373 EXTRACT_HELPER(IMM, 12, 8);
374 /* 16 bits signed immediate value */
375 EXTRACT_SHELPER(SIMM, 0, 16);
376 /* 16 bits unsigned immediate value */
377 EXTRACT_HELPER(UIMM, 0, 16);
378 /* 5 bits signed immediate value */
379 EXTRACT_HELPER(SIMM5, 16, 5);
380 /* 5 bits signed immediate value */
381 EXTRACT_HELPER(UIMM5, 16, 5);
382 /* Bit count */
383 EXTRACT_HELPER(NB, 11, 5);
384 /* Shift count */
385 EXTRACT_HELPER(SH, 11, 5);
386 /* Vector shift count */
387 EXTRACT_HELPER(VSH, 6, 4);
388 /* Mask start */
389 EXTRACT_HELPER(MB, 6, 5);
390 /* Mask end */
391 EXTRACT_HELPER(ME, 1, 5);
392 /* Trap operand */
393 EXTRACT_HELPER(TO, 21, 5);
394
395 EXTRACT_HELPER(CRM, 12, 8);
396 EXTRACT_HELPER(FM, 17, 8);
397 EXTRACT_HELPER(SR, 16, 4);
398 EXTRACT_HELPER(FPIMM, 12, 4);
399
400 /*** Jump target decoding ***/
401 /* Displacement */
402 EXTRACT_SHELPER(d, 0, 16);
403 /* Immediate address */
404 static always_inline target_ulong LI (uint32_t opcode)
405 {
406 return (opcode >> 0) & 0x03FFFFFC;
407 }
408
409 static always_inline uint32_t BD (uint32_t opcode)
410 {
411 return (opcode >> 0) & 0xFFFC;
412 }
413
414 EXTRACT_HELPER(BO, 21, 5);
415 EXTRACT_HELPER(BI, 16, 5);
416 /* Absolute/relative address */
417 EXTRACT_HELPER(AA, 1, 1);
418 /* Link */
419 EXTRACT_HELPER(LK, 0, 1);
420
421 /* Create a mask between <start> and <end> bits */
422 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
423 {
424 target_ulong ret;
425
426 #if defined(TARGET_PPC64)
427 if (likely(start == 0)) {
428 ret = UINT64_MAX << (63 - end);
429 } else if (likely(end == 63)) {
430 ret = UINT64_MAX >> start;
431 }
432 #else
433 if (likely(start == 0)) {
434 ret = UINT32_MAX << (31 - end);
435 } else if (likely(end == 31)) {
436 ret = UINT32_MAX >> start;
437 }
438 #endif
439 else {
440 ret = (((target_ulong)(-1ULL)) >> (start)) ^
441 (((target_ulong)(-1ULL) >> (end)) >> 1);
442 if (unlikely(start > end))
443 return ~ret;
444 }
445
446 return ret;
447 }
448
449 /*****************************************************************************/
450 /* PowerPC Instructions types definitions */
451 enum {
452 PPC_NONE = 0x0000000000000000ULL,
453 /* PowerPC base instructions set */
454 PPC_INSNS_BASE = 0x0000000000000001ULL,
455 /* integer operations instructions */
456 #define PPC_INTEGER PPC_INSNS_BASE
457 /* flow control instructions */
458 #define PPC_FLOW PPC_INSNS_BASE
459 /* virtual memory instructions */
460 #define PPC_MEM PPC_INSNS_BASE
461 /* ld/st with reservation instructions */
462 #define PPC_RES PPC_INSNS_BASE
463 /* spr/msr access instructions */
464 #define PPC_MISC PPC_INSNS_BASE
465 /* Deprecated instruction sets */
466 /* Original POWER instruction set */
467 PPC_POWER = 0x0000000000000002ULL,
468 /* POWER2 instruction set extension */
469 PPC_POWER2 = 0x0000000000000004ULL,
470 /* Power RTC support */
471 PPC_POWER_RTC = 0x0000000000000008ULL,
472 /* Power-to-PowerPC bridge (601) */
473 PPC_POWER_BR = 0x0000000000000010ULL,
474 /* 64 bits PowerPC instruction set */
475 PPC_64B = 0x0000000000000020ULL,
476 /* New 64 bits extensions (PowerPC 2.0x) */
477 PPC_64BX = 0x0000000000000040ULL,
478 /* 64 bits hypervisor extensions */
479 PPC_64H = 0x0000000000000080ULL,
480 /* New wait instruction (PowerPC 2.0x) */
481 PPC_WAIT = 0x0000000000000100ULL,
482 /* Time base mftb instruction */
483 PPC_MFTB = 0x0000000000000200ULL,
484
485 /* Fixed-point unit extensions */
486 /* PowerPC 602 specific */
487 PPC_602_SPEC = 0x0000000000000400ULL,
488 /* isel instruction */
489 PPC_ISEL = 0x0000000000000800ULL,
490 /* popcntb instruction */
491 PPC_POPCNTB = 0x0000000000001000ULL,
492 /* string load / store */
493 PPC_STRING = 0x0000000000002000ULL,
494
495 /* Floating-point unit extensions */
496 /* Optional floating point instructions */
497 PPC_FLOAT = 0x0000000000010000ULL,
498 /* New floating-point extensions (PowerPC 2.0x) */
499 PPC_FLOAT_EXT = 0x0000000000020000ULL,
500 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
501 PPC_FLOAT_FRES = 0x0000000000080000ULL,
502 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
503 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
504 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
505 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
506
507 /* Vector/SIMD extensions */
508 /* Altivec support */
509 PPC_ALTIVEC = 0x0000000001000000ULL,
510 /* PowerPC 2.03 SPE extension */
511 PPC_SPE = 0x0000000002000000ULL,
512 /* PowerPC 2.03 SPE single-precision floating-point extension */
513 PPC_SPE_SINGLE = 0x0000000004000000ULL,
514 /* PowerPC 2.03 SPE double-precision floating-point extension */
515 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
516
517 /* Optional memory control instructions */
518 PPC_MEM_TLBIA = 0x0000000010000000ULL,
519 PPC_MEM_TLBIE = 0x0000000020000000ULL,
520 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
521 /* sync instruction */
522 PPC_MEM_SYNC = 0x0000000080000000ULL,
523 /* eieio instruction */
524 PPC_MEM_EIEIO = 0x0000000100000000ULL,
525
526 /* Cache control instructions */
527 PPC_CACHE = 0x0000000200000000ULL,
528 /* icbi instruction */
529 PPC_CACHE_ICBI = 0x0000000400000000ULL,
530 /* dcbz instruction with fixed cache line size */
531 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
532 /* dcbz instruction with tunable cache line size */
533 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
534 /* dcba instruction */
535 PPC_CACHE_DCBA = 0x0000002000000000ULL,
536 /* Freescale cache locking instructions */
537 PPC_CACHE_LOCK = 0x0000004000000000ULL,
538
539 /* MMU related extensions */
540 /* external control instructions */
541 PPC_EXTERN = 0x0000010000000000ULL,
542 /* segment register access instructions */
543 PPC_SEGMENT = 0x0000020000000000ULL,
544 /* PowerPC 6xx TLB management instructions */
545 PPC_6xx_TLB = 0x0000040000000000ULL,
546 /* PowerPC 74xx TLB management instructions */
547 PPC_74xx_TLB = 0x0000080000000000ULL,
548 /* PowerPC 40x TLB management instructions */
549 PPC_40x_TLB = 0x0000100000000000ULL,
550 /* segment register access instructions for PowerPC 64 "bridge" */
551 PPC_SEGMENT_64B = 0x0000200000000000ULL,
552 /* SLB management */
553 PPC_SLBI = 0x0000400000000000ULL,
554
555 /* Embedded PowerPC dedicated instructions */
556 PPC_WRTEE = 0x0001000000000000ULL,
557 /* PowerPC 40x exception model */
558 PPC_40x_EXCP = 0x0002000000000000ULL,
559 /* PowerPC 405 Mac instructions */
560 PPC_405_MAC = 0x0004000000000000ULL,
561 /* PowerPC 440 specific instructions */
562 PPC_440_SPEC = 0x0008000000000000ULL,
563 /* BookE (embedded) PowerPC specification */
564 PPC_BOOKE = 0x0010000000000000ULL,
565 /* mfapidi instruction */
566 PPC_MFAPIDI = 0x0020000000000000ULL,
567 /* tlbiva instruction */
568 PPC_TLBIVA = 0x0040000000000000ULL,
569 /* tlbivax instruction */
570 PPC_TLBIVAX = 0x0080000000000000ULL,
571 /* PowerPC 4xx dedicated instructions */
572 PPC_4xx_COMMON = 0x0100000000000000ULL,
573 /* PowerPC 40x ibct instructions */
574 PPC_40x_ICBT = 0x0200000000000000ULL,
575 /* rfmci is not implemented in all BookE PowerPC */
576 PPC_RFMCI = 0x0400000000000000ULL,
577 /* rfdi instruction */
578 PPC_RFDI = 0x0800000000000000ULL,
579 /* DCR accesses */
580 PPC_DCR = 0x1000000000000000ULL,
581 /* DCR extended accesse */
582 PPC_DCRX = 0x2000000000000000ULL,
583 /* user-mode DCR access, implemented in PowerPC 460 */
584 PPC_DCRUX = 0x4000000000000000ULL,
585 };
586
587 /*****************************************************************************/
588 /* PowerPC instructions table */
589 #if HOST_LONG_BITS == 64
590 #define OPC_ALIGN 8
591 #else
592 #define OPC_ALIGN 4
593 #endif
594 #if defined(__APPLE__)
595 #define OPCODES_SECTION \
596 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
597 #else
598 #define OPCODES_SECTION \
599 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
600 #endif
601
602 #if defined(DO_PPC_STATISTICS)
603 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
604 OPCODES_SECTION opcode_t opc_##name = { \
605 .opc1 = op1, \
606 .opc2 = op2, \
607 .opc3 = op3, \
608 .pad = { 0, }, \
609 .handler = { \
610 .inval = invl, \
611 .type = _typ, \
612 .handler = &gen_##name, \
613 .oname = stringify(name), \
614 }, \
615 .oname = stringify(name), \
616 }
617 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
618 OPCODES_SECTION opcode_t opc_##name = { \
619 .opc1 = op1, \
620 .opc2 = op2, \
621 .opc3 = op3, \
622 .pad = { 0, }, \
623 .handler = { \
624 .inval = invl, \
625 .type = _typ, \
626 .handler = &gen_##name, \
627 .oname = onam, \
628 }, \
629 .oname = onam, \
630 }
631 #else
632 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
633 OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 }, \
643 .oname = stringify(name), \
644 }
645 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
646 OPCODES_SECTION opcode_t opc_##name = { \
647 .opc1 = op1, \
648 .opc2 = op2, \
649 .opc3 = op3, \
650 .pad = { 0, }, \
651 .handler = { \
652 .inval = invl, \
653 .type = _typ, \
654 .handler = &gen_##name, \
655 }, \
656 .oname = onam, \
657 }
658 #endif
659
660 #define GEN_OPCODE_MARK(name) \
661 OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = 0xFF, \
663 .opc2 = 0xFF, \
664 .opc3 = 0xFF, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = 0x00000000, \
668 .type = 0x00, \
669 .handler = NULL, \
670 }, \
671 .oname = stringify(name), \
672 }
673
674 /* SPR load/store helpers */
675 static always_inline void gen_load_spr(TCGv t, int reg)
676 {
677 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
678 }
679
680 static always_inline void gen_store_spr(int reg, TCGv t)
681 {
682 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
683 }
684
685 /* Start opcode list */
686 GEN_OPCODE_MARK(start);
687
688 /* Invalid instruction */
689 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
690 {
691 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
692 }
693
694 static opc_handler_t invalid_handler = {
695 .inval = 0xFFFFFFFF,
696 .type = PPC_NONE,
697 .handler = gen_invalid,
698 };
699
700 /*** Integer comparison ***/
701
702 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
703 {
704 int l1, l2, l3;
705
706 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
707 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
708 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
709
710 l1 = gen_new_label();
711 l2 = gen_new_label();
712 l3 = gen_new_label();
713 if (s) {
714 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
715 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
716 } else {
717 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
718 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
719 }
720 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
721 tcg_gen_br(l3);
722 gen_set_label(l1);
723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
724 tcg_gen_br(l3);
725 gen_set_label(l2);
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
727 gen_set_label(l3);
728 }
729
730 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
731 {
732 TCGv t0 = tcg_const_local_tl(arg1);
733 gen_op_cmp(arg0, t0, s, crf);
734 tcg_temp_free(t0);
735 }
736
737 #if defined(TARGET_PPC64)
738 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
739 {
740 TCGv t0, t1;
741 t0 = tcg_temp_local_new();
742 t1 = tcg_temp_local_new();
743 if (s) {
744 tcg_gen_ext32s_tl(t0, arg0);
745 tcg_gen_ext32s_tl(t1, arg1);
746 } else {
747 tcg_gen_ext32u_tl(t0, arg0);
748 tcg_gen_ext32u_tl(t1, arg1);
749 }
750 gen_op_cmp(t0, t1, s, crf);
751 tcg_temp_free(t1);
752 tcg_temp_free(t0);
753 }
754
755 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
756 {
757 TCGv t0 = tcg_const_local_tl(arg1);
758 gen_op_cmp32(arg0, t0, s, crf);
759 tcg_temp_free(t0);
760 }
761 #endif
762
763 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
764 {
765 #if defined(TARGET_PPC64)
766 if (!(ctx->sf_mode))
767 gen_op_cmpi32(reg, 0, 1, 0);
768 else
769 #endif
770 gen_op_cmpi(reg, 0, 1, 0);
771 }
772
773 /* cmp */
774 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
775 {
776 #if defined(TARGET_PPC64)
777 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
778 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
779 1, crfD(ctx->opcode));
780 else
781 #endif
782 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 }
785
786 /* cmpi */
787 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
788 {
789 #if defined(TARGET_PPC64)
790 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
791 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
792 1, crfD(ctx->opcode));
793 else
794 #endif
795 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 }
798
799 /* cmpl */
800 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
801 {
802 #if defined(TARGET_PPC64)
803 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
804 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
805 0, crfD(ctx->opcode));
806 else
807 #endif
808 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 }
811
812 /* cmpli */
813 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
814 {
815 #if defined(TARGET_PPC64)
816 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
817 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
818 0, crfD(ctx->opcode));
819 else
820 #endif
821 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 }
824
825 /* isel (PowerPC 2.03 specification) */
826 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
827 {
828 int l1, l2;
829 uint32_t bi = rC(ctx->opcode);
830 uint32_t mask;
831 TCGv_i32 t0;
832
833 l1 = gen_new_label();
834 l2 = gen_new_label();
835
836 mask = 1 << (3 - (bi & 0x03));
837 t0 = tcg_temp_new_i32();
838 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
839 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
840 if (rA(ctx->opcode) == 0)
841 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
842 else
843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
844 tcg_gen_br(l2);
845 gen_set_label(l1);
846 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
847 gen_set_label(l2);
848 tcg_temp_free_i32(t0);
849 }
850
851 /*** Integer arithmetic ***/
852
853 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
854 {
855 int l1;
856 TCGv t0;
857
858 l1 = gen_new_label();
859 /* Start with XER OV disabled, the most likely case */
860 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
861 t0 = tcg_temp_local_new();
862 tcg_gen_xor_tl(t0, arg0, arg1);
863 #if defined(TARGET_PPC64)
864 if (!ctx->sf_mode)
865 tcg_gen_ext32s_tl(t0, t0);
866 #endif
867 if (sub)
868 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
869 else
870 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
871 tcg_gen_xor_tl(t0, arg1, arg2);
872 #if defined(TARGET_PPC64)
873 if (!ctx->sf_mode)
874 tcg_gen_ext32s_tl(t0, t0);
875 #endif
876 if (sub)
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 else
879 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
880 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
881 gen_set_label(l1);
882 tcg_temp_free(t0);
883 }
884
885 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
886 {
887 int l1 = gen_new_label();
888
889 #if defined(TARGET_PPC64)
890 if (!(ctx->sf_mode)) {
891 TCGv t0, t1;
892 t0 = tcg_temp_new();
893 t1 = tcg_temp_new();
894
895 tcg_gen_ext32u_tl(t0, arg1);
896 tcg_gen_ext32u_tl(t1, arg2);
897 if (sub) {
898 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
899 } else {
900 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
901 }
902 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
903 gen_set_label(l1);
904 tcg_temp_free(t0);
905 tcg_temp_free(t1);
906 } else
907 #endif
908 {
909 if (sub) {
910 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
911 } else {
912 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
913 }
914 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
915 gen_set_label(l1);
916 }
917 }
918
919 /* Common add function */
920 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
921 int add_ca, int compute_ca, int compute_ov)
922 {
923 TCGv t0, t1;
924
925 if ((!compute_ca && !compute_ov) ||
926 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
927 t0 = ret;
928 } else {
929 t0 = tcg_temp_local_new();
930 }
931
932 if (add_ca) {
933 t1 = tcg_temp_local_new();
934 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
935 tcg_gen_shri_tl(t1, t1, XER_CA);
936 }
937
938 if (compute_ca && compute_ov) {
939 /* Start with XER CA and OV disabled, the most likely case */
940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
941 } else if (compute_ca) {
942 /* Start with XER CA disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
944 } else if (compute_ov) {
945 /* Start with XER OV disabled, the most likely case */
946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
947 }
948
949 tcg_gen_add_tl(t0, arg1, arg2);
950
951 if (compute_ca) {
952 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
953 }
954 if (add_ca) {
955 tcg_gen_add_tl(t0, t0, t1);
956 gen_op_arith_compute_ca(ctx, t0, t1, 0);
957 tcg_temp_free(t1);
958 }
959 if (compute_ov) {
960 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
961 }
962
963 if (unlikely(Rc(ctx->opcode) != 0))
964 gen_set_Rc0(ctx, t0);
965
966 if (!TCGV_EQUAL(t0, ret)) {
967 tcg_gen_mov_tl(ret, t0);
968 tcg_temp_free(t0);
969 }
970 }
971 /* Add functions with two operands */
972 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
973 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
974 { \
975 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
976 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
977 add_ca, compute_ca, compute_ov); \
978 }
979 /* Add functions with one operand and one immediate */
980 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
981 add_ca, compute_ca, compute_ov) \
982 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
983 { \
984 TCGv t0 = tcg_const_local_tl(const_val); \
985 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
986 cpu_gpr[rA(ctx->opcode)], t0, \
987 add_ca, compute_ca, compute_ov); \
988 tcg_temp_free(t0); \
989 }
990
991 /* add add. addo addo. */
992 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
993 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
994 /* addc addc. addco addco. */
995 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
996 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
997 /* adde adde. addeo addeo. */
998 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
999 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1000 /* addme addme. addmeo addmeo. */
1001 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1002 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1003 /* addze addze. addzeo addzeo.*/
1004 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1005 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1006 /* addi */
1007 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1008 {
1009 target_long simm = SIMM(ctx->opcode);
1010
1011 if (rA(ctx->opcode) == 0) {
1012 /* li case */
1013 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1014 } else {
1015 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1016 }
1017 }
1018 /* addic addic.*/
1019 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1020 int compute_Rc0)
1021 {
1022 target_long simm = SIMM(ctx->opcode);
1023
1024 /* Start with XER CA and OV disabled, the most likely case */
1025 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1026
1027 if (likely(simm != 0)) {
1028 TCGv t0 = tcg_temp_local_new();
1029 tcg_gen_addi_tl(t0, arg1, simm);
1030 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1031 tcg_gen_mov_tl(ret, t0);
1032 tcg_temp_free(t0);
1033 } else {
1034 tcg_gen_mov_tl(ret, arg1);
1035 }
1036 if (compute_Rc0) {
1037 gen_set_Rc0(ctx, ret);
1038 }
1039 }
1040 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1041 {
1042 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1043 }
1044 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1045 {
1046 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1047 }
1048 /* addis */
1049 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1050 {
1051 target_long simm = SIMM(ctx->opcode);
1052
1053 if (rA(ctx->opcode) == 0) {
1054 /* lis case */
1055 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1056 } else {
1057 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1058 }
1059 }
1060
1061 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1062 int sign, int compute_ov)
1063 {
1064 int l1 = gen_new_label();
1065 int l2 = gen_new_label();
1066 TCGv_i32 t0 = tcg_temp_local_new_i32();
1067 TCGv_i32 t1 = tcg_temp_local_new_i32();
1068
1069 tcg_gen_trunc_tl_i32(t0, arg1);
1070 tcg_gen_trunc_tl_i32(t1, arg2);
1071 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1072 if (sign) {
1073 int l3 = gen_new_label();
1074 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1075 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1076 gen_set_label(l3);
1077 tcg_gen_div_i32(t0, t0, t1);
1078 } else {
1079 tcg_gen_divu_i32(t0, t0, t1);
1080 }
1081 if (compute_ov) {
1082 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1083 }
1084 tcg_gen_br(l2);
1085 gen_set_label(l1);
1086 if (sign) {
1087 tcg_gen_sari_i32(t0, t0, 31);
1088 } else {
1089 tcg_gen_movi_i32(t0, 0);
1090 }
1091 if (compute_ov) {
1092 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1093 }
1094 gen_set_label(l2);
1095 tcg_gen_extu_i32_tl(ret, t0);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i32(t1);
1098 if (unlikely(Rc(ctx->opcode) != 0))
1099 gen_set_Rc0(ctx, ret);
1100 }
1101 /* Div functions */
1102 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1103 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1104 { \
1105 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1106 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1107 sign, compute_ov); \
1108 }
1109 /* divwu divwu. divwuo divwuo. */
1110 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1111 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1112 /* divw divw. divwo divwo. */
1113 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1114 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1115 #if defined(TARGET_PPC64)
1116 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1117 int sign, int compute_ov)
1118 {
1119 int l1 = gen_new_label();
1120 int l2 = gen_new_label();
1121
1122 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1123 if (sign) {
1124 int l3 = gen_new_label();
1125 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1126 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1127 gen_set_label(l3);
1128 tcg_gen_div_i64(ret, arg1, arg2);
1129 } else {
1130 tcg_gen_divu_i64(ret, arg1, arg2);
1131 }
1132 if (compute_ov) {
1133 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1134 }
1135 tcg_gen_br(l2);
1136 gen_set_label(l1);
1137 if (sign) {
1138 tcg_gen_sari_i64(ret, arg1, 63);
1139 } else {
1140 tcg_gen_movi_i64(ret, 0);
1141 }
1142 if (compute_ov) {
1143 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1144 }
1145 gen_set_label(l2);
1146 if (unlikely(Rc(ctx->opcode) != 0))
1147 gen_set_Rc0(ctx, ret);
1148 }
1149 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1150 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1151 { \
1152 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1153 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1154 sign, compute_ov); \
1155 }
1156 /* divwu divwu. divwuo divwuo. */
1157 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1158 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1159 /* divw divw. divwo divwo. */
1160 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1161 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1162 #endif
1163
1164 /* mulhw mulhw. */
1165 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1166 {
1167 TCGv_i64 t0, t1;
1168
1169 t0 = tcg_temp_new_i64();
1170 t1 = tcg_temp_new_i64();
1171 #if defined(TARGET_PPC64)
1172 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1173 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1174 tcg_gen_mul_i64(t0, t0, t1);
1175 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1176 #else
1177 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1178 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1179 tcg_gen_mul_i64(t0, t0, t1);
1180 tcg_gen_shri_i64(t0, t0, 32);
1181 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1182 #endif
1183 tcg_temp_free_i64(t0);
1184 tcg_temp_free_i64(t1);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1187 }
1188 /* mulhwu mulhwu. */
1189 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1190 {
1191 TCGv_i64 t0, t1;
1192
1193 t0 = tcg_temp_new_i64();
1194 t1 = tcg_temp_new_i64();
1195 #if defined(TARGET_PPC64)
1196 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1197 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1198 tcg_gen_mul_i64(t0, t0, t1);
1199 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1200 #else
1201 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1202 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1203 tcg_gen_mul_i64(t0, t0, t1);
1204 tcg_gen_shri_i64(t0, t0, 32);
1205 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1206 #endif
1207 tcg_temp_free_i64(t0);
1208 tcg_temp_free_i64(t1);
1209 if (unlikely(Rc(ctx->opcode) != 0))
1210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211 }
1212 /* mullw mullw. */
1213 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1214 {
1215 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1216 cpu_gpr[rB(ctx->opcode)]);
1217 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1218 if (unlikely(Rc(ctx->opcode) != 0))
1219 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1220 }
1221 /* mullwo mullwo. */
1222 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1223 {
1224 int l1;
1225 TCGv_i64 t0, t1;
1226
1227 t0 = tcg_temp_new_i64();
1228 t1 = tcg_temp_new_i64();
1229 l1 = gen_new_label();
1230 /* Start with XER OV disabled, the most likely case */
1231 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1232 #if defined(TARGET_PPC64)
1233 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1234 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1235 #else
1236 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1237 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1238 #endif
1239 tcg_gen_mul_i64(t0, t0, t1);
1240 #if defined(TARGET_PPC64)
1241 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1242 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1243 #else
1244 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1245 tcg_gen_ext32s_i64(t1, t0);
1246 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1247 #endif
1248 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1249 gen_set_label(l1);
1250 tcg_temp_free_i64(t0);
1251 tcg_temp_free_i64(t1);
1252 if (unlikely(Rc(ctx->opcode) != 0))
1253 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1254 }
1255 /* mulli */
1256 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1257 {
1258 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1259 SIMM(ctx->opcode));
1260 }
1261 #if defined(TARGET_PPC64)
1262 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1263 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1264 { \
1265 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1266 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1267 if (unlikely(Rc(ctx->opcode) != 0)) \
1268 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1269 }
1270 /* mulhd mulhd. */
1271 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1272 /* mulhdu mulhdu. */
1273 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1274 /* mulld mulld. */
1275 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1276 {
1277 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1278 cpu_gpr[rB(ctx->opcode)]);
1279 if (unlikely(Rc(ctx->opcode) != 0))
1280 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1281 }
1282 /* mulldo mulldo. */
1283 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1284 #endif
1285
1286 /* neg neg. nego nego. */
1287 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1288 {
1289 int l1 = gen_new_label();
1290 int l2 = gen_new_label();
1291 TCGv t0 = tcg_temp_local_new();
1292 #if defined(TARGET_PPC64)
1293 if (ctx->sf_mode) {
1294 tcg_gen_mov_tl(t0, arg1);
1295 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1296 } else
1297 #endif
1298 {
1299 tcg_gen_ext32s_tl(t0, arg1);
1300 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1301 }
1302 tcg_gen_neg_tl(ret, arg1);
1303 if (ov_check) {
1304 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1305 }
1306 tcg_gen_br(l2);
1307 gen_set_label(l1);
1308 tcg_gen_mov_tl(ret, t0);
1309 if (ov_check) {
1310 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1311 }
1312 gen_set_label(l2);
1313 tcg_temp_free(t0);
1314 if (unlikely(Rc(ctx->opcode) != 0))
1315 gen_set_Rc0(ctx, ret);
1316 }
1317 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1318 {
1319 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1320 }
1321 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1322 {
1323 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1324 }
1325
1326 /* Common subf function */
1327 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1328 int add_ca, int compute_ca, int compute_ov)
1329 {
1330 TCGv t0, t1;
1331
1332 if ((!compute_ca && !compute_ov) ||
1333 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1334 t0 = ret;
1335 } else {
1336 t0 = tcg_temp_local_new();
1337 }
1338
1339 if (add_ca) {
1340 t1 = tcg_temp_local_new();
1341 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1342 tcg_gen_shri_tl(t1, t1, XER_CA);
1343 }
1344
1345 if (compute_ca && compute_ov) {
1346 /* Start with XER CA and OV disabled, the most likely case */
1347 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1348 } else if (compute_ca) {
1349 /* Start with XER CA disabled, the most likely case */
1350 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1351 } else if (compute_ov) {
1352 /* Start with XER OV disabled, the most likely case */
1353 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1354 }
1355
1356 if (add_ca) {
1357 tcg_gen_not_tl(t0, arg1);
1358 tcg_gen_add_tl(t0, t0, arg2);
1359 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1360 tcg_gen_add_tl(t0, t0, t1);
1361 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1362 tcg_temp_free(t1);
1363 } else {
1364 tcg_gen_sub_tl(t0, arg2, arg1);
1365 if (compute_ca) {
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1367 }
1368 }
1369 if (compute_ov) {
1370 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1371 }
1372
1373 if (unlikely(Rc(ctx->opcode) != 0))
1374 gen_set_Rc0(ctx, t0);
1375
1376 if (!TCGV_EQUAL(t0, ret)) {
1377 tcg_gen_mov_tl(ret, t0);
1378 tcg_temp_free(t0);
1379 }
1380 }
1381 /* Sub functions with Two operands functions */
1382 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1383 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1384 { \
1385 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1386 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1387 add_ca, compute_ca, compute_ov); \
1388 }
1389 /* Sub functions with one operand and one immediate */
1390 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1391 add_ca, compute_ca, compute_ov) \
1392 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1393 { \
1394 TCGv t0 = tcg_const_local_tl(const_val); \
1395 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1396 cpu_gpr[rA(ctx->opcode)], t0, \
1397 add_ca, compute_ca, compute_ov); \
1398 tcg_temp_free(t0); \
1399 }
1400 /* subf subf. subfo subfo. */
1401 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1402 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1403 /* subfc subfc. subfco subfco. */
1404 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1405 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1406 /* subfe subfe. subfeo subfo. */
1407 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1408 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1409 /* subfme subfme. subfmeo subfmeo. */
1410 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1411 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1412 /* subfze subfze. subfzeo subfzeo.*/
1413 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1414 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1415 /* subfic */
1416 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1417 {
1418 /* Start with XER CA and OV disabled, the most likely case */
1419 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1420 TCGv t0 = tcg_temp_local_new();
1421 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1422 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1423 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1424 tcg_temp_free(t1);
1425 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1426 tcg_temp_free(t0);
1427 }
1428
1429 /*** Integer logical ***/
1430 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1431 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1432 { \
1433 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1434 cpu_gpr[rB(ctx->opcode)]); \
1435 if (unlikely(Rc(ctx->opcode) != 0)) \
1436 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1437 }
1438
1439 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1440 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1441 { \
1442 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1443 if (unlikely(Rc(ctx->opcode) != 0)) \
1444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1445 }
1446
1447 /* and & and. */
1448 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1449 /* andc & andc. */
1450 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1451 /* andi. */
1452 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1453 {
1454 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1456 }
1457 /* andis. */
1458 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1459 {
1460 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1462 }
1463 /* cntlzw */
1464 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1465 {
1466 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1467 if (unlikely(Rc(ctx->opcode) != 0))
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1469 }
1470 /* eqv & eqv. */
1471 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1472 /* extsb & extsb. */
1473 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1474 /* extsh & extsh. */
1475 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1476 /* nand & nand. */
1477 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1478 /* nor & nor. */
1479 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1480 /* or & or. */
1481 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1482 {
1483 int rs, ra, rb;
1484
1485 rs = rS(ctx->opcode);
1486 ra = rA(ctx->opcode);
1487 rb = rB(ctx->opcode);
1488 /* Optimisation for mr. ri case */
1489 if (rs != ra || rs != rb) {
1490 if (rs != rb)
1491 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1492 else
1493 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1494 if (unlikely(Rc(ctx->opcode) != 0))
1495 gen_set_Rc0(ctx, cpu_gpr[ra]);
1496 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1497 gen_set_Rc0(ctx, cpu_gpr[rs]);
1498 #if defined(TARGET_PPC64)
1499 } else {
1500 int prio = 0;
1501
1502 switch (rs) {
1503 case 1:
1504 /* Set process priority to low */
1505 prio = 2;
1506 break;
1507 case 6:
1508 /* Set process priority to medium-low */
1509 prio = 3;
1510 break;
1511 case 2:
1512 /* Set process priority to normal */
1513 prio = 4;
1514 break;
1515 #if !defined(CONFIG_USER_ONLY)
1516 case 31:
1517 if (ctx->mem_idx > 0) {
1518 /* Set process priority to very low */
1519 prio = 1;
1520 }
1521 break;
1522 case 5:
1523 if (ctx->mem_idx > 0) {
1524 /* Set process priority to medium-hight */
1525 prio = 5;
1526 }
1527 break;
1528 case 3:
1529 if (ctx->mem_idx > 0) {
1530 /* Set process priority to high */
1531 prio = 6;
1532 }
1533 break;
1534 case 7:
1535 if (ctx->mem_idx > 1) {
1536 /* Set process priority to very high */
1537 prio = 7;
1538 }
1539 break;
1540 #endif
1541 default:
1542 /* nop */
1543 break;
1544 }
1545 if (prio) {
1546 TCGv t0 = tcg_temp_new();
1547 gen_load_spr(t0, SPR_PPR);
1548 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1549 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1550 gen_store_spr(SPR_PPR, t0);
1551 tcg_temp_free(t0);
1552 }
1553 #endif
1554 }
1555 }
1556 /* orc & orc. */
1557 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1558 /* xor & xor. */
1559 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1560 {
1561 /* Optimisation for "set to zero" case */
1562 if (rS(ctx->opcode) != rB(ctx->opcode))
1563 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1564 else
1565 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1566 if (unlikely(Rc(ctx->opcode) != 0))
1567 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1568 }
1569 /* ori */
1570 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1571 {
1572 target_ulong uimm = UIMM(ctx->opcode);
1573
1574 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1575 /* NOP */
1576 /* XXX: should handle special NOPs for POWER series */
1577 return;
1578 }
1579 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1580 }
1581 /* oris */
1582 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1583 {
1584 target_ulong uimm = UIMM(ctx->opcode);
1585
1586 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1587 /* NOP */
1588 return;
1589 }
1590 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1591 }
1592 /* xori */
1593 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1594 {
1595 target_ulong uimm = UIMM(ctx->opcode);
1596
1597 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1598 /* NOP */
1599 return;
1600 }
1601 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1602 }
1603 /* xoris */
1604 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1605 {
1606 target_ulong uimm = UIMM(ctx->opcode);
1607
1608 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1609 /* NOP */
1610 return;
1611 }
1612 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1613 }
1614 /* popcntb : PowerPC 2.03 specification */
1615 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1616 {
1617 #if defined(TARGET_PPC64)
1618 if (ctx->sf_mode)
1619 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1620 else
1621 #endif
1622 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1623 }
1624
1625 #if defined(TARGET_PPC64)
1626 /* extsw & extsw. */
1627 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1628 /* cntlzd */
1629 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1630 {
1631 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1632 if (unlikely(Rc(ctx->opcode) != 0))
1633 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1634 }
1635 #endif
1636
1637 /*** Integer rotate ***/
1638 /* rlwimi & rlwimi. */
1639 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1640 {
1641 uint32_t mb, me, sh;
1642
1643 mb = MB(ctx->opcode);
1644 me = ME(ctx->opcode);
1645 sh = SH(ctx->opcode);
1646 if (likely(sh == 0 && mb == 0 && me == 31)) {
1647 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1648 } else {
1649 target_ulong mask;
1650 TCGv t1;
1651 TCGv t0 = tcg_temp_new();
1652 #if defined(TARGET_PPC64)
1653 TCGv_i32 t2 = tcg_temp_new_i32();
1654 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1655 tcg_gen_rotli_i32(t2, t2, sh);
1656 tcg_gen_extu_i32_i64(t0, t2);
1657 tcg_temp_free_i32(t2);
1658 #else
1659 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1660 #endif
1661 #if defined(TARGET_PPC64)
1662 mb += 32;
1663 me += 32;
1664 #endif
1665 mask = MASK(mb, me);
1666 t1 = tcg_temp_new();
1667 tcg_gen_andi_tl(t0, t0, mask);
1668 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1669 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1670 tcg_temp_free(t0);
1671 tcg_temp_free(t1);
1672 }
1673 if (unlikely(Rc(ctx->opcode) != 0))
1674 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1675 }
1676 /* rlwinm & rlwinm. */
1677 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1678 {
1679 uint32_t mb, me, sh;
1680
1681 sh = SH(ctx->opcode);
1682 mb = MB(ctx->opcode);
1683 me = ME(ctx->opcode);
1684
1685 if (likely(mb == 0 && me == (31 - sh))) {
1686 if (likely(sh == 0)) {
1687 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1688 } else {
1689 TCGv t0 = tcg_temp_new();
1690 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1691 tcg_gen_shli_tl(t0, t0, sh);
1692 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1693 tcg_temp_free(t0);
1694 }
1695 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1696 TCGv t0 = tcg_temp_new();
1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shri_tl(t0, t0, mb);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
1701 } else {
1702 TCGv t0 = tcg_temp_new();
1703 #if defined(TARGET_PPC64)
1704 TCGv_i32 t1 = tcg_temp_new_i32();
1705 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1706 tcg_gen_rotli_i32(t1, t1, sh);
1707 tcg_gen_extu_i32_i64(t0, t1);
1708 tcg_temp_free_i32(t1);
1709 #else
1710 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1711 #endif
1712 #if defined(TARGET_PPC64)
1713 mb += 32;
1714 me += 32;
1715 #endif
1716 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1717 tcg_temp_free(t0);
1718 }
1719 if (unlikely(Rc(ctx->opcode) != 0))
1720 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1721 }
1722 /* rlwnm & rlwnm. */
1723 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1724 {
1725 uint32_t mb, me;
1726 TCGv t0;
1727 #if defined(TARGET_PPC64)
1728 TCGv_i32 t1, t2;
1729 #endif
1730
1731 mb = MB(ctx->opcode);
1732 me = ME(ctx->opcode);
1733 t0 = tcg_temp_new();
1734 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1735 #if defined(TARGET_PPC64)
1736 t1 = tcg_temp_new_i32();
1737 t2 = tcg_temp_new_i32();
1738 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1739 tcg_gen_trunc_i64_i32(t2, t0);
1740 tcg_gen_rotl_i32(t1, t1, t2);
1741 tcg_gen_extu_i32_i64(t0, t1);
1742 tcg_temp_free_i32(t1);
1743 tcg_temp_free_i32(t2);
1744 #else
1745 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1746 #endif
1747 if (unlikely(mb != 0 || me != 31)) {
1748 #if defined(TARGET_PPC64)
1749 mb += 32;
1750 me += 32;
1751 #endif
1752 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1753 } else {
1754 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1755 }
1756 tcg_temp_free(t0);
1757 if (unlikely(Rc(ctx->opcode) != 0))
1758 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1759 }
1760
1761 #if defined(TARGET_PPC64)
1762 #define GEN_PPC64_R2(name, opc1, opc2) \
1763 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1764 { \
1765 gen_##name(ctx, 0); \
1766 } \
1767 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1768 PPC_64B) \
1769 { \
1770 gen_##name(ctx, 1); \
1771 }
1772 #define GEN_PPC64_R4(name, opc1, opc2) \
1773 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1774 { \
1775 gen_##name(ctx, 0, 0); \
1776 } \
1777 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1778 PPC_64B) \
1779 { \
1780 gen_##name(ctx, 0, 1); \
1781 } \
1782 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1783 PPC_64B) \
1784 { \
1785 gen_##name(ctx, 1, 0); \
1786 } \
1787 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1788 PPC_64B) \
1789 { \
1790 gen_##name(ctx, 1, 1); \
1791 }
1792
1793 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1794 uint32_t me, uint32_t sh)
1795 {
1796 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1797 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1798 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1799 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1800 } else {
1801 TCGv t0 = tcg_temp_new();
1802 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1803 if (likely(mb == 0 && me == 63)) {
1804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1805 } else {
1806 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1807 }
1808 tcg_temp_free(t0);
1809 }
1810 if (unlikely(Rc(ctx->opcode) != 0))
1811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1812 }
1813 /* rldicl - rldicl. */
1814 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1815 {
1816 uint32_t sh, mb;
1817
1818 sh = SH(ctx->opcode) | (shn << 5);
1819 mb = MB(ctx->opcode) | (mbn << 5);
1820 gen_rldinm(ctx, mb, 63, sh);
1821 }
1822 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1823 /* rldicr - rldicr. */
1824 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1825 {
1826 uint32_t sh, me;
1827
1828 sh = SH(ctx->opcode) | (shn << 5);
1829 me = MB(ctx->opcode) | (men << 5);
1830 gen_rldinm(ctx, 0, me, sh);
1831 }
1832 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1833 /* rldic - rldic. */
1834 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1835 {
1836 uint32_t sh, mb;
1837
1838 sh = SH(ctx->opcode) | (shn << 5);
1839 mb = MB(ctx->opcode) | (mbn << 5);
1840 gen_rldinm(ctx, mb, 63 - sh, sh);
1841 }
1842 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1843
1844 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1845 uint32_t me)
1846 {
1847 TCGv t0;
1848
1849 mb = MB(ctx->opcode);
1850 me = ME(ctx->opcode);
1851 t0 = tcg_temp_new();
1852 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1853 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1854 if (unlikely(mb != 0 || me != 63)) {
1855 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1856 } else {
1857 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1858 }
1859 tcg_temp_free(t0);
1860 if (unlikely(Rc(ctx->opcode) != 0))
1861 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1862 }
1863
1864 /* rldcl - rldcl. */
1865 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1866 {
1867 uint32_t mb;
1868
1869 mb = MB(ctx->opcode) | (mbn << 5);
1870 gen_rldnm(ctx, mb, 63);
1871 }
1872 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1873 /* rldcr - rldcr. */
1874 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1875 {
1876 uint32_t me;
1877
1878 me = MB(ctx->opcode) | (men << 5);
1879 gen_rldnm(ctx, 0, me);
1880 }
1881 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1882 /* rldimi - rldimi. */
1883 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1884 {
1885 uint32_t sh, mb, me;
1886
1887 sh = SH(ctx->opcode) | (shn << 5);
1888 mb = MB(ctx->opcode) | (mbn << 5);
1889 me = 63 - sh;
1890 if (unlikely(sh == 0 && mb == 0)) {
1891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1892 } else {
1893 TCGv t0, t1;
1894 target_ulong mask;
1895
1896 t0 = tcg_temp_new();
1897 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1898 t1 = tcg_temp_new();
1899 mask = MASK(mb, me);
1900 tcg_gen_andi_tl(t0, t0, mask);
1901 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1902 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t0);
1904 tcg_temp_free(t1);
1905 }
1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908 }
1909 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1910 #endif
1911
1912 /*** Integer shift ***/
1913 /* slw & slw. */
1914 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1915 {
1916 TCGv t0;
1917 int l1, l2;
1918 l1 = gen_new_label();
1919 l2 = gen_new_label();
1920
1921 t0 = tcg_temp_local_new();
1922 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1923 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1924 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1925 tcg_gen_br(l2);
1926 gen_set_label(l1);
1927 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1928 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1929 gen_set_label(l2);
1930 tcg_temp_free(t0);
1931 if (unlikely(Rc(ctx->opcode) != 0))
1932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1933 }
1934 /* sraw & sraw. */
1935 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1936 {
1937 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1938 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1939 if (unlikely(Rc(ctx->opcode) != 0))
1940 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1941 }
1942 /* srawi & srawi. */
1943 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1944 {
1945 int sh = SH(ctx->opcode);
1946 if (sh != 0) {
1947 int l1, l2;
1948 TCGv t0;
1949 l1 = gen_new_label();
1950 l2 = gen_new_label();
1951 t0 = tcg_temp_local_new();
1952 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1953 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1954 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1955 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1956 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1957 tcg_gen_br(l2);
1958 gen_set_label(l1);
1959 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1960 gen_set_label(l2);
1961 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1962 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1963 tcg_temp_free(t0);
1964 } else {
1965 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1967 }
1968 if (unlikely(Rc(ctx->opcode) != 0))
1969 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1970 }
1971 /* srw & srw. */
1972 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1973 {
1974 TCGv t0, t1;
1975 int l1, l2;
1976 l1 = gen_new_label();
1977 l2 = gen_new_label();
1978
1979 t0 = tcg_temp_local_new();
1980 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1981 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1982 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1983 tcg_gen_br(l2);
1984 gen_set_label(l1);
1985 t1 = tcg_temp_new();
1986 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1987 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1988 tcg_temp_free(t1);
1989 gen_set_label(l2);
1990 tcg_temp_free(t0);
1991 if (unlikely(Rc(ctx->opcode) != 0))
1992 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1993 }
1994 #if defined(TARGET_PPC64)
1995 /* sld & sld. */
1996 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1997 {
1998 TCGv t0;
1999 int l1, l2;
2000 l1 = gen_new_label();
2001 l2 = gen_new_label();
2002
2003 t0 = tcg_temp_local_new();
2004 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2005 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2006 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2007 tcg_gen_br(l2);
2008 gen_set_label(l1);
2009 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2010 gen_set_label(l2);
2011 tcg_temp_free(t0);
2012 if (unlikely(Rc(ctx->opcode) != 0))
2013 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2014 }
2015 /* srad & srad. */
2016 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2017 {
2018 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2019 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2020 if (unlikely(Rc(ctx->opcode) != 0))
2021 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2022 }
2023 /* sradi & sradi. */
2024 static always_inline void gen_sradi (DisasContext *ctx, int n)
2025 {
2026 int sh = SH(ctx->opcode) + (n << 5);
2027 if (sh != 0) {
2028 int l1, l2;
2029 TCGv t0;
2030 l1 = gen_new_label();
2031 l2 = gen_new_label();
2032 t0 = tcg_temp_local_new();
2033 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2034 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2035 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2036 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2037 tcg_gen_br(l2);
2038 gen_set_label(l1);
2039 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2040 gen_set_label(l2);
2041 tcg_temp_free(t0);
2042 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2043 } else {
2044 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2045 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2046 }
2047 if (unlikely(Rc(ctx->opcode) != 0))
2048 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2049 }
2050 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2051 {
2052 gen_sradi(ctx, 0);
2053 }
2054 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2055 {
2056 gen_sradi(ctx, 1);
2057 }
2058 /* srd & srd. */
2059 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2060 {
2061 TCGv t0;
2062 int l1, l2;
2063 l1 = gen_new_label();
2064 l2 = gen_new_label();
2065
2066 t0 = tcg_temp_local_new();
2067 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2068 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2069 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2070 tcg_gen_br(l2);
2071 gen_set_label(l1);
2072 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2073 gen_set_label(l2);
2074 tcg_temp_free(t0);
2075 if (unlikely(Rc(ctx->opcode) != 0))
2076 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2077 }
2078 #endif
2079
2080 /*** Floating-Point arithmetic ***/
2081 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2082 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2083 { \
2084 if (unlikely(!ctx->fpu_enabled)) { \
2085 gen_exception(ctx, POWERPC_EXCP_FPU); \
2086 return; \
2087 } \
2088 /* NIP cannot be restored if the memory exception comes from an helper */ \
2089 gen_update_nip(ctx, ctx->nip - 4); \
2090 gen_reset_fpstatus(); \
2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2093 if (isfloat) { \
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2095 } \
2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2097 Rc(ctx->opcode) != 0); \
2098 }
2099
2100 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2101 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2102 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2103
2104 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2105 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2106 { \
2107 if (unlikely(!ctx->fpu_enabled)) { \
2108 gen_exception(ctx, POWERPC_EXCP_FPU); \
2109 return; \
2110 } \
2111 /* NIP cannot be restored if the memory exception comes from an helper */ \
2112 gen_update_nip(ctx, ctx->nip - 4); \
2113 gen_reset_fpstatus(); \
2114 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2115 cpu_fpr[rB(ctx->opcode)]); \
2116 if (isfloat) { \
2117 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2118 } \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2120 set_fprf, Rc(ctx->opcode) != 0); \
2121 }
2122 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2123 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2124 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2125
2126 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2127 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2128 { \
2129 if (unlikely(!ctx->fpu_enabled)) { \
2130 gen_exception(ctx, POWERPC_EXCP_FPU); \
2131 return; \
2132 } \
2133 /* NIP cannot be restored if the memory exception comes from an helper */ \
2134 gen_update_nip(ctx, ctx->nip - 4); \
2135 gen_reset_fpstatus(); \
2136 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2137 cpu_fpr[rC(ctx->opcode)]); \
2138 if (isfloat) { \
2139 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2140 } \
2141 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2142 set_fprf, Rc(ctx->opcode) != 0); \
2143 }
2144 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2145 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2146 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2147
2148 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2149 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2150 { \
2151 if (unlikely(!ctx->fpu_enabled)) { \
2152 gen_exception(ctx, POWERPC_EXCP_FPU); \
2153 return; \
2154 } \
2155 /* NIP cannot be restored if the memory exception comes from an helper */ \
2156 gen_update_nip(ctx, ctx->nip - 4); \
2157 gen_reset_fpstatus(); \
2158 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2159 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2160 set_fprf, Rc(ctx->opcode) != 0); \
2161 }
2162
2163 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2164 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2165 { \
2166 if (unlikely(!ctx->fpu_enabled)) { \
2167 gen_exception(ctx, POWERPC_EXCP_FPU); \
2168 return; \
2169 } \
2170 /* NIP cannot be restored if the memory exception comes from an helper */ \
2171 gen_update_nip(ctx, ctx->nip - 4); \
2172 gen_reset_fpstatus(); \
2173 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2174 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2175 set_fprf, Rc(ctx->opcode) != 0); \
2176 }
2177
2178 /* fadd - fadds */
2179 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2180 /* fdiv - fdivs */
2181 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2182 /* fmul - fmuls */
2183 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2184
2185 /* fre */
2186 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2187
2188 /* fres */
2189 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2190
2191 /* frsqrte */
2192 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2193
2194 /* frsqrtes */
2195 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2196 {
2197 if (unlikely(!ctx->fpu_enabled)) {
2198 gen_exception(ctx, POWERPC_EXCP_FPU);
2199 return;
2200 }
2201 /* NIP cannot be restored if the memory exception comes from an helper */
2202 gen_update_nip(ctx, ctx->nip - 4);
2203 gen_reset_fpstatus();
2204 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2205 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2207 }
2208
2209 /* fsel */
2210 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2211 /* fsub - fsubs */
2212 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2213 /* Optional: */
2214 /* fsqrt */
2215 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2216 {
2217 if (unlikely(!ctx->fpu_enabled)) {
2218 gen_exception(ctx, POWERPC_EXCP_FPU);
2219 return;
2220 }
2221 /* NIP cannot be restored if the memory exception comes from an helper */
2222 gen_update_nip(ctx, ctx->nip - 4);
2223 gen_reset_fpstatus();
2224 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2225 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2226 }
2227
2228 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2229 {
2230 if (unlikely(!ctx->fpu_enabled)) {
2231 gen_exception(ctx, POWERPC_EXCP_FPU);
2232 return;
2233 }
2234 /* NIP cannot be restored if the memory exception comes from an helper */
2235 gen_update_nip(ctx, ctx->nip - 4);
2236 gen_reset_fpstatus();
2237 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2238 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2239 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2240 }
2241
2242 /*** Floating-Point multiply-and-add ***/
2243 /* fmadd - fmadds */
2244 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2245 /* fmsub - fmsubs */
2246 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2247 /* fnmadd - fnmadds */
2248 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2249 /* fnmsub - fnmsubs */
2250 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2251
2252 /*** Floating-Point round & convert ***/
2253 /* fctiw */
2254 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2255 /* fctiwz */
2256 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2257 /* frsp */
2258 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2259 #if defined(TARGET_PPC64)
2260 /* fcfid */
2261 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2262 /* fctid */
2263 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2264 /* fctidz */
2265 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2266 #endif
2267
2268 /* frin */
2269 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2270 /* friz */
2271 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2272 /* frip */
2273 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2274 /* frim */
2275 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2276
2277 /*** Floating-Point compare ***/
2278 /* fcmpo */
2279 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2280 {
2281 TCGv_i32 crf;
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 /* NIP cannot be restored if the memory exception comes from an helper */
2287 gen_update_nip(ctx, ctx->nip - 4);
2288 gen_reset_fpstatus();
2289 crf = tcg_const_i32(crfD(ctx->opcode));
2290 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2291 tcg_temp_free_i32(crf);
2292 gen_helper_float_check_status();
2293 }
2294
2295 /* fcmpu */
2296 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2297 {
2298 TCGv_i32 crf;
2299 if (unlikely(!ctx->fpu_enabled)) {
2300 gen_exception(ctx, POWERPC_EXCP_FPU);
2301 return;
2302 }
2303 /* NIP cannot be restored if the memory exception comes from an helper */
2304 gen_update_nip(ctx, ctx->nip - 4);
2305 gen_reset_fpstatus();
2306 crf = tcg_const_i32(crfD(ctx->opcode));
2307 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2308 tcg_temp_free_i32(crf);
2309 gen_helper_float_check_status();
2310 }
2311
2312 /*** Floating-point move ***/
2313 /* fabs */
2314 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2315 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2316
2317 /* fmr - fmr. */
2318 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2319 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2320 {
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 gen_exception(ctx, POWERPC_EXCP_FPU);
2323 return;
2324 }
2325 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2326 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2327 }
2328
2329 /* fnabs */
2330 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2331 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2332 /* fneg */
2333 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2334 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2335
2336 /*** Floating-Point status & ctrl register ***/
2337 /* mcrfs */
2338 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2339 {
2340 int bfa;
2341
2342 if (unlikely(!ctx->fpu_enabled)) {
2343 gen_exception(ctx, POWERPC_EXCP_FPU);
2344 return;
2345 }
2346 bfa = 4 * (7 - crfS(ctx->opcode));
2347 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2348 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2349 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2350 }
2351
2352 /* mffs */
2353 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2354 {
2355 if (unlikely(!ctx->fpu_enabled)) {
2356 gen_exception(ctx, POWERPC_EXCP_FPU);
2357 return;
2358 }
2359 gen_reset_fpstatus();
2360 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2361 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2362 }
2363
2364 /* mtfsb0 */
2365 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2366 {
2367 uint8_t crb;
2368
2369 if (unlikely(!ctx->fpu_enabled)) {
2370 gen_exception(ctx, POWERPC_EXCP_FPU);
2371 return;
2372 }
2373 crb = 31 - crbD(ctx->opcode);
2374 gen_reset_fpstatus();
2375 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2376 TCGv_i32 t0;
2377 /* NIP cannot be restored if the memory exception comes from an helper */
2378 gen_update_nip(ctx, ctx->nip - 4);
2379 t0 = tcg_const_i32(crb);
2380 gen_helper_fpscr_clrbit(t0);
2381 tcg_temp_free_i32(t0);
2382 }
2383 if (unlikely(Rc(ctx->opcode) != 0)) {
2384 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2385 }
2386 }
2387
2388 /* mtfsb1 */
2389 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2390 {
2391 uint8_t crb;
2392
2393 if (unlikely(!ctx->fpu_enabled)) {
2394 gen_exception(ctx, POWERPC_EXCP_FPU);
2395 return;
2396 }
2397 crb = 31 - crbD(ctx->opcode);
2398 gen_reset_fpstatus();
2399 /* XXX: we pretend we can only do IEEE floating-point computations */
2400 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2401 TCGv_i32 t0;
2402 /* NIP cannot be restored if the memory exception comes from an helper */
2403 gen_update_nip(ctx, ctx->nip - 4);
2404 t0 = tcg_const_i32(crb);
2405 gen_helper_fpscr_setbit(t0);
2406 tcg_temp_free_i32(t0);
2407 }
2408 if (unlikely(Rc(ctx->opcode) != 0)) {
2409 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2410 }
2411 /* We can raise a differed exception */
2412 gen_helper_float_check_status();
2413 }
2414
2415 /* mtfsf */
2416 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2417 {
2418 TCGv_i32 t0;
2419
2420 if (unlikely(!ctx->fpu_enabled)) {
2421 gen_exception(ctx, POWERPC_EXCP_FPU);
2422 return;
2423 }
2424 /* NIP cannot be restored if the memory exception comes from an helper */
2425 gen_update_nip(ctx, ctx->nip - 4);
2426 gen_reset_fpstatus();
2427 t0 = tcg_const_i32(FM(ctx->opcode));
2428 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2429 tcg_temp_free_i32(t0);
2430 if (unlikely(Rc(ctx->opcode) != 0)) {
2431 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2432 }
2433 /* We can raise a differed exception */
2434 gen_helper_float_check_status();
2435 }
2436
2437 /* mtfsfi */
2438 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2439 {
2440 int bf, sh;
2441 TCGv_i64 t0;
2442 TCGv_i32 t1;
2443
2444 if (unlikely(!ctx->fpu_enabled)) {
2445 gen_exception(ctx, POWERPC_EXCP_FPU);
2446 return;
2447 }
2448 bf = crbD(ctx->opcode) >> 2;
2449 sh = 7 - bf;
2450 /* NIP cannot be restored if the memory exception comes from an helper */
2451 gen_update_nip(ctx, ctx->nip - 4);
2452 gen_reset_fpstatus();
2453 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2454 t1 = tcg_const_i32(1 << sh);
2455 gen_helper_store_fpscr(t0, t1);
2456 tcg_temp_free_i64(t0);
2457 tcg_temp_free_i32(t1);
2458 if (unlikely(Rc(ctx->opcode) != 0)) {
2459 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2460 }
2461 /* We can raise a differed exception */
2462 gen_helper_float_check_status();
2463 }
2464
2465 /*** Addressing modes ***/
2466 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2467 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2468 {
2469 target_long simm = SIMM(ctx->opcode);
2470
2471 simm &= ~maskl;
2472 if (rA(ctx->opcode) == 0) {
2473 #if defined(TARGET_PPC64)
2474 if (!ctx->sf_mode) {
2475 tcg_gen_movi_tl(EA, (uint32_t)simm);
2476 } else
2477 #endif
2478 tcg_gen_movi_tl(EA, simm);
2479 } else if (likely(simm != 0)) {
2480 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2481 #if defined(TARGET_PPC64)
2482 if (!ctx->sf_mode) {
2483 tcg_gen_ext32u_tl(EA, EA);
2484 }
2485 #endif
2486 } else {
2487 #if defined(TARGET_PPC64)
2488 if (!ctx->sf_mode) {
2489 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2490 } else
2491 #endif
2492 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2493 }
2494 }
2495
2496 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2497 {
2498 if (rA(ctx->opcode) == 0) {
2499 #if defined(TARGET_PPC64)
2500 if (!ctx->sf_mode) {
2501 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2502 } else
2503 #endif
2504 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2505 } else {
2506 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2507 #if defined(TARGET_PPC64)
2508 if (!ctx->sf_mode) {
2509 tcg_gen_ext32u_tl(EA, EA);
2510 }
2511 #endif
2512 }
2513 }
2514
2515 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2516 {
2517 if (rA(ctx->opcode) == 0) {
2518 tcg_gen_movi_tl(EA, 0);
2519 } else {
2520 #if defined(TARGET_PPC64)
2521 if (!ctx->sf_mode) {
2522 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2523 } else
2524 #endif
2525 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2526 }
2527 }
2528
2529 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2530 {
2531 tcg_gen_addi_tl(ret, arg1, val);
2532 #if defined(TARGET_PPC64)
2533 if (!ctx->sf_mode) {
2534 tcg_gen_ext32u_tl(ret, ret);
2535 }
2536 #endif
2537 }
2538
2539 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2540 {
2541 int l1 = gen_new_label();
2542 TCGv t0 = tcg_temp_new();
2543 TCGv_i32 t1, t2;
2544 /* NIP cannot be restored if the memory exception comes from an helper */
2545 gen_update_nip(ctx, ctx->nip - 4);
2546 tcg_gen_andi_tl(t0, EA, mask);
2547 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2548 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2549 t2 = tcg_const_i32(0);
2550 gen_helper_raise_exception_err(t1, t2);
2551 tcg_temp_free_i32(t1);
2552 tcg_temp_free_i32(t2);
2553 gen_set_label(l1);
2554 tcg_temp_free(t0);
2555 }
2556
2557 /*** Integer load ***/
2558 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2559 {
2560 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2561 }
2562
2563 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2564 {
2565 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2566 }
2567
2568 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569 {
2570 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2571 if (unlikely(ctx->le_mode)) {
2572 #if defined(TARGET_PPC64)
2573 TCGv_i32 t0 = tcg_temp_new_i32();
2574 tcg_gen_trunc_tl_i32(t0, arg1);
2575 tcg_gen_bswap16_i32(t0, t0);
2576 tcg_gen_extu_i32_tl(arg1, t0);
2577 tcg_temp_free_i32(t0);
2578 #else
2579 tcg_gen_bswap16_i32(arg1, arg1);
2580 #endif
2581 }
2582 }
2583
2584 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2585 {
2586 if (unlikely(ctx->le_mode)) {
2587 #if defined(TARGET_PPC64)
2588 TCGv_i32 t0;
2589 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2590 t0 = tcg_temp_new_i32();
2591 tcg_gen_trunc_tl_i32(t0, arg1);
2592 tcg_gen_bswap16_i32(t0, t0);
2593 tcg_gen_extu_i32_tl(arg1, t0);
2594 tcg_gen_ext16s_tl(arg1, arg1);
2595 tcg_temp_free_i32(t0);
2596 #else
2597 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2598 tcg_gen_bswap16_i32(arg1, arg1);
2599 tcg_gen_ext16s_i32(arg1, arg1);
2600 #endif
2601 } else {
2602 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2603 }
2604 }
2605
2606 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2607 {
2608 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2609 if (unlikely(ctx->le_mode)) {
2610 #if defined(TARGET_PPC64)
2611 TCGv_i32 t0 = tcg_temp_new_i32();
2612 tcg_gen_trunc_tl_i32(t0, arg1);
2613 tcg_gen_bswap_i32(t0, t0);
2614 tcg_gen_extu_i32_tl(arg1, t0);
2615 tcg_temp_free_i32(t0);
2616 #else
2617 tcg_gen_bswap_i32(arg1, arg1);
2618 #endif
2619 }
2620 }
2621
2622 #if defined(TARGET_PPC64)
2623 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2624 {
2625 if (unlikely(ctx->mem_idx)) {
2626 TCGv_i32 t0;
2627 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2628 t0 = tcg_temp_new_i32();
2629 tcg_gen_trunc_tl_i32(t0, arg1);
2630 tcg_gen_bswap_i32(t0, t0);
2631 tcg_gen_ext_i32_tl(arg1, t0);
2632 tcg_temp_free_i32(t0);
2633 } else
2634 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2635 }
2636 #endif
2637
2638 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2639 {
2640 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2641 if (unlikely(ctx->le_mode)) {
2642 tcg_gen_bswap_i64(arg1, arg1);
2643 }
2644 }
2645
2646 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2647 {
2648 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2649 }
2650
2651 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2652 {
2653 if (unlikely(ctx->le_mode)) {
2654 #if defined(TARGET_PPC64)
2655 TCGv_i32 t0;
2656 TCGv t1;
2657 t0 = tcg_temp_new_i32();
2658 tcg_gen_trunc_tl_i32(t0, arg1);
2659 tcg_gen_ext16u_i32(t0, t0);
2660 tcg_gen_bswap16_i32(t0, t0);
2661 t1 = tcg_temp_new();
2662 tcg_gen_extu_i32_tl(t1, t0);
2663 tcg_temp_free_i32(t0);
2664 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2665 tcg_temp_free(t1);
2666 #else
2667 TCGv t0 = tcg_temp_new();
2668 tcg_gen_ext16u_tl(t0, arg1);
2669 tcg_gen_bswap16_i32(t0, t0);
2670 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2671 tcg_temp_free(t0);
2672 #endif
2673 } else {
2674 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2675 }
2676 }
2677
2678 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2679 {
2680 if (unlikely(ctx->le_mode)) {
2681 #if defined(TARGET_PPC64)
2682 TCGv_i32 t0;
2683 TCGv t1;
2684 t0 = tcg_temp_new_i32();
2685 tcg_gen_trunc_tl_i32(t0, arg1);
2686 tcg_gen_bswap_i32(t0, t0);
2687 t1 = tcg_temp_new();
2688 tcg_gen_extu_i32_tl(t1, t0);
2689 tcg_temp_free_i32(t0);
2690 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2691 tcg_temp_free(t1);
2692 #else
2693 TCGv t0 = tcg_temp_new_i32();
2694 tcg_gen_bswap_i32(t0, arg1);
2695 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2696 tcg_temp_free(t0);
2697 #endif
2698 } else {
2699 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2700 }
2701 }
2702
2703 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2704 {
2705 if (unlikely(ctx->le_mode)) {
2706 TCGv_i64 t0 = tcg_temp_new_i64();
2707 tcg_gen_bswap_i64(t0, arg1);
2708 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2709 tcg_temp_free_i64(t0);
2710 } else
2711 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2712 }
2713
2714 #define GEN_LD(name, ldop, opc, type) \
2715 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2716 { \
2717 TCGv EA; \
2718 gen_set_access_type(ctx, ACCESS_INT); \
2719 EA = tcg_temp_new(); \
2720 gen_addr_imm_index(ctx, EA, 0); \
2721 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2722 tcg_temp_free(EA); \
2723 }
2724
2725 #define GEN_LDU(name, ldop, opc, type) \
2726 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2727 { \
2728 TCGv EA; \
2729 if (unlikely(rA(ctx->opcode) == 0 || \
2730 rA(ctx->opcode) == rD(ctx->opcode))) { \
2731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2732 return; \
2733 } \
2734 gen_set_access_type(ctx, ACCESS_INT); \
2735 EA = tcg_temp_new(); \
2736 if (type == PPC_64B) \
2737 gen_addr_imm_index(ctx, EA, 0x03); \
2738 else \
2739 gen_addr_imm_index(ctx, EA, 0); \
2740 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2742 tcg_temp_free(EA); \
2743 }
2744
2745 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2746 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2747 { \
2748 TCGv EA; \
2749 if (unlikely(rA(ctx->opcode) == 0 || \
2750 rA(ctx->opcode) == rD(ctx->opcode))) { \
2751 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2752 return; \
2753 } \
2754 gen_set_access_type(ctx, ACCESS_INT); \
2755 EA = tcg_temp_new(); \
2756 gen_addr_reg_index(ctx, EA); \
2757 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2758 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2759 tcg_temp_free(EA); \
2760 }
2761
2762 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2763 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2764 { \
2765 TCGv EA; \
2766 gen_set_access_type(ctx, ACCESS_INT); \
2767 EA = tcg_temp_new(); \
2768 gen_addr_reg_index(ctx, EA); \
2769 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDS(name, ldop, op, type) \
2774 GEN_LD(name, ldop, op | 0x20, type); \
2775 GEN_LDU(name, ldop, op | 0x21, type); \
2776 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2777 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2778
2779 /* lbz lbzu lbzux lbzx */
2780 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2781 /* lha lhau lhaux lhax */
2782 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2783 /* lhz lhzu lhzux lhzx */
2784 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2785 /* lwz lwzu lwzux lwzx */
2786 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2787 #if defined(TARGET_PPC64)
2788 /* lwaux */
2789 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2790 /* lwax */
2791 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2792 /* ldux */
2793 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2794 /* ldx */
2795 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2796 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2797 {
2798 TCGv EA;
2799 if (Rc(ctx->opcode)) {
2800 if (unlikely(rA(ctx->opcode) == 0 ||
2801 rA(ctx->opcode) == rD(ctx->opcode))) {
2802 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2803 return;
2804 }
2805 }
2806 gen_set_access_type(ctx, ACCESS_INT);
2807 EA = tcg_temp_new();
2808 gen_addr_imm_index(ctx, EA, 0x03);
2809 if (ctx->opcode & 0x02) {
2810 /* lwa (lwau is undefined) */
2811 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2812 } else {
2813 /* ld - ldu */
2814 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2815 }
2816 if (Rc(ctx->opcode))
2817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2818 tcg_temp_free(EA);
2819 }
2820 /* lq */
2821 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2822 {
2823 #if defined(CONFIG_USER_ONLY)
2824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2825 #else
2826 int ra, rd;
2827 TCGv EA;
2828
2829 /* Restore CPU state */
2830 if (unlikely(ctx->mem_idx == 0)) {
2831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2832 return;
2833 }
2834 ra = rA(ctx->opcode);
2835 rd = rD(ctx->opcode);
2836 if (unlikely((rd & 1) || rd == ra)) {
2837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2838 return;
2839 }
2840 if (unlikely(ctx->le_mode)) {
2841 /* Little-endian mode is not handled */
2842 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2843 return;
2844 }
2845 gen_set_access_type(ctx, ACCESS_INT);
2846 EA = tcg_temp_new();
2847 gen_addr_imm_index(ctx, EA, 0x0F);
2848 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2849 gen_addr_add(ctx, EA, EA, 8);
2850 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2851 tcg_temp_free(EA);
2852 #endif
2853 }
2854 #endif
2855
2856 /*** Integer store ***/
2857 #define GEN_ST(name, stop, opc, type) \
2858 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2859 { \
2860 TCGv EA; \
2861 gen_set_access_type(ctx, ACCESS_INT); \
2862 EA = tcg_temp_new(); \
2863 gen_addr_imm_index(ctx, EA, 0); \
2864 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2865 tcg_temp_free(EA); \
2866 }
2867
2868 #define GEN_STU(name, stop, opc, type) \
2869 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2870 { \
2871 TCGv EA; \
2872 if (unlikely(rA(ctx->opcode) == 0)) { \
2873 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2874 return; \
2875 } \
2876 gen_set_access_type(ctx, ACCESS_INT); \
2877 EA = tcg_temp_new(); \
2878 if (type == PPC_64B) \
2879 gen_addr_imm_index(ctx, EA, 0x03); \
2880 else \
2881 gen_addr_imm_index(ctx, EA, 0); \
2882 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2883 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2884 tcg_temp_free(EA); \
2885 }
2886
2887 #define GEN_STUX(name, stop, opc2, opc3, type) \
2888 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2889 { \
2890 TCGv EA; \
2891 if (unlikely(rA(ctx->opcode) == 0)) { \
2892 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2893 return; \
2894 } \
2895 gen_set_access_type(ctx, ACCESS_INT); \
2896 EA = tcg_temp_new(); \
2897 gen_addr_reg_index(ctx, EA); \
2898 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2899 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2900 tcg_temp_free(EA); \
2901 }
2902
2903 #define GEN_STX(name, stop, opc2, opc3, type) \
2904 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2905 { \
2906 TCGv EA; \
2907 gen_set_access_type(ctx, ACCESS_INT); \
2908 EA = tcg_temp_new(); \
2909 gen_addr_reg_index(ctx, EA); \
2910 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2911 tcg_temp_free(EA); \
2912 }
2913
2914 #define GEN_STS(name, stop, op, type) \
2915 GEN_ST(name, stop, op | 0x20, type); \
2916 GEN_STU(name, stop, op | 0x21, type); \
2917 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2918 GEN_STX(name, stop, 0x17, op | 0x00, type)
2919
2920 /* stb stbu stbux stbx */
2921 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2922 /* sth sthu sthux sthx */
2923 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2924 /* stw stwu stwux stwx */
2925 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2926 #if defined(TARGET_PPC64)
2927 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2928 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2929 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2930 {
2931 int rs;
2932 TCGv EA;
2933
2934 rs = rS(ctx->opcode);
2935 if ((ctx->opcode & 0x3) == 0x2) {
2936 #if defined(CONFIG_USER_ONLY)
2937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2938 #else
2939 /* stq */
2940 if (unlikely(ctx->mem_idx == 0)) {
2941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2942 return;
2943 }
2944 if (unlikely(rs & 1)) {
2945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2946 return;
2947 }
2948 if (unlikely(ctx->le_mode)) {
2949 /* Little-endian mode is not handled */
2950 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2951 return;
2952 }
2953 gen_set_access_type(ctx, ACCESS_INT);
2954 EA = tcg_temp_new();
2955 gen_addr_imm_index(ctx, EA, 0x03);
2956 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2957 gen_addr_add(ctx, EA, EA, 8);
2958 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2959 tcg_temp_free(EA);
2960 #endif
2961 } else {
2962 /* std / stdu */
2963 if (Rc(ctx->opcode)) {
2964 if (unlikely(rA(ctx->opcode) == 0)) {
2965 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2966 return;
2967 }
2968 }
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 EA = tcg_temp_new();
2971 gen_addr_imm_index(ctx, EA, 0x03);
2972 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2973 if (Rc(ctx->opcode))
2974 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2975 tcg_temp_free(EA);
2976 }
2977 }
2978 #endif
2979 /*** Integer load and store with byte reverse ***/
2980 /* lhbrx */
2981 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2982 {
2983 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2984 if (likely(!ctx->le_mode)) {
2985 #if defined(TARGET_PPC64)
2986 TCGv_i32 t0 = tcg_temp_new_i32();
2987 tcg_gen_trunc_tl_i32(t0, arg1);
2988 tcg_gen_bswap16_i32(t0, t0);
2989 tcg_gen_extu_i32_tl(arg1, t0);
2990 tcg_temp_free_i32(t0);
2991 #else
2992 tcg_gen_bswap16_i32(arg1, arg1);
2993 #endif
2994 }
2995 }
2996 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2997
2998 /* lwbrx */
2999 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3000 {
3001 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3002 if (likely(!ctx->le_mode)) {
3003 #if defined(TARGET_PPC64)
3004 TCGv_i32 t0 = tcg_temp_new_i32();
3005 tcg_gen_trunc_tl_i32(t0, arg1);
3006 tcg_gen_bswap_i32(t0, t0);
3007 tcg_gen_extu_i32_tl(arg1, t0);
3008 tcg_temp_free_i32(t0);
3009 #else
3010 tcg_gen_bswap_i32(arg1, arg1);
3011 #endif
3012 }
3013 }
3014 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3015
3016 /* sthbrx */
3017 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3018 {
3019 if (likely(!ctx->le_mode)) {
3020 #if defined(TARGET_PPC64)
3021 TCGv_i32 t0;
3022 TCGv t1;
3023 t0 = tcg_temp_new_i32();
3024 tcg_gen_trunc_tl_i32(t0, arg1);
3025 tcg_gen_ext16u_i32(t0, t0);
3026 tcg_gen_bswap16_i32(t0, t0);
3027 t1 = tcg_temp_new();
3028 tcg_gen_extu_i32_tl(t1, t0);
3029 tcg_temp_free_i32(t0);
3030 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3031 tcg_temp_free(t1);
3032 #else
3033 TCGv t0 = tcg_temp_new();
3034 tcg_gen_ext16u_tl(t0, arg1);
3035 tcg_gen_bswap16_i32(t0, t0);
3036 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3037 tcg_temp_free(t0);
3038 #endif
3039 } else {
3040 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3041 }
3042 }
3043 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3044
3045 /* stwbrx */
3046 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3047 {
3048 if (likely(!ctx->le_mode)) {
3049 #if defined(TARGET_PPC64)
3050 TCGv_i32 t0;
3051 TCGv t1;
3052 t0 = tcg_temp_new_i32();
3053 tcg_gen_trunc_tl_i32(t0, arg1);
3054 tcg_gen_bswap_i32(t0, t0);
3055 t1 = tcg_temp_new();
3056 tcg_gen_extu_i32_tl(t1, t0);
3057 tcg_temp_free_i32(t0);
3058 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3059 tcg_temp_free(t1);
3060 #else
3061 TCGv t0 = tcg_temp_new_i32();
3062 tcg_gen_bswap_i32(t0, arg1);
3063 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3064 tcg_temp_free(t0);
3065 #endif
3066 } else {
3067 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3068 }
3069 }
3070 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3071
3072 /*** Integer load and store multiple ***/
3073 /* lmw */
3074 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3075 {
3076 TCGv t0;
3077 TCGv_i32 t1;
3078 gen_set_access_type(ctx, ACCESS_INT);
3079 /* NIP cannot be restored if the memory exception comes from an helper */
3080 gen_update_nip(ctx, ctx->nip - 4);
3081 t0 = tcg_temp_new();
3082 t1 = tcg_const_i32(rD(ctx->opcode));
3083 gen_addr_imm_index(ctx, t0, 0);
3084 gen_helper_lmw(t0, t1);
3085 tcg_temp_free(t0);
3086 tcg_temp_free_i32(t1);
3087 }
3088
3089 /* stmw */
3090 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3091 {
3092 TCGv t0;
3093 TCGv_i32 t1;
3094 gen_set_access_type(ctx, ACCESS_INT);
3095 /* NIP cannot be restored if the memory exception comes from an helper */
3096 gen_update_nip(ctx, ctx->nip - 4);
3097 t0 = tcg_temp_new();
3098 t1 = tcg_const_i32(rS(ctx->opcode));
3099 gen_addr_imm_index(ctx, t0, 0);
3100 gen_helper_stmw(t0, t1);
3101 tcg_temp_free(t0);
3102 tcg_temp_free_i32(t1);
3103 }
3104
3105 /*** Integer load and store strings ***/
3106 /* lswi */
3107 /* PowerPC32 specification says we must generate an exception if
3108 * rA is in the range of registers to be loaded.
3109 * In an other hand, IBM says this is valid, but rA won't be loaded.
3110 * For now, I'll follow the spec...
3111 */
3112 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3113 {
3114 TCGv t0;
3115 TCGv_i32 t1, t2;
3116 int nb = NB(ctx->opcode);
3117 int start = rD(ctx->opcode);
3118 int ra = rA(ctx->opcode);
3119 int nr;
3120
3121 if (nb == 0)
3122 nb = 32;
3123 nr = nb / 4;
3124 if (unlikely(((start + nr) > 32 &&
3125 start <= ra && (start + nr - 32) > ra) ||
3126 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3127 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3128 return;
3129 }
3130 gen_set_access_type(ctx, ACCESS_INT);
3131 /* NIP cannot be restored if the memory exception comes from an helper */
3132 gen_update_nip(ctx, ctx->nip - 4);
3133 t0 = tcg_temp_new();
3134 gen_addr_register(ctx, t0);
3135 t1 = tcg_const_i32(nb);
3136 t2 = tcg_const_i32(start);
3137 gen_helper_lsw(t0, t1, t2);
3138 tcg_temp_free(t0);
3139 tcg_temp_free_i32(t1);
3140 tcg_temp_free_i32(t2);
3141 }
3142
3143 /* lswx */
3144 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3145 {
3146 TCGv t0;
3147 TCGv_i32 t1, t2, t3;
3148 gen_set_access_type(ctx, ACCESS_INT);
3149 /* NIP cannot be restored if the memory exception comes from an helper */
3150 gen_update_nip(ctx, ctx->nip - 4);
3151 t0 = tcg_temp_new();
3152 gen_addr_reg_index(ctx, t0);
3153 t1 = tcg_const_i32(rD(ctx->opcode));
3154 t2 = tcg_const_i32(rA(ctx->opcode));
3155 t3 = tcg_const_i32(rB(ctx->opcode));
3156 gen_helper_lswx(t0, t1, t2, t3);
3157 tcg_temp_free(t0);
3158 tcg_temp_free_i32(t1);
3159 tcg_temp_free_i32(t2);
3160 tcg_temp_free_i32(t3);
3161 }
3162
3163 /* stswi */
3164 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3165 {
3166 TCGv t0;
3167 TCGv_i32 t1, t2;
3168 int nb = NB(ctx->opcode);
3169 gen_set_access_type(ctx, ACCESS_INT);
3170 /* NIP cannot be restored if the memory exception comes from an helper */
3171 gen_update_nip(ctx, ctx->nip - 4);
3172 t0 = tcg_temp_new();
3173 gen_addr_register(ctx, t0);
3174 if (nb == 0)
3175 nb = 32;
3176 t1 = tcg_const_i32(nb);
3177 t2 = tcg_const_i32(rS(ctx->opcode));
3178 gen_helper_stsw(t0, t1, t2);
3179 tcg_temp_free(t0);
3180 tcg_temp_free_i32(t1);
3181 tcg_temp_free_i32(t2);
3182 }
3183
3184 /* stswx */
3185 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3186 {
3187 TCGv t0;
3188 TCGv_i32 t1, t2;
3189 gen_set_access_type(ctx, ACCESS_INT);
3190 /* NIP cannot be restored if the memory exception comes from an helper */
3191 gen_update_nip(ctx, ctx->nip - 4);
3192 t0 = tcg_temp_new();
3193 gen_addr_reg_index(ctx, t0);
3194 t1 = tcg_temp_new_i32();
3195 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3196 tcg_gen_andi_i32(t1, t1, 0x7F);
3197 t2 = tcg_const_i32(rS(ctx->opcode));
3198 gen_helper_stsw(t0, t1, t2);
3199 tcg_temp_free(t0);
3200 tcg_temp_free_i32(t1);
3201 tcg_temp_free_i32(t2);
3202 }
3203
3204 /*** Memory synchronisation ***/
3205 /* eieio */
3206 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3207 {
3208 }
3209
3210 /* isync */
3211 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3212 {
3213 gen_stop_exception(ctx);
3214 }
3215
3216 /* lwarx */
3217 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3218 {
3219 TCGv t0;
3220 gen_set_access_type(ctx, ACCESS_RES);
3221 t0 = tcg_temp_local_new();
3222 gen_addr_reg_index(ctx, t0);
3223 gen_check_align(ctx, t0, 0x03);
3224 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3225 tcg_gen_mov_tl(cpu_reserve, t0);
3226 tcg_temp_free(t0);
3227 }
3228
3229 /* stwcx. */
3230 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3231 {
3232 int l1;
3233 TCGv t0;
3234 gen_set_access_type(ctx, ACCESS_RES);
3235 t0 = tcg_temp_local_new();
3236 gen_addr_reg_index(ctx, t0);
3237 gen_check_align(ctx, t0, 0x03);
3238 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3239 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3240 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3241 l1 = gen_new_label();
3242 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3243 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3244 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3245 gen_set_label(l1);
3246 tcg_gen_movi_tl(cpu_reserve, -1);
3247 tcg_temp_free(t0);
3248 }
3249
3250 #if defined(TARGET_PPC64)
3251 /* ldarx */
3252 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3253 {
3254 TCGv t0;
3255 gen_set_access_type(ctx, ACCESS_RES);
3256 t0 = tcg_temp_local_new();
3257 gen_addr_reg_index(ctx, t0);
3258 gen_check_align(ctx, t0, 0x07);
3259 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3260 tcg_gen_mov_tl(cpu_reserve, t0);
3261 tcg_temp_free(t0);
3262 }
3263
3264 /* stdcx. */
3265 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3266 {
3267 int l1;
3268 TCGv t0;
3269 gen_set_access_type(ctx, ACCESS_RES);
3270 t0 = tcg_temp_local_new();
3271 gen_addr_reg_index(ctx, t0);
3272 gen_check_align(ctx, t0, 0x07);
3273 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3274 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3275 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3276 l1 = gen_new_label();
3277 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3278 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3279 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3280 gen_set_label(l1);
3281 tcg_gen_movi_tl(cpu_reserve, -1);
3282 tcg_temp_free(t0);
3283 }
3284 #endif /* defined(TARGET_PPC64) */
3285
3286 /* sync */
3287 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3288 {
3289 }
3290
3291 /* wait */
3292 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3293 {
3294 TCGv_i32 t0 = tcg_temp_new_i32();
3295 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3296 tcg_temp_free_i32(t0);
3297 /* Stop translation, as the CPU is supposed to sleep from now */
3298 gen_exception_err(ctx, EXCP_HLT, 1);
3299 }
3300
3301 /*** Floating-point load ***/
3302 #define GEN_LDF(name, ldop, opc, type) \
3303 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3304 { \
3305 TCGv EA; \
3306 if (unlikely(!ctx->fpu_enabled)) { \
3307 gen_exception(ctx, POWERPC_EXCP_FPU); \
3308 return; \
3309 } \
3310 gen_set_access_type(ctx, ACCESS_FLOAT); \
3311 EA = tcg_temp_new(); \
3312 gen_addr_imm_index(ctx, EA, 0); \
3313 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3314 tcg_temp_free(EA); \
3315 }
3316
3317 #define GEN_LDUF(name, ldop, opc, type) \
3318 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3319 { \
3320 TCGv EA; \
3321 if (unlikely(!ctx->fpu_enabled)) { \
3322 gen_exception(ctx, POWERPC_EXCP_FPU); \
3323 return; \
3324 } \
3325 if (unlikely(rA(ctx->opcode) == 0)) { \
3326 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3327 return; \
3328 } \
3329 gen_set_access_type(ctx, ACCESS_FLOAT); \
3330 EA = tcg_temp_new(); \
3331 gen_addr_imm_index(ctx, EA, 0); \
3332 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3333 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3334 tcg_temp_free(EA); \
3335 }
3336
3337 #define GEN_LDUXF(name, ldop, opc, type) \
3338 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3339 { \
3340 TCGv EA; \
3341 if (unlikely(!ctx->fpu_enabled)) { \
3342 gen_exception(ctx, POWERPC_EXCP_FPU); \
3343 return; \
3344 } \
3345 if (unlikely(rA(ctx->opcode) == 0)) { \
3346 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3347 return; \
3348 } \
3349 gen_set_access_type(ctx, ACCESS_FLOAT); \
3350 EA = tcg_temp_new(); \
3351 gen_addr_reg_index(ctx, EA); \
3352 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3353 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3354 tcg_temp_free(EA); \
3355 }
3356
3357 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3358 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3359 { \
3360 TCGv EA; \
3361 if (unlikely(!ctx->fpu_enabled)) { \
3362 gen_exception(ctx, POWERPC_EXCP_FPU); \
3363 return; \
3364 } \
3365 gen_set_access_type(ctx, ACCESS_FLOAT); \
3366 EA = tcg_temp_new(); \
3367 gen_addr_reg_index(ctx, EA); \
3368 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3369 tcg_temp_free(EA); \
3370 }
3371
3372 #define GEN_LDFS(name, ldop, op, type) \
3373 GEN_LDF(name, ldop, op | 0x20, type); \
3374 GEN_LDUF(name, ldop, op | 0x21, type); \
3375 GEN_LDUXF(name, ldop, op | 0x01, type); \
3376 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3377
3378 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3379 {
3380 TCGv t0 = tcg_temp_new();
3381 TCGv_i32 t1 = tcg_temp_new_i32();
3382 gen_qemu_ld32u(ctx, t0, arg2);
3383 tcg_gen_trunc_tl_i32(t1, t0);
3384 tcg_temp_free(t0);
3385 gen_helper_float32_to_float64(arg1, t1);
3386 tcg_temp_free_i32(t1);
3387 }
3388
3389 /* lfd lfdu lfdux lfdx */
3390 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3391 /* lfs lfsu lfsux lfsx */
3392 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3393
3394 /*** Floating-point store ***/
3395 #define GEN_STF(name, stop, opc, type) \
3396 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3397 { \
3398 TCGv EA; \
3399 if (unlikely(!ctx->fpu_enabled)) { \
3400 gen_exception(ctx, POWERPC_EXCP_FPU); \
3401 return; \
3402 } \
3403 gen_set_access_type(ctx, ACCESS_FLOAT); \
3404 EA = tcg_temp_new(); \
3405 gen_addr_imm_index(ctx, EA, 0); \
3406 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3407 tcg_temp_free(EA); \
3408 }
3409
3410 #define GEN_STUF(name, stop, opc, type) \
3411 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3412 { \
3413 TCGv EA; \
3414 if (unlikely(!ctx->fpu_enabled)) { \
3415 gen_exception(ctx, POWERPC_EXCP_FPU); \
3416 return; \
3417 } \
3418 if (unlikely(rA(ctx->opcode) == 0)) { \
3419 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3420 return; \
3421 } \
3422 gen_set_access_type(ctx, ACCESS_FLOAT); \
3423 EA = tcg_temp_new(); \
3424 gen_addr_imm_index(ctx, EA, 0); \
3425 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3426 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3427 tcg_temp_free(EA); \
3428 }
3429
3430 #define GEN_STUXF(name, stop, opc, type) \
3431 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3432 { \
3433 TCGv EA; \
3434 if (unlikely(!ctx->fpu_enabled)) { \
3435 gen_exception(ctx, POWERPC_EXCP_FPU); \
3436 return; \
3437 } \
3438 if (unlikely(rA(ctx->opcode) == 0)) { \
3439 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3440 return; \
3441 } \
3442 gen_set_access_type(ctx, ACCESS_FLOAT); \
3443 EA = tcg_temp_new(); \
3444 gen_addr_reg_index(ctx, EA); \
3445 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3446 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3447 tcg_temp_free(EA); \
3448 }
3449
3450 #define GEN_STXF(name, stop, opc2, opc3, type) \
3451 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3452 { \
3453 TCGv EA; \
3454 if (unlikely(!ctx->fpu_enabled)) { \
3455 gen_exception(ctx, POWERPC_EXCP_FPU); \
3456 return; \
3457 } \
3458 gen_set_access_type(ctx, ACCESS_FLOAT); \
3459 EA = tcg_temp_new(); \
3460 gen_addr_reg_index(ctx, EA); \
3461 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3462 tcg_temp_free(EA); \
3463 }
3464
3465 #define GEN_STFS(name, stop, op, type) \
3466 GEN_STF(name, stop, op | 0x20, type); \
3467 GEN_STUF(name, stop, op | 0x21, type); \
3468 GEN_STUXF(name, stop, op | 0x01, type); \
3469 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3470
3471 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3472 {
3473 TCGv_i32 t0 = tcg_temp_new_i32();
3474 TCGv t1 = tcg_temp_new();
3475 gen_helper_float64_to_float32(t0, arg1);
3476 tcg_gen_extu_i32_tl(t1, t0);
3477 tcg_temp_free_i32(t0);
3478 gen_qemu_st32(ctx, t1, arg2);
3479 tcg_temp_free(t1);
3480 }
3481
3482 /* stfd stfdu stfdux stfdx */
3483 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3484 /* stfs stfsu stfsux stfsx */
3485 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3486
3487 /* Optional: */
3488 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3489 {
3490 TCGv t0 = tcg_temp_new();
3491 tcg_gen_trunc_i64_tl(t0, arg1),
3492 gen_qemu_st32(ctx, t0, arg2);
3493 tcg_temp_free(t0);
3494 }
3495 /* stfiwx */
3496 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3497
3498 /*** Branch ***/
3499 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3500 target_ulong dest)
3501 {
3502 TranslationBlock *tb;
3503 tb = ctx->tb;
3504 #if defined(TARGET_PPC64)
3505 if (!ctx->sf_mode)
3506 dest = (uint32_t) dest;
3507 #endif
3508 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3509 likely(!ctx->singlestep_enabled)) {
3510 tcg_gen_goto_tb(n);
3511 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3512 tcg_gen_exit_tb((long)tb + n);
3513 } else {
3514 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3515 if (unlikely(ctx->singlestep_enabled)) {
3516 if ((ctx->singlestep_enabled &
3517 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3518 ctx->exception == POWERPC_EXCP_BRANCH) {
3519 target_ulong tmp = ctx->nip;
3520 ctx->nip = dest;
3521 gen_exception(ctx, POWERPC_EXCP_TRACE);
3522 ctx->nip = tmp;
3523 }
3524 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3525 gen_debug_exception(ctx);
3526 }
3527 }
3528 tcg_gen_exit_tb(0);
3529 }
3530 }
3531
3532 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3533 {
3534 #if defined(TARGET_PPC64)
3535 if (ctx->sf_mode == 0)
3536 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3537 else
3538 #endif
3539 tcg_gen_movi_tl(cpu_lr, nip);
3540 }
3541
3542 /* b ba bl bla */
3543 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3544 {
3545 target_ulong li, target;
3546
3547 ctx->exception = POWERPC_EXCP_BRANCH;
3548 /* sign extend LI */
3549 #if defined(TARGET_PPC64)
3550 if (ctx->sf_mode)
3551 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3552 else
3553 #endif
3554 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3555 if (likely(AA(ctx->opcode) == 0))
3556 target = ctx->nip + li - 4;
3557 else
3558 target = li;
3559 if (LK(ctx->opcode))
3560 gen_setlr(ctx, ctx->nip);
3561 gen_goto_tb(ctx, 0, target);
3562 }
3563
3564 #define BCOND_IM 0
3565 #define BCOND_LR 1
3566 #define BCOND_CTR 2
3567
3568 static always_inline void gen_bcond (DisasContext *ctx, int type)
3569 {
3570 uint32_t bo = BO(ctx->opcode);
3571 int l1 = gen_new_label();
3572 TCGv target;
3573
3574 ctx->exception = POWERPC_EXCP_BRANCH;
3575 if (type == BCOND_LR || type == BCOND_CTR) {
3576 target = tcg_temp_local_new();
3577 if (type == BCOND_CTR)
3578 tcg_gen_mov_tl(target, cpu_ctr);
3579 else
3580 tcg_gen_mov_tl(target, cpu_lr);
3581 }
3582 if (LK(ctx->opcode))
3583 gen_setlr(ctx, ctx->nip);
3584 l1 = gen_new_label();
3585 if ((bo & 0x4) == 0) {
3586 /* Decrement and test CTR */
3587 TCGv temp = tcg_temp_new();
3588 if (unlikely(type == BCOND_CTR)) {
3589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3590 return;
3591 }
3592 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3593 #if defined(TARGET_PPC64)
3594 if (!ctx->sf_mode)
3595 tcg_gen_ext32u_tl(temp, cpu_ctr);
3596 else
3597 #endif
3598 tcg_gen_mov_tl(temp, cpu_ctr);
3599 if (bo & 0x2) {
3600 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3601 } else {
3602 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3603 }
3604 tcg_temp_free(temp);
3605 }
3606 if ((bo & 0x10) == 0) {
3607 /* Test CR */
3608 uint32_t bi = BI(ctx->opcode);
3609 uint32_t mask = 1 << (3 - (bi & 0x03));
3610 TCGv_i32 temp = tcg_temp_new_i32();
3611
3612 if (bo & 0x8) {
3613 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3614 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3615 } else {
3616 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3617 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3618 }
3619 tcg_temp_free_i32(temp);
3620 }
3621 if (type == BCOND_IM) {
3622 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3623 if (likely(AA(ctx->opcode) == 0)) {
3624 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3625 } else {
3626 gen_goto_tb(ctx, 0, li);
3627 }
3628 gen_set_label(l1);
3629 gen_goto_tb(ctx, 1, ctx->nip);
3630 } else {
3631 #if defined(TARGET_PPC64)
3632 if (!(ctx->sf_mode))
3633 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3634 else
3635 #endif
3636 tcg_gen_andi_tl(cpu_nip, target, ~3);
3637 tcg_gen_exit_tb(0);
3638 gen_set_label(l1);
3639 #if defined(TARGET_PPC64)
3640 if (!(ctx->sf_mode))
3641 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3642 else
3643 #endif
3644 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3645 tcg_gen_exit_tb(0);
3646 }
3647 }
3648
3649 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3650 {
3651 gen_bcond(ctx, BCOND_IM);
3652 }
3653
3654 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3655 {
3656 gen_bcond(ctx, BCOND_CTR);
3657 }
3658
3659 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3660 {
3661 gen_bcond(ctx, BCOND_LR);
3662 }
3663
3664 /*** Condition register logical ***/
3665 #define GEN_CRLOGIC(name, tcg_op, opc) \
3666 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3667 { \
3668 uint8_t bitmask; \
3669 int sh; \
3670 TCGv_i32 t0, t1; \
3671 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3672 t0 = tcg_temp_new_i32(); \
3673 if (sh > 0) \
3674 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3675 else if (sh < 0) \
3676 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3677 else \
3678 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3679 t1 = tcg_temp_new_i32(); \
3680 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3681 if (sh > 0) \
3682 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3683 else if (sh < 0) \
3684 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3685 else \
3686 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3687 tcg_op(t0, t0, t1); \
3688 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3689 tcg_gen_andi_i32(t0, t0, bitmask); \
3690 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3691 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3692 tcg_temp_free_i32(t0); \
3693 tcg_temp_free_i32(t1); \
3694 }
3695
3696 /* crand */
3697 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3698 /* crandc */
3699 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3700 /* creqv */
3701 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3702 /* crnand */
3703 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3704 /* crnor */
3705 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3706 /* cror */
3707 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3708 /* crorc */
3709 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3710 /* crxor */
3711 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3712 /* mcrf */
3713 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3714 {
3715 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3716 }
3717
3718 /*** System linkage ***/
3719 /* rfi (mem_idx only) */
3720 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3721 {
3722 #if defined(CONFIG_USER_ONLY)
3723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3724 #else
3725 /* Restore CPU state */
3726 if (unlikely(!ctx->mem_idx)) {
3727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3728 return;
3729 }
3730 gen_helper_rfi();
3731 gen_sync_exception(ctx);
3732 #endif
3733 }
3734
3735 #if defined(TARGET_PPC64)
3736 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3737 {
3738 #if defined(CONFIG_USER_ONLY)
3739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3740 #else
3741 /* Restore CPU state */
3742 if (unlikely(!ctx->mem_idx)) {
3743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3744 return;
3745 }
3746 gen_helper_rfid();
3747 gen_sync_exception(ctx);
3748 #endif
3749 }
3750
3751 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3752 {
3753 #if defined(CONFIG_USER_ONLY)
3754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3755 #else
3756 /* Restore CPU state */
3757 if (unlikely(ctx->mem_idx <= 1)) {
3758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3759 return;
3760 }
3761 gen_helper_hrfid();
3762 gen_sync_exception(ctx);
3763 #endif
3764 }
3765 #endif
3766
3767 /* sc */
3768 #if defined(CONFIG_USER_ONLY)
3769 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3770 #else
3771 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3772 #endif
3773 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3774 {
3775 uint32_t lev;
3776
3777 lev = (ctx->opcode >> 5) & 0x7F;
3778 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3779 }
3780
3781 /*** Trap ***/
3782 /* tw */
3783 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3784 {
3785 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3786 /* Update the nip since this might generate a trap exception */
3787 gen_update_nip(ctx, ctx->nip);
3788 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3789 tcg_temp_free_i32(t0);
3790 }
3791
3792 /* twi */
3793 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3794 {
3795 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3796 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3797 /* Update the nip since this might generate a trap exception */
3798 gen_update_nip(ctx, ctx->nip);
3799 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3800 tcg_temp_free(t0);
3801 tcg_temp_free_i32(t1);
3802 }
3803
3804 #if defined(TARGET_PPC64)
3805 /* td */
3806 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3807 {
3808 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3809 /* Update the nip since this might generate a trap exception */
3810 gen_update_nip(ctx, ctx->nip);
3811 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3812 tcg_temp_free_i32(t0);
3813 }
3814
3815 /* tdi */
3816 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3817 {
3818 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3819 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3820 /* Update the nip since this might generate a trap exception */
3821 gen_update_nip(ctx, ctx->nip);
3822 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3823 tcg_temp_free(t0);
3824 tcg_temp_free_i32(t1);
3825 }
3826 #endif
3827
3828 /*** Processor control ***/
3829 /* mcrxr */
3830 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3831 {
3832 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3833 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3835 }
3836
3837 /* mfcr */
3838 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3839 {
3840 uint32_t crm, crn;
3841
3842 if (likely(ctx->opcode & 0x00100000)) {
3843 crm = CRM(ctx->opcode);
3844 if (likely((crm ^ (crm - 1)) == 0)) {
3845 crn = ffs(crm);
3846 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3847 }
3848 } else {
3849 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3850 }
3851 }
3852
3853 /* mfmsr */
3854 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3855 {
3856 #if defined(CONFIG_USER_ONLY)
3857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3858 #else
3859 if (unlikely(!ctx->mem_idx)) {
3860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3861 return;
3862 }
3863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3864 #endif
3865 }
3866
3867 #if 1
3868 #define SPR_NOACCESS ((void *)(-1UL))
3869 #else
3870 static void spr_noaccess (void *opaque, int sprn)
3871 {
3872 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3873 printf("ERROR: try to access SPR %d !\n", sprn);
3874 }
3875 #define SPR_NOACCESS (&spr_noaccess)
3876 #endif
3877
3878 /* mfspr */
3879 static always_inline void gen_op_mfspr (DisasContext *ctx)
3880 {
3881 void (*read_cb)(void *opaque, int gprn, int sprn);
3882 uint32_t sprn = SPR(ctx->opcode);
3883
3884 #if !defined(CONFIG_USER_ONLY)
3885 if (ctx->mem_idx == 2)
3886 read_cb = ctx->spr_cb[sprn].hea_read;
3887 else if (ctx->mem_idx)
3888 read_cb = ctx->spr_cb[sprn].oea_read;
3889 else
3890 #endif
3891 read_cb = ctx->spr_cb[sprn].uea_read;
3892 if (likely(read_cb != NULL)) {
3893 if (likely(read_cb != SPR_NOACCESS)) {
3894 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3895 } else {
3896 /* Privilege exception */
3897 /* This is a hack to avoid warnings when running Linux:
3898 * this OS breaks the PowerPC virtualisation model,
3899 * allowing userland application to read the PVR
3900 */
3901 if (sprn != SPR_PVR) {
3902 qemu_log("Trying to read privileged spr %d %03x at "
3903 ADDRX "\n", sprn, sprn, ctx->nip);
3904 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3905 sprn, sprn, ctx->nip);
3906 }
3907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3908 }
3909 } else {
3910 /* Not defined */
3911 qemu_log("Trying to read invalid spr %d %03x at "
3912 ADDRX "\n", sprn, sprn, ctx->nip);
3913 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3914 sprn, sprn, ctx->nip);
3915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3916 }
3917 }
3918
3919 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3920 {
3921 gen_op_mfspr(ctx);
3922 }
3923
3924 /* mftb */
3925 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3926 {
3927 gen_op_mfspr(ctx);
3928 }
3929
3930 /* mtcrf */
3931 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3932 {
3933 uint32_t crm, crn;
3934
3935 crm = CRM(ctx->opcode);
3936 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3937 TCGv_i32 temp = tcg_temp_new_i32();
3938 crn = ffs(crm);
3939 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3940 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3941 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3942 tcg_temp_free_i32(temp);
3943 } else {
3944 TCGv_i32 temp = tcg_const_i32(crm);
3945 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3946 tcg_temp_free_i32(temp);
3947 }
3948 }
3949
3950 /* mtmsr */
3951 #if defined(TARGET_PPC64)
3952 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3953 {
3954 #if defined(CONFIG_USER_ONLY)
3955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3956 #else
3957 if (unlikely(!ctx->mem_idx)) {
3958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3959 return;
3960 }
3961 if (ctx->opcode & 0x00010000) {
3962 /* Special form that does not need any synchronisation */
3963 TCGv t0 = tcg_temp_new();
3964 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3965 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3966 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3967 tcg_temp_free(t0);
3968 } else {
3969 /* XXX: we need to update nip before the store
3970 * if we enter power saving mode, we will exit the loop
3971 * directly from ppc_store_msr
3972 */
3973 gen_update_nip(ctx, ctx->nip);
3974 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3975 /* Must stop the translation as machine state (may have) changed */
3976 /* Note that mtmsr is not always defined as context-synchronizing */
3977 gen_stop_exception(ctx);
3978 }
3979 #endif
3980 }
3981 #endif
3982
3983 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3984 {
3985 #if defined(CONFIG_USER_ONLY)
3986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3987 #else
3988 if (unlikely(!ctx->mem_idx)) {
3989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3990 return;
3991 }
3992 if (ctx->opcode & 0x00010000) {
3993 /* Special form that does not need any synchronisation */
3994 TCGv t0 = tcg_temp_new();
3995 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3996 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3997 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3998 tcg_temp_free(t0);
3999 } else {
4000 /* XXX: we need to update nip before the store
4001 * if we enter power saving mode, we will exit the loop
4002 * directly from ppc_store_msr
4003 */
4004 gen_update_nip(ctx, ctx->nip);
4005 #if defined(TARGET_PPC64)
4006 if (!ctx->sf_mode) {
4007 TCGv t0 = tcg_temp_new();
4008 TCGv t1 = tcg_temp_new();
4009 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4010 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4011 tcg_gen_or_tl(t0, t0, t1);
4012 tcg_temp_free(t1);
4013 gen_helper_store_msr(t0);
4014 tcg_temp_free(t0);
4015 } else
4016 #endif
4017 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4018 /* Must stop the translation as machine state (may have) changed */
4019 /* Note that mtmsr is not always defined as context-synchronizing */
4020 gen_stop_exception(ctx);
4021 }
4022 #endif
4023 }
4024
4025 /* mtspr */
4026 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4027 {
4028 void (*write_cb)(void *opaque, int sprn, int gprn);
4029 uint32_t sprn = SPR(ctx->opcode);
4030
4031 #if !defined(CONFIG_USER_ONLY)
4032 if (ctx->mem_idx == 2)
4033 write_cb = ctx->spr_cb[sprn].hea_write;
4034 else if (ctx->mem_idx)
4035 write_cb = ctx->spr_cb[sprn].oea_write;
4036 else
4037 #endif
4038 write_cb = ctx->spr_cb[sprn].uea_write;
4039 if (likely(write_cb != NULL)) {
4040 if (likely(write_cb != SPR_NOACCESS)) {
4041 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4042 } else {
4043 /* Privilege exception */
4044 qemu_log("Trying to write privileged spr %d %03x at "
4045 ADDRX "\n", sprn, sprn, ctx->nip);
4046 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4047 sprn, sprn, ctx->nip);
4048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4049 }
4050 } else {
4051 /* Not defined */
4052 qemu_log("Trying to write invalid spr %d %03x at "
4053 ADDRX "\n", sprn, sprn, ctx->nip);
4054 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4055 sprn, sprn, ctx->nip);
4056 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4057 }
4058 }
4059
4060 /*** Cache management ***/
4061 /* dcbf */
4062 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4063 {
4064 /* XXX: specification says this is treated as a load by the MMU */
4065 TCGv t0;
4066 gen_set_access_type(ctx, ACCESS_CACHE);
4067 t0 = tcg_temp_new();
4068 gen_addr_reg_index(ctx, t0);
4069 gen_qemu_ld8u(ctx, t0, t0);
4070 tcg_temp_free(t0);
4071 }
4072
4073 /* dcbi (Supervisor only) */
4074 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4075 {
4076 #if defined(CONFIG_USER_ONLY)
4077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4078 #else
4079 TCGv EA, val;
4080 if (unlikely(!ctx->mem_idx)) {
4081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4082 return;
4083 }
4084 EA = tcg_temp_new();
4085 gen_set_access_type(ctx, ACCESS_CACHE);
4086 gen_addr_reg_index(ctx, EA);
4087 val = tcg_temp_new();
4088 /* XXX: specification says this should be treated as a store by the MMU */
4089 gen_qemu_ld8u(ctx, val, EA);
4090 gen_qemu_st8(ctx, val, EA);
4091 tcg_temp_free(val);
4092 tcg_temp_free(EA);
4093 #endif
4094 }
4095
4096 /* dcdst */
4097 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4098 {
4099 /* XXX: specification say this is treated as a load by the MMU */
4100 TCGv t0;
4101 gen_set_access_type(ctx, ACCESS_CACHE);
4102 t0 = tcg_temp_new();
4103 gen_addr_reg_index(ctx, t0);
4104 gen_qemu_ld8u(ctx, t0, t0);
4105 tcg_temp_free(t0);
4106 }
4107
4108 /* dcbt */
4109 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4110 {
4111 /* interpreted as no-op */
4112 /* XXX: specification say this is treated as a load by the MMU
4113 * but does not generate any exception
4114 */
4115 }
4116
4117 /* dcbtst */
4118 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4119 {
4120 /* interpreted as no-op */
4121 /* XXX: specification say this is treated as a load by the MMU
4122 * but does not generate any exception
4123 */
4124 }
4125
4126 /* dcbz */
4127 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4128 {
4129 TCGv t0;
4130 gen_set_access_type(ctx, ACCESS_CACHE);
4131 /* NIP cannot be restored if the memory exception comes from an helper */
4132 gen_update_nip(ctx, ctx->nip - 4);
4133 t0 = tcg_temp_new();
4134 gen_addr_reg_index(ctx, t0);
4135 gen_helper_dcbz(t0);
4136 tcg_temp_free(t0);
4137 }
4138
4139 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4140 {
4141 TCGv t0;
4142 gen_set_access_type(ctx, ACCESS_CACHE);
4143 /* NIP cannot be restored if the memory exception comes from an helper */
4144 gen_update_nip(ctx, ctx->nip - 4);
4145 t0 = tcg_temp_new();
4146 gen_addr_reg_index(ctx, t0);
4147 if (ctx->opcode & 0x00200000)
4148 gen_helper_dcbz(t0);
4149 else
4150 gen_helper_dcbz_970(t0);
4151 tcg_temp_free(t0);
4152 }
4153
4154 /* dst / dstt */
4155 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4156 {
4157 if (rA(ctx->opcode) == 0) {
4158 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4159 } else {
4160 /* interpreted as no-op */
4161 }
4162 }
4163
4164 /* dstst /dststt */
4165 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4166 {
4167 if (rA(ctx->opcode) == 0) {
4168 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4169 } else {
4170 /* interpreted as no-op */
4171 }
4172
4173 }
4174
4175 /* dss / dssall */
4176 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4177 {
4178 /* interpreted as no-op */
4179 }
4180
4181 /* icbi */
4182 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4183 {
4184 TCGv t0;
4185 gen_set_access_type(ctx, ACCESS_CACHE);
4186 /* NIP cannot be restored if the memory exception comes from an helper */
4187 gen_update_nip(ctx, ctx->nip - 4);
4188 t0 = tcg_temp_new();
4189 gen_addr_reg_index(ctx, t0);
4190 gen_helper_icbi(t0);
4191 tcg_temp_free(t0);
4192 }
4193
4194 /* Optional: */
4195 /* dcba */
4196 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4197 {
4198 /* interpreted as no-op */
4199 /* XXX: specification say this is treated as a store by the MMU
4200 * but does not generate any exception
4201 */
4202 }
4203
4204 /*** Segment register manipulation ***/
4205 /* Supervisor only: */
4206 /* mfsr */
4207 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4208 {
4209 #if defined(CONFIG_USER_ONLY)
4210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4211 #else
4212 TCGv t0;
4213 if (unlikely(!ctx->mem_idx)) {
4214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4215 return;
4216 }
4217 t0 = tcg_const_tl(SR(ctx->opcode));
4218 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4219 tcg_temp_free(t0);
4220 #endif
4221 }
4222
4223 /* mfsrin */
4224 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4225 {
4226 #if defined(CONFIG_USER_ONLY)
4227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4228 #else
4229 TCGv t0;
4230 if (unlikely(!ctx->mem_idx)) {
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 return;
4233 }
4234 t0 = tcg_temp_new();
4235 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4236 tcg_gen_andi_tl(t0, t0, 0xF);
4237 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4238 tcg_temp_free(t0);
4239 #endif
4240 }
4241
4242 /* mtsr */
4243 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4244 {
4245 #if defined(CONFIG_USER_ONLY)
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 #else
4248 TCGv t0;
4249 if (unlikely(!ctx->mem_idx)) {
4250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4251 return;
4252 }
4253 t0 = tcg_const_tl(SR(ctx->opcode));
4254 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4255 tcg_temp_free(t0);
4256 #endif
4257 }
4258
4259 /* mtsrin */
4260 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4261 {
4262 #if defined(CONFIG_USER_ONLY)
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 #else
4265 TCGv t0;
4266 if (unlikely(!ctx->mem_idx)) {
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 return;
4269 }
4270 t0 = tcg_temp_new();
4271 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4272 tcg_gen_andi_tl(t0, t0, 0xF);
4273 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4274 tcg_temp_free(t0);
4275 #endif
4276 }
4277
4278 #if defined(TARGET_PPC64)
4279 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4280 /* mfsr */
4281 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4282 {
4283 #if defined(CONFIG_USER_ONLY)
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 #else
4286 TCGv t0;
4287 if (unlikely(!ctx->mem_idx)) {
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4289 return;
4290 }
4291 t0 = tcg_const_tl(SR(ctx->opcode));
4292 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4293 tcg_temp_free(t0);
4294 #endif
4295 }
4296
4297 /* mfsrin */
4298 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4299 PPC_SEGMENT_64B)
4300 {
4301 #if defined(CONFIG_USER_ONLY)
4302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4303 #else
4304 TCGv t0;
4305 if (unlikely(!ctx->mem_idx)) {
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 return;
4308 }
4309 t0 = tcg_temp_new();
4310 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4311 tcg_gen_andi_tl(t0, t0, 0xF);
4312 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4313 tcg_temp_free(t0);
4314 #endif
4315 }
4316
4317 /* mtsr */
4318 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4319 {
4320 #if defined(CONFIG_USER_ONLY)
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 #else
4323 TCGv t0;
4324 if (unlikely(!ctx->mem_idx)) {
4325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4326 return;
4327 }
4328 t0 = tcg_const_tl(SR(ctx->opcode));
4329 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4330 tcg_temp_free(t0);
4331 #endif
4332 }
4333
4334 /* mtsrin */
4335 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4336 PPC_SEGMENT_64B)
4337 {
4338 #if defined(CONFIG_USER_ONLY)
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4340 #else
4341 TCGv t0;
4342 if (unlikely(!ctx->mem_idx)) {
4343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4344 return;
4345 }
4346 t0 = tcg_temp_new();
4347 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4348 tcg_gen_andi_tl(t0, t0, 0xF);
4349 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4350 tcg_temp_free(t0);
4351 #endif
4352 }
4353 #endif /* defined(TARGET_PPC64) */
4354
4355 /*** Lookaside buffer management ***/
4356 /* Optional & mem_idx only: */
4357 /* tlbia */
4358 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4362 #else
4363 if (unlikely(!ctx->mem_idx)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 return;
4366 }
4367 gen_helper_tlbia();
4368 #endif
4369 }
4370
4371 /* tlbie */
4372 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4373 {
4374 #if defined(CONFIG_USER_ONLY)
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4376 #else
4377 if (unlikely(!ctx->mem_idx)) {
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4379 return;
4380 }
4381 #if defined(TARGET_PPC64)
4382 if (!ctx->sf_mode) {
4383 TCGv t0 = tcg_temp_new();
4384 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4385 gen_helper_tlbie(t0);
4386 tcg_temp_free(t0);
4387 } else
4388 #endif
4389 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4390 #endif
4391 }
4392
4393 /* tlbsync */
4394 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4395 {
4396 #if defined(CONFIG_USER_ONLY)
4397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4398 #else
4399 if (unlikely(!ctx->mem_idx)) {
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 return;
4402 }
4403 /* This has no effect: it should ensure that all previous
4404 * tlbie have completed
4405 */
4406 gen_stop_exception(ctx);
4407 #endif
4408 }
4409
4410 #if defined(TARGET_PPC64)
4411 /* slbia */
4412 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4416 #else
4417 if (unlikely(!ctx->mem_idx)) {
4418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4419 return;
4420 }
4421 gen_helper_slbia();
4422 #endif
4423 }
4424
4425 /* slbie */
4426 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4427 {
4428 #if defined(CONFIG_USER_ONLY)
4429 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4430 #else
4431 if (unlikely(!ctx->mem_idx)) {
4432 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4433 return;
4434 }
4435 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4436 #endif
4437 }
4438 #endif
4439
4440 /*** External control ***/
4441 /* Optional: */
4442 /* eciwx */
4443 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4444 {
4445 TCGv t0;
4446 /* Should check EAR[E] ! */
4447 gen_set_access_type(ctx, ACCESS_EXT);
4448 t0 = tcg_temp_new();
4449 gen_addr_reg_index(ctx, t0);
4450 gen_check_align(ctx, t0, 0x03);
4451 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4452 tcg_temp_free(t0);
4453 }
4454
4455 /* ecowx */
4456 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4457 {
4458 TCGv t0;
4459 /* Should check EAR[E] ! */
4460 gen_set_access_type(ctx, ACCESS_EXT);
4461 t0 = tcg_temp_new();
4462 gen_addr_reg_index(ctx, t0);
4463 gen_check_align(ctx, t0, 0x03);
4464 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4465 tcg_temp_free(t0);
4466 }
4467
4468 /* PowerPC 601 specific instructions */
4469 /* abs - abs. */
4470 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4471 {
4472 int l1 = gen_new_label();
4473 int l2 = gen_new_label();
4474 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4475 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4476 tcg_gen_br(l2);
4477 gen_set_label(l1);
4478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4479 gen_set_label(l2);
4480 if (unlikely(Rc(ctx->opcode) != 0))
4481 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4482 }
4483
4484 /* abso - abso. */
4485 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4486 {
4487 int l1 = gen_new_label();
4488 int l2 = gen_new_label();
4489 int l3 = gen_new_label();
4490 /* Start with XER OV disabled, the most likely case */
4491 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4492 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4493 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4494 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4495 tcg_gen_br(l2);
4496 gen_set_label(l1);
4497 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4498 tcg_gen_br(l3);
4499 gen_set_label(l2);
4500 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4501 gen_set_label(l3);
4502 if (unlikely(Rc(ctx->opcode) != 0))
4503 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4504 }
4505
4506 /* clcs */
4507 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4508 {
4509 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4510 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4511 tcg_temp_free_i32(t0);
4512 /* Rc=1 sets CR0 to an undefined state */
4513 }
4514
4515 /* div - div. */
4516 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4517 {
4518 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4519 if (unlikely(Rc(ctx->opcode) != 0))
4520 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4521 }
4522
4523 /* divo - divo. */
4524 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4525 {
4526 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4527 if (unlikely(Rc(ctx->opcode) != 0))
4528 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4529 }
4530
4531 /* divs - divs. */
4532 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4533 {
4534 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4537 }
4538
4539 /* divso - divso. */
4540 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4541 {
4542 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4543 if (unlikely(Rc(ctx->opcode) != 0))
4544 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4545 }
4546
4547 /* doz - doz. */
4548 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4549 {
4550 int l1 = gen_new_label();
4551 int l2 = gen_new_label();
4552 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4553 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4554 tcg_gen_br(l2);
4555 gen_set_label(l1);
4556 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4557 gen_set_label(l2);
4558 if (unlikely(Rc(ctx->opcode) != 0))
4559 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4560 }
4561
4562 /* dozo - dozo. */
4563 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4564 {
4565 int l1 = gen_new_label();
4566 int l2 = gen_new_label();
4567 TCGv t0 = tcg_temp_new();
4568 TCGv t1 = tcg_temp_new();
4569 TCGv t2 = tcg_temp_new();
4570 /* Start with XER OV disabled, the most likely case */
4571 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4572 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4573 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4574 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4575 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4576 tcg_gen_andc_tl(t1, t1, t2);
4577 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4578 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4579 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4580 tcg_gen_br(l2);
4581 gen_set_label(l1);
4582 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4583 gen_set_label(l2);
4584 tcg_temp_free(t0);
4585 tcg_temp_free(t1);
4586 tcg_temp_free(t2);
4587 if (unlikely(Rc(ctx->opcode) != 0))
4588 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4589 }
4590
4591 /* dozi */
4592 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4593 {
4594 target_long simm = SIMM(ctx->opcode);
4595 int l1 = gen_new_label();
4596 int l2 = gen_new_label();
4597 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4598 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4599 tcg_gen_br(l2);
4600 gen_set_label(l1);
4601 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4602 gen_set_label(l2);
4603 if (unlikely(Rc(ctx->opcode) != 0))
4604 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4605 }
4606
4607 /* lscbx - lscbx. */
4608 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4609 {
4610 TCGv t0 = tcg_temp_new();
4611 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4612 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4613 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4614
4615 gen_addr_reg_index(ctx, t0);
4616 /* NIP cannot be restored if the memory exception comes from an helper */
4617 gen_update_nip(ctx, ctx->nip - 4);
4618 gen_helper_lscbx(t0, t0, t1, t2, t3);
4619 tcg_temp_free_i32(t1);
4620 tcg_temp_free_i32(t2);
4621 tcg_temp_free_i32(t3);
4622 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4623 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4624 if (unlikely(Rc(ctx->opcode) != 0))
4625 gen_set_Rc0(ctx, t0);
4626 tcg_temp_free(t0);
4627 }
4628
4629 /* maskg - maskg. */
4630 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4631 {
4632 int l1 = gen_new_label();
4633 TCGv t0 = tcg_temp_new();
4634 TCGv t1 = tcg_temp_new();
4635 TCGv t2 = tcg_temp_new();
4636 TCGv t3 = tcg_temp_new();
4637 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4638 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4639 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4640 tcg_gen_addi_tl(t2, t0, 1);
4641 tcg_gen_shr_tl(t2, t3, t2);
4642 tcg_gen_shr_tl(t3, t3, t1);
4643 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4644 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4645 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4646 gen_set_label(l1);
4647 tcg_temp_free(t0);
4648 tcg_temp_free(t1);
4649 tcg_temp_free(t2);
4650 tcg_temp_free(t3);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4653 }
4654
4655 /* maskir - maskir. */
4656 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4657 {
4658 TCGv t0 = tcg_temp_new();
4659 TCGv t1 = tcg_temp_new();
4660 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4661 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4662 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4663 tcg_temp_free(t0);
4664 tcg_temp_free(t1);
4665 if (unlikely(Rc(ctx->opcode) != 0))
4666 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4667 }
4668
4669 /* mul - mul. */
4670 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4671 {
4672 TCGv_i64 t0 = tcg_temp_new_i64();
4673 TCGv_i64 t1 = tcg_temp_new_i64();
4674 TCGv t2 = tcg_temp_new();
4675 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4676 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4677 tcg_gen_mul_i64(t0, t0, t1);
4678 tcg_gen_trunc_i64_tl(t2, t0);
4679 gen_store_spr(SPR_MQ, t2);
4680 tcg_gen_shri_i64(t1, t0, 32);
4681 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4682 tcg_temp_free_i64(t0);
4683 tcg_temp_free_i64(t1);
4684 tcg_temp_free(t2);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4687 }
4688
4689 /* mulo - mulo. */
4690 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4691 {
4692 int l1 = gen_new_label();
4693 TCGv_i64 t0 = tcg_temp_new_i64();
4694 TCGv_i64 t1 = tcg_temp_new_i64();
4695 TCGv t2 = tcg_temp_new();
4696 /* Start with XER OV disabled, the most likely case */
4697 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4698 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4699 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4700 tcg_gen_mul_i64(t0, t0, t1);
4701 tcg_gen_trunc_i64_tl(t2, t0);
4702 gen_store_spr(SPR_MQ, t2);
4703 tcg_gen_shri_i64(t1, t0, 32);
4704 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4705 tcg_gen_ext32s_i64(t1, t0);
4706 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4707 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4708 gen_set_label(l1);
4709 tcg_temp_free_i64(t0);
4710 tcg_temp_free_i64(t1);
4711 tcg_temp_free(t2);
4712 if (unlikely(Rc(ctx->opcode) != 0))
4713 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4714 }
4715
4716 /* nabs - nabs. */
4717 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4718 {
4719 int l1 = gen_new_label();
4720 int l2 = gen_new_label();
4721 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4723 tcg_gen_br(l2);
4724 gen_set_label(l1);
4725 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4726 gen_set_label(l2);
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4729 }
4730
4731 /* nabso - nabso. */
4732 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4733 {
4734 int l1 = gen_new_label();
4735 int l2 = gen_new_label();
4736 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4738 tcg_gen_br(l2);
4739 gen_set_label(l1);
4740 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4741 gen_set_label(l2);
4742 /* nabs never overflows */
4743 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4744 if (unlikely(Rc(ctx->opcode) != 0))
4745 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4746 }
4747
4748 /* rlmi - rlmi. */
4749 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4750 {
4751 uint32_t mb = MB(ctx->opcode);
4752 uint32_t me = ME(ctx->opcode);
4753 TCGv t0 = tcg_temp_new();
4754 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4756 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4757 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4758 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4759 tcg_temp_free(t0);
4760 if (unlikely(Rc(ctx->opcode) != 0))
4761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4762 }
4763
4764 /* rrib - rrib. */
4765 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4766 {
4767 TCGv t0 = tcg_temp_new();
4768 TCGv t1 = tcg_temp_new();
4769 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4770 tcg_gen_movi_tl(t1, 0x80000000);
4771 tcg_gen_shr_tl(t1, t1, t0);
4772 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4773 tcg_gen_and_tl(t0, t0, t1);
4774 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4775 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4776 tcg_temp_free(t0);
4777 tcg_temp_free(t1);
4778 if (unlikely(Rc(ctx->opcode) != 0))
4779 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4780 }
4781
4782 /* sle - sle. */
4783 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4784 {
4785 TCGv t0 = tcg_temp_new();
4786 TCGv t1 = tcg_temp_new();
4787 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4788 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4789 tcg_gen_subfi_tl(t1, 32, t1);
4790 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4791 tcg_gen_or_tl(t1, t0, t1);
4792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4793 gen_store_spr(SPR_MQ, t1);
4794 tcg_temp_free(t0);
4795 tcg_temp_free(t1);
4796 if (unlikely(Rc(ctx->opcode) != 0))
4797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4798 }
4799
4800 /* sleq - sleq. */
4801 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4802 {
4803 TCGv t0 = tcg_temp_new();
4804 TCGv t1 = tcg_temp_new();
4805 TCGv t2 = tcg_temp_new();
4806 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4807 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4808 tcg_gen_shl_tl(t2, t2, t0);
4809 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4810 gen_load_spr(t1, SPR_MQ);
4811 gen_store_spr(SPR_MQ, t0);
4812 tcg_gen_and_tl(t0, t0, t2);
4813 tcg_gen_andc_tl(t1, t1, t2);
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4815 tcg_temp_free(t0);
4816 tcg_temp_free(t1);
4817 tcg_temp_free(t2);
4818 if (unlikely(Rc(ctx->opcode) != 0))
4819 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4820 }
4821
4822 /* sliq - sliq. */
4823 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4824 {
4825 int sh = SH(ctx->opcode);
4826 TCGv t0 = tcg_temp_new();
4827 TCGv t1 = tcg_temp_new();
4828 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4829 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4830 tcg_gen_or_tl(t1, t0, t1);
4831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4832 gen_store_spr(SPR_MQ, t1);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* slliq - slliq. */
4840 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4841 {
4842 int sh = SH(ctx->opcode);
4843 TCGv t0 = tcg_temp_new();
4844 TCGv t1 = tcg_temp_new();
4845 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4846 gen_load_spr(t1, SPR_MQ);
4847 gen_store_spr(SPR_MQ, t0);
4848 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4849 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4850 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4851 tcg_temp_free(t0);
4852 tcg_temp_free(t1);
4853 if (unlikely(Rc(ctx->opcode) != 0))
4854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4855 }
4856
4857 /* sllq - sllq. */
4858 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4859 {
4860 int l1 = gen_new_label();
4861 int l2 = gen_new_label();
4862 TCGv t0 = tcg_temp_local_new();
4863 TCGv t1 = tcg_temp_local_new();
4864 TCGv t2 = tcg_temp_local_new();
4865 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4866 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4867 tcg_gen_shl_tl(t1, t1, t2);
4868 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4869 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4870 gen_load_spr(t0, SPR_MQ);
4871 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4872 tcg_gen_br(l2);
4873 gen_set_label(l1);
4874 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4875 gen_load_spr(t2, SPR_MQ);
4876 tcg_gen_andc_tl(t1, t2, t1);
4877 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4878 gen_set_label(l2);
4879 tcg_temp_free(t0);
4880 tcg_temp_free(t1);
4881 tcg_temp_free(t2);
4882 if (unlikely(Rc(ctx->opcode) != 0))
4883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4884 }
4885
4886 /* slq - slq. */
4887 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4888 {
4889 int l1 = gen_new_label();
4890 TCGv t0 = tcg_temp_new();
4891 TCGv t1 = tcg_temp_new();
4892 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4893 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4894 tcg_gen_subfi_tl(t1, 32, t1);
4895 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4896 tcg_gen_or_tl(t1, t0, t1);
4897 gen_store_spr(SPR_MQ, t1);
4898 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4899 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4900 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4901 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4902 gen_set_label(l1);
4903 tcg_temp_free(t0);
4904 tcg_temp_free(t1);
4905 if (unlikely(Rc(ctx->opcode) != 0))
4906 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4907 }
4908
4909 /* sraiq - sraiq. */
4910 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4911 {
4912 int sh = SH(ctx->opcode);
4913 int l1 = gen_new_label();
4914 TCGv t0 = tcg_temp_new();
4915 TCGv t1 = tcg_temp_new();
4916 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4917 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4918 tcg_gen_or_tl(t0, t0, t1);
4919 gen_store_spr(SPR_MQ, t0);
4920 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4921 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4922 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4923 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4924 gen_set_label(l1);
4925 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4926 tcg_temp_free(t0);
4927 tcg_temp_free(t1);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4930 }
4931
4932 /* sraq - sraq. */
4933 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4934 {
4935 int l1 = gen_new_label();
4936 int l2 = gen_new_label();
4937 TCGv t0 = tcg_temp_new();
4938 TCGv t1 = tcg_temp_local_new();
4939 TCGv t2 = tcg_temp_local_new();
4940 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4941 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4942 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4943 tcg_gen_subfi_tl(t2, 32, t2);
4944 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4945 tcg_gen_or_tl(t0, t0, t2);
4946 gen_store_spr(SPR_MQ, t0);
4947 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4948 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4949 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4950 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4951 gen_set_label(l1);
4952 tcg_temp_free(t0);
4953 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4954 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4955 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4956 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4957 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4958 gen_set_label(l2);
4959 tcg_temp_free(t1);
4960 tcg_temp_free(t2);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963 }
4964
4965 /* sre - sre. */
4966 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4967 {
4968 TCGv t0 = tcg_temp_new();
4969 TCGv t1 = tcg_temp_new();
4970 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4971 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4972 tcg_gen_subfi_tl(t1, 32, t1);
4973 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4974 tcg_gen_or_tl(t1, t0, t1);
4975 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4976 gen_store_spr(SPR_MQ, t1);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
4979 if (unlikely(Rc(ctx->opcode) != 0))
4980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4981 }
4982
4983 /* srea - srea. */
4984 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4985 {
4986 TCGv t0 = tcg_temp_new();
4987 TCGv t1 = tcg_temp_new();
4988 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4989 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4990 gen_store_spr(SPR_MQ, t0);
4991 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4992 tcg_temp_free(t0);
4993 tcg_temp_free(t1);
4994 if (unlikely(Rc(ctx->opcode) != 0))
4995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4996 }
4997
4998 /* sreq */
4999 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5000 {
5001 TCGv t0 = tcg_temp_new();
5002 TCGv t1 = tcg_temp_new();
5003 TCGv t2 = tcg_temp_new();
5004 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5005 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5006 tcg_gen_shr_tl(t1, t1, t0);
5007 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5008 gen_load_spr(t2, SPR_MQ);
5009 gen_store_spr(SPR_MQ, t0);
5010 tcg_gen_and_tl(t0, t0, t1);
5011 tcg_gen_andc_tl(t2, t2, t1);
5012 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5013 tcg_temp_free(t0);
5014 tcg_temp_free(t1);
5015 tcg_temp_free(t2);
5016 if (unlikely(Rc(ctx->opcode) != 0))
5017 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5018 }
5019
5020 /* sriq */
5021 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5022 {
5023 int sh = SH(ctx->opcode);
5024 TCGv t0 = tcg_temp_new();
5025 TCGv t1 = tcg_temp_new();
5026 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5027 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5028 tcg_gen_or_tl(t1, t0, t1);
5029 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5030 gen_store_spr(SPR_MQ, t1);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5035 }
5036
5037 /* srliq */
5038 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5039 {
5040 int sh = SH(ctx->opcode);
5041 TCGv t0 = tcg_temp_new();
5042 TCGv t1 = tcg_temp_new();
5043 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5044 gen_load_spr(t1, SPR_MQ);
5045 gen_store_spr(SPR_MQ, t0);
5046 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5047 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5048 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5049 tcg_temp_free(t0);
5050 tcg_temp_free(t1);
5051 if (unlikely(Rc(ctx->opcode) != 0))
5052 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5053 }
5054
5055 /* srlq */
5056 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5057 {
5058 int l1 = gen_new_label();
5059 int l2 = gen_new_label();
5060 TCGv t0 = tcg_temp_local_new();
5061 TCGv t1 = tcg_temp_local_new();
5062 TCGv t2 = tcg_temp_local_new();
5063 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5064 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5065 tcg_gen_shr_tl(t2, t1, t2);
5066 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5067 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5068 gen_load_spr(t0, SPR_MQ);
5069 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5070 tcg_gen_br(l2);
5071 gen_set_label(l1);
5072 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5073 tcg_gen_and_tl(t0, t0, t2);
5074 gen_load_spr(t1, SPR_MQ);
5075 tcg_gen_andc_tl(t1, t1, t2);
5076 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5077 gen_set_label(l2);
5078 tcg_temp_free(t0);
5079 tcg_temp_free(t1);
5080 tcg_temp_free(t2);
5081 if (unlikely(Rc(ctx->opcode) != 0))
5082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5083 }
5084
5085 /* srq */
5086 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5087 {
5088 int l1 = gen_new_label();
5089 TCGv t0 = tcg_temp_new();
5090 TCGv t1 = tcg_temp_new();
5091 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5092 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5093 tcg_gen_subfi_tl(t1, 32, t1);
5094 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 gen_store_spr(SPR_MQ, t1);
5097 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5098 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5099 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5100 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5101 gen_set_label(l1);
5102 tcg_temp_free(t0);
5103 tcg_temp_free(t1);
5104 if (unlikely(Rc(ctx->opcode) != 0))
5105 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5106 }
5107
5108 /* PowerPC 602 specific instructions */
5109 /* dsa */
5110 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5111 {
5112 /* XXX: TODO */
5113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5114 }
5115
5116 /* esa */
5117 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5118 {
5119 /* XXX: TODO */
5120 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5121 }
5122
5123 /* mfrom */
5124 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5125 {
5126 #if defined(CONFIG_USER_ONLY)
5127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5128 #else
5129 if (unlikely(!ctx->mem_idx)) {
5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5131 return;
5132 }
5133 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5134 #endif
5135 }
5136
5137 /* 602 - 603 - G2 TLB management */
5138 /* tlbld */
5139 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5140 {
5141 #if defined(CONFIG_USER_ONLY)
5142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5143 #else
5144 if (unlikely(!ctx->mem_idx)) {
5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5146 return;
5147 }
5148 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5149 #endif
5150 }
5151
5152 /* tlbli */
5153 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5154 {
5155 #if defined(CONFIG_USER_ONLY)
5156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5157 #else
5158 if (unlikely(!ctx->mem_idx)) {
5159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5160 return;
5161 }
5162 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5163 #endif
5164 }
5165
5166 /* 74xx TLB management */
5167 /* tlbld */
5168 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5169 {
5170 #if defined(CONFIG_USER_ONLY)
5171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5172 #else
5173 if (unlikely(!ctx->mem_idx)) {
5174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5175 return;
5176 }
5177 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5178 #endif
5179 }
5180
5181 /* tlbli */
5182 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5183 {
5184 #if defined(CONFIG_USER_ONLY)
5185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5186 #else
5187 if (unlikely(!ctx->mem_idx)) {
5188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5189 return;
5190 }
5191 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5192 #endif
5193 }
5194
5195 /* POWER instructions not in PowerPC 601 */
5196 /* clf */
5197 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5198 {
5199 /* Cache line flush: implemented as no-op */
5200 }
5201
5202 /* cli */
5203 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5204 {
5205 /* Cache line invalidate: privileged and treated as no-op */
5206 #if defined(CONFIG_USER_ONLY)
5207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5208 #else
5209 if (unlikely(!ctx->mem_idx)) {
5210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5211 return;
5212 }
5213 #endif
5214 }
5215
5216 /* dclst */
5217 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5218 {
5219 /* Data cache line store: treated as no-op */
5220 }
5221
5222 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5223 {
5224 #if defined(CONFIG_USER_ONLY)
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 #else
5227 int ra = rA(ctx->opcode);
5228 int rd = rD(ctx->opcode);
5229 TCGv t0;
5230 if (unlikely(!ctx->mem_idx)) {
5231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5232 return;
5233 }
5234 t0 = tcg_temp_new();
5235 gen_addr_reg_index(ctx, t0);
5236 tcg_gen_shri_tl(t0, t0, 28);
5237 tcg_gen_andi_tl(t0, t0, 0xF);
5238 gen_helper_load_sr(cpu_gpr[rd], t0);
5239 tcg_temp_free(t0);
5240 if (ra != 0 && ra != rd)
5241 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5242 #endif
5243 }
5244
5245 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5246 {
5247 #if defined(CONFIG_USER_ONLY)
5248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5249 #else
5250 TCGv t0;
5251 if (unlikely(!ctx->mem_idx)) {
5252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5253 return;
5254 }
5255 t0 = tcg_temp_new();
5256 gen_addr_reg_index(ctx, t0);
5257 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5258 tcg_temp_free(t0);
5259 #endif
5260 }
5261
5262 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5263 {
5264 #if defined(CONFIG_USER_ONLY)
5265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5266 #else
5267 if (unlikely(!ctx->mem_idx)) {
5268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5269 return;
5270 }
5271 gen_helper_rfsvc();
5272 gen_sync_exception(ctx);
5273 #endif
5274 }
5275
5276 /* svc is not implemented for now */
5277
5278 /* POWER2 specific instructions */
5279 /* Quad manipulation (load/store two floats at a time) */
5280
5281 /* lfq */
5282 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5283 {
5284 int rd = rD(ctx->opcode);
5285 TCGv t0;
5286 gen_set_access_type(ctx, ACCESS_FLOAT);
5287 t0 = tcg_temp_new();
5288 gen_addr_imm_index(ctx, t0, 0);
5289 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5290 gen_addr_add(ctx, t0, t0, 8);
5291 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5292 tcg_temp_free(t0);
5293 }
5294
5295 /* lfqu */
5296 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5297 {
5298 int ra = rA(ctx->opcode);
5299 int rd = rD(ctx->opcode);
5300 TCGv t0, t1;
5301 gen_set_access_type(ctx, ACCESS_FLOAT);
5302 t0 = tcg_temp_new();
5303 t1 = tcg_temp_new();
5304 gen_addr_imm_index(ctx, t0, 0);
5305 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5306 gen_addr_add(ctx, t1, t0, 8);
5307 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5308 if (ra != 0)
5309 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5310 tcg_temp_free(t0);
5311 tcg_temp_free(t1);
5312 }
5313
5314 /* lfqux */
5315 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5316 {
5317 int ra = rA(ctx->opcode);
5318 int rd = rD(ctx->opcode);
5319 gen_set_access_type(ctx, ACCESS_FLOAT);
5320 TCGv t0, t1;
5321 t0 = tcg_temp_new();
5322 gen_addr_reg_index(ctx, t0);
5323 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5324 t1 = tcg_temp_new();
5325 gen_addr_add(ctx, t1, t0, 8);
5326 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5327 tcg_temp_free(t1);
5328 if (ra != 0)
5329 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5330 tcg_temp_free(t0);
5331 }
5332
5333 /* lfqx */
5334 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5335 {
5336 int rd = rD(ctx->opcode);
5337 TCGv t0;
5338 gen_set_access_type(ctx, ACCESS_FLOAT);
5339 t0 = tcg_temp_new();
5340 gen_addr_reg_index(ctx, t0);
5341 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5342 gen_addr_add(ctx, t0, t0, 8);
5343 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5344 tcg_temp_free(t0);
5345 }
5346
5347 /* stfq */
5348 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5349 {
5350 int rd = rD(ctx->opcode);
5351 TCGv t0;
5352 gen_set_access_type(ctx, ACCESS_FLOAT);
5353 t0 = tcg_temp_new();
5354 gen_addr_imm_index(ctx, t0, 0);
5355 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5356 gen_addr_add(ctx, t0, t0, 8);
5357 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5358 tcg_temp_free(t0);
5359 }
5360
5361 /* stfqu */
5362 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5363 {
5364 int ra = rA(ctx->opcode);
5365 int rd = rD(ctx->opcode);
5366 TCGv t0, t1;
5367 gen_set_access_type(ctx, ACCESS_FLOAT);
5368 t0 = tcg_temp_new();
5369 gen_addr_imm_index(ctx, t0, 0);
5370 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5371 t1 = tcg_temp_new();
5372 gen_addr_add(ctx, t1, t0, 8);
5373 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5374 tcg_temp_free(t1);
5375 if (ra != 0)
5376 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5377 tcg_temp_free(t0);
5378 }
5379
5380 /* stfqux */
5381 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5382 {
5383 int ra = rA(ctx->opcode);
5384 int rd = rD(ctx->opcode);
5385 TCGv t0, t1;
5386 gen_set_access_type(ctx, ACCESS_FLOAT);
5387 t0 = tcg_temp_new();
5388 gen_addr_reg_index(ctx, t0);
5389 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5390 t1 = tcg_temp_new();
5391 gen_addr_add(ctx, t1, t0, 8);
5392 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5393 tcg_temp_free(t1);
5394 if (ra != 0)
5395 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5396 tcg_temp_free(t0);
5397 }
5398
5399 /* stfqx */
5400 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5401 {
5402 int rd = rD(ctx->opcode);
5403 TCGv t0;
5404 gen_set_access_type(ctx, ACCESS_FLOAT);
5405 t0 = tcg_temp_new();
5406 gen_addr_reg_index(ctx, t0);
5407 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5408 gen_addr_add(ctx, t0, t0, 8);
5409 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5410 tcg_temp_free(t0);
5411 }
5412
5413 /* BookE specific instructions */
5414 /* XXX: not implemented on 440 ? */
5415 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5416 {
5417 /* XXX: TODO */
5418 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5419 }
5420
5421 /* XXX: not implemented on 440 ? */
5422 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5423 {
5424 #if defined(CONFIG_USER_ONLY)
5425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5426 #else
5427 TCGv t0;
5428 if (unlikely(!ctx->mem_idx)) {
5429 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5430 return;
5431 }
5432 t0 = tcg_temp_new();
5433 gen_addr_reg_index(ctx, t0);
5434 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5435 tcg_temp_free(t0);
5436 #endif
5437 }
5438
5439 /* All 405 MAC instructions are translated here */
5440 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5441 int opc2, int opc3,
5442 int ra, int rb, int rt, int Rc)
5443 {
5444 TCGv t0, t1;
5445
5446 t0 = tcg_temp_local_new();
5447 t1 = tcg_temp_local_new();
5448
5449 switch (opc3 & 0x0D) {
5450 case 0x05:
5451 /* macchw - macchw. - macchwo - macchwo. */
5452 /* macchws - macchws. - macchwso - macchwso. */
5453 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5454 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5455 /* mulchw - mulchw. */
5456 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5457 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5458 tcg_gen_ext16s_tl(t1, t1);
5459 break;
5460 case 0x04:
5461 /* macchwu - macchwu. - macchwuo - macchwuo. */
5462 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5463 /* mulchwu - mulchwu. */
5464 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5465 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5466 tcg_gen_ext16u_tl(t1, t1);
5467 break;
5468 case 0x01:
5469 /* machhw - machhw. - machhwo - machhwo. */
5470 /* machhws - machhws. - machhwso - machhwso. */
5471 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5472 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5473 /* mulhhw - mulhhw. */
5474 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5475 tcg_gen_ext16s_tl(t0, t0);
5476 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5477 tcg_gen_ext16s_tl(t1, t1);
5478 break;
5479 case 0x00:
5480 /* machhwu - machhwu. - machhwuo - machhwuo. */
5481 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5482 /* mulhhwu - mulhhwu. */
5483 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5484 tcg_gen_ext16u_tl(t0, t0);
5485 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5486 tcg_gen_ext16u_tl(t1, t1);
5487 break;
5488 case 0x0D:
5489 /* maclhw - maclhw. - maclhwo - maclhwo. */
5490 /* maclhws - maclhws. - maclhwso - maclhwso. */
5491 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5492 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5493 /* mullhw - mullhw. */
5494 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5495 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5496 break;
5497 case 0x0C:
5498 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5499 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5500 /* mullhwu - mullhwu. */
5501 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5502 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5503 break;
5504 }
5505 if (opc2 & 0x04) {
5506 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5507 tcg_gen_mul_tl(t1, t0, t1);
5508 if (opc2 & 0x02) {
5509 /* nmultiply-and-accumulate (0x0E) */
5510 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5511 } else {
5512 /* multiply-and-accumulate (0x0C) */
5513 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5514 }
5515
5516 if (opc3 & 0x12) {
5517 /* Check overflow and/or saturate */
5518 int l1 = gen_new_label();
5519
5520 if (opc3 & 0x10) {
5521 /* Start with XER OV disabled, the most likely case */
5522 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5523 }
5524 if (opc3 & 0x01) {
5525 /* Signed */
5526 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5527 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5528 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5529 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5530 if (opc3 & 0x02) {
5531 /* Saturate */
5532 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5533 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5534 }
5535 } else {
5536 /* Unsigned */
5537 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5538 if (opc3 & 0x02) {
5539 /* Saturate */
5540 tcg_gen_movi_tl(t0, UINT32_MAX);
5541 }
5542 }
5543 if (opc3 & 0x10) {
5544 /* Check overflow */
5545 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5546 }
5547 gen_set_label(l1);
5548 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5549 }
5550 } else {
5551 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5552 }
5553 tcg_temp_free(t0);
5554 tcg_temp_free(t1);
5555 if (unlikely(Rc) != 0) {
5556 /* Update Rc0 */
5557 gen_set_Rc0(ctx, cpu_gpr[rt]);
5558 }
5559 }
5560
5561 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5562 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5563 { \
5564 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5565 rD(ctx->opcode), Rc(ctx->opcode)); \
5566 }
5567
5568 /* macchw - macchw. */
5569 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5570 /* macchwo - macchwo. */
5571 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5572 /* macchws - macchws. */
5573 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5574 /* macchwso - macchwso. */
5575 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5576 /* macchwsu - macchwsu. */
5577 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5578 /* macchwsuo - macchwsuo. */
5579 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5580 /* macchwu - macchwu. */
5581 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5582 /* macchwuo - macchwuo. */
5583 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5584 /* machhw - machhw. */
5585 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5586 /* machhwo - machhwo. */
5587 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5588 /* machhws - machhws. */
5589 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5590 /* machhwso - machhwso. */
5591 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5592 /* machhwsu - machhwsu. */
5593 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5594 /* machhwsuo - machhwsuo. */
5595 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5596 /* machhwu - machhwu. */
5597 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5598 /* machhwuo - machhwuo. */
5599 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5600 /* maclhw - maclhw. */
5601 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5602 /* maclhwo - maclhwo. */
5603 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5604 /* maclhws - maclhws. */
5605 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5606 /* maclhwso - maclhwso. */
5607 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5608 /* maclhwu - maclhwu. */
5609 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5610 /* maclhwuo - maclhwuo. */
5611 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5612 /* maclhwsu - maclhwsu. */
5613 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5614 /* maclhwsuo - maclhwsuo. */
5615 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5616 /* nmacchw - nmacchw. */
5617 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5618 /* nmacchwo - nmacchwo. */
5619 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5620 /* nmacchws - nmacchws. */
5621 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5622 /* nmacchwso - nmacchwso. */
5623 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5624 /* nmachhw - nmachhw. */
5625 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5626 /* nmachhwo - nmachhwo. */
5627 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5628 /* nmachhws - nmachhws. */
5629 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5630 /* nmachhwso - nmachhwso. */
5631 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5632 /* nmaclhw - nmaclhw. */
5633 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5634 /* nmaclhwo - nmaclhwo. */
5635 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5636 /* nmaclhws - nmaclhws. */
5637 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5638 /* nmaclhwso - nmaclhwso. */
5639 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5640
5641 /* mulchw - mulchw. */
5642 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5643 /* mulchwu - mulchwu. */
5644 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5645 /* mulhhw - mulhhw. */
5646 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5647 /* mulhhwu - mulhhwu. */
5648 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5649 /* mullhw - mullhw. */
5650 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5651 /* mullhwu - mullhwu. */
5652 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5653
5654 /* mfdcr */
5655 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5656 {
5657 #if defined(CONFIG_USER_ONLY)
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5659 #else
5660 TCGv dcrn;
5661 if (unlikely(!ctx->mem_idx)) {
5662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5663 return;
5664 }
5665 /* NIP cannot be restored if the memory exception comes from an helper */
5666 gen_update_nip(ctx, ctx->nip - 4);
5667 dcrn = tcg_const_tl(SPR(ctx->opcode));
5668 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5669 tcg_temp_free(dcrn);
5670 #endif
5671 }
5672
5673 /* mtdcr */
5674 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5675 {
5676 #if defined(CONFIG_USER_ONLY)
5677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5678 #else
5679 TCGv dcrn;
5680 if (unlikely(!ctx->mem_idx)) {
5681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5682 return;
5683 }
5684 /* NIP cannot be restored if the memory exception comes from an helper */
5685 gen_update_nip(ctx, ctx->nip - 4);
5686 dcrn = tcg_const_tl(SPR(ctx->opcode));
5687 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5688 tcg_temp_free(dcrn);
5689 #endif
5690 }
5691
5692 /* mfdcrx */
5693 /* XXX: not implemented on 440 ? */
5694 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5695 {
5696 #if defined(CONFIG_USER_ONLY)
5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5698 #else
5699 if (unlikely(!ctx->mem_idx)) {
5700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5701 return;
5702 }
5703 /* NIP cannot be restored if the memory exception comes from an helper */
5704 gen_update_nip(ctx, ctx->nip - 4);
5705 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707 #endif
5708 }
5709
5710 /* mtdcrx */
5711 /* XXX: not implemented on 440 ? */
5712 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5716 #else
5717 if (unlikely(!ctx->mem_idx)) {
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5719 return;
5720 }
5721 /* NIP cannot be restored if the memory exception comes from an helper */
5722 gen_update_nip(ctx, ctx->nip - 4);
5723 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5724 /* Note: Rc update flag set leads to undefined state of Rc0 */
5725 #endif
5726 }
5727
5728 /* mfdcrux (PPC 460) : user-mode access to DCR */
5729 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5730 {
5731 /* NIP cannot be restored if the memory exception comes from an helper */
5732 gen_update_nip(ctx, ctx->nip - 4);
5733 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5734 /* Note: Rc update flag set leads to undefined state of Rc0 */
5735 }
5736
5737 /* mtdcrux (PPC 460) : user-mode access to DCR */
5738 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5739 {
5740 /* NIP cannot be restored if the memory exception comes from an helper */
5741 gen_update_nip(ctx, ctx->nip - 4);
5742 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5743 /* Note: Rc update flag set leads to undefined state of Rc0 */
5744 }
5745
5746 /* dccci */
5747 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5748 {
5749 #if defined(CONFIG_USER_ONLY)
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5751 #else
5752 if (unlikely(!ctx->mem_idx)) {
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 return;
5755 }
5756 /* interpreted as no-op */
5757 #endif
5758 }
5759
5760 /* dcread */
5761 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5762 {
5763 #if defined(CONFIG_USER_ONLY)
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 #else
5766 TCGv EA, val;
5767 if (unlikely(!ctx->mem_idx)) {
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5769 return;
5770 }
5771 gen_set_access_type(ctx, ACCESS_CACHE);
5772 EA = tcg_temp_new();
5773 gen_addr_reg_index(ctx, EA);
5774 val = tcg_temp_new();
5775 gen_qemu_ld32u(ctx, val, EA);
5776 tcg_temp_free(val);
5777 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5778 tcg_temp_free(EA);
5779 #endif
5780 }
5781
5782 /* icbt */
5783 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5784 {
5785 /* interpreted as no-op */
5786 /* XXX: specification say this is treated as a load by the MMU
5787 * but does not generate any exception
5788 */
5789 }
5790
5791 /* iccci */
5792 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5793 {
5794 #if defined(CONFIG_USER_ONLY)
5795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5796 #else
5797 if (unlikely(!ctx->mem_idx)) {
5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5799 return;
5800 }
5801 /* interpreted as no-op */
5802 #endif
5803 }
5804
5805 /* icread */
5806 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5807 {
5808 #if defined(CONFIG_USER_ONLY)
5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5810 #else
5811 if (unlikely(!ctx->mem_idx)) {
5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5813 return;
5814 }
5815 /* interpreted as no-op */
5816 #endif
5817 }
5818
5819 /* rfci (mem_idx only) */
5820 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5821 {
5822 #if defined(CONFIG_USER_ONLY)
5823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5824 #else
5825 if (unlikely(!ctx->mem_idx)) {
5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 return;
5828 }
5829 /* Restore CPU state */
5830 gen_helper_40x_rfci();
5831 gen_sync_exception(ctx);
5832 #endif
5833 }
5834
5835 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5839 #else
5840 if (unlikely(!ctx->mem_idx)) {
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 return;
5843 }
5844 /* Restore CPU state */
5845 gen_helper_rfci();
5846 gen_sync_exception(ctx);
5847 #endif
5848 }
5849
5850 /* BookE specific */
5851 /* XXX: not implemented on 440 ? */
5852 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5853 {
5854 #if defined(CONFIG_USER_ONLY)
5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5856 #else
5857 if (unlikely(!ctx->mem_idx)) {
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 return;
5860 }
5861 /* Restore CPU state */
5862 gen_helper_rfdi();
5863 gen_sync_exception(ctx);
5864 #endif
5865 }
5866
5867 /* XXX: not implemented on 440 ? */
5868 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5872 #else
5873 if (unlikely(!ctx->mem_idx)) {
5874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5875 return;
5876 }
5877 /* Restore CPU state */
5878 gen_helper_rfmci();
5879 gen_sync_exception(ctx);
5880 #endif
5881 }
5882
5883 /* TLB management - PowerPC 405 implementation */
5884 /* tlbre */
5885 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5886 {
5887 #if defined(CONFIG_USER_ONLY)
5888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5889 #else
5890 if (unlikely(!ctx->mem_idx)) {
5891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5892 return;
5893 }
5894 switch (rB(ctx->opcode)) {
5895 case 0:
5896 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5897 break;
5898 case 1:
5899 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5900 break;
5901 default:
5902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5903 break;
5904 }
5905 #endif
5906 }
5907
5908 /* tlbsx - tlbsx. */
5909 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5910 {
5911 #if defined(CONFIG_USER_ONLY)
5912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5913 #else
5914 TCGv t0;
5915 if (unlikely(!ctx->mem_idx)) {
5916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5917 return;
5918 }
5919 t0 = tcg_temp_new();
5920 gen_addr_reg_index(ctx, t0);
5921 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5922 tcg_temp_free(t0);
5923 if (Rc(ctx->opcode)) {
5924 int l1 = gen_new_label();
5925 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5926 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5927 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5928 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5929 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5930 gen_set_label(l1);
5931 }
5932 #endif
5933 }
5934
5935 /* tlbwe */
5936 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5937 {
5938 #if defined(CONFIG_USER_ONLY)
5939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5940 #else
5941 if (unlikely(!ctx->mem_idx)) {
5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5943 return;
5944 }
5945 switch (rB(ctx->opcode)) {
5946 case 0:
5947 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5948 break;
5949 case 1:
5950 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5951 break;
5952 default:
5953 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5954 break;
5955 }
5956 #endif
5957 }
5958
5959 /* TLB management - PowerPC 440 implementation */
5960 /* tlbre */
5961 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5962 {
5963 #if defined(CONFIG_USER_ONLY)
5964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5965 #else
5966 if (unlikely(!ctx->mem_idx)) {
5967 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5968 return;
5969 }
5970 switch (rB(ctx->opcode)) {
5971 case 0:
5972 case 1:
5973 case 2:
5974 {
5975 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5976 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5977 tcg_temp_free_i32(t0);
5978 }
5979 break;
5980 default:
5981 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5982 break;
5983 }
5984 #endif
5985 }
5986
5987 /* tlbsx - tlbsx. */
5988 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5989 {
5990 #if defined(CONFIG_USER_ONLY)
5991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5992 #else
5993 TCGv t0;
5994 if (unlikely(!ctx->mem_idx)) {
5995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5996 return;
5997 }
5998 t0 = tcg_temp_new();
5999 gen_addr_reg_index(ctx, t0);
6000 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6001 tcg_temp_free(t0);
6002 if (Rc(ctx->opcode)) {
6003 int l1 = gen_new_label();
6004 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6005 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6006 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6007 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6008 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6009 gen_set_label(l1);
6010 }
6011 #endif
6012 }
6013
6014 /* tlbwe */
6015 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
6016 {
6017 #if defined(CONFIG_USER_ONLY)
6018 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6019 #else
6020 if (unlikely(!ctx->mem_idx)) {
6021 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6022 return;
6023 }
6024 switch (rB(ctx->opcode)) {
6025 case 0:
6026 case 1:
6027 case 2:
6028 {
6029 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6030 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6031 tcg_temp_free_i32(t0);
6032 }
6033 break;
6034 default:
6035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6036 break;
6037 }
6038 #endif
6039 }
6040
6041 /* wrtee */
6042 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6046 #else
6047 TCGv t0;
6048 if (unlikely(!ctx->mem_idx)) {
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 return;
6051 }
6052 t0 = tcg_temp_new();
6053 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6054 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6055 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6056 tcg_temp_free(t0);
6057 /* Stop translation to have a chance to raise an exception
6058 * if we just set msr_ee to 1
6059 */
6060 gen_stop_exception(ctx);
6061 #endif
6062 }
6063
6064 /* wrteei */
6065 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6066 {
6067 #if defined(CONFIG_USER_ONLY)
6068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6069 #else
6070 if (unlikely(!ctx->mem_idx)) {
6071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6072 return;
6073 }
6074 if (ctx->opcode & 0x00010000) {
6075 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6076 /* Stop translation to have a chance to raise an exception */
6077 gen_stop_exception(ctx);
6078 } else {
6079 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6080 }
6081 #endif
6082 }
6083
6084 /* PowerPC 440 specific instructions */
6085 /* dlmzb */
6086 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6087 {
6088 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6089 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6090 cpu_gpr[rB(ctx->opcode)], t0);
6091 tcg_temp_free_i32(t0);
6092 }
6093
6094 /* mbar replaces eieio on 440 */
6095 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6096 {
6097 /* interpreted as no-op */
6098 }
6099
6100 /* msync replaces sync on 440 */
6101 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6102 {
6103 /* interpreted as no-op */
6104 }
6105
6106 /* icbt */
6107 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6108 {
6109 /* interpreted as no-op */
6110 /* XXX: specification say this is treated as a load by the MMU
6111 * but does not generate any exception
6112 */
6113 }
6114
6115 /*** Altivec vector extension ***/
6116 /* Altivec registers moves */
6117
6118 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6119 {
6120 TCGv_ptr r = tcg_temp_new_ptr();
6121 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6122 return r;
6123 }
6124
6125 #define GEN_VR_LDX(name, opc2, opc3) \
6126 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6127 { \
6128 TCGv EA; \
6129 if (unlikely(!ctx->altivec_enabled)) { \
6130 gen_exception(ctx, POWERPC_EXCP_VPU); \
6131 return; \
6132 } \
6133 gen_set_access_type(ctx, ACCESS_INT); \
6134 EA = tcg_temp_new(); \
6135 gen_addr_reg_index(ctx, EA); \
6136 tcg_gen_andi_tl(EA, EA, ~0xf); \
6137 if (ctx->le_mode) { \
6138 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6139 tcg_gen_addi_tl(EA, EA, 8); \
6140 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6141 } else { \
6142 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6143 tcg_gen_addi_tl(EA, EA, 8); \
6144 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6145 } \
6146 tcg_temp_free(EA); \
6147 }
6148
6149 #define GEN_VR_STX(name, opc2, opc3) \
6150 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6151 { \
6152 TCGv EA; \
6153 if (unlikely(!ctx->altivec_enabled)) { \
6154 gen_exception(ctx, POWERPC_EXCP_VPU); \
6155 return; \
6156 } \
6157 gen_set_access_type(ctx, ACCESS_INT); \
6158 EA = tcg_temp_new(); \
6159 gen_addr_reg_index(ctx, EA); \
6160 tcg_gen_andi_tl(EA, EA, ~0xf); \
6161 if (ctx->le_mode) { \
6162 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6163 tcg_gen_addi_tl(EA, EA, 8); \
6164 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6165 } else { \
6166 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6167 tcg_gen_addi_tl(EA, EA, 8); \
6168 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6169 } \
6170 tcg_temp_free(EA); \
6171 }
6172
6173 #define GEN_VR_LVE(name, opc2, opc3) \
6174 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6175 { \
6176 TCGv EA; \
6177 TCGv_ptr rs; \
6178 if (unlikely(!ctx->altivec_enabled)) { \
6179 gen_exception(ctx, POWERPC_EXCP_VPU); \
6180 return; \
6181 } \
6182 gen_set_access_type(ctx, ACCESS_INT); \
6183 EA = tcg_temp_new(); \
6184 gen_addr_reg_index(ctx, EA); \
6185 rs = gen_avr_ptr(rS(ctx->opcode)); \
6186 gen_helper_lve##name (rs, EA); \
6187 tcg_temp_free(EA); \
6188 tcg_temp_free_ptr(rs); \
6189 }
6190
6191 #define GEN_VR_STVE(name, opc2, opc3) \
6192 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6193 { \
6194 TCGv EA; \
6195 TCGv_ptr rs; \
6196 if (unlikely(!ctx->altivec_enabled)) { \
6197 gen_exception(ctx, POWERPC_EXCP_VPU); \
6198 return; \
6199 } \
6200 gen_set_access_type(ctx, ACCESS_INT); \
6201 EA = tcg_temp_new(); \
6202 gen_addr_reg_index(ctx, EA); \
6203 rs = gen_avr_ptr(rS(ctx->opcode)); \
6204 gen_helper_stve##name (rs, EA); \
6205 tcg_temp_free(EA); \
6206 tcg_temp_free_ptr(rs); \
6207 }
6208
6209 GEN_VR_LDX(lvx, 0x07, 0x03);
6210 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6211 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6212
6213 GEN_VR_LVE(bx, 0x07, 0x00);
6214 GEN_VR_LVE(hx, 0x07, 0x01);
6215 GEN_VR_LVE(wx, 0x07, 0x02);
6216
6217 GEN_VR_STX(svx, 0x07, 0x07);
6218 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6219 GEN_VR_STX(svxl, 0x07, 0x0F);
6220
6221 GEN_VR_STVE(bx, 0x07, 0x04);
6222 GEN_VR_STVE(hx, 0x07, 0x05);
6223 GEN_VR_STVE(wx, 0x07, 0x06);
6224
6225 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6226 {
6227 TCGv_ptr rd;
6228 TCGv EA;
6229 if (unlikely(!ctx->altivec_enabled)) {
6230 gen_exception(ctx, POWERPC_EXCP_VPU);
6231 return;
6232 }
6233 EA = tcg_temp_new();
6234 gen_addr_reg_index(ctx, EA);
6235 rd = gen_avr_ptr(rD(ctx->opcode));
6236 gen_helper_lvsl(rd, EA);
6237 tcg_temp_free(EA);
6238 tcg_temp_free_ptr(rd);
6239 }
6240
6241 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6242 {
6243 TCGv_ptr rd;
6244 TCGv EA;
6245 if (unlikely(!ctx->altivec_enabled)) {
6246 gen_exception(ctx, POWERPC_EXCP_VPU);
6247 return;
6248 }
6249 EA = tcg_temp_new();
6250 gen_addr_reg_index(ctx, EA);
6251 rd = gen_avr_ptr(rD(ctx->opcode));
6252 gen_helper_lvsr(rd, EA);
6253 tcg_temp_free(EA);
6254 tcg_temp_free_ptr(rd);
6255 }
6256
6257 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6258 {
6259 TCGv_i32 t;
6260 if (unlikely(!ctx->altivec_enabled)) {
6261 gen_exception(ctx, POWERPC_EXCP_VPU);
6262 return;
6263 }
6264 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6265 t = tcg_temp_new_i32();
6266 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6267 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6268 tcg_temp_free_i32(t);
6269 }
6270
6271 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6272 {
6273 TCGv_ptr p;
6274 if (unlikely(!ctx->altivec_enabled)) {
6275 gen_exception(ctx, POWERPC_EXCP_VPU);
6276 return;
6277 }
6278 p = gen_avr_ptr(rD(ctx->opcode));
6279 gen_helper_mtvscr(p);
6280 tcg_temp_free_ptr(p);
6281 }
6282
6283 /* Logical operations */
6284 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6285 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6286 { \
6287 if (unlikely(!ctx->altivec_enabled)) { \
6288 gen_exception(ctx, POWERPC_EXCP_VPU); \
6289 return; \
6290 } \
6291 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6292 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6293 }
6294
6295 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6296 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6297 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6298 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6299 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6300
6301 #define GEN_VXFORM(name, opc2, opc3) \
6302 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6303 { \
6304 TCGv_ptr ra, rb, rd; \
6305 if (unlikely(!ctx->altivec_enabled)) { \
6306 gen_exception(ctx, POWERPC_EXCP_VPU); \
6307 return; \
6308 } \
6309 ra = gen_avr_ptr(rA(ctx->opcode)); \
6310 rb = gen_avr_ptr(rB(ctx->opcode)); \
6311 rd = gen_avr_ptr(rD(ctx->opcode)); \
6312 gen_helper_##name (rd, ra, rb); \
6313 tcg_temp_free_ptr(ra); \
6314 tcg_temp_free_ptr(rb); \
6315 tcg_temp_free_ptr(rd); \
6316 }
6317
6318 GEN_VXFORM(vaddubm, 0, 0);
6319 GEN_VXFORM(vadduhm, 0, 1);
6320 GEN_VXFORM(vadduwm, 0, 2);
6321 GEN_VXFORM(vsububm, 0, 16);
6322 GEN_VXFORM(vsubuhm, 0, 17);
6323 GEN_VXFORM(vsubuwm, 0, 18);
6324 GEN_VXFORM(vmaxub, 1, 0);
6325 GEN_VXFORM(vmaxuh, 1, 1);
6326 GEN_VXFORM(vmaxuw, 1, 2);
6327 GEN_VXFORM(vmaxsb, 1, 4);
6328 GEN_VXFORM(vmaxsh, 1, 5);
6329 GEN_VXFORM(vmaxsw, 1, 6);
6330 GEN_VXFORM(vminub, 1, 8);
6331 GEN_VXFORM(vminuh, 1, 9);
6332 GEN_VXFORM(vminuw, 1, 10);
6333 GEN_VXFORM(vminsb, 1, 12);
6334 GEN_VXFORM(vminsh, 1, 13);
6335 GEN_VXFORM(vminsw, 1, 14);
6336 GEN_VXFORM(vavgub, 1, 16);
6337 GEN_VXFORM(vavguh, 1, 17);
6338 GEN_VXFORM(vavguw, 1, 18);
6339 GEN_VXFORM(vavgsb, 1, 20);
6340 GEN_VXFORM(vavgsh, 1, 21);
6341 GEN_VXFORM(vavgsw, 1, 22);
6342 GEN_VXFORM(vmrghb, 6, 0);
6343 GEN_VXFORM(vmrghh, 6, 1);
6344 GEN_VXFORM(vmrghw, 6, 2);
6345 GEN_VXFORM(vmrglb, 6, 4);
6346 GEN_VXFORM(vmrglh, 6, 5);
6347 GEN_VXFORM(vmrglw, 6, 6);
6348 GEN_VXFORM(vmuloub, 4, 0);
6349 GEN_VXFORM(vmulouh, 4, 1);
6350 GEN_VXFORM(vmulosb, 4, 4);
6351 GEN_VXFORM(vmulosh, 4, 5);
6352 GEN_VXFORM(vmuleub, 4, 8);
6353 GEN_VXFORM(vmuleuh, 4, 9);
6354 GEN_VXFORM(vmulesb, 4, 12);
6355 GEN_VXFORM(vmulesh, 4, 13);
6356 GEN_VXFORM(vslb, 2, 4);
6357 GEN_VXFORM(vslh, 2, 5);
6358 GEN_VXFORM(vslw, 2, 6);
6359 GEN_VXFORM(vsrb, 2, 8);
6360 GEN_VXFORM(vsrh, 2, 9);
6361 GEN_VXFORM(vsrw, 2, 10);
6362 GEN_VXFORM(vsrab, 2, 12);
6363 GEN_VXFORM(vsrah, 2, 13);
6364 GEN_VXFORM(vsraw, 2, 14);
6365 GEN_VXFORM(vslo, 6, 16);
6366 GEN_VXFORM(vsro, 6, 17);
6367 GEN_VXFORM(vaddcuw, 0, 6);
6368 GEN_VXFORM(vsubcuw, 0, 22);
6369 GEN_VXFORM(vaddubs, 0, 8);
6370 GEN_VXFORM(vadduhs, 0, 9);
6371 GEN_VXFORM(vadduws, 0, 10);
6372 GEN_VXFORM(vaddsbs, 0, 12);
6373 GEN_VXFORM(vaddshs, 0, 13);
6374 GEN_VXFORM(vaddsws, 0, 14);
6375 GEN_VXFORM(vsububs, 0, 24);
6376 GEN_VXFORM(vsubuhs, 0, 25);
6377 GEN_VXFORM(vsubuws, 0, 26);
6378 GEN_VXFORM(vsubsbs, 0, 28);
6379 GEN_VXFORM(vsubshs, 0, 29);
6380 GEN_VXFORM(vsubsws, 0, 30);
6381 GEN_VXFORM(vrlb, 2, 0);
6382 GEN_VXFORM(vrlh, 2, 1);
6383 GEN_VXFORM(vrlw, 2, 2);
6384 GEN_VXFORM(vsl, 2, 7);
6385 GEN_VXFORM(vsr, 2, 11);
6386 GEN_VXFORM(vpkuhum, 7, 0);
6387 GEN_VXFORM(vpkuwum, 7, 1);
6388 GEN_VXFORM(vpkuhus, 7, 2);
6389 GEN_VXFORM(vpkuwus, 7, 3);
6390 GEN_VXFORM(vpkshus, 7, 4);
6391 GEN_VXFORM(vpkswus, 7, 5);
6392 GEN_VXFORM(vpkshss, 7, 6);
6393 GEN_VXFORM(vpkswss, 7, 7);
6394 GEN_VXFORM(vpkpx, 7, 12);
6395 GEN_VXFORM(vsum4ubs, 4, 24);
6396 GEN_VXFORM(vsum4sbs, 4, 28);
6397 GEN_VXFORM(vsum4shs, 4, 25);
6398 GEN_VXFORM(vsum2sws, 4, 26);
6399 GEN_VXFORM(vsumsws, 4, 30);
6400 GEN_VXFORM(vaddfp, 5, 0);
6401 GEN_VXFORM(vsubfp, 5, 1);
6402 GEN_VXFORM(vmaxfp, 5, 16);
6403 GEN_VXFORM(vminfp, 5, 17);
6404
6405 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6406 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6407 { \
6408 TCGv_ptr ra, rb, rd; \
6409 if (unlikely(!ctx->altivec_enabled)) { \
6410 gen_exception(ctx, POWERPC_EXCP_VPU); \
6411 return; \
6412 } \
6413 ra = gen_avr_ptr(rA(ctx->opcode)); \
6414 rb = gen_avr_ptr(rB(ctx->opcode)); \
6415 rd = gen_avr_ptr(rD(ctx->opcode)); \
6416 gen_helper_##opname (rd, ra, rb); \
6417 tcg_temp_free_ptr(ra); \
6418 tcg_temp_free_ptr(rb); \
6419 tcg_temp_free_ptr(rd); \
6420 }
6421
6422 #define GEN_VXRFORM(name, opc2, opc3) \
6423 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6424 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6425
6426 GEN_VXRFORM(vcmpequb, 3, 0)
6427 GEN_VXRFORM(vcmpequh, 3, 1)
6428 GEN_VXRFORM(vcmpequw, 3, 2)
6429 GEN_VXRFORM(vcmpgtsb, 3, 12)
6430 GEN_VXRFORM(vcmpgtsh, 3, 13)
6431 GEN_VXRFORM(vcmpgtsw, 3, 14)
6432 GEN_VXRFORM(vcmpgtub, 3, 8)
6433 GEN_VXRFORM(vcmpgtuh, 3, 9)
6434 GEN_VXRFORM(vcmpgtuw, 3, 10)
6435 GEN_VXRFORM(vcmpeqfp, 3, 3)
6436 GEN_VXRFORM(vcmpgefp, 3, 7)
6437 GEN_VXRFORM(vcmpgtfp, 3, 11)
6438 GEN_VXRFORM(vcmpbfp, 3, 15)
6439
6440 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6441 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6442 { \
6443 TCGv_ptr rd; \
6444 TCGv_i32 simm; \
6445 if (unlikely(!ctx->altivec_enabled)) { \
6446 gen_exception(ctx, POWERPC_EXCP_VPU); \
6447 return; \
6448 } \
6449 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6450 rd = gen_avr_ptr(rD(ctx->opcode)); \
6451 gen_helper_##name (rd, simm); \
6452 tcg_temp_free_i32(simm); \
6453 tcg_temp_free_ptr(rd); \
6454 }
6455
6456 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6457 GEN_VXFORM_SIMM(vspltish, 6, 13);
6458 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6459
6460 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6461 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6462 { \
6463 TCGv_ptr rb, rd; \
6464 if (unlikely(!ctx->altivec_enabled)) { \
6465 gen_exception(ctx, POWERPC_EXCP_VPU); \
6466 return; \
6467 } \
6468 rb = gen_avr_ptr(rB(ctx->opcode)); \
6469 rd = gen_avr_ptr(rD(ctx->opcode)); \
6470 gen_helper_##name (rd, rb); \
6471 tcg_temp_free_ptr(rb); \
6472 tcg_temp_free_ptr(rd); \
6473 }
6474
6475 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6476 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6477 GEN_VXFORM_NOA(vupklsb, 7, 10);
6478 GEN_VXFORM_NOA(vupklsh, 7, 11);
6479 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6480 GEN_VXFORM_NOA(vupklpx, 7, 15);
6481 GEN_VXFORM_NOA(vrefp, 5, 4);
6482 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6483 GEN_VXFORM_NOA(vlogefp, 5, 7);
6484 GEN_VXFORM_NOA(vrfim, 5, 8);
6485 GEN_VXFORM_NOA(vrfin, 5, 9);
6486 GEN_VXFORM_NOA(vrfip, 5, 10);
6487 GEN_VXFORM_NOA(vrfiz, 5, 11);
6488
6489 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6490 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6491 { \
6492 TCGv_ptr rd; \
6493 TCGv_i32 simm; \
6494 if (unlikely(!ctx->altivec_enabled)) { \
6495 gen_exception(ctx, POWERPC_EXCP_VPU); \
6496 return; \
6497 } \
6498 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6499 rd = gen_avr_ptr(rD(ctx->opcode)); \
6500 gen_helper_##name (rd, simm); \
6501 tcg_temp_free_i32(simm); \
6502 tcg_temp_free_ptr(rd); \
6503 }
6504
6505 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6506 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6507 { \
6508 TCGv_ptr rb, rd; \
6509 TCGv_i32 uimm; \
6510 if (unlikely(!ctx->altivec_enabled)) { \
6511 gen_exception(ctx, POWERPC_EXCP_VPU); \
6512 return; \
6513 } \
6514 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6515 rb = gen_avr_ptr(rB(ctx->opcode)); \
6516 rd = gen_avr_ptr(rD(ctx->opcode)); \
6517 gen_helper_##name (rd, rb, uimm); \
6518 tcg_temp_free_i32(uimm); \
6519 tcg_temp_free_ptr(rb); \
6520 tcg_temp_free_ptr(rd); \
6521 }
6522
6523 GEN_VXFORM_UIMM(vspltb, 6, 8);
6524 GEN_VXFORM_UIMM(vsplth, 6, 9);
6525 GEN_VXFORM_UIMM(vspltw, 6, 10);
6526 GEN_VXFORM_UIMM(vcfux, 5, 12);
6527 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6528 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6529 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6530
6531 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6532 {
6533 TCGv_ptr ra, rb, rd;
6534 TCGv_i32 sh;
6535 if (unlikely(!ctx->altivec_enabled)) {
6536 gen_exception(ctx, POWERPC_EXCP_VPU);
6537 return;
6538 }
6539 ra = gen_avr_ptr(rA(ctx->opcode));
6540 rb = gen_avr_ptr(rB(ctx->opcode));
6541 rd = gen_avr_ptr(rD(ctx->opcode));
6542 sh = tcg_const_i32(VSH(ctx->opcode));
6543 gen_helper_vsldoi (rd, ra, rb, sh);
6544 tcg_temp_free_ptr(ra);
6545 tcg_temp_free_ptr(rb);
6546 tcg_temp_free_ptr(rd);
6547 tcg_temp_free_i32(sh);
6548 }
6549
6550 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6551 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6552 { \
6553 TCGv_ptr ra, rb, rc, rd; \
6554 if (unlikely(!ctx->altivec_enabled)) { \
6555 gen_exception(ctx, POWERPC_EXCP_VPU); \
6556 return; \
6557 } \
6558 ra = gen_avr_ptr(rA(ctx->opcode)); \
6559 rb = gen_avr_ptr(rB(ctx->opcode)); \
6560 rc = gen_avr_ptr(rC(ctx->opcode)); \
6561 rd = gen_avr_ptr(rD(ctx->opcode)); \
6562 if (Rc(ctx->opcode)) { \
6563 gen_helper_##name1 (rd, ra, rb, rc); \
6564 } else { \
6565 gen_helper_##name0 (rd, ra, rb, rc); \
6566 } \
6567 tcg_temp_free_ptr(ra); \
6568 tcg_temp_free_ptr(rb); \
6569 tcg_temp_free_ptr(rc); \
6570 tcg_temp_free_ptr(rd); \
6571 }
6572
6573 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6574
6575 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6576 {
6577 TCGv_ptr ra, rb, rc, rd;
6578 if (unlikely(!ctx->altivec_enabled)) {
6579 gen_exception(ctx, POWERPC_EXCP_VPU);
6580 return;
6581 }
6582 ra = gen_avr_ptr(rA(ctx->opcode));
6583 rb = gen_avr_ptr(rB(ctx->opcode));
6584 rc = gen_avr_ptr(rC(ctx->opcode));
6585 rd = gen_avr_ptr(rD(ctx->opcode));
6586 gen_helper_vmladduhm(rd, ra, rb, rc);
6587 tcg_temp_free_ptr(ra);
6588 tcg_temp_free_ptr(rb);
6589 tcg_temp_free_ptr(rc);
6590 tcg_temp_free_ptr(rd);
6591 }
6592
6593 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6594 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6595 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6596 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6597 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6598
6599 /*** SPE extension ***/
6600 /* Register moves */
6601
6602 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6603 #if defined(TARGET_PPC64)
6604 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6605 #else
6606 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6607 #endif
6608 }
6609
6610 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6611 #if defined(TARGET_PPC64)
6612 tcg_gen_mov_i64(cpu_gpr[reg], t);
6613 #else
6614 TCGv_i64 tmp = tcg_temp_new_i64();
6615 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6616 tcg_gen_shri_i64(tmp, t, 32);
6617 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6618 tcg_temp_free_i64(tmp);
6619 #endif
6620 }
6621
6622 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6623 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6624 { \
6625 if (Rc(ctx->opcode)) \
6626 gen_##name1(ctx); \
6627 else \
6628 gen_##name0(ctx); \
6629 }
6630
6631 /* Handler for undefined SPE opcodes */
6632 static always_inline void gen_speundef (DisasContext *ctx)
6633 {
6634 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6635 }
6636
6637 /* SPE logic */
6638 #if defined(TARGET_PPC64)
6639 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6640 static always_inline void gen_##name (DisasContext *ctx) \
6641 { \
6642 if (unlikely(!ctx->spe_enabled)) { \
6643 gen_exception(ctx, POWERPC_EXCP_APU); \
6644 return; \
6645 } \
6646 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6647 cpu_gpr[rB(ctx->opcode)]); \
6648 }
6649 #else
6650 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6651 static always_inline void gen_##name (DisasContext *ctx) \
6652 { \
6653 if (unlikely(!ctx->spe_enabled)) { \
6654 gen_exception(ctx, POWERPC_EXCP_APU); \
6655 return; \
6656 } \
6657 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6658 cpu_gpr[rB(ctx->opcode)]); \
6659 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6660 cpu_gprh[rB(ctx->opcode)]); \
6661 }
6662 #endif
6663
6664 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6665 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6666 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6667 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6668 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6669 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6670 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6671 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6672
6673 /* SPE logic immediate */
6674 #if defined(TARGET_PPC64)
6675 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6676 static always_inline void gen_##name (DisasContext *ctx) \
6677 { \
6678 if (unlikely(!ctx->spe_enabled)) { \
6679 gen_exception(ctx, POWERPC_EXCP_APU); \
6680 return; \
6681 } \
6682 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6683 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6684 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6685 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6686 tcg_opi(t0, t0, rB(ctx->opcode)); \
6687 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6688 tcg_gen_trunc_i64_i32(t1, t2); \
6689 tcg_temp_free_i64(t2); \
6690 tcg_opi(t1, t1, rB(ctx->opcode)); \
6691 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6692 tcg_temp_free_i32(t0); \
6693 tcg_temp_free_i32(t1); \
6694 }
6695 #else
6696 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6697 static always_inline void gen_##name (DisasContext *ctx) \
6698 { \
6699 if (unlikely(!ctx->spe_enabled)) { \
6700 gen_exception(ctx, POWERPC_EXCP_APU); \
6701 return; \
6702 } \
6703 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6704 rB(ctx->opcode)); \
6705 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6706 rB(ctx->opcode)); \
6707 }
6708 #endif
6709 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6710 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6711 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6712 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6713
6714 /* SPE arithmetic */
6715 #if defined(TARGET_PPC64)
6716 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6717 static always_inline void gen_##name (DisasContext *ctx) \
6718 { \
6719 if (unlikely(!ctx->spe_enabled)) { \
6720 gen_exception(ctx, POWERPC_EXCP_APU); \
6721 return; \
6722 } \
6723 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6724 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6725 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6726 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6727 tcg_op(t0, t0); \
6728 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6729 tcg_gen_trunc_i64_i32(t1, t2); \
6730 tcg_temp_free_i64(t2); \
6731 tcg_op(t1, t1); \
6732 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6733 tcg_temp_free_i32(t0); \
6734 tcg_temp_free_i32(t1); \
6735 }
6736 #else
6737 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6738 static always_inline void gen_##name (DisasContext *ctx) \
6739 { \
6740 if (unlikely(!ctx->spe_enabled)) { \
6741 gen_exception(ctx, POWERPC_EXCP_APU); \
6742 return; \
6743 } \
6744 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6745 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6746 }
6747 #endif
6748
6749 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6750 {
6751 int l1 = gen_new_label();
6752 int l2 = gen_new_label();
6753
6754 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6755 tcg_gen_neg_i32(ret, arg1);
6756 tcg_gen_br(l2);
6757 gen_set_label(l1);
6758 tcg_gen_mov_i32(ret, arg1);
6759 gen_set_label(l2);
6760 }
6761 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6762 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6763 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6764 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6765 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6766 {
6767 tcg_gen_addi_i32(ret, arg1, 0x8000);
6768 tcg_gen_ext16u_i32(ret, ret);
6769 }
6770 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6771 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6772 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6773
6774 #if defined(TARGET_PPC64)
6775 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6776 static always_inline void gen_##name (DisasContext *ctx) \
6777 { \
6778 if (unlikely(!ctx->spe_enabled)) { \
6779 gen_exception(ctx, POWERPC_EXCP_APU); \
6780 return; \
6781 } \
6782 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6783 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6784 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6785 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6786 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6787 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6788 tcg_op(t0, t0, t2); \
6789 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6790 tcg_gen_trunc_i64_i32(t1, t3); \
6791 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6792 tcg_gen_trunc_i64_i32(t2, t3); \
6793 tcg_temp_free_i64(t3); \
6794 tcg_op(t1, t1, t2); \
6795 tcg_temp_free_i32(t2); \
6796 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6797 tcg_temp_free_i32(t0); \
6798 tcg_temp_free_i32(t1); \
6799 }
6800 #else
6801 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6802 static always_inline void gen_##name (DisasContext *ctx) \
6803 { \
6804 if (unlikely(!ctx->spe_enabled)) { \
6805 gen_exception(ctx, POWERPC_EXCP_APU); \
6806 return; \
6807 } \
6808 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6809 cpu_gpr[rB(ctx->opcode)]); \
6810 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6811 cpu_gprh[rB(ctx->opcode)]); \
6812 }
6813 #endif
6814
6815 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6816 {
6817 TCGv_i32 t0;
6818 int l1, l2;
6819
6820 l1 = gen_new_label();
6821 l2 = gen_new_label();
6822 t0 = tcg_temp_local_new_i32();
6823 /* No error here: 6 bits are used */
6824 tcg_gen_andi_i32(t0, arg2, 0x3F);
6825 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6826 tcg_gen_shr_i32(ret, arg1, t0);
6827 tcg_gen_br(l2);
6828 gen_set_label(l1);
6829 tcg_gen_movi_i32(ret, 0);
6830 tcg_gen_br(l2);
6831 tcg_temp_free_i32(t0);
6832 }
6833 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6834 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6835 {
6836 TCGv_i32 t0;
6837 int l1, l2;
6838
6839 l1 = gen_new_label();
6840 l2 = gen_new_label();
6841 t0 = tcg_temp_local_new_i32();
6842 /* No error here: 6 bits are used */
6843 tcg_gen_andi_i32(t0, arg2, 0x3F);
6844 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6845 tcg_gen_sar_i32(ret, arg1, t0);
6846 tcg_gen_br(l2);
6847 gen_set_label(l1);
6848 tcg_gen_movi_i32(ret, 0);
6849 tcg_gen_br(l2);
6850 tcg_temp_free_i32(t0);
6851 }
6852 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6853 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6854 {
6855 TCGv_i32 t0;
6856 int l1, l2;
6857
6858 l1 = gen_new_label();
6859 l2 = gen_new_label();
6860 t0 = tcg_temp_local_new_i32();
6861 /* No error here: 6 bits are used */
6862 tcg_gen_andi_i32(t0, arg2, 0x3F);
6863 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6864 tcg_gen_shl_i32(ret, arg1, t0);
6865 tcg_gen_br(l2);
6866 gen_set_label(l1);
6867 tcg_gen_movi_i32(ret, 0);
6868 tcg_gen_br(l2);
6869 tcg_temp_free_i32(t0);
6870 }
6871 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6872 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6873 {
6874 TCGv_i32 t0 = tcg_temp_new_i32();
6875 tcg_gen_andi_i32(t0, arg2, 0x1F);
6876 tcg_gen_rotl_i32(ret, arg1, t0);
6877 tcg_temp_free_i32(t0);
6878 }
6879 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6880 static always_inline void gen_evmergehi (DisasContext *ctx)
6881 {
6882 if (unlikely(!ctx->spe_enabled)) {
6883 gen_exception(ctx, POWERPC_EXCP_APU);
6884 return;
6885 }
6886 #if defined(TARGET_PPC64)
6887 TCGv t0 = tcg_temp_new();
6888 TCGv t1 = tcg_temp_new();
6889 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6890 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6891 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6892 tcg_temp_free(t0);
6893 tcg_temp_free(t1);
6894 #else
6895 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6896 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6897 #endif
6898 }
6899 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6900 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6901 {
6902 tcg_gen_sub_i32(ret, arg2, arg1);
6903 }
6904 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6905
6906 /* SPE arithmetic immediate */
6907 #if defined(TARGET_PPC64)
6908 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6909 static always_inline void gen_##name (DisasContext *ctx) \
6910 { \
6911 if (unlikely(!ctx->spe_enabled)) { \
6912 gen_exception(ctx, POWERPC_EXCP_APU); \
6913 return; \
6914 } \
6915 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6916 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6917 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6918 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6919 tcg_op(t0, t0, rA(ctx->opcode)); \
6920 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6921 tcg_gen_trunc_i64_i32(t1, t2); \
6922 tcg_temp_free_i64(t2); \
6923 tcg_op(t1, t1, rA(ctx->opcode)); \
6924 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6925 tcg_temp_free_i32(t0); \
6926 tcg_temp_free_i32(t1); \
6927 }
6928 #else
6929 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6930 static always_inline void gen_##name (DisasContext *ctx) \
6931 { \
6932 if (unlikely(!ctx->spe_enabled)) { \
6933 gen_exception(ctx, POWERPC_EXCP_APU); \
6934 return; \
6935 } \
6936 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6937 rA(ctx->opcode)); \
6938 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6939 rA(ctx->opcode)); \
6940 }
6941 #endif
6942 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6943 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6944
6945 /* SPE comparison */
6946 #if defined(TARGET_PPC64)
6947 #define GEN_SPEOP_COMP(name, tcg_cond) \
6948 static always_inline void gen_##name (DisasContext *ctx) \
6949 { \
6950 if (unlikely(!ctx->spe_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_APU); \
6952 return; \
6953 } \
6954 int l1 = gen_new_label(); \
6955 int l2 = gen_new_label(); \
6956 int l3 = gen_new_label(); \
6957 int l4 = gen_new_label(); \
6958 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6959 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6960 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6961 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6962 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6963 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6964 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6965 tcg_gen_br(l2); \
6966 gen_set_label(l1); \
6967 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6968 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6969 gen_set_label(l2); \
6970 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6971 tcg_gen_trunc_i64_i32(t0, t2); \
6972 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6973 tcg_gen_trunc_i64_i32(t1, t2); \
6974 tcg_temp_free_i64(t2); \
6975 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6976 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6977 ~(CRF_CH | CRF_CH_AND_CL)); \
6978 tcg_gen_br(l4); \
6979 gen_set_label(l3); \
6980 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6981 CRF_CH | CRF_CH_OR_CL); \
6982 gen_set_label(l4); \
6983 tcg_temp_free_i32(t0); \
6984 tcg_temp_free_i32(t1); \
6985 }
6986 #else
6987 #define GEN_SPEOP_COMP(name, tcg_cond) \
6988 static always_inline void gen_##name (DisasContext *ctx) \
6989 { \
6990 if (unlikely(!ctx->spe_enabled)) { \
6991 gen_exception(ctx, POWERPC_EXCP_APU); \
6992 return; \
6993 } \
6994 int l1 = gen_new_label(); \
6995 int l2 = gen_new_label(); \
6996 int l3 = gen_new_label(); \
6997 int l4 = gen_new_label(); \
6998 \
6999 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7000 cpu_gpr[rB(ctx->opcode)], l1); \
7001 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7002 tcg_gen_br(l2); \
7003 gen_set_label(l1); \
7004 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7005 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7006 gen_set_label(l2); \
7007 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7008 cpu_gprh[rB(ctx->opcode)], l3); \
7009 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7010 ~(CRF_CH | CRF_CH_AND_CL)); \
7011 tcg_gen_br(l4); \
7012 gen_set_label(l3); \
7013 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7014 CRF_CH | CRF_CH_OR_CL); \
7015 gen_set_label(l4); \
7016 }
7017 #endif
7018 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7019 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7020 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7021 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7022 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7023
7024 /* SPE misc */
7025 static always_inline void gen_brinc (DisasContext *ctx)
7026 {
7027 /* Note: brinc is usable even if SPE is disabled */
7028 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7030 }
7031 static always_inline void gen_evmergelo (DisasContext *ctx)
7032 {
7033 if (unlikely(!ctx->spe_enabled)) {
7034 gen_exception(ctx, POWERPC_EXCP_APU);
7035 return;
7036 }
7037 #if defined(TARGET_PPC64)
7038 TCGv t0 = tcg_temp_new();
7039 TCGv t1 = tcg_temp_new();
7040 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7041 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7042 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7043 tcg_temp_free(t0);
7044 tcg_temp_free(t1);
7045 #else
7046 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7047 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7048 #endif
7049 }
7050 static always_inline void gen_evmergehilo (DisasContext *ctx)
7051 {
7052 if (unlikely(!ctx->spe_enabled)) {
7053 gen_exception(ctx, POWERPC_EXCP_APU);
7054 return;
7055 }
7056 #if defined(TARGET_PPC64)
7057 TCGv t0 = tcg_temp_new();
7058 TCGv t1 = tcg_temp_new();
7059 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7060 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7061 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7062 tcg_temp_free(t0);
7063 tcg_temp_free(t1);
7064 #else
7065 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7066 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7067 #endif
7068 }
7069 static always_inline void gen_evmergelohi (DisasContext *ctx)
7070 {
7071 if (unlikely(!ctx->spe_enabled)) {
7072 gen_exception(ctx, POWERPC_EXCP_APU);
7073 return;
7074 }
7075 #if defined(TARGET_PPC64)
7076 TCGv t0 = tcg_temp_new();
7077 TCGv t1 = tcg_temp_new();
7078 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7079 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7080 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7081 tcg_temp_free(t0);
7082 tcg_temp_free(t1);
7083 #else
7084 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7085 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7086 #endif
7087 }
7088 static always_inline void gen_evsplati (DisasContext *ctx)
7089 {
7090 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7091
7092 #if defined(TARGET_PPC64)
7093 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7094 #else
7095 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7096 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7097 #endif
7098 }
7099 static always_inline void gen_evsplatfi (DisasContext *ctx)
7100 {
7101 uint64_t imm = rA(ctx->opcode) << 11;
7102
7103 #if defined(TARGET_PPC64)
7104 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7105 #else
7106 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7107 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7108 #endif
7109 }
7110
7111 static always_inline void gen_evsel (DisasContext *ctx)
7112 {
7113 int l1 = gen_new_label();
7114 int l2 = gen_new_label();
7115 int l3 = gen_new_label();
7116 int l4 = gen_new_label();
7117 TCGv_i32 t0 = tcg_temp_local_new_i32();
7118 #if defined(TARGET_PPC64)
7119 TCGv t1 = tcg_temp_local_new();
7120 TCGv t2 = tcg_temp_local_new();
7121 #endif
7122 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7123 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7124 #if defined(TARGET_PPC64)
7125 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7126 #else
7127 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7128 #endif
7129 tcg_gen_br(l2);
7130 gen_set_label(l1);
7131 #if defined(TARGET_PPC64)
7132 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7133 #else
7134 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7135 #endif
7136 gen_set_label(l2);
7137 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7138 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7139 #if defined(TARGET_PPC64)
7140 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7141 #else
7142 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7143 #endif
7144 tcg_gen_br(l4);
7145 gen_set_label(l3);
7146 #if defined(TARGET_PPC64)
7147 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7148 #else
7149 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7150 #endif
7151 gen_set_label(l4);
7152 tcg_temp_free_i32(t0);
7153 #if defined(TARGET_PPC64)
7154 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7155 tcg_temp_free(t1);
7156 tcg_temp_free(t2);
7157 #endif
7158 }
7159 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7160 {
7161 gen_evsel(ctx);
7162 }
7163 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7164 {
7165 gen_evsel(ctx);
7166 }
7167 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7168 {
7169 gen_evsel(ctx);
7170 }
7171 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7172 {
7173 gen_evsel(ctx);
7174 }
7175
7176 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7177 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7178 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7179 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7180 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7181 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7182 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7183 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7184 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7185 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7186 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7187 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7188 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7189 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7190 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7191 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7192 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7193 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7194 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7195 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7196 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7197 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7198 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7199 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7200 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7201
7202 /* SPE load and stores */
7203 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7204 {
7205 target_ulong uimm = rB(ctx->opcode);
7206
7207 if (rA(ctx->opcode) == 0) {
7208 tcg_gen_movi_tl(EA, uimm << sh);
7209 } else {
7210 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7211 #if defined(TARGET_PPC64)
7212 if (!ctx->sf_mode) {
7213 tcg_gen_ext32u_tl(EA, EA);
7214 }
7215 #endif
7216 }
7217 }
7218
7219 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7220 {
7221 #if defined(TARGET_PPC64)
7222 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7223 #else
7224 TCGv_i64 t0 = tcg_temp_new_i64();
7225 gen_qemu_ld64(ctx, t0, addr);
7226 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7227 tcg_gen_shri_i64(t0, t0, 32);
7228 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7229 tcg_temp_free_i64(t0);
7230 #endif
7231 }
7232
7233 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7234 {
7235 #if defined(TARGET_PPC64)
7236 TCGv t0 = tcg_temp_new();
7237 gen_qemu_ld32u(ctx, t0, addr);
7238 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7239 gen_addr_add(ctx, addr, addr, 4);
7240 gen_qemu_ld32u(ctx, t0, addr);
7241 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7242 tcg_temp_free(t0);
7243 #else
7244 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7245 gen_addr_add(ctx, addr, addr, 4);
7246 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7247 #endif
7248 }
7249
7250 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7251 {
7252 TCGv t0 = tcg_temp_new();
7253 #if defined(TARGET_PPC64)
7254 gen_qemu_ld16u(ctx, t0, addr);
7255 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7256 gen_addr_add(ctx, addr, addr, 2);
7257 gen_qemu_ld16u(ctx, t0, addr);
7258 tcg_gen_shli_tl(t0, t0, 32);
7259 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7260 gen_addr_add(ctx, addr, addr, 2);
7261 gen_qemu_ld16u(ctx, t0, addr);
7262 tcg_gen_shli_tl(t0, t0, 16);
7263 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7264 gen_addr_add(ctx, addr, addr, 2);
7265 gen_qemu_ld16u(ctx, t0, addr);
7266 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7267 #else
7268 gen_qemu_ld16u(ctx, t0, addr);
7269 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7270 gen_addr_add(ctx, addr, addr, 2);
7271 gen_qemu_ld16u(ctx, t0, addr);
7272 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7273 gen_addr_add(ctx, addr, addr, 2);
7274 gen_qemu_ld16u(ctx, t0, addr);
7275 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7276 gen_addr_add(ctx, addr, addr, 2);
7277 gen_qemu_ld16u(ctx, t0, addr);
7278 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7279 #endif
7280 tcg_temp_free(t0);
7281 }
7282
7283 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7284 {
7285 TCGv t0 = tcg_temp_new();
7286 gen_qemu_ld16u(ctx, t0, addr);
7287 #if defined(TARGET_PPC64)
7288 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7289 tcg_gen_shli_tl(t0, t0, 16);
7290 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7291 #else
7292 tcg_gen_shli_tl(t0, t0, 16);
7293 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7294 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7295 #endif
7296 tcg_temp_free(t0);
7297 }
7298
7299 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7300 {
7301 TCGv t0 = tcg_temp_new();
7302 gen_qemu_ld16u(ctx, t0, addr);
7303 #if defined(TARGET_PPC64)
7304 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7305 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7306 #else
7307 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7308 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7309 #endif
7310 tcg_temp_free(t0);
7311 }
7312
7313 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7314 {
7315 TCGv t0 = tcg_temp_new();
7316 gen_qemu_ld16s(ctx, t0, addr);
7317 #if defined(TARGET_PPC64)
7318 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7319 tcg_gen_ext32u_tl(t0, t0);
7320 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7321 #else
7322 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7323 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7324 #endif
7325 tcg_temp_free(t0);
7326 }
7327
7328 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7329 {
7330 TCGv t0 = tcg_temp_new();
7331 #if defined(TARGET_PPC64)
7332 gen_qemu_ld16u(ctx, t0, addr);
7333 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7334 gen_addr_add(ctx, addr, addr, 2);
7335 gen_qemu_ld16u(ctx, t0, addr);
7336 tcg_gen_shli_tl(t0, t0, 16);
7337 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7338 #else
7339 gen_qemu_ld16u(ctx, t0, addr);
7340 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7341 gen_addr_add(ctx, addr, addr, 2);
7342 gen_qemu_ld16u(ctx, t0, addr);
7343 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7344 #endif
7345 tcg_temp_free(t0);
7346 }
7347
7348 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7349 {
7350 #if defined(TARGET_PPC64)
7351 TCGv t0 = tcg_temp_new();
7352 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7353 gen_addr_add(ctx, addr, addr, 2);
7354 gen_qemu_ld16u(ctx, t0, addr);
7355 tcg_gen_shli_tl(t0, t0, 32);
7356 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7357 tcg_temp_free(t0);
7358 #else
7359 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7360 gen_addr_add(ctx, addr, addr, 2);
7361 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7362 #endif
7363 }
7364
7365 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7366 {
7367 #if defined(TARGET_PPC64)
7368 TCGv t0 = tcg_temp_new();
7369 gen_qemu_ld16s(ctx, t0, addr);
7370 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7371 gen_addr_add(ctx, addr, addr, 2);
7372 gen_qemu_ld16s(ctx, t0, addr);
7373 tcg_gen_shli_tl(t0, t0, 32);
7374 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7375 tcg_temp_free(t0);
7376 #else
7377 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7378 gen_addr_add(ctx, addr, addr, 2);
7379 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7380 #endif
7381 }
7382
7383 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7384 {
7385 TCGv t0 = tcg_temp_new();
7386 gen_qemu_ld32u(ctx, t0, addr);
7387 #if defined(TARGET_PPC64)
7388 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7389 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7390 #else
7391 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7393 #endif
7394 tcg_temp_free(t0);
7395 }
7396
7397 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7398 {
7399 TCGv t0 = tcg_temp_new();
7400 #if defined(TARGET_PPC64)
7401 gen_qemu_ld16u(ctx, t0, addr);
7402 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7403 tcg_gen_shli_tl(t0, t0, 32);
7404 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7405 gen_addr_add(ctx, addr, addr, 2);
7406 gen_qemu_ld16u(ctx, t0, addr);
7407 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7408 tcg_gen_shli_tl(t0, t0, 16);
7409 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7410 #else
7411 gen_qemu_ld16u(ctx, t0, addr);
7412 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7413 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7414 gen_addr_add(ctx, addr, addr, 2);
7415 gen_qemu_ld16u(ctx, t0, addr);
7416 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7417 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7418 #endif
7419 tcg_temp_free(t0);
7420 }
7421
7422 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7423 {
7424 #if defined(TARGET_PPC64)
7425 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7426 #else
7427 TCGv_i64 t0 = tcg_temp_new_i64();
7428 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7429 gen_qemu_st64(ctx, t0, addr);
7430 tcg_temp_free_i64(t0);
7431 #endif
7432 }
7433
7434 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7435 {
7436 #if defined(TARGET_PPC64)
7437 TCGv t0 = tcg_temp_new();
7438 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7439 gen_qemu_st32(ctx, t0, addr);
7440 tcg_temp_free(t0);
7441 #else
7442 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7443 #endif
7444 gen_addr_add(ctx, addr, addr, 4);
7445 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7446 }
7447
7448 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7449 {
7450 TCGv t0 = tcg_temp_new();
7451 #if defined(TARGET_PPC64)
7452 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7453 #else
7454 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7455 #endif
7456 gen_qemu_st16(ctx, t0, addr);
7457 gen_addr_add(ctx, addr, addr, 2);
7458 #if defined(TARGET_PPC64)
7459 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7460 gen_qemu_st16(ctx, t0, addr);
7461 #else
7462 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7463 #endif
7464 gen_addr_add(ctx, addr, addr, 2);
7465 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7466 gen_qemu_st16(ctx, t0, addr);
7467 tcg_temp_free(t0);
7468 gen_addr_add(ctx, addr, addr, 2);
7469 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7470 }
7471
7472 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7473 {
7474 TCGv t0 = tcg_temp_new();
7475 #if defined(TARGET_PPC64)
7476 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7477 #else
7478 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7479 #endif
7480 gen_qemu_st16(ctx, t0, addr);
7481 gen_addr_add(ctx, addr, addr, 2);
7482 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7483 gen_qemu_st16(ctx, t0, addr);
7484 tcg_temp_free(t0);
7485 }
7486
7487 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7488 {
7489 #if defined(TARGET_PPC64)
7490 TCGv t0 = tcg_temp_new();
7491 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7492 gen_qemu_st16(ctx, t0, addr);
7493 tcg_temp_free(t0);
7494 #else
7495 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7496 #endif
7497 gen_addr_add(ctx, addr, addr, 2);
7498 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7499 }
7500
7501 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7502 {
7503 #if defined(TARGET_PPC64)
7504 TCGv t0 = tcg_temp_new();
7505 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7506 gen_qemu_st32(ctx, t0, addr);
7507 tcg_temp_free(t0);
7508 #else
7509 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7510 #endif
7511 }
7512
7513 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7514 {
7515 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7516 }
7517
7518 #define GEN_SPEOP_LDST(name, opc2, sh) \
7519 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7520 { \
7521 TCGv t0; \
7522 if (unlikely(!ctx->spe_enabled)) { \
7523 gen_exception(ctx, POWERPC_EXCP_APU); \
7524 return; \
7525 } \
7526 gen_set_access_type(ctx, ACCESS_INT); \
7527 t0 = tcg_temp_new(); \
7528 if (Rc(ctx->opcode)) { \
7529 gen_addr_spe_imm_index(ctx, t0, sh); \
7530 } else { \
7531 gen_addr_reg_index(ctx, t0); \
7532 } \
7533 gen_op_##name(ctx, t0); \
7534 tcg_temp_free(t0); \
7535 }
7536
7537 GEN_SPEOP_LDST(evldd, 0x00, 3);
7538 GEN_SPEOP_LDST(evldw, 0x01, 3);
7539 GEN_SPEOP_LDST(evldh, 0x02, 3);
7540 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7541 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7542 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7543 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7544 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7545 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7546 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7547 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7548
7549 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7550 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7551 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7552 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7553 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7554 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7555 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7556
7557 /* Multiply and add - TODO */
7558 #if 0
7559 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7560 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7561 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7562 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7563 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7564 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7565 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7566 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7567 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7568 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7569 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7570 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7571
7572 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7573 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7574 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7575 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7576 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7577 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7578 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7579 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7580 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7581 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7582 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7583 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7584 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7585 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7586
7587 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7588 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7589 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7590 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7591 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7592 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7593
7594 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7595 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7596 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7597 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7598 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7599 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7600 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7601 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7602 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7603 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7604 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7605 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7606
7607 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7608 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7609 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7610 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7611 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7612
7613 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7614 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7615 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7616 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7617 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7618 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7619 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7620 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7621 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7622 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7623 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7624 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7625
7626 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7627 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7628 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7629 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7630 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7631 #endif
7632
7633 /*** SPE floating-point extension ***/
7634 #if defined(TARGET_PPC64)
7635 #define GEN_SPEFPUOP_CONV_32_32(name) \
7636 static always_inline void gen_##name (DisasContext *ctx) \
7637 { \
7638 TCGv_i32 t0; \
7639 TCGv t1; \
7640 t0 = tcg_temp_new_i32(); \
7641 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7642 gen_helper_##name(t0, t0); \
7643 t1 = tcg_temp_new(); \
7644 tcg_gen_extu_i32_tl(t1, t0); \
7645 tcg_temp_free_i32(t0); \
7646 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7647 0xFFFFFFFF00000000ULL); \
7648 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7649 tcg_temp_free(t1); \
7650 }
7651 #define GEN_SPEFPUOP_CONV_32_64(name) \
7652 static always_inline void gen_##name (DisasContext *ctx) \
7653 { \
7654 TCGv_i32 t0; \
7655 TCGv t1; \
7656 t0 = tcg_temp_new_i32(); \
7657 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7658 t1 = tcg_temp_new(); \
7659 tcg_gen_extu_i32_tl(t1, t0); \
7660 tcg_temp_free_i32(t0); \
7661 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7662 0xFFFFFFFF00000000ULL); \
7663 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7664 tcg_temp_free(t1); \
7665 }
7666 #define GEN_SPEFPUOP_CONV_64_32(name) \
7667 static always_inline void gen_##name (DisasContext *ctx) \
7668 { \
7669 TCGv_i32 t0 = tcg_temp_new_i32(); \
7670 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7671 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7672 tcg_temp_free_i32(t0); \
7673 }
7674 #define GEN_SPEFPUOP_CONV_64_64(name) \
7675 static always_inline void gen_##name (DisasContext *ctx) \
7676 { \
7677 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7678 }
7679 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7680 static always_inline void gen_##name (DisasContext *ctx) \
7681 { \
7682 TCGv_i32 t0, t1; \
7683 TCGv_i64 t2; \
7684 if (unlikely(!ctx->spe_enabled)) { \
7685 gen_exception(ctx, POWERPC_EXCP_APU); \
7686 return; \
7687 } \
7688 t0 = tcg_temp_new_i32(); \
7689 t1 = tcg_temp_new_i32(); \
7690 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7691 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7692 gen_helper_##name(t0, t0, t1); \
7693 tcg_temp_free_i32(t1); \
7694 t2 = tcg_temp_new(); \
7695 tcg_gen_extu_i32_tl(t2, t0); \
7696 tcg_temp_free_i32(t0); \
7697 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7698 0xFFFFFFFF00000000ULL); \
7699 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7700 tcg_temp_free(t2); \
7701 }
7702 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7703 static always_inline void gen_##name (DisasContext *ctx) \
7704 { \
7705 if (unlikely(!ctx->spe_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_APU); \
7707 return; \
7708 } \
7709 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7710 cpu_gpr[rB(ctx->opcode)]); \
7711 }
7712 #define GEN_SPEFPUOP_COMP_32(name) \
7713 static always_inline void gen_##name (DisasContext *ctx) \
7714 { \
7715 TCGv_i32 t0, t1; \
7716 if (unlikely(!ctx->spe_enabled)) { \
7717 gen_exception(ctx, POWERPC_EXCP_APU); \
7718 return; \
7719 } \
7720 t0 = tcg_temp_new_i32(); \
7721 t1 = tcg_temp_new_i32(); \
7722 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7723 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7724 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7725 tcg_temp_free_i32(t0); \
7726 tcg_temp_free_i32(t1); \
7727 }
7728 #define GEN_SPEFPUOP_COMP_64(name) \
7729 static always_inline void gen_##name (DisasContext *ctx) \
7730 { \
7731 if (unlikely(!ctx->spe_enabled)) { \
7732 gen_exception(ctx, POWERPC_EXCP_APU); \
7733 return; \
7734 } \
7735 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7736 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7737 }
7738 #else
7739 #define GEN_SPEFPUOP_CONV_32_32(name) \
7740 static always_inline void gen_##name (DisasContext *ctx) \
7741 { \
7742 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7743 }
7744 #define GEN_SPEFPUOP_CONV_32_64(name) \
7745 static always_inline void gen_##name (DisasContext *ctx) \
7746 { \
7747 TCGv_i64 t0 = tcg_temp_new_i64(); \
7748 gen_load_gpr64(t0, rB(ctx->opcode)); \
7749 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7750 tcg_temp_free_i64(t0); \
7751 }
7752 #define GEN_SPEFPUOP_CONV_64_32(name) \
7753 static always_inline void gen_##name (DisasContext *ctx) \
7754 { \
7755 TCGv_i64 t0 = tcg_temp_new_i64(); \
7756 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7757 gen_store_gpr64(rD(ctx->opcode), t0); \
7758 tcg_temp_free_i64(t0); \
7759 }
7760 #define GEN_SPEFPUOP_CONV_64_64(name) \
7761 static always_inline void gen_##name (DisasContext *ctx) \
7762 { \
7763 TCGv_i64 t0 = tcg_temp_new_i64(); \
7764 gen_load_gpr64(t0, rB(ctx->opcode)); \
7765 gen_helper_##name(t0, t0); \
7766 gen_store_gpr64(rD(ctx->opcode), t0); \
7767 tcg_temp_free_i64(t0); \
7768 }
7769 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7770 static always_inline void gen_##name (DisasContext *ctx) \
7771 { \
7772 if (unlikely(!ctx->spe_enabled)) { \
7773 gen_exception(ctx, POWERPC_EXCP_APU); \
7774 return; \
7775 } \
7776 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7777 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7778 }
7779 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7780 static always_inline void gen_##name (DisasContext *ctx) \
7781 { \
7782 TCGv_i64 t0, t1; \
7783 if (unlikely(!ctx->spe_enabled)) { \
7784 gen_exception(ctx, POWERPC_EXCP_APU); \
7785 return; \
7786 } \
7787 t0 = tcg_temp_new_i64(); \
7788 t1 = tcg_temp_new_i64(); \
7789 gen_load_gpr64(t0, rA(ctx->opcode)); \
7790 gen_load_gpr64(t1, rB(ctx->opcode)); \
7791 gen_helper_##name(t0, t0, t1); \
7792 gen_store_gpr64(rD(ctx->opcode), t0); \
7793 tcg_temp_free_i64(t0); \
7794 tcg_temp_free_i64(t1); \
7795 }
7796 #define GEN_SPEFPUOP_COMP_32(name) \
7797 static always_inline void gen_##name (DisasContext *ctx) \
7798 { \
7799 if (unlikely(!ctx->spe_enabled)) { \
7800 gen_exception(ctx, POWERPC_EXCP_APU); \
7801 return; \
7802 } \
7803 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7804 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7805 }
7806 #define GEN_SPEFPUOP_COMP_64(name) \
7807 static always_inline void gen_##name (DisasContext *ctx) \
7808 { \
7809 TCGv_i64 t0, t1; \
7810 if (unlikely(!ctx->spe_enabled)) { \
7811 gen_exception(ctx, POWERPC_EXCP_APU); \
7812 return; \
7813 } \
7814 t0 = tcg_temp_new_i64(); \
7815 t1 = tcg_temp_new_i64(); \
7816 gen_load_gpr64(t0, rA(ctx->opcode)); \
7817 gen_load_gpr64(t1, rB(ctx->opcode)); \
7818 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7819 tcg_temp_free_i64(t0); \
7820 tcg_temp_free_i64(t1); \
7821 }
7822 #endif
7823
7824 /* Single precision floating-point vectors operations */
7825 /* Arithmetic */
7826 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7827 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7828 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7829 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7830 static always_inline void gen_evfsabs (DisasContext *ctx)
7831 {
7832 if (unlikely(!ctx->spe_enabled)) {
7833 gen_exception(ctx, POWERPC_EXCP_APU);
7834 return;
7835 }
7836 #if defined(TARGET_PPC64)
7837 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7838 #else
7839 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7840 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7841 #endif
7842 }
7843 static always_inline void gen_evfsnabs (DisasContext *ctx)
7844 {
7845 if (unlikely(!ctx->spe_enabled)) {
7846 gen_exception(ctx, POWERPC_EXCP_APU);
7847 return;
7848 }
7849 #if defined(TARGET_PPC64)
7850 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7851 #else
7852 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7853 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7854 #endif
7855 }
7856 static always_inline void gen_evfsneg (DisasContext *ctx)
7857 {
7858 if (unlikely(!ctx->spe_enabled)) {
7859 gen_exception(ctx, POWERPC_EXCP_APU);
7860 return;
7861 }
7862 #if defined(TARGET_PPC64)
7863 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7864 #else
7865 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7866 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7867 #endif
7868 }
7869
7870 /* Conversion */
7871 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7872 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7873 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7874 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7875 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7876 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7877 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7878 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7879 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7880 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7881
7882 /* Comparison */
7883 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7884 GEN_SPEFPUOP_COMP_64(evfscmplt);
7885 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7886 GEN_SPEFPUOP_COMP_64(evfststgt);
7887 GEN_SPEFPUOP_COMP_64(evfststlt);
7888 GEN_SPEFPUOP_COMP_64(evfststeq);
7889
7890 /* Opcodes definitions */
7891 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7892 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7893 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7894 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7895 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7896 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7897 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7898 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7899 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7900 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7901 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7902 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7903 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7904 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7905
7906 /* Single precision floating-point operations */
7907 /* Arithmetic */
7908 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7909 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7910 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7911 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7912 static always_inline void gen_efsabs (DisasContext *ctx)
7913 {
7914 if (unlikely(!ctx->spe_enabled)) {
7915 gen_exception(ctx, POWERPC_EXCP_APU);
7916 return;
7917 }
7918 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7919 }
7920 static always_inline void gen_efsnabs (DisasContext *ctx)
7921 {
7922 if (unlikely(!ctx->spe_enabled)) {
7923 gen_exception(ctx, POWERPC_EXCP_APU);
7924 return;
7925 }
7926 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7927 }
7928 static always_inline void gen_efsneg (DisasContext *ctx)
7929 {
7930 if (unlikely(!ctx->spe_enabled)) {
7931 gen_exception(ctx, POWERPC_EXCP_APU);
7932 return;
7933 }
7934 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7935 }
7936
7937 /* Conversion */
7938 GEN_SPEFPUOP_CONV_32_32(efscfui);
7939 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7940 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7941 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7942 GEN_SPEFPUOP_CONV_32_32(efsctui);
7943 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7944 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7945 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7946 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7947 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7948 GEN_SPEFPUOP_CONV_32_64(efscfd);
7949
7950 /* Comparison */
7951 GEN_SPEFPUOP_COMP_32(efscmpgt);
7952 GEN_SPEFPUOP_COMP_32(efscmplt);
7953 GEN_SPEFPUOP_COMP_32(efscmpeq);
7954 GEN_SPEFPUOP_COMP_32(efststgt);
7955 GEN_SPEFPUOP_COMP_32(efststlt);
7956 GEN_SPEFPUOP_COMP_32(efststeq);
7957
7958 /* Opcodes definitions */
7959 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7960 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7961 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7962 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7963 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7964 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7965 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7966 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7967 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7968 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7969 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7970 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7971 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7972 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7973
7974 /* Double precision floating-point operations */
7975 /* Arithmetic */
7976 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7977 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7978 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7979 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7980 static always_inline void gen_efdabs (DisasContext *ctx)
7981 {
7982 if (unlikely(!ctx->spe_enabled)) {
7983 gen_exception(ctx, POWERPC_EXCP_APU);
7984 return;
7985 }
7986 #if defined(TARGET_PPC64)
7987 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7988 #else
7989 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7990 #endif
7991 }
7992 static always_inline void gen_efdnabs (DisasContext *ctx)
7993 {
7994 if (unlikely(!ctx->spe_enabled)) {
7995 gen_exception(ctx, POWERPC_EXCP_APU);
7996 return;
7997 }
7998 #if defined(TARGET_PPC64)
7999 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8000 #else
8001 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8002 #endif
8003 }
8004 static always_inline void gen_efdneg (DisasContext *ctx)
8005 {
8006 if (unlikely(!ctx->spe_enabled)) {
8007 gen_exception(ctx, POWERPC_EXCP_APU);
8008 return;
8009 }
8010 #if defined(TARGET_PPC64)
8011 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8012 #else
8013 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8014 #endif
8015 }
8016
8017 /* Conversion */
8018 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8019 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8020 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8021 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8022 GEN_SPEFPUOP_CONV_32_64(efdctui);
8023 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8024 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8025 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8026 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8027 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8028 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8029 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8030 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8031 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8032 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8033
8034 /* Comparison */
8035 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8036 GEN_SPEFPUOP_COMP_64(efdcmplt);
8037 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8038 GEN_SPEFPUOP_COMP_64(efdtstgt);
8039 GEN_SPEFPUOP_COMP_64(efdtstlt);
8040 GEN_SPEFPUOP_COMP_64(efdtsteq);
8041
8042 /* Opcodes definitions */
8043 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8044 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8045 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8046 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8047 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8048 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8049 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8050 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8051 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8052 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8053 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8054 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8055 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8056 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8057 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8058 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8059
8060 /* End opcode list */
8061 GEN_OPCODE_MARK(end);
8062
8063 #include "translate_init.c"
8064 #include "helper_regs.h"
8065
8066 /*****************************************************************************/
8067 /* Misc PowerPC helpers */
8068 void cpu_dump_state (CPUState *env, FILE *f,
8069 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8070 int flags)
8071 {
8072 #define RGPL 4
8073 #define RFPL 4
8074
8075 int i;
8076
8077 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8078 env->nip, env->lr, env->ctr, env->xer);
8079 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8080 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8081 #if !defined(NO_TIMER_DUMP)
8082 cpu_fprintf(f, "TB %08x %08x "
8083 #if !defined(CONFIG_USER_ONLY)
8084 "DECR %08x"
8085 #endif
8086 "\n",
8087 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8088 #if !defined(CONFIG_USER_ONLY)
8089 , cpu_ppc_load_decr(env)
8090 #endif
8091 );
8092 #endif
8093 for (i = 0; i < 32; i++) {
8094 if ((i & (RGPL - 1)) == 0)
8095 cpu_fprintf(f, "GPR%02d", i);
8096 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8097 if ((i & (RGPL - 1)) == (RGPL - 1))
8098 cpu_fprintf(f, "\n");
8099 }
8100 cpu_fprintf(f, "CR ");
8101 for (i = 0; i < 8; i++)
8102 cpu_fprintf(f, "%01x", env->crf[i]);
8103 cpu_fprintf(f, " [");
8104 for (i = 0; i < 8; i++) {
8105 char a = '-';
8106 if (env->crf[i] & 0x08)
8107 a = 'L';
8108 else if (env->crf[i] & 0x04)
8109 a = 'G';
8110 else if (env->crf[i] & 0x02)
8111 a = 'E';
8112 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8113 }
8114 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8115 for (i = 0; i < 32; i++) {
8116 if ((i & (RFPL - 1)) == 0)
8117 cpu_fprintf(f, "FPR%02d", i);
8118 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8119 if ((i & (RFPL - 1)) == (RFPL - 1))
8120 cpu_fprintf(f, "\n");
8121 }
8122 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8123 #if !defined(CONFIG_USER_ONLY)
8124 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8125 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8126 #endif
8127
8128 #undef RGPL
8129 #undef RFPL
8130 }
8131
8132 void cpu_dump_statistics (CPUState *env, FILE*f,
8133 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8134 int flags)
8135 {
8136 #if defined(DO_PPC_STATISTICS)
8137 opc_handler_t **t1, **t2, **t3, *handler;
8138 int op1, op2, op3;
8139
8140 t1 = env->opcodes;
8141 for (op1 = 0; op1 < 64; op1++) {
8142 handler = t1[op1];
8143 if (is_indirect_opcode(handler)) {
8144 t2 = ind_table(handler);
8145 for (op2 = 0; op2 < 32; op2++) {
8146 handler = t2[op2];
8147 if (is_indirect_opcode(handler)) {
8148 t3 = ind_table(handler);
8149 for (op3 = 0; op3 < 32; op3++) {
8150 handler = t3[op3];
8151 if (handler->count == 0)
8152 continue;
8153 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8154 "%016llx %lld\n",
8155 op1, op2, op3, op1, (op3 << 5) | op2,
8156 handler->oname,
8157 handler->count, handler->count);
8158 }
8159 } else {
8160 if (handler->count == 0)
8161 continue;
8162 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8163 "%016llx %lld\n",
8164 op1, op2, op1, op2, handler->oname,
8165 handler->count, handler->count);
8166 }
8167 }
8168 } else {
8169 if (handler->count == 0)
8170 continue;
8171 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8172 op1, op1, handler->oname,
8173 handler->count, handler->count);
8174 }
8175 }
8176 #endif
8177 }
8178
8179 /*****************************************************************************/
8180 static always_inline void gen_intermediate_code_internal (CPUState *env,
8181 TranslationBlock *tb,
8182 int search_pc)
8183 {
8184 DisasContext ctx, *ctxp = &ctx;
8185 opc_handler_t **table, *handler;
8186 target_ulong pc_start;
8187 uint16_t *gen_opc_end;
8188 CPUBreakpoint *bp;
8189 int j, lj = -1;
8190 int num_insns;
8191 int max_insns;
8192
8193 pc_start = tb->pc;
8194 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8195 ctx.nip = pc_start;
8196 ctx.tb = tb;
8197 ctx.exception = POWERPC_EXCP_NONE;
8198 ctx.spr_cb = env->spr_cb;
8199 ctx.mem_idx = env->mmu_idx;
8200 ctx.access_type = -1;
8201 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8202 #if defined(TARGET_PPC64)
8203 ctx.sf_mode = msr_sf;
8204 #endif
8205 ctx.fpu_enabled = msr_fp;
8206 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8207 ctx.spe_enabled = msr_spe;
8208 else
8209 ctx.spe_enabled = 0;
8210 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8211 ctx.altivec_enabled = msr_vr;
8212 else
8213 ctx.altivec_enabled = 0;
8214 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8215 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8216 else
8217 ctx.singlestep_enabled = 0;
8218 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8219 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8220 if (unlikely(env->singlestep_enabled))
8221 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8222 #if defined (DO_SINGLE_STEP) && 0
8223 /* Single step trace mode */
8224 msr_se = 1;
8225 #endif
8226 num_insns = 0;
8227 max_insns = tb->cflags & CF_COUNT_MASK;
8228 if (max_insns == 0)
8229 max_insns = CF_COUNT_MASK;
8230
8231 gen_icount_start();
8232 /* Set env in case of segfault during code fetch */
8233 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8234 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8235 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8236 if (bp->pc == ctx.nip) {
8237 gen_debug_exception(ctxp);
8238 break;
8239 }
8240 }
8241 }
8242 if (unlikely(search_pc)) {
8243 j = gen_opc_ptr - gen_opc_buf;
8244 if (lj < j) {
8245 lj++;
8246 while (lj < j)
8247 gen_opc_instr_start[lj++] = 0;
8248 gen_opc_pc[lj] = ctx.nip;
8249 gen_opc_instr_start[lj] = 1;
8250 gen_opc_icount[lj] = num_insns;
8251 }
8252 }
8253 LOG_DISAS("----------------\n");
8254 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8255 ctx.nip, ctx.mem_idx, (int)msr_ir);
8256 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8257 gen_io_start();
8258 if (unlikely(ctx.le_mode)) {
8259 ctx.opcode = bswap32(ldl_code(ctx.nip));
8260 } else {
8261 ctx.opcode = ldl_code(ctx.nip);
8262 }
8263 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8264 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8265 opc3(ctx.opcode), little_endian ? "little" : "big");
8266 ctx.nip += 4;
8267 table = env->opcodes;
8268 num_insns++;
8269 handler = table[opc1(ctx.opcode)];
8270 if (is_indirect_opcode(handler)) {
8271 table = ind_table(handler);
8272 handler = table[opc2(ctx.opcode)];
8273 if (is_indirect_opcode(handler)) {
8274 table = ind_table(handler);
8275 handler = table[opc3(ctx.opcode)];
8276 }
8277 }
8278 /* Is opcode *REALLY* valid ? */
8279 if (unlikely(handler->handler == &gen_invalid)) {
8280 if (qemu_log_enabled()) {
8281 qemu_log("invalid/unsupported opcode: "
8282 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8283 opc1(ctx.opcode), opc2(ctx.opcode),
8284 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8285 } else {
8286 printf("invalid/unsupported opcode: "
8287 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8288 opc1(ctx.opcode), opc2(ctx.opcode),
8289 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8290 }
8291 } else {
8292 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8293 if (qemu_log_enabled()) {
8294 qemu_log("invalid bits: %08x for opcode: "
8295 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8296 ctx.opcode & handler->inval, opc1(ctx.opcode),
8297 opc2(ctx.opcode), opc3(ctx.opcode),
8298 ctx.opcode, ctx.nip - 4);
8299 } else {
8300 printf("invalid bits: %08x for opcode: "
8301 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8302 ctx.opcode & handler->inval, opc1(ctx.opcode),
8303 opc2(ctx.opcode), opc3(ctx.opcode),
8304 ctx.opcode, ctx.nip - 4);
8305 }
8306 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8307 break;
8308 }
8309 }
8310 (*(handler->handler))(&ctx);
8311 #if defined(DO_PPC_STATISTICS)
8312 handler->count++;
8313 #endif
8314 /* Check trace mode exceptions */
8315 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8316 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8317 ctx.exception != POWERPC_SYSCALL &&
8318 ctx.exception != POWERPC_EXCP_TRAP &&
8319 ctx.exception != POWERPC_EXCP_BRANCH)) {
8320 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8321 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8322 (env->singlestep_enabled) ||
8323 num_insns >= max_insns)) {
8324 /* if we reach a page boundary or are single stepping, stop
8325 * generation
8326 */
8327 break;
8328 }
8329 #if defined (DO_SINGLE_STEP)
8330 break;
8331 #endif
8332 }
8333 if (tb->cflags & CF_LAST_IO)
8334 gen_io_end();
8335 if (ctx.exception == POWERPC_EXCP_NONE) {
8336 gen_goto_tb(&ctx, 0, ctx.nip);
8337 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8338 if (unlikely(env->singlestep_enabled)) {
8339 gen_debug_exception(ctxp);
8340 }
8341 /* Generate the return instruction */
8342 tcg_gen_exit_tb(0);
8343 }
8344 gen_icount_end(tb, num_insns);
8345 *gen_opc_ptr = INDEX_op_end;
8346 if (unlikely(search_pc)) {
8347 j = gen_opc_ptr - gen_opc_buf;
8348 lj++;
8349 while (lj <= j)
8350 gen_opc_instr_start[lj++] = 0;
8351 } else {
8352 tb->size = ctx.nip - pc_start;
8353 tb->icount = num_insns;
8354 }
8355 #if defined(DEBUG_DISAS)
8356 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8357 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8358 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8359 int flags;
8360 flags = env->bfd_mach;
8361 flags |= ctx.le_mode << 16;
8362 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8363 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8364 qemu_log("\n");
8365 }
8366 #endif
8367 }
8368
8369 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8370 {
8371 gen_intermediate_code_internal(env, tb, 0);
8372 }
8373
8374 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8375 {
8376 gen_intermediate_code_internal(env, tb, 1);
8377 }
8378
8379 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8380 unsigned long searched_pc, int pc_pos, void *puc)
8381 {
8382 env->nip = gen_opc_pc[pc_pos];
8383 }
Samsung s3c2440 and arm920t support for the mini2440 dev board