target-sparc/op_helper.c

   1 #include "exec.h"
   2 #include "host-utils.h"
   3
   4 //#define DEBUG_PCALL
   5 //#define DEBUG_MMU
   6 //#define DEBUG_MXCC
   7 //#define DEBUG_UNALIGNED
   8 //#define DEBUG_UNASSIGNED
   9
  10 #ifdef DEBUG_MMU
  11 #define DPRINTF_MMU(fmt, args...) \
  12 do { printf("MMU: " fmt , ##args); } while (0)
  13 #else
  14 #define DPRINTF_MMU(fmt, args...)
  15 #endif
  16
  17 #ifdef DEBUG_MXCC
  18 #define DPRINTF_MXCC(fmt, args...) \
  19 do { printf("MXCC: " fmt , ##args); } while (0)
  20 #else
  21 #define DPRINTF_MXCC(fmt, args...)
  22 #endif
  23
  24 void raise_exception(int tt)
  25 {
  26     env->exception_index = tt;
  27     cpu_loop_exit();
  28 }
  29
  30 void check_ieee_exceptions()
  31 {
  32      T0 = get_float_exception_flags(&env->fp_status);
  33      if (T0)
  34      {
  35         /* Copy IEEE 754 flags into FSR */
  36         if (T0 & float_flag_invalid)
  37             env->fsr |= FSR_NVC;
  38         if (T0 & float_flag_overflow)
  39             env->fsr |= FSR_OFC;
  40         if (T0 & float_flag_underflow)
  41             env->fsr |= FSR_UFC;
  42         if (T0 & float_flag_divbyzero)
  43             env->fsr |= FSR_DZC;
  44         if (T0 & float_flag_inexact)
  45             env->fsr |= FSR_NXC;
  46
  47         if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
  48         {
  49             /* Unmasked exception, generate a trap */
  50             env->fsr |= FSR_FTT_IEEE_EXCP;
  51             raise_exception(TT_FP_EXCP);
  52         }
  53         else
  54         {
  55             /* Accumulate exceptions */
  56             env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
  57         }
  58      }
  59 }
  60
  61 #ifdef USE_INT_TO_FLOAT_HELPERS
  62 void do_fitos(void)
  63 {
  64     set_float_exception_flags(0, &env->fp_status);
  65     FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
  66     check_ieee_exceptions();
  67 }
  68
  69 void do_fitod(void)
  70 {
  71     DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
  72 }
  73 #ifdef TARGET_SPARC64
  74 void do_fxtos(void)
  75 {
  76     set_float_exception_flags(0, &env->fp_status);
  77     FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
  78     check_ieee_exceptions();
  79 }
  80
  81 void do_fxtod(void)
  82 {
  83     set_float_exception_flags(0, &env->fp_status);
  84     DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
  85     check_ieee_exceptions();
  86 }
  87 #endif
  88 #endif
  89
  90 void do_fabss(void)
  91 {
  92     FT0 = float32_abs(FT1);
  93 }
  94
  95 #ifdef TARGET_SPARC64
  96 void do_fabsd(void)
  97 {
  98     DT0 = float64_abs(DT1);
  99 }
 100 #endif
 101
 102 void do_fsqrts(void)
 103 {
 104     set_float_exception_flags(0, &env->fp_status);
 105     FT0 = float32_sqrt(FT1, &env->fp_status);
 106     check_ieee_exceptions();
 107 }
 108
 109 void do_fsqrtd(void)
 110 {
 111     set_float_exception_flags(0, &env->fp_status);
 112     DT0 = float64_sqrt(DT1, &env->fp_status);
 113     check_ieee_exceptions();
 114 }
 115
 116 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP)                      \
 117     void glue(do_, name) (void)                                         \
 118     {                                                                   \
 119         env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
 120         switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
 121         case float_relation_unordered:                                  \
 122             T0 = (FSR_FCC1 | FSR_FCC0) << FS;                           \
 123             if ((env->fsr & FSR_NVM) || TRAP) {                         \
 124                 env->fsr |= T0;                                         \
 125                 env->fsr |= FSR_NVC;                                    \
 126                 env->fsr |= FSR_FTT_IEEE_EXCP;                          \
 127                 raise_exception(TT_FP_EXCP);                            \
 128             } else {                                                    \
 129                 env->fsr |= FSR_NVA;                                    \
 130             }                                                           \
 131             break;                                                      \
 132         case float_relation_less:                                       \
 133             T0 = FSR_FCC0 << FS;                                        \
 134             break;                                                      \
 135         case float_relation_greater:                                    \
 136             T0 = FSR_FCC1 << FS;                                        \
 137             break;                                                      \
 138         default:                                                        \
 139             T0 = 0;                                                     \
 140             break;                                                      \
 141         }                                                               \
 142         env->fsr |= T0;                                                 \
 143     }
 144
 145 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
 146 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
 147
 148 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
 149 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
 150
 151 #ifdef TARGET_SPARC64
 152 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
 153 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
 154
 155 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
 156 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
 157
 158 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
 159 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
 160
 161 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
 162 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
 163
 164 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
 165 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
 166
 167 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
 168 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
 169 #endif
 170
 171 #ifndef TARGET_SPARC64
 172 #ifndef CONFIG_USER_ONLY
 173
 174 #ifdef DEBUG_MXCC
 175 static void dump_mxcc(CPUState *env)
 176 {
 177     printf("mxccdata: %016llx %016llx %016llx %016llx\n",
 178         env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
 179     printf("mxccregs: %016llx %016llx %016llx %016llx\n"
 180            "          %016llx %016llx %016llx %016llx\n",
 181         env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
 182         env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
 183 }
 184 #endif
 185
 186 void helper_ld_asi(int asi, int size, int sign)
 187 {
 188     uint32_t ret = 0;
 189     uint64_t tmp;
 190 #ifdef DEBUG_MXCC
 191     uint32_t last_T0 = T0;
 192 #endif
 193
 194     switch (asi) {
 195     case 2: /* SuperSparc MXCC registers */
 196         switch (T0) {
 197         case 0x01c00a00: /* MXCC control register */
 198             if (size == 8) {
 199                 ret = env->mxccregs[3];
 200                 T0 = env->mxccregs[3] >> 32;
 201             } else
 202                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 203             break;
 204         case 0x01c00a04: /* MXCC control register */
 205             if (size == 4)
 206                 ret = env->mxccregs[3];
 207             else
 208                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 209             break;
 210         case 0x01c00c00: /* Module reset register */
 211             if (size == 8) {
 212                 ret = env->mxccregs[5] >> 32;
 213                 T0 = env->mxccregs[5];
 214                 // should we do something here?
 215             } else
 216                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 217             break;
 218         case 0x01c00f00: /* MBus port address register */
 219             if (size == 8) {
 220                 ret = env->mxccregs[7];
 221                 T0 = env->mxccregs[7] >> 32;
 222             } else
 223                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 224             break;
 225         default:
 226             DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
 227             break;
 228         }
 229         DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
 230                      "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
 231 #ifdef DEBUG_MXCC
 232         dump_mxcc(env);
 233 #endif
 234         break;
 235     case 3: /* MMU probe */
 236         {
 237             int mmulev;
 238
 239             mmulev = (T0 >> 8) & 15;
 240             if (mmulev > 4)
 241                 ret = 0;
 242             else {
 243                 ret = mmu_probe(env, T0, mmulev);
 244                 //bswap32s(&ret);
 245             }
 246             DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
 247         }
 248         break;
 249     case 4: /* read MMU regs */
 250         {
 251             int reg = (T0 >> 8) & 0xf;
 252
 253             ret = env->mmuregs[reg];
 254             if (reg == 3) /* Fault status cleared on read */
 255                 env->mmuregs[reg] = 0;
 256             DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
 257         }
 258         break;
 259     case 9: /* Supervisor code access */
 260         switch(size) {
 261         case 1:
 262             ret = ldub_code(T0);
 263             break;
 264         case 2:
 265             ret = lduw_code(T0 & ~1);
 266             break;
 267         default:
 268         case 4:
 269             ret = ldl_code(T0 & ~3);
 270             break;
 271         case 8:
 272             tmp = ldq_code(T0 & ~7);
 273             ret = tmp >> 32;
 274             T0 = tmp;
 275             break;
 276         }
 277         break;
 278     case 0xa: /* User data access */
 279         switch(size) {
 280         case 1:
 281             ret = ldub_user(T0);
 282             break;
 283         case 2:
 284             ret = lduw_user(T0 & ~1);
 285             break;
 286         default:
 287         case 4:
 288             ret = ldl_user(T0 & ~3);
 289             break;
 290         case 8:
 291             tmp = ldq_user(T0 & ~7);
 292             ret = tmp >> 32;
 293             T0 = tmp;
 294             break;
 295         }
 296         break;
 297     case 0xb: /* Supervisor data access */
 298         switch(size) {
 299         case 1:
 300             ret = ldub_kernel(T0);
 301             break;
 302         case 2:
 303             ret = lduw_kernel(T0 & ~1);
 304             break;
 305         default:
 306         case 4:
 307             ret = ldl_kernel(T0 & ~3);
 308             break;
 309         case 8:
 310             tmp = ldq_kernel(T0 & ~7);
 311             ret = tmp >> 32;
 312             T0 = tmp;
 313             break;
 314         }
 315         break;
 316     case 0xc: /* I-cache tag */
 317     case 0xd: /* I-cache data */
 318     case 0xe: /* D-cache tag */
 319     case 0xf: /* D-cache data */
 320         break;
 321     case 0x20: /* MMU passthrough */
 322         switch(size) {
 323         case 1:
 324             ret = ldub_phys(T0);
 325             break;
 326         case 2:
 327             ret = lduw_phys(T0 & ~1);
 328             break;
 329         default:
 330         case 4:
 331             ret = ldl_phys(T0 & ~3);
 332             break;
 333         case 8:
 334             tmp = ldq_phys(T0 & ~7);
 335             ret = tmp >> 32;
 336             T0 = tmp;
 337             break;
 338         }
 339         break;
 340     case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
 341     case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
 342         switch(size) {
 343         case 1:
 344             ret = ldub_phys((target_phys_addr_t)T0
 345                             | ((target_phys_addr_t)(asi & 0xf) << 32));
 346             break;
 347         case 2:
 348             ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
 349                             | ((target_phys_addr_t)(asi & 0xf) << 32));
 350             break;
 351         default:
 352         case 4:
 353             ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
 354                            | ((target_phys_addr_t)(asi & 0xf) << 32));
 355             break;
 356         case 8:
 357             tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
 358                            | ((target_phys_addr_t)(asi & 0xf) << 32));
 359             ret = tmp >> 32;
 360             T0 = tmp;
 361             break;
 362         }
 363         break;
 364     case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
 365     default:
 366         do_unassigned_access(T0, 0, 0, 1);
 367         ret = 0;
 368         break;
 369     }
 370     if (sign) {
 371         switch(size) {
 372         case 1:
 373             T1 = (int8_t) ret;
 374             break;
 375         case 2:
 376             T1 = (int16_t) ret;
 377             break;
 378         default:
 379             T1 = ret;
 380             break;
 381         }
 382     }
 383     else
 384         T1 = ret;
 385 }
 386
 387 void helper_st_asi(int asi, int size)
 388 {
 389     switch(asi) {
 390     case 2: /* SuperSparc MXCC registers */
 391         switch (T0) {
 392         case 0x01c00000: /* MXCC stream data register 0 */
 393             if (size == 8)
 394                 env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
 395             else
 396                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 397             break;
 398         case 0x01c00008: /* MXCC stream data register 1 */
 399             if (size == 8)
 400                 env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
 401             else
 402                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 403             break;
 404         case 0x01c00010: /* MXCC stream data register 2 */
 405             if (size == 8)
 406                 env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
 407             else
 408                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 409             break;
 410         case 0x01c00018: /* MXCC stream data register 3 */
 411             if (size == 8)
 412                 env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
 413             else
 414                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 415             break;
 416         case 0x01c00100: /* MXCC stream source */
 417             if (size == 8)
 418                 env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
 419             else
 420                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 421             env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +  0);
 422             env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +  8);
 423             env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
 424             env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
 425             break;
 426         case 0x01c00200: /* MXCC stream destination */
 427             if (size == 8)
 428                 env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
 429             else
 430                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 431             stq_phys((env->mxccregs[1] & 0xffffffffULL) +  0, env->mxccdata[0]);
 432             stq_phys((env->mxccregs[1] & 0xffffffffULL) +  8, env->mxccdata[1]);
 433             stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
 434             stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
 435             break;
 436         case 0x01c00a00: /* MXCC control register */
 437             if (size == 8)
 438                 env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
 439             else
 440                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 441             break;
 442         case 0x01c00a04: /* MXCC control register */
 443             if (size == 4)
 444                 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1;
 445             else
 446                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 447             break;
 448         case 0x01c00e00: /* MXCC error register  */
 449             // writing a 1 bit clears the error
 450             if (size == 8)
 451                 env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
 452             else
 453                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 454             break;
 455         case 0x01c00f00: /* MBus port address register */
 456             if (size == 8)
 457                 env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
 458             else
 459                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
 460             break;
 461         default:
 462             DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
 463             break;
 464         }
 465         DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
 466 #ifdef DEBUG_MXCC
 467         dump_mxcc(env);
 468 #endif
 469         break;
 470     case 3: /* MMU flush */
 471         {
 472             int mmulev;
 473
 474             mmulev = (T0 >> 8) & 15;
 475             DPRINTF_MMU("mmu flush level %d\n", mmulev);
 476             switch (mmulev) {
 477             case 0: // flush page
 478                 tlb_flush_page(env, T0 & 0xfffff000);
 479                 break;
 480             case 1: // flush segment (256k)
 481             case 2: // flush region (16M)
 482             case 3: // flush context (4G)
 483             case 4: // flush entire
 484                 tlb_flush(env, 1);
 485                 break;
 486             default:
 487                 break;
 488             }
 489 #ifdef DEBUG_MMU
 490             dump_mmu(env);
 491 #endif
 492             return;
 493         }
 494     case 4: /* write MMU regs */
 495         {
 496             int reg = (T0 >> 8) & 0xf;
 497             uint32_t oldreg;
 498
 499             oldreg = env->mmuregs[reg];
 500             switch(reg) {
 501             case 0:
 502                 env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
 503                 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
 504                 // Mappings generated during no-fault mode or MMU
 505                 // disabled mode are invalid in normal mode
 506                 if (oldreg != env->mmuregs[reg])
 507                     tlb_flush(env, 1);
 508                 break;
 509             case 2:
 510                 env->mmuregs[reg] = T1;
 511                 if (oldreg != env->mmuregs[reg]) {
 512                     /* we flush when the MMU context changes because
 513                        QEMU has no MMU context support */
 514                     tlb_flush(env, 1);
 515                 }
 516                 break;
 517             case 3:
 518             case 4:
 519                 break;
 520             default:
 521                 env->mmuregs[reg] = T1;
 522                 break;
 523             }
 524             if (oldreg != env->mmuregs[reg]) {
 525                 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
 526             }
 527 #ifdef DEBUG_MMU
 528             dump_mmu(env);
 529 #endif
 530             return;
 531         }
 532     case 0xa: /* User data access */
 533         switch(size) {
 534         case 1:
 535             stb_user(T0, T1);
 536             break;
 537         case 2:
 538             stw_user(T0 & ~1, T1);
 539             break;
 540         default:
 541         case 4:
 542             stl_user(T0 & ~3, T1);
 543             break;
 544         case 8:
 545             stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
 546             break;
 547         }
 548         break;
 549     case 0xb: /* Supervisor data access */
 550         switch(size) {
 551         case 1:
 552             stb_kernel(T0, T1);
 553             break;
 554         case 2:
 555             stw_kernel(T0 & ~1, T1);
 556             break;
 557         default:
 558         case 4:
 559             stl_kernel(T0 & ~3, T1);
 560             break;
 561         case 8:
 562             stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
 563             break;
 564         }
 565         break;
 566     case 0xc: /* I-cache tag */
 567     case 0xd: /* I-cache data */
 568     case 0xe: /* D-cache tag */
 569     case 0xf: /* D-cache data */
 570     case 0x10: /* I/D-cache flush page */
 571     case 0x11: /* I/D-cache flush segment */
 572     case 0x12: /* I/D-cache flush region */
 573     case 0x13: /* I/D-cache flush context */
 574     case 0x14: /* I/D-cache flush user */
 575         break;
 576     case 0x17: /* Block copy, sta access */
 577         {
 578             // value (T1) = src
 579             // address (T0) = dst
 580             // copy 32 bytes
 581             unsigned int i;
 582             uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
 583
 584             for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
 585                 temp = ldl_kernel(src);
 586                 stl_kernel(dst, temp);
 587             }
 588         }
 589         return;
 590     case 0x1f: /* Block fill, stda access */
 591         {
 592             // value (T1, T2)
 593             // address (T0) = dst
 594             // fill 32 bytes
 595             unsigned int i;
 596             uint32_t dst = T0 & 7;
 597             uint64_t val;
 598
 599             val = (((uint64_t)T1) << 32) | T2;
 600
 601             for (i = 0; i < 32; i += 8, dst += 8)
 602                 stq_kernel(dst, val);
 603         }
 604         return;
 605     case 0x20: /* MMU passthrough */
 606         {
 607             switch(size) {
 608             case 1:
 609                 stb_phys(T0, T1);
 610                 break;
 611             case 2:
 612                 stw_phys(T0 & ~1, T1);
 613                 break;
 614             case 4:
 615             default:
 616                 stl_phys(T0 & ~3, T1);
 617                 break;
 618             case 8:
 619                 stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
 620                 break;
 621             }
 622         }
 623         return;
 624     case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
 625     case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
 626         {
 627             switch(size) {
 628             case 1:
 629                 stb_phys((target_phys_addr_t)T0
 630                          | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
 631                 break;
 632             case 2:
 633                 stw_phys((target_phys_addr_t)(T0 & ~1)
 634                             | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
 635                 break;
 636             case 4:
 637             default:
 638                 stl_phys((target_phys_addr_t)(T0 & ~3)
 639                            | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
 640                 break;
 641             case 8:
 642                 stq_phys((target_phys_addr_t)(T0 & ~7)
 643                            | ((target_phys_addr_t)(asi & 0xf) << 32),
 644                          ((uint64_t)T1 << 32) | T2);
 645                 break;
 646             }
 647         }
 648         return;
 649     case 0x31: /* Ross RT620 I-cache flush */
 650     case 0x36: /* I-cache flash clear */
 651     case 0x37: /* D-cache flash clear */
 652         break;
 653     case 9: /* Supervisor code access, XXX */
 654     case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
 655     default:
 656         do_unassigned_access(T0, 1, 0, 1);
 657         return;
 658     }
 659 }
 660
 661 #endif /* CONFIG_USER_ONLY */
 662 #else /* TARGET_SPARC64 */
 663
 664 #ifdef CONFIG_USER_ONLY
 665 void helper_ld_asi(int asi, int size, int sign)
 666 {
 667     uint64_t ret = 0;
 668
 669     if (asi < 0x80)
 670         raise_exception(TT_PRIV_ACT);
 671
 672     switch (asi) {
 673     case 0x80: // Primary
 674     case 0x82: // Primary no-fault
 675     case 0x88: // Primary LE
 676     case 0x8a: // Primary no-fault LE
 677         {
 678             switch(size) {
 679             case 1:
 680                 ret = ldub_raw(T0);
 681                 break;
 682             case 2:
 683                 ret = lduw_raw(T0 & ~1);
 684                 break;
 685             case 4:
 686                 ret = ldl_raw(T0 & ~3);
 687                 break;
 688             default:
 689             case 8:
 690                 ret = ldq_raw(T0 & ~7);
 691                 break;
 692             }
 693         }
 694         break;
 695     case 0x81: // Secondary
 696     case 0x83: // Secondary no-fault
 697     case 0x89: // Secondary LE
 698     case 0x8b: // Secondary no-fault LE
 699         // XXX
 700         break;
 701     default:
 702         break;
 703     }
 704
 705     /* Convert from little endian */
 706     switch (asi) {
 707     case 0x88: // Primary LE
 708     case 0x89: // Secondary LE
 709     case 0x8a: // Primary no-fault LE
 710     case 0x8b: // Secondary no-fault LE
 711         switch(size) {
 712         case 2:
 713             ret = bswap16(ret);
 714             break;
 715         case 4:
 716             ret = bswap32(ret);
 717             break;
 718         case 8:
 719             ret = bswap64(ret);
 720             break;
 721         default:
 722             break;
 723         }
 724     default:
 725         break;
 726     }
 727
 728     /* Convert to signed number */
 729     if (sign) {
 730         switch(size) {
 731         case 1:
 732             ret = (int8_t) ret;
 733             break;
 734         case 2:
 735             ret = (int16_t) ret;
 736             break;
 737         case 4:
 738             ret = (int32_t) ret;
 739             break;
 740         default:
 741             break;
 742         }
 743     }
 744     T1 = ret;
 745 }
 746
 747 void helper_st_asi(int asi, int size)
 748 {
 749     if (asi < 0x80)
 750         raise_exception(TT_PRIV_ACT);
 751
 752     /* Convert to little endian */
 753     switch (asi) {
 754     case 0x88: // Primary LE
 755     case 0x89: // Secondary LE
 756         switch(size) {
 757         case 2:
 758             T0 = bswap16(T0);
 759             break;
 760         case 4:
 761             T0 = bswap32(T0);
 762             break;
 763         case 8:
 764             T0 = bswap64(T0);
 765             break;
 766         default:
 767             break;
 768         }
 769     default:
 770         break;
 771     }
 772
 773     switch(asi) {
 774     case 0x80: // Primary
 775     case 0x88: // Primary LE
 776         {
 777             switch(size) {
 778             case 1:
 779                 stb_raw(T0, T1);
 780                 break;
 781             case 2:
 782                 stw_raw(T0 & ~1, T1);
 783                 break;
 784             case 4:
 785                 stl_raw(T0 & ~3, T1);
 786                 break;
 787             case 8:
 788             default:
 789                 stq_raw(T0 & ~7, T1);
 790                 break;
 791             }
 792         }
 793         break;
 794     case 0x81: // Secondary
 795     case 0x89: // Secondary LE
 796         // XXX
 797         return;
 798
 799     case 0x82: // Primary no-fault, RO
 800     case 0x83: // Secondary no-fault, RO
 801     case 0x8a: // Primary no-fault LE, RO
 802     case 0x8b: // Secondary no-fault LE, RO
 803     default:
 804         do_unassigned_access(T0, 1, 0, 1);
 805         return;
 806     }
 807 }
 808
 809 #else /* CONFIG_USER_ONLY */
 810
 811 void helper_ld_asi(int asi, int size, int sign)
 812 {
 813     uint64_t ret = 0;
 814
 815     if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
 816         || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
 817         raise_exception(TT_PRIV_ACT);
 818
 819     switch (asi) {
 820     case 0x10: // As if user primary
 821     case 0x18: // As if user primary LE
 822     case 0x80: // Primary
 823     case 0x82: // Primary no-fault
 824     case 0x88: // Primary LE
 825     case 0x8a: // Primary no-fault LE
 826         if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
 827             if (env->hpstate & HS_PRIV) {
 828                 switch(size) {
 829                 case 1:
 830                     ret = ldub_hypv(T0);
 831                     break;
 832                 case 2:
 833                     ret = lduw_hypv(T0 & ~1);
 834                     break;
 835                 case 4:
 836                     ret = ldl_hypv(T0 & ~3);
 837                     break;
 838                 default:
 839                 case 8:
 840                     ret = ldq_hypv(T0 & ~7);
 841                     break;
 842                 }
 843             } else {
 844                 switch(size) {
 845                 case 1:
 846                     ret = ldub_kernel(T0);
 847                     break;
 848                 case 2:
 849                     ret = lduw_kernel(T0 & ~1);
 850                     break;
 851                 case 4:
 852                     ret = ldl_kernel(T0 & ~3);
 853                     break;
 854                 default:
 855                 case 8:
 856                     ret = ldq_kernel(T0 & ~7);
 857                     break;
 858                 }
 859             }
 860         } else {
 861             switch(size) {
 862             case 1:
 863                 ret = ldub_user(T0);
 864                 break;
 865             case 2:
 866                 ret = lduw_user(T0 & ~1);
 867                 break;
 868             case 4:
 869                 ret = ldl_user(T0 & ~3);
 870                 break;
 871             default:
 872             case 8:
 873                 ret = ldq_user(T0 & ~7);
 874                 break;
 875             }
 876         }
 877         break;
 878     case 0x14: // Bypass
 879     case 0x15: // Bypass, non-cacheable
 880     case 0x1c: // Bypass LE
 881     case 0x1d: // Bypass, non-cacheable LE
 882         {
 883             switch(size) {
 884             case 1:
 885                 ret = ldub_phys(T0);
 886                 break;
 887             case 2:
 888                 ret = lduw_phys(T0 & ~1);
 889                 break;
 890             case 4:
 891                 ret = ldl_phys(T0 & ~3);
 892                 break;
 893             default:
 894             case 8:
 895                 ret = ldq_phys(T0 & ~7);
 896                 break;
 897             }
 898             break;
 899         }
 900     case 0x04: // Nucleus
 901     case 0x0c: // Nucleus Little Endian (LE)
 902     case 0x11: // As if user secondary
 903     case 0x19: // As if user secondary LE
 904     case 0x24: // Nucleus quad LDD 128 bit atomic
 905     case 0x2c: // Nucleus quad LDD 128 bit atomic
 906     case 0x4a: // UPA config
 907     case 0x81: // Secondary
 908     case 0x83: // Secondary no-fault
 909     case 0x89: // Secondary LE
 910     case 0x8b: // Secondary no-fault LE
 911         // XXX
 912         break;
 913     case 0x45: // LSU
 914         ret = env->lsu;
 915         break;
 916     case 0x50: // I-MMU regs
 917         {
 918             int reg = (T0 >> 3) & 0xf;
 919
 920             ret = env->immuregs[reg];
 921             break;
 922         }
 923     case 0x51: // I-MMU 8k TSB pointer
 924     case 0x52: // I-MMU 64k TSB pointer
 925     case 0x55: // I-MMU data access
 926         // XXX
 927         break;
 928     case 0x56: // I-MMU tag read
 929         {
 930             unsigned int i;
 931
 932             for (i = 0; i < 64; i++) {
 933                 // Valid, ctx match, vaddr match
 934                 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
 935                     env->itlb_tag[i] == T0) {
 936                     ret = env->itlb_tag[i];
 937                     break;
 938                 }
 939             }
 940             break;
 941         }
 942     case 0x58: // D-MMU regs
 943         {
 944             int reg = (T0 >> 3) & 0xf;
 945
 946             ret = env->dmmuregs[reg];
 947             break;
 948         }
 949     case 0x5e: // D-MMU tag read
 950         {
 951             unsigned int i;
 952
 953             for (i = 0; i < 64; i++) {
 954                 // Valid, ctx match, vaddr match
 955                 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
 956                     env->dtlb_tag[i] == T0) {
 957                     ret = env->dtlb_tag[i];
 958                     break;
 959                 }
 960             }
 961             break;
 962         }
 963     case 0x59: // D-MMU 8k TSB pointer
 964     case 0x5a: // D-MMU 64k TSB pointer
 965     case 0x5b: // D-MMU data pointer
 966     case 0x5d: // D-MMU data access
 967     case 0x48: // Interrupt dispatch, RO
 968     case 0x49: // Interrupt data receive
 969     case 0x7f: // Incoming interrupt vector, RO
 970         // XXX
 971         break;
 972     case 0x54: // I-MMU data in, WO
 973     case 0x57: // I-MMU demap, WO
 974     case 0x5c: // D-MMU data in, WO
 975     case 0x5f: // D-MMU demap, WO
 976     case 0x77: // Interrupt vector, WO
 977     default:
 978         do_unassigned_access(T0, 0, 0, 1);
 979         ret = 0;
 980         break;
 981     }
 982
 983     /* Convert from little endian */
 984     switch (asi) {
 985     case 0x0c: // Nucleus Little Endian (LE)
 986     case 0x18: // As if user primary LE
 987     case 0x19: // As if user secondary LE
 988     case 0x1c: // Bypass LE
 989     case 0x1d: // Bypass, non-cacheable LE
 990     case 0x88: // Primary LE
 991     case 0x89: // Secondary LE
 992     case 0x8a: // Primary no-fault LE
 993     case 0x8b: // Secondary no-fault LE
 994         switch(size) {
 995         case 2:
 996             ret = bswap16(ret);
 997             break;
 998         case 4:
 999             ret = bswap32(ret);
1000             break;
1001         case 8:
1002             ret = bswap64(ret);
1003             break;
1004         default:
1005             break;
1006         }
1007     default:
1008         break;
1009     }
1010
1011     /* Convert to signed number */
1012     if (sign) {
1013         switch(size) {
1014         case 1:
1015             ret = (int8_t) ret;
1016             break;
1017         case 2:
1018             ret = (int16_t) ret;
1019             break;
1020         case 4:
1021             ret = (int32_t) ret;
1022             break;
1023         default:
1024             break;
1025         }
1026     }
1027     T1 = ret;
1028 }
1029
1030 void helper_st_asi(int asi, int size)
1031 {
1032     if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1033         || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1034         raise_exception(TT_PRIV_ACT);
1035
1036     /* Convert to little endian */
1037     switch (asi) {
1038     case 0x0c: // Nucleus Little Endian (LE)
1039     case 0x18: // As if user primary LE
1040     case 0x19: // As if user secondary LE
1041     case 0x1c: // Bypass LE
1042     case 0x1d: // Bypass, non-cacheable LE
1043     case 0x88: // Primary LE
1044     case 0x89: // Secondary LE
1045         switch(size) {
1046         case 2:
1047             T0 = bswap16(T0);
1048             break;
1049         case 4:
1050             T0 = bswap32(T0);
1051             break;
1052         case 8:
1053             T0 = bswap64(T0);
1054             break;
1055         default:
1056             break;
1057         }
1058     default:
1059         break;
1060     }
1061
1062     switch(asi) {
1063     case 0x10: // As if user primary
1064     case 0x18: // As if user primary LE
1065     case 0x80: // Primary
1066     case 0x88: // Primary LE
1067         if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1068             if (env->hpstate & HS_PRIV) {
1069                 switch(size) {
1070                 case 1:
1071                     stb_hypv(T0, T1);
1072                     break;
1073                 case 2:
1074                     stw_hypv(T0 & ~1, T1);
1075                     break;
1076                 case 4:
1077                     stl_hypv(T0 & ~3, T1);
1078                     break;
1079                 case 8:
1080                 default:
1081                     stq_hypv(T0 & ~7, T1);
1082                     break;
1083                 }
1084             } else {
1085                 switch(size) {
1086                 case 1:
1087                     stb_kernel(T0, T1);
1088                     break;
1089                 case 2:
1090                     stw_kernel(T0 & ~1, T1);
1091                     break;
1092                 case 4:
1093                     stl_kernel(T0 & ~3, T1);
1094                     break;
1095                 case 8:
1096                 default:
1097                     stq_kernel(T0 & ~7, T1);
1098                     break;
1099                 }
1100             }
1101         } else {
1102             switch(size) {
1103             case 1:
1104                 stb_user(T0, T1);
1105                 break;
1106             case 2:
1107                 stw_user(T0 & ~1, T1);
1108                 break;
1109             case 4:
1110                 stl_user(T0 & ~3, T1);
1111                 break;
1112             case 8:
1113             default:
1114                 stq_user(T0 & ~7, T1);
1115                 break;
1116             }
1117         }
1118         break;
1119     case 0x14: // Bypass
1120     case 0x15: // Bypass, non-cacheable
1121     case 0x1c: // Bypass LE
1122     case 0x1d: // Bypass, non-cacheable LE
1123         {
1124             switch(size) {
1125             case 1:
1126                 stb_phys(T0, T1);
1127                 break;
1128             case 2:
1129                 stw_phys(T0 & ~1, T1);
1130                 break;
1131             case 4:
1132                 stl_phys(T0 & ~3, T1);
1133                 break;
1134             case 8:
1135             default:
1136                 stq_phys(T0 & ~7, T1);
1137                 break;
1138             }
1139         }
1140         return;
1141     case 0x04: // Nucleus
1142     case 0x0c: // Nucleus Little Endian (LE)
1143     case 0x11: // As if user secondary
1144     case 0x19: // As if user secondary LE
1145     case 0x24: // Nucleus quad LDD 128 bit atomic
1146     case 0x2c: // Nucleus quad LDD 128 bit atomic
1147     case 0x4a: // UPA config
1148     case 0x81: // Secondary
1149     case 0x89: // Secondary LE
1150         // XXX
1151         return;
1152     case 0x45: // LSU
1153         {
1154             uint64_t oldreg;
1155
1156             oldreg = env->lsu;
1157             env->lsu = T1 & (DMMU_E | IMMU_E);
1158             // Mappings generated during D/I MMU disabled mode are
1159             // invalid in normal mode
1160             if (oldreg != env->lsu) {
1161                 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
1162 #ifdef DEBUG_MMU
1163                 dump_mmu(env);
1164 #endif
1165                 tlb_flush(env, 1);
1166             }
1167             return;
1168         }
1169     case 0x50: // I-MMU regs
1170         {
1171             int reg = (T0 >> 3) & 0xf;
1172             uint64_t oldreg;
1173
1174             oldreg = env->immuregs[reg];
1175             switch(reg) {
1176             case 0: // RO
1177             case 4:
1178                 return;
1179             case 1: // Not in I-MMU
1180             case 2:
1181             case 7:
1182             case 8:
1183                 return;
1184             case 3: // SFSR
1185                 if ((T1 & 1) == 0)
1186                     T1 = 0; // Clear SFSR
1187                 break;
1188             case 5: // TSB access
1189             case 6: // Tag access
1190             default:
1191                 break;
1192             }
1193             env->immuregs[reg] = T1;
1194             if (oldreg != env->immuregs[reg]) {
1195                 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1196             }
1197 #ifdef DEBUG_MMU
1198             dump_mmu(env);
1199 #endif
1200             return;
1201         }
1202     case 0x54: // I-MMU data in
1203         {
1204             unsigned int i;
1205
1206             // Try finding an invalid entry
1207             for (i = 0; i < 64; i++) {
1208                 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1209                     env->itlb_tag[i] = env->immuregs[6];
1210                     env->itlb_tte[i] = T1;
1211                     return;
1212                 }
1213             }
1214             // Try finding an unlocked entry
1215             for (i = 0; i < 64; i++) {
1216                 if ((env->itlb_tte[i] & 0x40) == 0) {
1217                     env->itlb_tag[i] = env->immuregs[6];
1218                     env->itlb_tte[i] = T1;
1219                     return;
1220                 }
1221             }
1222             // error state?
1223             return;
1224         }
1225     case 0x55: // I-MMU data access
1226         {
1227             unsigned int i = (T0 >> 3) & 0x3f;
1228
1229             env->itlb_tag[i] = env->immuregs[6];
1230             env->itlb_tte[i] = T1;
1231             return;
1232         }
1233     case 0x57: // I-MMU demap
1234         // XXX
1235         return;
1236     case 0x58: // D-MMU regs
1237         {
1238             int reg = (T0 >> 3) & 0xf;
1239             uint64_t oldreg;
1240
1241             oldreg = env->dmmuregs[reg];
1242             switch(reg) {
1243             case 0: // RO
1244             case 4:
1245                 return;
1246             case 3: // SFSR
1247                 if ((T1 & 1) == 0) {
1248                     T1 = 0; // Clear SFSR, Fault address
1249                     env->dmmuregs[4] = 0;
1250                 }
1251                 env->dmmuregs[reg] = T1;
1252                 break;
1253             case 1: // Primary context
1254             case 2: // Secondary context
1255             case 5: // TSB access
1256             case 6: // Tag access
1257             case 7: // Virtual Watchpoint
1258             case 8: // Physical Watchpoint
1259             default:
1260                 break;
1261             }
1262             env->dmmuregs[reg] = T1;
1263             if (oldreg != env->dmmuregs[reg]) {
1264                 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1265             }
1266 #ifdef DEBUG_MMU
1267             dump_mmu(env);
1268 #endif
1269             return;
1270         }
1271     case 0x5c: // D-MMU data in
1272         {
1273             unsigned int i;
1274
1275             // Try finding an invalid entry
1276             for (i = 0; i < 64; i++) {
1277                 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1278                     env->dtlb_tag[i] = env->dmmuregs[6];
1279                     env->dtlb_tte[i] = T1;
1280                     return;
1281                 }
1282             }
1283             // Try finding an unlocked entry
1284             for (i = 0; i < 64; i++) {
1285                 if ((env->dtlb_tte[i] & 0x40) == 0) {
1286                     env->dtlb_tag[i] = env->dmmuregs[6];
1287                     env->dtlb_tte[i] = T1;
1288                     return;
1289                 }
1290             }
1291             // error state?
1292             return;
1293         }
1294     case 0x5d: // D-MMU data access
1295         {
1296             unsigned int i = (T0 >> 3) & 0x3f;
1297
1298             env->dtlb_tag[i] = env->dmmuregs[6];
1299             env->dtlb_tte[i] = T1;
1300             return;
1301         }
1302     case 0x5f: // D-MMU demap
1303     case 0x49: // Interrupt data receive
1304         // XXX
1305         return;
1306     case 0x51: // I-MMU 8k TSB pointer, RO
1307     case 0x52: // I-MMU 64k TSB pointer, RO
1308     case 0x56: // I-MMU tag read, RO
1309     case 0x59: // D-MMU 8k TSB pointer, RO
1310     case 0x5a: // D-MMU 64k TSB pointer, RO
1311     case 0x5b: // D-MMU data pointer, RO
1312     case 0x5e: // D-MMU tag read, RO
1313     case 0x48: // Interrupt dispatch, RO
1314     case 0x7f: // Incoming interrupt vector, RO
1315     case 0x82: // Primary no-fault, RO
1316     case 0x83: // Secondary no-fault, RO
1317     case 0x8a: // Primary no-fault LE, RO
1318     case 0x8b: // Secondary no-fault LE, RO
1319     default:
1320         do_unassigned_access(T0, 1, 0, 1);
1321         return;
1322     }
1323 }
1324 #endif /* CONFIG_USER_ONLY */
1325
1326 void helper_ldf_asi(int asi, int size, int rd)
1327 {
1328     target_ulong tmp_T0 = T0, tmp_T1 = T1;
1329     unsigned int i;
1330
1331     switch (asi) {
1332     case 0xf0: // Block load primary
1333     case 0xf1: // Block load secondary
1334     case 0xf8: // Block load primary LE
1335     case 0xf9: // Block load secondary LE
1336         if (rd & 7) {
1337             raise_exception(TT_ILL_INSN);
1338             return;
1339         }
1340         if (T0 & 0x3f) {
1341             raise_exception(TT_UNALIGNED);
1342             return;
1343         }
1344         for (i = 0; i < 16; i++) {
1345             helper_ld_asi(asi & 0x8f, 4, 0);
1346             *(uint32_t *)&env->fpr[rd++] = T1;
1347             T0 += 4;
1348         }
1349         T0 = tmp_T0;
1350         T1 = tmp_T1;
1351
1352         return;
1353     default:
1354         break;
1355     }
1356
1357     helper_ld_asi(asi, size, 0);
1358     switch(size) {
1359     default:
1360     case 4:
1361         *((uint32_t *)&FT0) = T1;
1362         break;
1363     case 8:
1364         *((int64_t *)&DT0) = T1;
1365         break;
1366     }
1367     T1 = tmp_T1;
1368 }
1369
1370 void helper_stf_asi(int asi, int size, int rd)
1371 {
1372     target_ulong tmp_T0 = T0, tmp_T1 = T1;
1373     unsigned int i;
1374
1375     switch (asi) {
1376     case 0xf0: // Block store primary
1377     case 0xf1: // Block store secondary
1378     case 0xf8: // Block store primary LE
1379     case 0xf9: // Block store secondary LE
1380         if (rd & 7) {
1381             raise_exception(TT_ILL_INSN);
1382             return;
1383         }
1384         if (T0 & 0x3f) {
1385             raise_exception(TT_UNALIGNED);
1386             return;
1387         }
1388         for (i = 0; i < 16; i++) {
1389             T1 = *(uint32_t *)&env->fpr[rd++];
1390             helper_st_asi(asi & 0x8f, 4);
1391             T0 += 4;
1392         }
1393         T0 = tmp_T0;
1394         T1 = tmp_T1;
1395
1396         return;
1397     default:
1398         break;
1399     }
1400
1401     switch(size) {
1402     default:
1403     case 4:
1404         T1 = *((uint32_t *)&FT0);
1405         break;
1406     case 8:
1407         T1 = *((int64_t *)&DT0);
1408         break;
1409     }
1410     helper_st_asi(asi, size);
1411     T1 = tmp_T1;
1412 }
1413
1414 #endif /* TARGET_SPARC64 */
1415
1416 #ifndef TARGET_SPARC64
1417 void helper_rett()
1418 {
1419     unsigned int cwp;
1420
1421     if (env->psret == 1)
1422         raise_exception(TT_ILL_INSN);
1423
1424     env->psret = 1;
1425     cwp = (env->cwp + 1) & (NWINDOWS - 1);
1426     if (env->wim & (1 << cwp)) {
1427         raise_exception(TT_WIN_UNF);
1428     }
1429     set_cwp(cwp);
1430     env->psrs = env->psrps;
1431 }
1432 #endif
1433
1434 void helper_ldfsr(void)
1435 {
1436     int rnd_mode;
1437     switch (env->fsr & FSR_RD_MASK) {
1438     case FSR_RD_NEAREST:
1439         rnd_mode = float_round_nearest_even;
1440         break;
1441     default:
1442     case FSR_RD_ZERO:
1443         rnd_mode = float_round_to_zero;
1444         break;
1445     case FSR_RD_POS:
1446         rnd_mode = float_round_up;
1447         break;
1448     case FSR_RD_NEG:
1449         rnd_mode = float_round_down;
1450         break;
1451     }
1452     set_float_rounding_mode(rnd_mode, &env->fp_status);
1453 }
1454
1455 void helper_debug()
1456 {
1457     env->exception_index = EXCP_DEBUG;
1458     cpu_loop_exit();
1459 }
1460
1461 #ifndef TARGET_SPARC64
1462 void do_wrpsr()
1463 {
1464     if ((T0 & PSR_CWP) >= NWINDOWS)
1465         raise_exception(TT_ILL_INSN);
1466     else
1467         PUT_PSR(env, T0);
1468 }
1469
1470 void do_rdpsr()
1471 {
1472     T0 = GET_PSR(env);
1473 }
1474
1475 #else
1476
1477 void do_popc()
1478 {
1479     T0 = ctpop64(T1);
1480 }
1481
1482 static inline uint64_t *get_gregset(uint64_t pstate)
1483 {
1484     switch (pstate) {
1485     default:
1486     case 0:
1487         return env->bgregs;
1488     case PS_AG:
1489         return env->agregs;
1490     case PS_MG:
1491         return env->mgregs;
1492     case PS_IG:
1493         return env->igregs;
1494     }
1495 }
1496
1497 static inline void change_pstate(uint64_t new_pstate)
1498 {
1499     uint64_t pstate_regs, new_pstate_regs;
1500     uint64_t *src, *dst;
1501
1502     pstate_regs = env->pstate & 0xc01;
1503     new_pstate_regs = new_pstate & 0xc01;
1504     if (new_pstate_regs != pstate_regs) {
1505         // Switch global register bank
1506         src = get_gregset(new_pstate_regs);
1507         dst = get_gregset(pstate_regs);
1508         memcpy32(dst, env->gregs);
1509         memcpy32(env->gregs, src);
1510     }
1511     env->pstate = new_pstate;
1512 }
1513
1514 void do_wrpstate(void)
1515 {
1516     change_pstate(T0 & 0xf3f);
1517 }
1518
1519 void do_done(void)
1520 {
1521     env->tl--;
1522     env->pc = env->tnpc[env->tl];
1523     env->npc = env->tnpc[env->tl] + 4;
1524     PUT_CCR(env, env->tstate[env->tl] >> 32);
1525     env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1526     change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1527     PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1528 }
1529
1530 void do_retry(void)
1531 {
1532     env->tl--;
1533     env->pc = env->tpc[env->tl];
1534     env->npc = env->tnpc[env->tl];
1535     PUT_CCR(env, env->tstate[env->tl] >> 32);
1536     env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1537     change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1538     PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1539 }
1540 #endif
1541
1542 void set_cwp(int new_cwp)
1543 {
1544     /* put the modified wrap registers at their proper location */
1545     if (env->cwp == (NWINDOWS - 1))
1546         memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1547     env->cwp = new_cwp;
1548     /* put the wrap registers at their temporary location */
1549     if (new_cwp == (NWINDOWS - 1))
1550         memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1551     env->regwptr = env->regbase + (new_cwp * 16);
1552     REGWPTR = env->regwptr;
1553 }
1554
1555 void cpu_set_cwp(CPUState *env1, int new_cwp)
1556 {
1557     CPUState *saved_env;
1558 #ifdef reg_REGWPTR
1559     target_ulong *saved_regwptr;
1560 #endif
1561
1562     saved_env = env;
1563 #ifdef reg_REGWPTR
1564     saved_regwptr = REGWPTR;
1565 #endif
1566     env = env1;
1567     set_cwp(new_cwp);
1568     env = saved_env;
1569 #ifdef reg_REGWPTR
1570     REGWPTR = saved_regwptr;
1571 #endif
1572 }
1573
1574 #ifdef TARGET_SPARC64
1575 void do_interrupt(int intno)
1576 {
1577 #ifdef DEBUG_PCALL
1578     if (loglevel & CPU_LOG_INT) {
1579         static int count;
1580         fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
1581                 count, intno,
1582                 env->pc,
1583                 env->npc, env->regwptr[6]);
1584         cpu_dump_state(env, logfile, fprintf, 0);
1585 #if 0
1586         {
1587             int i;
1588             uint8_t *ptr;
1589
1590             fprintf(logfile, "       code=");
1591             ptr = (uint8_t *)env->pc;
1592             for(i = 0; i < 16; i++) {
1593                 fprintf(logfile, " %02x", ldub(ptr + i));
1594             }
1595             fprintf(logfile, "\n");
1596         }
1597 #endif
1598         count++;
1599     }
1600 #endif
1601 #if !defined(CONFIG_USER_ONLY)
1602     if (env->tl == MAXTL) {
1603         cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
1604         return;
1605     }
1606 #endif
1607     env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
1608         ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
1609     env->tpc[env->tl] = env->pc;
1610     env->tnpc[env->tl] = env->npc;
1611     env->tt[env->tl] = intno;
1612     change_pstate(PS_PEF | PS_PRIV | PS_AG);
1613
1614     if (intno == TT_CLRWIN)
1615         set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1616     else if ((intno & 0x1c0) == TT_SPILL)
1617         set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1618     else if ((intno & 0x1c0) == TT_FILL)
1619         set_cwp((env->cwp + 1) & (NWINDOWS - 1));
1620     env->tbr &= ~0x7fffULL;
1621     env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1622     if (env->tl < MAXTL - 1) {
1623         env->tl++;
1624     } else {
1625         env->pstate |= PS_RED;
1626         if (env->tl != MAXTL)
1627             env->tl++;
1628     }
1629     env->pc = env->tbr;
1630     env->npc = env->pc + 4;
1631     env->exception_index = 0;
1632 }
1633 #else
1634 void do_interrupt(int intno)
1635 {
1636     int cwp;
1637
1638 #ifdef DEBUG_PCALL
1639     if (loglevel & CPU_LOG_INT) {
1640         static int count;
1641         fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
1642                 count, intno,
1643                 env->pc,
1644                 env->npc, env->regwptr[6]);
1645         cpu_dump_state(env, logfile, fprintf, 0);
1646 #if 0
1647         {
1648             int i;
1649             uint8_t *ptr;
1650
1651             fprintf(logfile, "       code=");
1652             ptr = (uint8_t *)env->pc;
1653             for(i = 0; i < 16; i++) {
1654                 fprintf(logfile, " %02x", ldub(ptr + i));
1655             }
1656             fprintf(logfile, "\n");
1657         }
1658 #endif
1659         count++;
1660     }
1661 #endif
1662 #if !defined(CONFIG_USER_ONLY)
1663     if (env->psret == 0) {
1664         cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1665         return;
1666     }
1667 #endif
1668     env->psret = 0;
1669     cwp = (env->cwp - 1) & (NWINDOWS - 1);
1670     set_cwp(cwp);
1671     env->regwptr[9] = env->pc;
1672     env->regwptr[10] = env->npc;
1673     env->psrps = env->psrs;
1674     env->psrs = 1;
1675     env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1676     env->pc = env->tbr;
1677     env->npc = env->pc + 4;
1678     env->exception_index = 0;
1679 }
1680 #endif
1681
1682 #if !defined(CONFIG_USER_ONLY)
1683
1684 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1685                                 void *retaddr);
1686
1687 #define MMUSUFFIX _mmu
1688 #define ALIGNED_ONLY
1689 #ifdef __s390__
1690 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
1691 #else
1692 # define GETPC() (__builtin_return_address(0))
1693 #endif
1694
1695 #define SHIFT 0
1696 #include "softmmu_template.h"
1697
1698 #define SHIFT 1
1699 #include "softmmu_template.h"
1700
1701 #define SHIFT 2
1702 #include "softmmu_template.h"
1703
1704 #define SHIFT 3
1705 #include "softmmu_template.h"
1706
1707 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1708                                 void *retaddr)
1709 {
1710 #ifdef DEBUG_UNALIGNED
1711     printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1712 #endif
1713     raise_exception(TT_UNALIGNED);
1714 }
1715
1716 /* try to fill the TLB and return an exception if error. If retaddr is
1717    NULL, it means that the function was called in C code (i.e. not
1718    from generated code or from helper.c) */
1719 /* XXX: fix it to restore all registers */
1720 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1721 {
1722     TranslationBlock *tb;
1723     int ret;
1724     unsigned long pc;
1725     CPUState *saved_env;
1726
1727     /* XXX: hack to restore env in all cases, even if not called from
1728        generated code */
1729     saved_env = env;
1730     env = cpu_single_env;
1731
1732     ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1733     if (ret) {
1734         if (retaddr) {
1735             /* now we have a real cpu fault */
1736             pc = (unsigned long)retaddr;
1737             tb = tb_find_pc(pc);
1738             if (tb) {
1739                 /* the PC is inside the translated code. It means that we have
1740                    a virtual CPU fault */
1741                 cpu_restore_state(tb, env, pc, (void *)T2);
1742             }
1743         }
1744         cpu_loop_exit();
1745     }
1746     env = saved_env;
1747 }
1748
1749 #endif
1750
1751 #ifndef TARGET_SPARC64
1752 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1753                           int is_asi)
1754 {
1755     CPUState *saved_env;
1756
1757     /* XXX: hack to restore env in all cases, even if not called from
1758        generated code */
1759     saved_env = env;
1760     env = cpu_single_env;
1761     if (env->mmuregs[3]) /* Fault status register */
1762         env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1763     if (is_asi)
1764         env->mmuregs[3] |= 1 << 16;
1765     if (env->psrs)
1766         env->mmuregs[3] |= 1 << 5;
1767     if (is_exec)
1768         env->mmuregs[3] |= 1 << 6;
1769     if (is_write)
1770         env->mmuregs[3] |= 1 << 7;
1771     env->mmuregs[3] |= (5 << 2) | 2;
1772     env->mmuregs[4] = addr; /* Fault address register */
1773     if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1774 #ifdef DEBUG_UNASSIGNED
1775         printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1776                "\n", addr, env->pc);
1777 #endif
1778         if (is_exec)
1779             raise_exception(TT_CODE_ACCESS);
1780         else
1781             raise_exception(TT_DATA_ACCESS);
1782     }
1783     env = saved_env;
1784 }
1785 #else
1786 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1787                           int is_asi)
1788 {
1789 #ifdef DEBUG_UNASSIGNED
1790     CPUState *saved_env;
1791
1792     /* XXX: hack to restore env in all cases, even if not called from
1793        generated code */
1794     saved_env = env;
1795     env = cpu_single_env;
1796     printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
1797            addr, env->pc);
1798     env = saved_env;
1799 #endif
1800     if (is_exec)
1801         raise_exception(TT_CODE_ACCESS);
1802     else
1803         raise_exception(TT_DATA_ACCESS);
1804 }
1805 #endif
1806