2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
15 #include "scsi-disk.h"
18 //#define DEBUG_LSI_REG
21 #define DPRINTF(fmt, args...) \
22 do { printf("lsi_scsi: " fmt , ##args); } while (0)
23 #define BADF(fmt, args...) \
24 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
26 #define DPRINTF(fmt, args...) do {} while(0)
27 #define BADF(fmt, args...) \
28 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
31 #define LSI_SCNTL0_TRG 0x01
32 #define LSI_SCNTL0_AAP 0x02
33 #define LSI_SCNTL0_EPC 0x08
34 #define LSI_SCNTL0_WATN 0x10
35 #define LSI_SCNTL0_START 0x20
37 #define LSI_SCNTL1_SST 0x01
38 #define LSI_SCNTL1_IARB 0x02
39 #define LSI_SCNTL1_AESP 0x04
40 #define LSI_SCNTL1_RST 0x08
41 #define LSI_SCNTL1_CON 0x10
42 #define LSI_SCNTL1_DHP 0x20
43 #define LSI_SCNTL1_ADB 0x40
44 #define LSI_SCNTL1_EXC 0x80
46 #define LSI_SCNTL2_WSR 0x01
47 #define LSI_SCNTL2_VUE0 0x02
48 #define LSI_SCNTL2_VUE1 0x04
49 #define LSI_SCNTL2_WSS 0x08
50 #define LSI_SCNTL2_SLPHBEN 0x10
51 #define LSI_SCNTL2_SLPMD 0x20
52 #define LSI_SCNTL2_CHM 0x40
53 #define LSI_SCNTL2_SDU 0x80
55 #define LSI_ISTAT0_DIP 0x01
56 #define LSI_ISTAT0_SIP 0x02
57 #define LSI_ISTAT0_INTF 0x04
58 #define LSI_ISTAT0_CON 0x08
59 #define LSI_ISTAT0_SEM 0x10
60 #define LSI_ISTAT0_SIGP 0x20
61 #define LSI_ISTAT0_SRST 0x40
62 #define LSI_ISTAT0_ABRT 0x80
64 #define LSI_ISTAT1_SI 0x01
65 #define LSI_ISTAT1_SRUN 0x02
66 #define LSI_ISTAT1_FLSH 0x04
68 #define LSI_SSTAT0_SDP0 0x01
69 #define LSI_SSTAT0_RST 0x02
70 #define LSI_SSTAT0_WOA 0x04
71 #define LSI_SSTAT0_LOA 0x08
72 #define LSI_SSTAT0_AIP 0x10
73 #define LSI_SSTAT0_OLF 0x20
74 #define LSI_SSTAT0_ORF 0x40
75 #define LSI_SSTAT0_ILF 0x80
77 #define LSI_SIST0_PAR 0x01
78 #define LSI_SIST0_RST 0x02
79 #define LSI_SIST0_UDC 0x04
80 #define LSI_SIST0_SGE 0x08
81 #define LSI_SIST0_RSL 0x10
82 #define LSI_SIST0_SEL 0x20
83 #define LSI_SIST0_CMP 0x40
84 #define LSI_SIST0_MA 0x80
86 #define LSI_SIST1_HTH 0x01
87 #define LSI_SIST1_GEN 0x02
88 #define LSI_SIST1_STO 0x04
89 #define LSI_SIST1_SBMC 0x10
91 #define LSI_SOCL_IO 0x01
92 #define LSI_SOCL_CD 0x02
93 #define LSI_SOCL_MSG 0x04
94 #define LSI_SOCL_ATN 0x08
95 #define LSI_SOCL_SEL 0x10
96 #define LSI_SOCL_BSY 0x20
97 #define LSI_SOCL_ACK 0x40
98 #define LSI_SOCL_REQ 0x80
100 #define LSI_DSTAT_IID 0x01
101 #define LSI_DSTAT_SIR 0x04
102 #define LSI_DSTAT_SSI 0x08
103 #define LSI_DSTAT_ABRT 0x10
104 #define LSI_DSTAT_BF 0x20
105 #define LSI_DSTAT_MDPE 0x40
106 #define LSI_DSTAT_DFE 0x80
108 #define LSI_DCNTL_COM 0x01
109 #define LSI_DCNTL_IRQD 0x02
110 #define LSI_DCNTL_STD 0x04
111 #define LSI_DCNTL_IRQM 0x08
112 #define LSI_DCNTL_SSM 0x10
113 #define LSI_DCNTL_PFEN 0x20
114 #define LSI_DCNTL_PFF 0x40
115 #define LSI_DCNTL_CLSE 0x80
117 #define LSI_DMODE_MAN 0x01
118 #define LSI_DMODE_BOF 0x02
119 #define LSI_DMODE_ERMP 0x04
120 #define LSI_DMODE_ERL 0x08
121 #define LSI_DMODE_DIOM 0x10
122 #define LSI_DMODE_SIOM 0x20
124 #define LSI_CTEST2_DACK 0x01
125 #define LSI_CTEST2_DREQ 0x02
126 #define LSI_CTEST2_TEOP 0x04
127 #define LSI_CTEST2_PCICIE 0x08
128 #define LSI_CTEST2_CM 0x10
129 #define LSI_CTEST2_CIO 0x20
130 #define LSI_CTEST2_SIGP 0x40
131 #define LSI_CTEST2_DDIR 0x80
133 #define LSI_CTEST5_BL2 0x04
134 #define LSI_CTEST5_DDIR 0x08
135 #define LSI_CTEST5_MASR 0x10
136 #define LSI_CTEST5_DFSN 0x20
137 #define LSI_CTEST5_BBCK 0x40
138 #define LSI_CTEST5_ADCK 0x80
140 #define LSI_CCNTL0_DILS 0x01
141 #define LSI_CCNTL0_DISFC 0x10
142 #define LSI_CCNTL0_ENNDJ 0x20
143 #define LSI_CCNTL0_PMJCTL 0x40
144 #define LSI_CCNTL0_ENPMJ 0x80
154 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */
155 #define LSI_MAX_DEVS 7
157 /* Maximum length of MSG IN data. */
158 #define LSI_MAX_MSGIN_LEN 8
160 /* Flag set if this is a tagged command. */
161 #define LSI_TAG_VALID (1 << 16)
173 uint32_t script_ram_base
;
175 int carry
; /* ??? Should this be an a visible register somewhere? */
177 /* Action to take at the end of a MSG IN phase.
178 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
181 uint8_t msg
[LSI_MAX_MSGIN_LEN
];
182 /* 0 if SCRIPTS are running or stopped.
183 * 1 if a Wait Reselect instruction has been issued.
184 * 2 if processing DMA from lsi_execute_script.
185 * 3 if a DMA operation is in progress. */
187 SCSIDevice
*scsi_dev
[LSI_MAX_DEVS
];
188 SCSIDevice
*current_dev
;
190 /* The tag is a combination of the device ID and the SCSI tag. */
191 uint32_t current_tag
;
192 uint32_t current_dma_len
;
256 uint32_t scratch
[18]; /* SCRATCHA-SCRATCHR */
258 /* Script ram is stored as 32-bit words in host byteorder. */
259 uint32_t script_ram
[2048];
262 static void lsi_soft_reset(LSIState
*s
)
272 memset(s
->scratch
, 0, sizeof(s
->scratch
));
326 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
);
327 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
);
328 static void lsi_execute_script(LSIState
*s
);
330 static inline uint32_t read_dword(LSIState
*s
, uint32_t addr
)
334 /* Optimize reading from SCRIPTS RAM. */
335 if ((addr
& 0xffffe000) == s
->script_ram_base
) {
336 return s
->script_ram
[(addr
& 0x1fff) >> 2];
338 cpu_physical_memory_read(addr
, (uint8_t *)&buf
, 4);
339 return cpu_to_le32(buf
);
342 static void lsi_stop_script(LSIState
*s
)
344 s
->istat1
&= ~LSI_ISTAT1_SRUN
;
347 static void lsi_update_irq(LSIState
*s
)
350 static int last_level
;
352 /* It's unclear whether the DIP/SIP bits should be cleared when the
353 Interrupt Status Registers are cleared or when istat0 is read.
354 We currently do the formwer, which seems to work. */
357 if (s
->dstat
& s
->dien
)
359 s
->istat0
|= LSI_ISTAT0_DIP
;
361 s
->istat0
&= ~LSI_ISTAT0_DIP
;
364 if (s
->sist0
|| s
->sist1
) {
365 if ((s
->sist0
& s
->sien0
) || (s
->sist1
& s
->sien1
))
367 s
->istat0
|= LSI_ISTAT0_SIP
;
369 s
->istat0
&= ~LSI_ISTAT0_SIP
;
371 if (s
->istat0
& LSI_ISTAT0_INTF
)
374 if (level
!= last_level
) {
375 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
376 level
, s
->dstat
, s
->sist1
, s
->sist0
);
379 qemu_set_irq(s
->pci_dev
.irq
[0], level
);
382 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
383 static void lsi_script_scsi_interrupt(LSIState
*s
, int stat0
, int stat1
)
388 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
389 stat1
, stat0
, s
->sist1
, s
->sist0
);
392 /* Stop processor on fatal or unmasked interrupt. As a special hack
393 we don't stop processing when raising STO. Instead continue
394 execution and stop at the next insn that accesses the SCSI bus. */
395 mask0
= s
->sien0
| ~(LSI_SIST0_CMP
| LSI_SIST0_SEL
| LSI_SIST0_RSL
);
396 mask1
= s
->sien1
| ~(LSI_SIST1_GEN
| LSI_SIST1_HTH
);
397 mask1
&= ~LSI_SIST1_STO
;
398 if (s
->sist0
& mask0
|| s
->sist1
& mask1
) {
404 /* Stop SCRIPTS execution and raise a DMA interrupt. */
405 static void lsi_script_dma_interrupt(LSIState
*s
, int stat
)
407 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat
, s
->dstat
);
413 static inline void lsi_set_phase(LSIState
*s
, int phase
)
415 s
->sstat1
= (s
->sstat1
& ~PHASE_MASK
) | phase
;
418 static void lsi_bad_phase(LSIState
*s
, int out
, int new_phase
)
420 /* Trigger a phase mismatch. */
421 if (s
->ccntl0
& LSI_CCNTL0_ENPMJ
) {
422 if ((s
->ccntl0
& LSI_CCNTL0_PMJCTL
) || out
) {
427 DPRINTF("Data phase mismatch jump to %08x\n", s
->dsp
);
429 DPRINTF("Phase mismatch interrupt\n");
430 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
433 lsi_set_phase(s
, new_phase
);
437 /* Resume SCRIPTS execution after a DMA operation. */
438 static void lsi_resume_script(LSIState
*s
)
440 if (s
->waiting
!= 2) {
442 lsi_execute_script(s
);
448 /* Initiate a SCSI layer data transfer. */
449 static void lsi_do_dma(LSIState
*s
, int out
)
454 if (!s
->current_dma_len
) {
455 /* Wait until data is available. */
456 DPRINTF("DMA no data available\n");
461 if (count
> s
->current_dma_len
)
462 count
= s
->current_dma_len
;
463 DPRINTF("DMA addr=0x%08x len=%d\n", s
->dnad
, count
);
470 if (s
->dma_buf
== NULL
) {
471 s
->dma_buf
= scsi_get_buf(s
->current_dev
, s
->current_tag
);
474 /* ??? Set SFBR to first data byte. */
476 cpu_physical_memory_read(addr
, s
->dma_buf
, count
);
478 cpu_physical_memory_write(addr
, s
->dma_buf
, count
);
480 s
->current_dma_len
-= count
;
481 if (s
->current_dma_len
== 0) {
484 /* Write the data. */
485 scsi_write_data(s
->current_dev
, s
->current_tag
);
487 /* Request any remaining data. */
488 scsi_read_data(s
->current_dev
, s
->current_tag
);
492 lsi_resume_script(s
);
497 /* Add a command to the queue. */
498 static void lsi_queue_command(LSIState
*s
)
502 DPRINTF("Queueing tag=0x%x\n", s
->current_tag
);
503 if (s
->queue_len
== s
->active_commands
) {
505 s
->queue
= realloc(s
->queue
, s
->queue_len
* sizeof(lsi_queue
));
507 p
= &s
->queue
[s
->active_commands
++];
508 p
->tag
= s
->current_tag
;
510 p
->out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
513 /* Queue a byte for a MSG IN phase. */
514 static void lsi_add_msg_byte(LSIState
*s
, uint8_t data
)
516 if (s
->msg_len
>= LSI_MAX_MSGIN_LEN
) {
517 BADF("MSG IN data too long\n");
519 DPRINTF("MSG IN 0x%02x\n", data
);
520 s
->msg
[s
->msg_len
++] = data
;
524 /* Perform reselection to continue a command. */
525 static void lsi_reselect(LSIState
*s
, uint32_t tag
)
532 for (n
= 0; n
< s
->active_commands
; n
++) {
537 if (n
== s
->active_commands
) {
538 BADF("Reselected non-existant command tag=0x%x\n", tag
);
541 id
= (tag
>> 8) & 0xf;
543 DPRINTF("Reselected target %d\n", id
);
544 s
->current_dev
= s
->scsi_dev
[id
];
545 s
->current_tag
= tag
;
546 s
->scntl1
|= LSI_SCNTL1_CON
;
547 lsi_set_phase(s
, PHASE_MI
);
548 s
->msg_action
= p
->out
? 2 : 3;
549 s
->current_dma_len
= p
->pending
;
551 lsi_add_msg_byte(s
, 0x80);
552 if (s
->current_tag
& LSI_TAG_VALID
) {
553 lsi_add_msg_byte(s
, 0x20);
554 lsi_add_msg_byte(s
, tag
& 0xff);
557 s
->active_commands
--;
558 if (n
!= s
->active_commands
) {
559 s
->queue
[n
] = s
->queue
[s
->active_commands
];
563 /* Record that data is available for a queued command. Returns zero if
564 the device was reselected, nonzero if the IO is deferred. */
565 static int lsi_queue_tag(LSIState
*s
, uint32_t tag
, uint32_t arg
)
569 for (i
= 0; i
< s
->active_commands
; i
++) {
573 BADF("Multiple IO pending for tag %d\n", tag
);
576 if (s
->waiting
== 1) {
577 /* Reselect device. */
578 lsi_reselect(s
, tag
);
581 DPRINTF("Queueing IO tag=0x%x\n", tag
);
587 BADF("IO with unknown tag %d\n", tag
);
591 /* Callback to indicate that the SCSI layer has completed a transfer. */
592 static void lsi_command_complete(void *opaque
, int reason
, uint32_t tag
,
595 LSIState
*s
= (LSIState
*)opaque
;
598 out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
599 if (reason
== SCSI_REASON_DONE
) {
600 DPRINTF("Command complete sense=%d\n", (int)arg
);
602 if (s
->waiting
&& s
->dbc
!= 0) {
603 /* Raise phase mismatch for short transfers. */
604 lsi_bad_phase(s
, out
, PHASE_ST
);
606 lsi_set_phase(s
, PHASE_ST
);
608 lsi_resume_script(s
);
612 if (s
->waiting
== 1 || tag
!= s
->current_tag
) {
613 if (lsi_queue_tag(s
, tag
, arg
))
616 DPRINTF("Data ready tag=0x%x len=%d\n", tag
, arg
);
617 s
->current_dma_len
= arg
;
620 if (s
->waiting
== 1 || s
->dbc
== 0) {
621 lsi_resume_script(s
);
627 static void lsi_do_command(LSIState
*s
)
632 DPRINTF("Send command len=%d\n", s
->dbc
);
635 cpu_physical_memory_read(s
->dnad
, buf
, s
->dbc
);
637 n
= scsi_send_command(s
->current_dev
, s
->current_tag
, buf
, s
->current_lun
);
639 lsi_set_phase(s
, PHASE_DI
);
640 scsi_read_data(s
->current_dev
, s
->current_tag
);
642 lsi_set_phase(s
, PHASE_DO
);
643 scsi_write_data(s
->current_dev
, s
->current_tag
);
645 if (n
&& s
->current_dma_len
== 0) {
646 /* Command did not complete immediately so disconnect. */
647 lsi_add_msg_byte(s
, 2); /* SAVE DATA POINTER */
648 lsi_add_msg_byte(s
, 4); /* DISCONNECT */
649 lsi_set_phase(s
, PHASE_MI
);
651 lsi_queue_command(s
);
655 static void lsi_do_status(LSIState
*s
)
658 DPRINTF("Get status len=%d sense=%d\n", s
->dbc
, s
->sense
);
660 BADF("Bad Status move\n");
664 cpu_physical_memory_write(s
->dnad
, &sense
, 1);
665 lsi_set_phase(s
, PHASE_MI
);
667 lsi_add_msg_byte(s
, 0); /* COMMAND COMPLETE */
670 static void lsi_disconnect(LSIState
*s
)
672 s
->scntl1
&= ~LSI_SCNTL1_CON
;
673 s
->sstat1
&= ~PHASE_MASK
;
676 static void lsi_do_msgin(LSIState
*s
)
679 DPRINTF("Message in len=%d/%d\n", s
->dbc
, s
->msg_len
);
684 cpu_physical_memory_write(s
->dnad
, s
->msg
, len
);
685 /* Linux drivers rely on the last byte being in the SIDL. */
686 s
->sidl
= s
->msg
[len
- 1];
689 memmove(s
->msg
, s
->msg
+ len
, s
->msg_len
);
691 /* ??? Check if ATN (not yet implemented) is asserted and maybe
692 switch to PHASE_MO. */
693 switch (s
->msg_action
) {
695 lsi_set_phase(s
, PHASE_CMD
);
701 lsi_set_phase(s
, PHASE_DO
);
704 lsi_set_phase(s
, PHASE_DI
);
712 /* Read the next byte during a MSGOUT phase. */
713 static uint8_t lsi_get_msgbyte(LSIState
*s
)
716 cpu_physical_memory_read(s
->dnad
, &data
, 1);
722 static void lsi_do_msgout(LSIState
*s
)
727 DPRINTF("MSG out len=%d\n", s
->dbc
);
729 msg
= lsi_get_msgbyte(s
);
734 DPRINTF("MSG: Disconnect\n");
738 DPRINTF("MSG: No Operation\n");
739 lsi_set_phase(s
, PHASE_CMD
);
742 len
= lsi_get_msgbyte(s
);
743 msg
= lsi_get_msgbyte(s
);
744 DPRINTF("Extended message 0x%x (len %d)\n", msg
, len
);
747 DPRINTF("SDTR (ignored)\n");
751 DPRINTF("WDTR (ignored)\n");
758 case 0x20: /* SIMPLE queue */
759 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
760 DPRINTF("SIMPLE queue tag=0x%x\n", s
->current_tag
& 0xff);
762 case 0x21: /* HEAD of queue */
763 BADF("HEAD queue not implemented\n");
764 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
766 case 0x22: /* ORDERED queue */
767 BADF("ORDERED queue not implemented\n");
768 s
->current_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
771 if ((msg
& 0x80) == 0) {
774 s
->current_lun
= msg
& 7;
775 DPRINTF("Select LUN %d\n", s
->current_lun
);
776 lsi_set_phase(s
, PHASE_CMD
);
782 BADF("Unimplemented message 0x%02x\n", msg
);
783 lsi_set_phase(s
, PHASE_MI
);
784 lsi_add_msg_byte(s
, 7); /* MESSAGE REJECT */
788 /* Sign extend a 24-bit value. */
789 static inline int32_t sxt24(int32_t n
)
791 return (n
<< 8) >> 8;
794 static void lsi_memcpy(LSIState
*s
, uint32_t dest
, uint32_t src
, int count
)
797 uint8_t buf
[TARGET_PAGE_SIZE
];
799 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest
, src
, count
);
801 n
= (count
> TARGET_PAGE_SIZE
) ? TARGET_PAGE_SIZE
: count
;
802 cpu_physical_memory_read(src
, buf
, n
);
803 cpu_physical_memory_write(dest
, buf
, n
);
810 static void lsi_wait_reselect(LSIState
*s
)
813 DPRINTF("Wait Reselect\n");
814 if (s
->current_dma_len
)
815 BADF("Reselect with pending DMA\n");
816 for (i
= 0; i
< s
->active_commands
; i
++) {
817 if (s
->queue
[i
].pending
) {
818 lsi_reselect(s
, s
->queue
[i
].tag
);
822 if (s
->current_dma_len
== 0) {
827 static void lsi_execute_script(LSIState
*s
)
833 s
->istat1
|= LSI_ISTAT1_SRUN
;
835 insn
= read_dword(s
, s
->dsp
);
836 addr
= read_dword(s
, s
->dsp
+ 4);
837 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s
->dsp
, insn
, addr
);
839 s
->dcmd
= insn
>> 24;
841 switch (insn
>> 30) {
842 case 0: /* Block move. */
843 if (s
->sist1
& LSI_SIST1_STO
) {
844 DPRINTF("Delayed select timeout\n");
848 s
->dbc
= insn
& 0xffffff;
850 if (insn
& (1 << 29)) {
851 /* Indirect addressing. */
852 addr
= read_dword(s
, addr
);
853 } else if (insn
& (1 << 28)) {
856 /* Table indirect addressing. */
857 offset
= sxt24(addr
);
858 cpu_physical_memory_read(s
->dsa
+ offset
, (uint8_t *)buf
, 8);
859 s
->dbc
= cpu_to_le32(buf
[0]);
861 addr
= cpu_to_le32(buf
[1]);
863 if ((s
->sstat1
& PHASE_MASK
) != ((insn
>> 24) & 7)) {
864 DPRINTF("Wrong phase got %d expected %d\n",
865 s
->sstat1
& PHASE_MASK
, (insn
>> 24) & 7);
866 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
872 switch (s
->sstat1
& 0x7) {
898 BADF("Unimplemented phase %d\n", s
->sstat1
& PHASE_MASK
);
901 s
->dfifo
= s
->dbc
& 0xff;
902 s
->ctest5
= (s
->ctest5
& 0xfc) | ((s
->dbc
>> 8) & 3);
905 s
->ua
= addr
+ s
->dbc
;
908 case 1: /* IO or Read/Write instruction. */
909 opcode
= (insn
>> 27) & 7;
913 if (insn
& (1 << 25)) {
914 id
= read_dword(s
, s
->dsa
+ sxt24(insn
));
918 id
= (id
>> 16) & 0xf;
919 if (insn
& (1 << 26)) {
920 addr
= s
->dsp
+ sxt24(addr
);
926 if (s
->current_dma_len
&& (s
->ssid
& 0xf) == id
) {
927 DPRINTF("Already reselected by target %d\n", id
);
930 s
->sstat0
|= LSI_SSTAT0_WOA
;
931 s
->scntl1
&= ~LSI_SCNTL1_IARB
;
932 if (id
>= LSI_MAX_DEVS
|| !s
->scsi_dev
[id
]) {
933 DPRINTF("Selected absent target %d\n", id
);
934 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_STO
);
938 DPRINTF("Selected target %d%s\n",
939 id
, insn
& (1 << 3) ? " ATN" : "");
940 /* ??? Linux drivers compain when this is set. Maybe
941 it only applies in low-level mode (unimplemented).
942 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
943 s
->current_dev
= s
->scsi_dev
[id
];
944 s
->current_tag
= id
<< 8;
945 s
->scntl1
|= LSI_SCNTL1_CON
;
946 if (insn
& (1 << 3)) {
947 s
->socl
|= LSI_SOCL_ATN
;
949 lsi_set_phase(s
, PHASE_MO
);
951 case 1: /* Disconnect */
952 DPRINTF("Wait Disconect\n");
953 s
->scntl1
&= ~LSI_SCNTL1_CON
;
955 case 2: /* Wait Reselect */
956 lsi_wait_reselect(s
);
959 DPRINTF("Set%s%s%s%s\n",
960 insn
& (1 << 3) ? " ATN" : "",
961 insn
& (1 << 6) ? " ACK" : "",
962 insn
& (1 << 9) ? " TM" : "",
963 insn
& (1 << 10) ? " CC" : "");
964 if (insn
& (1 << 3)) {
965 s
->socl
|= LSI_SOCL_ATN
;
966 lsi_set_phase(s
, PHASE_MO
);
968 if (insn
& (1 << 9)) {
969 BADF("Target mode not implemented\n");
972 if (insn
& (1 << 10))
976 DPRINTF("Clear%s%s%s%s\n",
977 insn
& (1 << 3) ? " ATN" : "",
978 insn
& (1 << 6) ? " ACK" : "",
979 insn
& (1 << 9) ? " TM" : "",
980 insn
& (1 << 10) ? " CC" : "");
981 if (insn
& (1 << 3)) {
982 s
->socl
&= ~LSI_SOCL_ATN
;
984 if (insn
& (1 << 10))
995 static const char *opcode_names
[3] =
996 {"Write", "Read", "Read-Modify-Write"};
997 static const char *operator_names
[8] =
998 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1001 reg
= ((insn
>> 16) & 0x7f) | (insn
& 0x80);
1002 data8
= (insn
>> 8) & 0xff;
1003 opcode
= (insn
>> 27) & 7;
1004 operator = (insn
>> 24) & 7;
1005 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1006 opcode_names
[opcode
- 5], reg
,
1007 operator_names
[operator], data8
, s
->sfbr
,
1008 (insn
& (1 << 23)) ? " SFBR" : "");
1011 case 5: /* From SFBR */
1015 case 6: /* To SFBR */
1017 op0
= lsi_reg_readb(s
, reg
);
1020 case 7: /* Read-modify-write */
1022 op0
= lsi_reg_readb(s
, reg
);
1023 if (insn
& (1 << 23)) {
1035 case 1: /* Shift left */
1037 op0
= (op0
<< 1) | s
->carry
;
1051 op0
= (op0
>> 1) | (s
->carry
<< 7);
1056 s
->carry
= op0
< op1
;
1059 op0
+= op1
+ s
->carry
;
1061 s
->carry
= op0
<= op1
;
1063 s
->carry
= op0
< op1
;
1068 case 5: /* From SFBR */
1069 case 7: /* Read-modify-write */
1070 lsi_reg_writeb(s
, reg
, op0
);
1072 case 6: /* To SFBR */
1079 case 2: /* Transfer Control. */
1084 if ((insn
& 0x002e0000) == 0) {
1088 if (s
->sist1
& LSI_SIST1_STO
) {
1089 DPRINTF("Delayed select timeout\n");
1093 cond
= jmp
= (insn
& (1 << 19)) != 0;
1094 if (cond
== jmp
&& (insn
& (1 << 21))) {
1095 DPRINTF("Compare carry %d\n", s
->carry
== jmp
);
1096 cond
= s
->carry
!= 0;
1098 if (cond
== jmp
&& (insn
& (1 << 17))) {
1099 DPRINTF("Compare phase %d %c= %d\n",
1100 (s
->sstat1
& PHASE_MASK
),
1102 ((insn
>> 24) & 7));
1103 cond
= (s
->sstat1
& PHASE_MASK
) == ((insn
>> 24) & 7);
1105 if (cond
== jmp
&& (insn
& (1 << 18))) {
1108 mask
= (~insn
>> 8) & 0xff;
1109 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1110 s
->sfbr
, mask
, jmp
? '=' : '!', insn
& mask
);
1111 cond
= (s
->sfbr
& mask
) == (insn
& mask
);
1114 if (insn
& (1 << 23)) {
1115 /* Relative address. */
1116 addr
= s
->dsp
+ sxt24(addr
);
1118 switch ((insn
>> 27) & 7) {
1120 DPRINTF("Jump to 0x%08x\n", addr
);
1124 DPRINTF("Call 0x%08x\n", addr
);
1128 case 2: /* Return */
1129 DPRINTF("Return to 0x%08x\n", s
->temp
);
1132 case 3: /* Interrupt */
1133 DPRINTF("Interrupt 0x%08x\n", s
->dsps
);
1134 if ((insn
& (1 << 20)) != 0) {
1135 s
->istat0
|= LSI_ISTAT0_INTF
;
1138 lsi_script_dma_interrupt(s
, LSI_DSTAT_SIR
);
1142 DPRINTF("Illegal transfer control\n");
1143 lsi_script_dma_interrupt(s
, LSI_DSTAT_IID
);
1147 DPRINTF("Control condition failed\n");
1153 if ((insn
& (1 << 29)) == 0) {
1156 /* ??? The docs imply the destination address is loaded into
1157 the TEMP register. However the Linux drivers rely on
1158 the value being presrved. */
1159 dest
= read_dword(s
, s
->dsp
);
1161 lsi_memcpy(s
, dest
, addr
, insn
& 0xffffff);
1168 if (insn
& (1 << 28)) {
1169 addr
= s
->dsa
+ sxt24(addr
);
1172 reg
= (insn
>> 16) & 0xff;
1173 if (insn
& (1 << 24)) {
1174 cpu_physical_memory_read(addr
, data
, n
);
1175 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg
, n
,
1176 addr
, *(int *)data
);
1177 for (i
= 0; i
< n
; i
++) {
1178 lsi_reg_writeb(s
, reg
+ i
, data
[i
]);
1181 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg
, n
, addr
);
1182 for (i
= 0; i
< n
; i
++) {
1183 data
[i
] = lsi_reg_readb(s
, reg
+ i
);
1185 cpu_physical_memory_write(addr
, data
, n
);
1189 /* ??? Need to avoid infinite loops. */
1190 if (s
->istat1
& LSI_ISTAT1_SRUN
&& !s
->waiting
) {
1191 if (s
->dcntl
& LSI_DCNTL_SSM
) {
1192 lsi_script_dma_interrupt(s
, LSI_DSTAT_SSI
);
1197 DPRINTF("SCRIPTS execution stopped\n");
1200 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
)
1203 #define CASE_GET_REG32(name, addr) \
1204 case addr: return s->name & 0xff; \
1205 case addr + 1: return (s->name >> 8) & 0xff; \
1206 case addr + 2: return (s->name >> 16) & 0xff; \
1207 case addr + 3: return (s->name >> 24) & 0xff;
1209 #ifdef DEBUG_LSI_REG
1210 DPRINTF("Read reg %x\n", offset
);
1213 case 0x00: /* SCNTL0 */
1215 case 0x01: /* SCNTL1 */
1217 case 0x02: /* SCNTL2 */
1219 case 0x03: /* SCNTL3 */
1221 case 0x04: /* SCID */
1223 case 0x05: /* SXFER */
1225 case 0x06: /* SDID */
1227 case 0x07: /* GPREG0 */
1229 case 0xa: /* SSID */
1231 case 0xb: /* SBCL */
1232 /* ??? This is not correct. However it's (hopefully) only
1233 used for diagnostics, so should be ok. */
1235 case 0xc: /* DSTAT */
1236 tmp
= s
->dstat
| 0x80;
1237 if ((s
->istat0
& LSI_ISTAT0_INTF
) == 0)
1241 case 0x0d: /* SSTAT0 */
1243 case 0x0e: /* SSTAT1 */
1245 case 0x0f: /* SSTAT2 */
1246 return s
->scntl1
& LSI_SCNTL1_CON
? 0 : 2;
1247 CASE_GET_REG32(dsa
, 0x10)
1248 case 0x14: /* ISTAT0 */
1250 case 0x16: /* MBOX0 */
1252 case 0x17: /* MBOX1 */
1254 case 0x18: /* CTEST0 */
1256 case 0x19: /* CTEST1 */
1258 case 0x1a: /* CTEST2 */
1259 tmp
= LSI_CTEST2_DACK
| LSI_CTEST2_CM
;
1260 if (s
->istat0
& LSI_ISTAT0_SIGP
) {
1261 s
->istat0
&= ~LSI_ISTAT0_SIGP
;
1262 tmp
|= LSI_CTEST2_SIGP
;
1265 case 0x1b: /* CTEST3 */
1267 CASE_GET_REG32(temp
, 0x1c)
1268 case 0x20: /* DFIFO */
1270 case 0x21: /* CTEST4 */
1272 case 0x22: /* CTEST5 */
1274 case 0x24: /* DBC[0:7] */
1275 return s
->dbc
& 0xff;
1276 case 0x25: /* DBC[8:15] */
1277 return (s
->dbc
>> 8) & 0xff;
1278 case 0x26: /* DBC[16->23] */
1279 return (s
->dbc
>> 16) & 0xff;
1280 case 0x27: /* DCMD */
1282 CASE_GET_REG32(dsp
, 0x2c)
1283 CASE_GET_REG32(dsps
, 0x30)
1284 CASE_GET_REG32(scratch
[0], 0x34)
1285 case 0x38: /* DMODE */
1287 case 0x39: /* DIEN */
1289 case 0x3b: /* DCNTL */
1291 case 0x40: /* SIEN0 */
1293 case 0x41: /* SIEN1 */
1295 case 0x42: /* SIST0 */
1300 case 0x43: /* SIST1 */
1305 case 0x47: /* GPCNTL0 */
1307 case 0x48: /* STIME0 */
1309 case 0x4a: /* RESPID0 */
1311 case 0x4b: /* RESPID1 */
1313 case 0x4d: /* STEST1 */
1315 case 0x4e: /* STEST2 */
1317 case 0x4f: /* STEST3 */
1319 case 0x50: /* SIDL */
1320 /* This is needed by the linux drivers. We currently only update it
1321 during the MSG IN phase. */
1323 case 0x52: /* STEST4 */
1325 case 0x56: /* CCNTL0 */
1327 case 0x57: /* CCNTL1 */
1329 case 0x58: /* SBDL */
1330 /* Some drivers peek at the data bus during the MSG IN phase. */
1331 if ((s
->sstat1
& PHASE_MASK
) == PHASE_MI
)
1334 case 0x59: /* SBDL high */
1336 CASE_GET_REG32(mmrs
, 0xa0)
1337 CASE_GET_REG32(mmws
, 0xa4)
1338 CASE_GET_REG32(sfs
, 0xa8)
1339 CASE_GET_REG32(drs
, 0xac)
1340 CASE_GET_REG32(sbms
, 0xb0)
1341 CASE_GET_REG32(dmbs
, 0xb4)
1342 CASE_GET_REG32(dnad64
, 0xb8)
1343 CASE_GET_REG32(pmjad1
, 0xc0)
1344 CASE_GET_REG32(pmjad2
, 0xc4)
1345 CASE_GET_REG32(rbc
, 0xc8)
1346 CASE_GET_REG32(ua
, 0xcc)
1347 CASE_GET_REG32(ia
, 0xd4)
1348 CASE_GET_REG32(sbc
, 0xd8)
1349 CASE_GET_REG32(csbc
, 0xdc)
1351 if (offset
>= 0x5c && offset
< 0xa0) {
1354 n
= (offset
- 0x58) >> 2;
1355 shift
= (offset
& 3) * 8;
1356 return (s
->scratch
[n
] >> shift
) & 0xff;
1358 BADF("readb 0x%x\n", offset
);
1360 #undef CASE_GET_REG32
1363 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
)
1365 #define CASE_SET_REG32(name, addr) \
1366 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1367 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1368 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1369 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1371 #ifdef DEBUG_LSI_REG
1372 DPRINTF("Write reg %x = %02x\n", offset
, val
);
1375 case 0x00: /* SCNTL0 */
1377 if (val
& LSI_SCNTL0_START
) {
1378 BADF("Start sequence not implemented\n");
1381 case 0x01: /* SCNTL1 */
1382 s
->scntl1
= val
& ~LSI_SCNTL1_SST
;
1383 if (val
& LSI_SCNTL1_IARB
) {
1384 BADF("Immediate Arbritration not implemented\n");
1386 if (val
& LSI_SCNTL1_RST
) {
1387 s
->sstat0
|= LSI_SSTAT0_RST
;
1388 lsi_script_scsi_interrupt(s
, LSI_SIST0_RST
, 0);
1390 s
->sstat0
&= ~LSI_SSTAT0_RST
;
1393 case 0x02: /* SCNTL2 */
1394 val
&= ~(LSI_SCNTL2_WSR
| LSI_SCNTL2_WSS
);
1397 case 0x03: /* SCNTL3 */
1400 case 0x04: /* SCID */
1403 case 0x05: /* SXFER */
1406 case 0x06: /* SDID */
1407 if ((val
& 0xf) != (s
->ssid
& 0xf))
1408 BADF("Destination ID does not match SSID\n");
1409 s
->sdid
= val
& 0xf;
1411 case 0x07: /* GPREG0 */
1413 case 0x08: /* SFBR */
1414 /* The CPU is not allowed to write to this register. However the
1415 SCRIPTS register move instructions are. */
1418 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1419 /* Linux writes to these readonly registers on startup. */
1421 CASE_SET_REG32(dsa
, 0x10)
1422 case 0x14: /* ISTAT0 */
1423 s
->istat0
= (s
->istat0
& 0x0f) | (val
& 0xf0);
1424 if (val
& LSI_ISTAT0_ABRT
) {
1425 lsi_script_dma_interrupt(s
, LSI_DSTAT_ABRT
);
1427 if (val
& LSI_ISTAT0_INTF
) {
1428 s
->istat0
&= ~LSI_ISTAT0_INTF
;
1431 if (s
->waiting
== 1 && val
& LSI_ISTAT0_SIGP
) {
1432 DPRINTF("Woken by SIGP\n");
1435 lsi_execute_script(s
);
1437 if (val
& LSI_ISTAT0_SRST
) {
1441 case 0x16: /* MBOX0 */
1444 case 0x17: /* MBOX1 */
1447 case 0x1b: /* CTEST3 */
1448 s
->ctest3
= val
& 0x0f;
1450 CASE_SET_REG32(temp
, 0x1c)
1451 case 0x21: /* CTEST4 */
1453 BADF("Unimplemented CTEST4-FBL 0x%x\n", val
);
1457 case 0x22: /* CTEST5 */
1458 if (val
& (LSI_CTEST5_ADCK
| LSI_CTEST5_BBCK
)) {
1459 BADF("CTEST5 DMA increment not implemented\n");
1463 case 0x2c: /* DSP[0:7] */
1464 s
->dsp
&= 0xffffff00;
1467 case 0x2d: /* DSP[8:15] */
1468 s
->dsp
&= 0xffff00ff;
1471 case 0x2e: /* DSP[16:23] */
1472 s
->dsp
&= 0xff00ffff;
1473 s
->dsp
|= val
<< 16;
1475 case 0x2f: /* DSP[24:31] */
1476 s
->dsp
&= 0x00ffffff;
1477 s
->dsp
|= val
<< 24;
1478 if ((s
->dmode
& LSI_DMODE_MAN
) == 0
1479 && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1480 lsi_execute_script(s
);
1482 CASE_SET_REG32(dsps
, 0x30)
1483 CASE_SET_REG32(scratch
[0], 0x34)
1484 case 0x38: /* DMODE */
1485 if (val
& (LSI_DMODE_SIOM
| LSI_DMODE_DIOM
)) {
1486 BADF("IO mappings not implemented\n");
1490 case 0x39: /* DIEN */
1494 case 0x3b: /* DCNTL */
1495 s
->dcntl
= val
& ~(LSI_DCNTL_PFF
| LSI_DCNTL_STD
);
1496 if ((val
& LSI_DCNTL_STD
) && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1497 lsi_execute_script(s
);
1499 case 0x40: /* SIEN0 */
1503 case 0x41: /* SIEN1 */
1507 case 0x47: /* GPCNTL0 */
1509 case 0x48: /* STIME0 */
1512 case 0x49: /* STIME1 */
1514 DPRINTF("General purpose timer not implemented\n");
1515 /* ??? Raising the interrupt immediately seems to be sufficient
1516 to keep the FreeBSD driver happy. */
1517 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_GEN
);
1520 case 0x4a: /* RESPID0 */
1523 case 0x4b: /* RESPID1 */
1526 case 0x4d: /* STEST1 */
1529 case 0x4e: /* STEST2 */
1531 BADF("Low level mode not implemented\n");
1535 case 0x4f: /* STEST3 */
1537 BADF("SCSI FIFO test mode not implemented\n");
1541 case 0x56: /* CCNTL0 */
1544 case 0x57: /* CCNTL1 */
1547 CASE_SET_REG32(mmrs
, 0xa0)
1548 CASE_SET_REG32(mmws
, 0xa4)
1549 CASE_SET_REG32(sfs
, 0xa8)
1550 CASE_SET_REG32(drs
, 0xac)
1551 CASE_SET_REG32(sbms
, 0xb0)
1552 CASE_SET_REG32(dmbs
, 0xb4)
1553 CASE_SET_REG32(dnad64
, 0xb8)
1554 CASE_SET_REG32(pmjad1
, 0xc0)
1555 CASE_SET_REG32(pmjad2
, 0xc4)
1556 CASE_SET_REG32(rbc
, 0xc8)
1557 CASE_SET_REG32(ua
, 0xcc)
1558 CASE_SET_REG32(ia
, 0xd4)
1559 CASE_SET_REG32(sbc
, 0xd8)
1560 CASE_SET_REG32(csbc
, 0xdc)
1562 if (offset
>= 0x5c && offset
< 0xa0) {
1565 n
= (offset
- 0x58) >> 2;
1566 shift
= (offset
& 3) * 8;
1567 s
->scratch
[n
] &= ~(0xff << shift
);
1568 s
->scratch
[n
] |= (val
& 0xff) << shift
;
1570 BADF("Unhandled writeb 0x%x = 0x%x\n", offset
, val
);
1573 #undef CASE_SET_REG32
1576 static void lsi_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1578 LSIState
*s
= (LSIState
*)opaque
;
1580 lsi_reg_writeb(s
, addr
& 0xff, val
);
1583 static void lsi_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1585 LSIState
*s
= (LSIState
*)opaque
;
1588 lsi_reg_writeb(s
, addr
, val
& 0xff);
1589 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1592 static void lsi_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1594 LSIState
*s
= (LSIState
*)opaque
;
1597 lsi_reg_writeb(s
, addr
, val
& 0xff);
1598 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1599 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
1600 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
1603 static uint32_t lsi_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1605 LSIState
*s
= (LSIState
*)opaque
;
1607 return lsi_reg_readb(s
, addr
& 0xff);
1610 static uint32_t lsi_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1612 LSIState
*s
= (LSIState
*)opaque
;
1616 val
= lsi_reg_readb(s
, addr
);
1617 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1621 static uint32_t lsi_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1623 LSIState
*s
= (LSIState
*)opaque
;
1626 val
= lsi_reg_readb(s
, addr
);
1627 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1628 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1629 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1633 static CPUReadMemoryFunc
*lsi_mmio_readfn
[3] = {
1639 static CPUWriteMemoryFunc
*lsi_mmio_writefn
[3] = {
1645 static void lsi_ram_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1647 LSIState
*s
= (LSIState
*)opaque
;
1652 newval
= s
->script_ram
[addr
>> 2];
1653 shift
= (addr
& 3) * 8;
1654 newval
&= ~(0xff << shift
);
1655 newval
|= val
<< shift
;
1656 s
->script_ram
[addr
>> 2] = newval
;
1659 static void lsi_ram_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1661 LSIState
*s
= (LSIState
*)opaque
;
1665 newval
= s
->script_ram
[addr
>> 2];
1667 newval
= (newval
& 0xffff) | (val
<< 16);
1669 newval
= (newval
& 0xffff0000) | val
;
1671 s
->script_ram
[addr
>> 2] = newval
;
1675 static void lsi_ram_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1677 LSIState
*s
= (LSIState
*)opaque
;
1680 s
->script_ram
[addr
>> 2] = val
;
1683 static uint32_t lsi_ram_readb(void *opaque
, target_phys_addr_t addr
)
1685 LSIState
*s
= (LSIState
*)opaque
;
1689 val
= s
->script_ram
[addr
>> 2];
1690 val
>>= (addr
& 3) * 8;
1694 static uint32_t lsi_ram_readw(void *opaque
, target_phys_addr_t addr
)
1696 LSIState
*s
= (LSIState
*)opaque
;
1700 val
= s
->script_ram
[addr
>> 2];
1703 return le16_to_cpu(val
);
1706 static uint32_t lsi_ram_readl(void *opaque
, target_phys_addr_t addr
)
1708 LSIState
*s
= (LSIState
*)opaque
;
1711 return le32_to_cpu(s
->script_ram
[addr
>> 2]);
1714 static CPUReadMemoryFunc
*lsi_ram_readfn
[3] = {
1720 static CPUWriteMemoryFunc
*lsi_ram_writefn
[3] = {
1726 static uint32_t lsi_io_readb(void *opaque
, uint32_t addr
)
1728 LSIState
*s
= (LSIState
*)opaque
;
1729 return lsi_reg_readb(s
, addr
& 0xff);
1732 static uint32_t lsi_io_readw(void *opaque
, uint32_t addr
)
1734 LSIState
*s
= (LSIState
*)opaque
;
1737 val
= lsi_reg_readb(s
, addr
);
1738 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1742 static uint32_t lsi_io_readl(void *opaque
, uint32_t addr
)
1744 LSIState
*s
= (LSIState
*)opaque
;
1747 val
= lsi_reg_readb(s
, addr
);
1748 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1749 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1750 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1754 static void lsi_io_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
1756 LSIState
*s
= (LSIState
*)opaque
;
1757 lsi_reg_writeb(s
, addr
& 0xff, val
);
1760 static void lsi_io_writew(void *opaque
, uint32_t addr
, uint32_t val
)
1762 LSIState
*s
= (LSIState
*)opaque
;
1764 lsi_reg_writeb(s
, addr
, val
& 0xff);
1765 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1768 static void lsi_io_writel(void *opaque
, uint32_t addr
, uint32_t val
)
1770 LSIState
*s
= (LSIState
*)opaque
;
1772 lsi_reg_writeb(s
, addr
, val
& 0xff);
1773 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1774 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
1775 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
1778 static void lsi_io_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1779 uint32_t addr
, uint32_t size
, int type
)
1781 LSIState
*s
= (LSIState
*)pci_dev
;
1783 DPRINTF("Mapping IO at %08x\n", addr
);
1785 register_ioport_write(addr
, 256, 1, lsi_io_writeb
, s
);
1786 register_ioport_read(addr
, 256, 1, lsi_io_readb
, s
);
1787 register_ioport_write(addr
, 256, 2, lsi_io_writew
, s
);
1788 register_ioport_read(addr
, 256, 2, lsi_io_readw
, s
);
1789 register_ioport_write(addr
, 256, 4, lsi_io_writel
, s
);
1790 register_ioport_read(addr
, 256, 4, lsi_io_readl
, s
);
1793 static void lsi_ram_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1794 uint32_t addr
, uint32_t size
, int type
)
1796 LSIState
*s
= (LSIState
*)pci_dev
;
1798 DPRINTF("Mapping ram at %08x\n", addr
);
1799 s
->script_ram_base
= addr
;
1800 cpu_register_physical_memory(addr
+ 0, 0x2000, s
->ram_io_addr
);
1803 static void lsi_mmio_mapfunc(PCIDevice
*pci_dev
, int region_num
,
1804 uint32_t addr
, uint32_t size
, int type
)
1806 LSIState
*s
= (LSIState
*)pci_dev
;
1808 DPRINTF("Mapping registers at %08x\n", addr
);
1809 cpu_register_physical_memory(addr
+ 0, 0x400, s
->mmio_io_addr
);
1812 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
)
1814 LSIState
*s
= (LSIState
*)opaque
;
1817 for (id
= 0; id
< LSI_MAX_DEVS
; id
++) {
1818 if (s
->scsi_dev
[id
] == NULL
)
1822 if (id
>= LSI_MAX_DEVS
) {
1823 BADF("Bad Device ID %d\n", id
);
1826 if (s
->scsi_dev
[id
]) {
1827 DPRINTF("Destroying device %d\n", id
);
1828 scsi_disk_destroy(s
->scsi_dev
[id
]);
1830 DPRINTF("Attaching block device %d\n", id
);
1831 s
->scsi_dev
[id
] = scsi_disk_init(bd
, 1, lsi_command_complete
, s
);
1834 void *lsi_scsi_init(PCIBus
*bus
, int devfn
)
1838 s
= (LSIState
*)pci_register_device(bus
, "LSI53C895A SCSI HBA",
1839 sizeof(*s
), devfn
, NULL
, NULL
);
1841 fprintf(stderr
, "lsi-scsi: Failed to register PCI device\n");
1845 s
->pci_dev
.config
[0x00] = 0x00;
1846 s
->pci_dev
.config
[0x01] = 0x10;
1847 s
->pci_dev
.config
[0x02] = 0x12;
1848 s
->pci_dev
.config
[0x03] = 0x00;
1849 s
->pci_dev
.config
[0x0b] = 0x01;
1850 s
->pci_dev
.config
[0x3d] = 0x01; /* interrupt pin 1 */
1852 s
->mmio_io_addr
= cpu_register_io_memory(0, lsi_mmio_readfn
,
1853 lsi_mmio_writefn
, s
);
1854 s
->ram_io_addr
= cpu_register_io_memory(0, lsi_ram_readfn
,
1855 lsi_ram_writefn
, s
);
1857 pci_register_io_region((struct PCIDevice
*)s
, 0, 256,
1858 PCI_ADDRESS_SPACE_IO
, lsi_io_mapfunc
);
1859 pci_register_io_region((struct PCIDevice
*)s
, 1, 0x400,
1860 PCI_ADDRESS_SPACE_MEM
, lsi_mmio_mapfunc
);
1861 pci_register_io_region((struct PCIDevice
*)s
, 2, 0x2000,
1862 PCI_ADDRESS_SPACE_MEM
, lsi_ram_mapfunc
);
1863 s
->queue
= qemu_malloc(sizeof(lsi_queue
));
1865 s
->active_commands
= 0;