4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include "m68k-qreg.h"
33 //#define DEBUG_DISPATCH 1
35 static inline void qemu_assert(int cond
, const char *msg
)
38 fprintf (stderr
, "badness: %s\n", msg
);
43 /* internal defines */
44 typedef struct DisasContext
{
46 target_ulong insn_pc
; /* Start of the current instruction. */
52 struct TranslationBlock
*tb
;
53 int singlestep_enabled
;
56 #define DISAS_JUMP_NEXT 4
58 #if defined(CONFIG_USER_ONLY)
61 #define IS_USER(s) s->user
64 /* XXX: move that elsewhere */
65 /* ??? Fix exceptions. */
66 static void *gen_throws_exception
;
67 #define gen_last_qop NULL
69 static uint16_t *gen_opc_ptr
;
70 static uint32_t *gen_opparam_ptr
;
75 #define DEF(s, n, copy_size) INDEX_op_ ## s,
83 #if defined(CONFIG_USER_ONLY)
84 #define gen_st(s, name, addr, val) gen_op_st##name##_raw(addr, val)
85 #define gen_ld(s, name, val, addr) gen_op_ld##name##_raw(val, addr)
87 #define gen_st(s, name, addr, val) do { \
89 gen_op_st##name##_user(addr, val); \
91 gen_op_st##name##_kernel(addr, val); \
93 #define gen_ld(s, name, val, addr) do { \
95 gen_op_ld##name##_user(val, addr); \
97 gen_op_ld##name##_kernel(val, addr); \
101 #include "op-hacks.h"
109 #define DREG(insn, pos) (((insn >> pos) & 7) + QREG_D0)
110 #define AREG(insn, pos) (((insn >> pos) & 7) + QREG_A0)
111 #define FREG(insn, pos) (((insn >> pos) & 7) + QREG_F0)
113 typedef void (*disas_proc
)(DisasContext
*, uint16_t);
115 #ifdef DEBUG_DISPATCH
116 #define DISAS_INSN(name) \
117 static void real_disas_##name (DisasContext *s, uint16_t insn); \
118 static void disas_##name (DisasContext *s, uint16_t insn) { \
119 if (logfile) fprintf(logfile, "Dispatch " #name "\n"); \
120 real_disas_##name(s, insn); } \
121 static void real_disas_##name (DisasContext *s, uint16_t insn)
123 #define DISAS_INSN(name) \
124 static void disas_##name (DisasContext *s, uint16_t insn)
127 /* Generate a load from the specified address. Narrow values are
128 sign extended to full register width. */
129 static inline int gen_load(DisasContext
* s
, int opsize
, int addr
, int sign
)
134 tmp
= gen_new_qreg(QMODE_I32
);
136 gen_ld(s
, 8s32
, tmp
, addr
);
138 gen_ld(s
, 8u32, tmp
, addr
);
141 tmp
= gen_new_qreg(QMODE_I32
);
143 gen_ld(s
, 16s32
, tmp
, addr
);
145 gen_ld(s
, 16u32, tmp
, addr
);
148 tmp
= gen_new_qreg(QMODE_I32
);
149 gen_ld(s
, 32, tmp
, addr
);
152 tmp
= gen_new_qreg(QMODE_F32
);
153 gen_ld(s
, f32
, tmp
, addr
);
156 tmp
= gen_new_qreg(QMODE_F64
);
157 gen_ld(s
, f64
, tmp
, addr
);
160 qemu_assert(0, "bad load size");
162 gen_throws_exception
= gen_last_qop
;
166 /* Generate a store. */
167 static inline void gen_store(DisasContext
*s
, int opsize
, int addr
, int val
)
171 gen_st(s
, 8, addr
, val
);
174 gen_st(s
, 16, addr
, val
);
177 gen_st(s
, 32, addr
, val
);
180 gen_st(s
, f32
, addr
, val
);
183 gen_st(s
, f64
, addr
, val
);
186 qemu_assert(0, "bad store size");
188 gen_throws_exception
= gen_last_qop
;
191 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
192 otherwise generate a store. */
193 static int gen_ldst(DisasContext
*s
, int opsize
, int addr
, int val
)
196 gen_store(s
, opsize
, addr
, val
);
199 return gen_load(s
, opsize
, addr
, val
!= 0);
203 /* Read a 32-bit immediate constant. */
204 static inline uint32_t read_im32(DisasContext
*s
)
207 im
= ((uint32_t)lduw_code(s
->pc
)) << 16;
209 im
|= lduw_code(s
->pc
);
214 /* Calculate and address index. */
215 static int gen_addr_index(uint16_t ext
, int tmp
)
220 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
221 if ((ext
& 0x800) == 0) {
222 gen_op_ext16s32(tmp
, add
);
225 scale
= (ext
>> 9) & 3;
227 gen_op_shl32(tmp
, add
, gen_im32(scale
));
233 /* Handle a base + index + displacement effective addresss. A base of
234 -1 means pc-relative. */
235 static int gen_lea_indexed(DisasContext
*s
, int opsize
, int base
)
244 ext
= lduw_code(s
->pc
);
247 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
251 /* full extension word format */
252 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
255 if ((ext
& 0x30) > 0x10) {
256 /* base displacement */
257 if ((ext
& 0x30) == 0x20) {
258 bd
= (int16_t)lduw_code(s
->pc
);
266 tmp
= gen_new_qreg(QMODE_I32
);
267 if ((ext
& 0x44) == 0) {
269 add
= gen_addr_index(ext
, tmp
);
273 if ((ext
& 0x80) == 0) {
274 /* base not suppressed */
276 base
= gen_im32(offset
+ bd
);
280 gen_op_add32(tmp
, add
, base
);
288 gen_op_add32(tmp
, add
, gen_im32(bd
));
294 if ((ext
& 3) != 0) {
295 /* memory indirect */
296 base
= gen_load(s
, OS_LONG
, add
, 0);
297 if ((ext
& 0x44) == 4) {
298 add
= gen_addr_index(ext
, tmp
);
299 gen_op_add32(tmp
, add
, base
);
305 /* outer displacement */
306 if ((ext
& 3) == 2) {
307 od
= (int16_t)lduw_code(s
->pc
);
316 gen_op_add32(tmp
, add
, gen_im32(od
));
321 /* brief extension word format */
322 tmp
= gen_new_qreg(QMODE_I32
);
323 add
= gen_addr_index(ext
, tmp
);
325 gen_op_add32(tmp
, add
, base
);
327 gen_op_add32(tmp
, tmp
, gen_im32((int8_t)ext
));
329 gen_op_add32(tmp
, add
, gen_im32(offset
+ (int8_t)ext
));
336 /* Update the CPU env CC_OP state. */
337 static inline void gen_flush_cc_op(DisasContext
*s
)
339 if (s
->cc_op
!= CC_OP_DYNAMIC
)
340 gen_op_mov32(QREG_CC_OP
, gen_im32(s
->cc_op
));
343 /* Evaluate all the CC flags. */
344 static inline void gen_flush_flags(DisasContext
*s
)
346 if (s
->cc_op
== CC_OP_FLAGS
)
348 gen_op_flush_flags(s
->cc_op
);
349 s
->cc_op
= CC_OP_FLAGS
;
352 static inline int opsize_bytes(int opsize
)
355 case OS_BYTE
: return 1;
356 case OS_WORD
: return 2;
357 case OS_LONG
: return 4;
358 case OS_SINGLE
: return 4;
359 case OS_DOUBLE
: return 8;
361 qemu_assert(0, "bad operand size");
365 /* Assign value to a register. If the width is less than the register width
366 only the low part of the register is set. */
367 static void gen_partset_reg(int opsize
, int reg
, int val
)
372 gen_op_and32(reg
, reg
, gen_im32(0xffffff00));
373 tmp
= gen_new_qreg(QMODE_I32
);
374 gen_op_and32(tmp
, val
, gen_im32(0xff));
375 gen_op_or32(reg
, reg
, tmp
);
378 gen_op_and32(reg
, reg
, gen_im32(0xffff0000));
379 tmp
= gen_new_qreg(QMODE_I32
);
380 gen_op_and32(tmp
, val
, gen_im32(0xffff));
381 gen_op_or32(reg
, reg
, tmp
);
384 gen_op_mov32(reg
, val
);
387 gen_op_pack_32_f32(reg
, val
);
390 qemu_assert(0, "Bad operand size");
395 /* Sign or zero extend a value. */
396 static inline int gen_extend(int val
, int opsize
, int sign
)
402 tmp
= gen_new_qreg(QMODE_I32
);
404 gen_op_ext8s32(tmp
, val
);
406 gen_op_ext8u32(tmp
, val
);
409 tmp
= gen_new_qreg(QMODE_I32
);
411 gen_op_ext16s32(tmp
, val
);
413 gen_op_ext16u32(tmp
, val
);
419 tmp
= gen_new_qreg(QMODE_F32
);
420 gen_op_pack_f32_32(tmp
, val
);
423 qemu_assert(0, "Bad operand size");
428 /* Generate code for an "effective address". Does not adjust the base
429 register for autoincrememnt addressing modes. */
430 static int gen_lea(DisasContext
*s
, uint16_t insn
, int opsize
)
438 switch ((insn
>> 3) & 7) {
439 case 0: /* Data register direct. */
440 case 1: /* Address register direct. */
442 case 2: /* Indirect register */
443 case 3: /* Indirect postincrement. */
446 case 4: /* Indirect predecrememnt. */
448 tmp
= gen_new_qreg(QMODE_I32
);
449 gen_op_sub32(tmp
, reg
, gen_im32(opsize_bytes(opsize
)));
451 case 5: /* Indirect displacement. */
453 tmp
= gen_new_qreg(QMODE_I32
);
454 ext
= lduw_code(s
->pc
);
456 gen_op_add32(tmp
, reg
, gen_im32((int16_t)ext
));
458 case 6: /* Indirect index + displacement. */
460 return gen_lea_indexed(s
, opsize
, reg
);
463 case 0: /* Absolute short. */
464 offset
= ldsw_code(s
->pc
);
466 return gen_im32(offset
);
467 case 1: /* Absolute long. */
468 offset
= read_im32(s
);
469 return gen_im32(offset
);
470 case 2: /* pc displacement */
471 tmp
= gen_new_qreg(QMODE_I32
);
473 offset
+= ldsw_code(s
->pc
);
475 return gen_im32(offset
);
476 case 3: /* pc index+displacement. */
477 return gen_lea_indexed(s
, opsize
, -1);
478 case 4: /* Immediate. */
483 /* Should never happen. */
487 /* Helper function for gen_ea. Reuse the computed address between the
488 for read/write operands. */
489 static inline int gen_ea_once(DisasContext
*s
, uint16_t insn
, int opsize
,
494 if (addrp
&& val
> 0) {
497 tmp
= gen_lea(s
, insn
, opsize
);
503 return gen_ldst(s
, opsize
, tmp
, val
);
506 /* Generate code to load/store a value ito/from an EA. If VAL > 0 this is
507 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
508 ADDRP is non-null for readwrite operands. */
509 static int gen_ea(DisasContext
*s
, uint16_t insn
, int opsize
, int val
,
517 switch ((insn
>> 3) & 7) {
518 case 0: /* Data register direct. */
521 gen_partset_reg(opsize
, reg
, val
);
524 return gen_extend(reg
, opsize
, val
);
526 case 1: /* Address register direct. */
529 gen_op_mov32(reg
, val
);
532 return gen_extend(reg
, opsize
, val
);
534 case 2: /* Indirect register */
536 return gen_ldst(s
, opsize
, reg
, val
);
537 case 3: /* Indirect postincrement. */
539 result
= gen_ldst(s
, opsize
, reg
, val
);
540 /* ??? This is not exception safe. The instruction may still
541 fault after this point. */
542 if (val
> 0 || !addrp
)
543 gen_op_add32(reg
, reg
, gen_im32(opsize_bytes(opsize
)));
545 case 4: /* Indirect predecrememnt. */
548 if (addrp
&& val
> 0) {
551 tmp
= gen_lea(s
, insn
, opsize
);
557 result
= gen_ldst(s
, opsize
, tmp
, val
);
558 /* ??? This is not exception safe. The instruction may still
559 fault after this point. */
560 if (val
> 0 || !addrp
) {
562 gen_op_mov32(reg
, tmp
);
566 case 5: /* Indirect displacement. */
567 case 6: /* Indirect index + displacement. */
568 return gen_ea_once(s
, insn
, opsize
, val
, addrp
);
571 case 0: /* Absolute short. */
572 case 1: /* Absolute long. */
573 case 2: /* pc displacement */
574 case 3: /* pc index+displacement. */
575 return gen_ea_once(s
, insn
, opsize
, val
, addrp
);
576 case 4: /* Immediate. */
577 /* Sign extend values for consistency. */
581 offset
= ldsb_code(s
->pc
+ 1);
583 offset
= ldub_code(s
->pc
+ 1);
588 offset
= ldsw_code(s
->pc
);
590 offset
= lduw_code(s
->pc
);
594 offset
= read_im32(s
);
597 qemu_assert(0, "Bad immediate operand");
599 return gen_im32(offset
);
604 /* Should never happen. */
608 static void gen_logic_cc(DisasContext
*s
, int val
)
610 gen_op_logic_cc(val
);
611 s
->cc_op
= CC_OP_LOGIC
;
614 static void gen_jmpcc(DisasContext
*s
, int cond
, int l1
)
625 case 2: /* HI (!C && !Z) */
626 tmp
= gen_new_qreg(QMODE_I32
);
627 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_C
| CCF_Z
));
628 gen_op_jmp_z32(tmp
, l1
);
630 case 3: /* LS (C || Z) */
631 tmp
= gen_new_qreg(QMODE_I32
);
632 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_C
| CCF_Z
));
633 gen_op_jmp_nz32(tmp
, l1
);
635 case 4: /* CC (!C) */
636 tmp
= gen_new_qreg(QMODE_I32
);
637 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_C
));
638 gen_op_jmp_z32(tmp
, l1
);
641 tmp
= gen_new_qreg(QMODE_I32
);
642 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_C
));
643 gen_op_jmp_nz32(tmp
, l1
);
645 case 6: /* NE (!Z) */
646 tmp
= gen_new_qreg(QMODE_I32
);
647 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_Z
));
648 gen_op_jmp_z32(tmp
, l1
);
651 tmp
= gen_new_qreg(QMODE_I32
);
652 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_Z
));
653 gen_op_jmp_nz32(tmp
, l1
);
655 case 8: /* VC (!V) */
656 tmp
= gen_new_qreg(QMODE_I32
);
657 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_V
));
658 gen_op_jmp_z32(tmp
, l1
);
661 tmp
= gen_new_qreg(QMODE_I32
);
662 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_V
));
663 gen_op_jmp_nz32(tmp
, l1
);
665 case 10: /* PL (!N) */
666 tmp
= gen_new_qreg(QMODE_I32
);
667 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_N
));
668 gen_op_jmp_z32(tmp
, l1
);
670 case 11: /* MI (N) */
671 tmp
= gen_new_qreg(QMODE_I32
);
672 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_N
));
673 gen_op_jmp_nz32(tmp
, l1
);
675 case 12: /* GE (!(N ^ V)) */
676 tmp
= gen_new_qreg(QMODE_I32
);
677 gen_op_shr32(tmp
, QREG_CC_DEST
, gen_im32(2));
678 gen_op_xor32(tmp
, tmp
, QREG_CC_DEST
);
679 gen_op_and32(tmp
, tmp
, gen_im32(CCF_V
));
680 gen_op_jmp_z32(tmp
, l1
);
682 case 13: /* LT (N ^ V) */
683 tmp
= gen_new_qreg(QMODE_I32
);
684 gen_op_shr32(tmp
, QREG_CC_DEST
, gen_im32(2));
685 gen_op_xor32(tmp
, tmp
, QREG_CC_DEST
);
686 gen_op_and32(tmp
, tmp
, gen_im32(CCF_V
));
687 gen_op_jmp_nz32(tmp
, l1
);
689 case 14: /* GT (!(Z || (N ^ V))) */
692 l2
= gen_new_label();
693 tmp
= gen_new_qreg(QMODE_I32
);
694 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_Z
));
695 gen_op_jmp_nz32(tmp
, l2
);
696 tmp
= gen_new_qreg(QMODE_I32
);
697 gen_op_shr32(tmp
, QREG_CC_DEST
, gen_im32(2));
698 gen_op_xor32(tmp
, tmp
, QREG_CC_DEST
);
699 gen_op_and32(tmp
, tmp
, gen_im32(CCF_V
));
700 gen_op_jmp_nz32(tmp
, l2
);
705 case 15: /* LE (Z || (N ^ V)) */
706 tmp
= gen_new_qreg(QMODE_I32
);
707 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_Z
));
708 gen_op_jmp_nz32(tmp
, l1
);
709 tmp
= gen_new_qreg(QMODE_I32
);
710 gen_op_shr32(tmp
, QREG_CC_DEST
, gen_im32(2));
711 gen_op_xor32(tmp
, tmp
, QREG_CC_DEST
);
712 gen_op_and32(tmp
, tmp
, gen_im32(CCF_V
));
713 gen_op_jmp_nz32(tmp
, l1
);
716 /* Should ever happen. */
727 l1
= gen_new_label();
728 cond
= (insn
>> 8) & 0xf;
730 gen_op_and32(reg
, reg
, gen_im32(0xffffff00));
731 gen_jmpcc(s
, cond
^ 1, l1
);
732 gen_op_or32(reg
, reg
, gen_im32(0xff));
736 /* Force a TB lookup after an instruction that changes the CPU state. */
737 static void gen_lookup_tb(DisasContext
*s
)
740 gen_op_mov32(QREG_PC
, gen_im32(s
->pc
));
741 s
->is_jmp
= DISAS_UPDATE
;
744 /* Generate a jump to to the address in qreg DEST. */
745 static void gen_jmp(DisasContext
*s
, int dest
)
748 gen_op_mov32(QREG_PC
, dest
);
749 s
->is_jmp
= DISAS_JUMP
;
752 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
755 gen_jmp(s
, gen_im32(where
));
756 gen_op_raise_exception(nr
);
759 static inline void gen_addr_fault(DisasContext
*s
)
761 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
764 #define SRC_EA(result, opsize, val, addrp) do { \
765 result = gen_ea(s, insn, opsize, val, addrp); \
766 if (result == -1) { \
772 #define DEST_EA(insn, opsize, val, addrp) do { \
773 int ea_result = gen_ea(s, insn, opsize, val, addrp); \
774 if (ea_result == -1) { \
780 /* Generate a jump to an immediate address. */
781 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
783 TranslationBlock
*tb
;
786 if (__builtin_expect (s
->singlestep_enabled
, 0)) {
787 gen_exception(s
, dest
, EXCP_DEBUG
);
788 } else if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
789 (s
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
790 gen_op_goto_tb(0, n
, (long)tb
);
791 gen_op_mov32(QREG_PC
, gen_im32(dest
));
792 gen_op_mov32(QREG_T0
, gen_im32((long)tb
+ n
));
795 gen_jmp(s
, gen_im32(dest
));
796 gen_op_mov32(QREG_T0
, gen_im32(0));
799 s
->is_jmp
= DISAS_TB_JUMP
;
802 DISAS_INSN(undef_mac
)
804 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
807 DISAS_INSN(undef_fpu
)
809 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
814 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
815 cpu_abort(cpu_single_env
, "Illegal instruction: %04x @ %08x",
826 sign
= (insn
& 0x100) != 0;
828 tmp
= gen_new_qreg(QMODE_I32
);
830 gen_op_ext16s32(tmp
, reg
);
832 gen_op_ext16u32(tmp
, reg
);
833 SRC_EA(src
, OS_WORD
, sign
? -1 : 0, NULL
);
834 gen_op_mul32(tmp
, tmp
, src
);
835 gen_op_mov32(reg
, tmp
);
836 /* Unlike m68k, coldfire always clears the overflow bit. */
837 gen_logic_cc(s
, tmp
);
847 sign
= (insn
& 0x100) != 0;
850 gen_op_ext16s32(QREG_DIV1
, reg
);
852 gen_op_ext16u32(QREG_DIV1
, reg
);
854 SRC_EA(src
, OS_WORD
, sign
? -1 : 0, NULL
);
855 gen_op_mov32(QREG_DIV2
, src
);
862 tmp
= gen_new_qreg(QMODE_I32
);
863 src
= gen_new_qreg(QMODE_I32
);
864 gen_op_ext16u32(tmp
, QREG_DIV1
);
865 gen_op_shl32(src
, QREG_DIV2
, gen_im32(16));
866 gen_op_or32(reg
, tmp
, src
);
868 s
->cc_op
= CC_OP_FLAGS
;
878 ext
= lduw_code(s
->pc
);
881 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
886 gen_op_mov32(QREG_DIV1
, num
);
887 SRC_EA(den
, OS_LONG
, 0, NULL
);
888 gen_op_mov32(QREG_DIV2
, den
);
896 gen_op_mov32 (reg
, QREG_DIV1
);
899 gen_op_mov32 (reg
, QREG_DIV2
);
902 s
->cc_op
= CC_OP_FLAGS
;
914 add
= (insn
& 0x4000) != 0;
916 dest
= gen_new_qreg(QMODE_I32
);
918 SRC_EA(tmp
, OS_LONG
, 0, &addr
);
922 SRC_EA(src
, OS_LONG
, 0, NULL
);
925 gen_op_add32(dest
, tmp
, src
);
926 gen_op_update_xflag_lt(dest
, src
);
927 s
->cc_op
= CC_OP_ADD
;
929 gen_op_update_xflag_lt(tmp
, src
);
930 gen_op_sub32(dest
, tmp
, src
);
931 s
->cc_op
= CC_OP_SUB
;
933 gen_op_update_cc_add(dest
, src
);
935 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
937 gen_op_mov32(reg
, dest
);
942 /* Reverse the order of the bits in REG. */
950 val
= gen_new_qreg(QMODE_I32
);
951 tmp1
= gen_new_qreg(QMODE_I32
);
952 tmp2
= gen_new_qreg(QMODE_I32
);
954 gen_op_mov32(val
, reg
);
955 /* Reverse bits within each nibble. */
956 gen_op_shl32(tmp1
, val
, gen_im32(3));
957 gen_op_and32(tmp1
, tmp1
, gen_im32(0x88888888));
958 gen_op_shl32(tmp2
, val
, gen_im32(1));
959 gen_op_and32(tmp2
, tmp2
, gen_im32(0x44444444));
960 gen_op_or32(tmp1
, tmp1
, tmp2
);
961 gen_op_shr32(tmp2
, val
, gen_im32(1));
962 gen_op_and32(tmp2
, tmp2
, gen_im32(0x22222222));
963 gen_op_or32(tmp1
, tmp1
, tmp2
);
964 gen_op_shr32(tmp2
, val
, gen_im32(3));
965 gen_op_and32(tmp2
, tmp2
, gen_im32(0x11111111));
966 gen_op_or32(tmp1
, tmp1
, tmp2
);
967 /* Reverse nibbles withing bytes. */
968 gen_op_shl32(val
, tmp1
, gen_im32(4));
969 gen_op_and32(val
, val
, gen_im32(0xf0f0f0f0));
970 gen_op_shr32(tmp2
, tmp1
, gen_im32(4));
971 gen_op_and32(tmp2
, tmp2
, gen_im32(0x0f0f0f0f));
972 gen_op_or32(val
, val
, tmp2
);
974 gen_op_bswap32(reg
, val
);
975 gen_op_mov32(reg
, val
);
978 DISAS_INSN(bitop_reg
)
988 if ((insn
& 0x38) != 0)
992 op
= (insn
>> 6) & 3;
993 SRC_EA(src1
, opsize
, 0, op
? &addr
: NULL
);
994 src2
= DREG(insn
, 9);
995 dest
= gen_new_qreg(QMODE_I32
);
998 tmp
= gen_new_qreg(QMODE_I32
);
999 if (opsize
== OS_BYTE
)
1000 gen_op_and32(tmp
, src2
, gen_im32(7));
1002 gen_op_and32(tmp
, src2
, gen_im32(31));
1004 tmp
= gen_new_qreg(QMODE_I32
);
1005 gen_op_shl32(tmp
, gen_im32(1), src2
);
1007 gen_op_btest(src1
, tmp
);
1010 gen_op_xor32(dest
, src1
, tmp
);
1013 gen_op_not32(tmp
, tmp
);
1014 gen_op_and32(dest
, src1
, tmp
);
1017 gen_op_or32(dest
, src1
, tmp
);
1023 DEST_EA(insn
, opsize
, dest
, &addr
);
1032 reg
= DREG(insn
, 0);
1033 tmp
= gen_new_qreg(QMODE_I32
);
1035 gen_op_and32(tmp
, QREG_CC_DEST
, gen_im32(CCF_V
));
1036 l1
= gen_new_label();
1037 gen_op_jmp_z32(tmp
, l1
);
1038 tmp
= gen_new_qreg(QMODE_I32
);
1039 gen_op_shr32(tmp
, reg
, gen_im32(31));
1040 gen_op_xor32(tmp
, tmp
, gen_im32(0x80000000));
1041 gen_op_mov32(reg
, tmp
);
1043 gen_logic_cc(s
, tmp
);
1046 static void gen_push(DisasContext
*s
, int val
)
1050 tmp
= gen_new_qreg(QMODE_I32
);
1051 gen_op_sub32(tmp
, QREG_SP
, gen_im32(4));
1052 gen_store(s
, OS_LONG
, tmp
, val
);
1053 gen_op_mov32(QREG_SP
, tmp
);
1065 mask
= lduw_code(s
->pc
);
1067 tmp
= gen_lea(s
, insn
, OS_LONG
);
1072 addr
= gen_new_qreg(QMODE_I32
);
1073 gen_op_mov32(addr
, tmp
);
1074 is_load
= ((insn
& 0x0400) != 0);
1075 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1082 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1083 gen_op_mov32(reg
, tmp
);
1085 gen_store(s
, OS_LONG
, addr
, reg
);
1088 gen_op_add32(addr
, addr
, gen_im32(4));
1093 DISAS_INSN(bitop_im
)
1104 if ((insn
& 0x38) != 0)
1108 op
= (insn
>> 6) & 3;
1110 bitnum
= lduw_code(s
->pc
);
1112 if (bitnum
& 0xff00) {
1113 disas_undef(s
, insn
);
1117 SRC_EA(src1
, opsize
, 0, op
? &addr
: NULL
);
1120 tmp
= gen_new_qreg(QMODE_I32
);
1121 if (opsize
== OS_BYTE
)
1127 gen_op_btest(src1
, gen_im32(mask
));
1129 dest
= gen_new_qreg(QMODE_I32
);
1135 gen_op_xor32(dest
, src1
, gen_im32(mask
));
1138 gen_op_and32(dest
, src1
, gen_im32(~mask
));
1141 gen_op_or32(dest
, src1
, gen_im32(mask
));
1147 DEST_EA(insn
, opsize
, dest
, &addr
);
1150 DISAS_INSN(arith_im
)
1158 op
= (insn
>> 9) & 7;
1159 SRC_EA(src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1160 src2
= gen_im32(read_im32(s
));
1161 dest
= gen_new_qreg(QMODE_I32
);
1164 gen_op_or32(dest
, src1
, src2
);
1165 gen_logic_cc(s
, dest
);
1168 gen_op_and32(dest
, src1
, src2
);
1169 gen_logic_cc(s
, dest
);
1172 gen_op_mov32(dest
, src1
);
1173 gen_op_update_xflag_lt(dest
, src2
);
1174 gen_op_sub32(dest
, dest
, src2
);
1175 gen_op_update_cc_add(dest
, src2
);
1176 s
->cc_op
= CC_OP_SUB
;
1179 gen_op_mov32(dest
, src1
);
1180 gen_op_add32(dest
, dest
, src2
);
1181 gen_op_update_cc_add(dest
, src2
);
1182 gen_op_update_xflag_lt(dest
, src2
);
1183 s
->cc_op
= CC_OP_ADD
;
1186 gen_op_xor32(dest
, src1
, src2
);
1187 gen_logic_cc(s
, dest
);
1190 gen_op_mov32(dest
, src1
);
1191 gen_op_sub32(dest
, dest
, src2
);
1192 gen_op_update_cc_add(dest
, src2
);
1193 s
->cc_op
= CC_OP_SUB
;
1199 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
1207 reg
= DREG(insn
, 0);
1208 gen_op_bswap32(reg
, reg
);
1218 switch (insn
>> 12) {
1219 case 1: /* move.b */
1222 case 2: /* move.l */
1225 case 3: /* move.w */
1231 SRC_EA(src
, opsize
, -1, NULL
);
1232 op
= (insn
>> 6) & 7;
1235 /* The value will already have been sign extended. */
1236 dest
= AREG(insn
, 9);
1237 gen_op_mov32(dest
, src
);
1241 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1242 DEST_EA(dest_ea
, opsize
, src
, NULL
);
1243 /* This will be correct because loads sign extend. */
1244 gen_logic_cc(s
, src
);
1255 reg
= DREG(insn
, 0);
1256 dest
= gen_new_qreg(QMODE_I32
);
1257 gen_op_mov32 (dest
, gen_im32(0));
1258 gen_op_subx_cc(dest
, reg
);
1260 tmp
= gen_new_qreg(QMODE_I32
);
1261 gen_op_mov32 (tmp
, QREG_CC_DEST
);
1262 gen_op_update_cc_add(dest
, reg
);
1263 gen_op_mov32(reg
, dest
);
1264 s
->cc_op
= CC_OP_DYNAMIC
;
1266 gen_op_or32(tmp
, tmp
, gen_im32(~CCF_Z
));
1267 gen_op_and32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1268 s
->cc_op
= CC_OP_FLAGS
;
1276 reg
= AREG(insn
, 9);
1277 tmp
= gen_lea(s
, insn
, OS_LONG
);
1282 gen_op_mov32(reg
, tmp
);
1289 switch ((insn
>> 6) & 3) {
1302 DEST_EA(insn
, opsize
, gen_im32(0), NULL
);
1303 gen_logic_cc(s
, gen_im32(0));
1306 static int gen_get_ccr(DisasContext
*s
)
1311 dest
= gen_new_qreg(QMODE_I32
);
1312 gen_op_get_xflag(dest
);
1313 gen_op_shl32(dest
, dest
, gen_im32(4));
1314 gen_op_or32(dest
, dest
, QREG_CC_DEST
);
1318 DISAS_INSN(move_from_ccr
)
1323 ccr
= gen_get_ccr(s
);
1324 reg
= DREG(insn
, 0);
1325 gen_partset_reg(OS_WORD
, reg
, ccr
);
1333 reg
= DREG(insn
, 0);
1334 src1
= gen_new_qreg(QMODE_I32
);
1335 gen_op_mov32(src1
, reg
);
1336 gen_op_neg32(reg
, src1
);
1337 s
->cc_op
= CC_OP_SUB
;
1338 gen_op_update_cc_add(reg
, src1
);
1339 gen_op_update_xflag_lt(gen_im32(0), src1
);
1340 s
->cc_op
= CC_OP_SUB
;
1343 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1345 gen_op_logic_cc(gen_im32(val
& 0xf));
1346 gen_op_update_xflag_tst(gen_im32((val
& 0x10) >> 4));
1348 gen_op_mov32(QREG_SR
, gen_im32(val
& 0xff00));
1352 static void gen_set_sr(DisasContext
*s
, uint16_t insn
, int ccr_only
)
1357 s
->cc_op
= CC_OP_FLAGS
;
1358 if ((insn
& 0x38) == 0)
1360 src1
= gen_new_qreg(QMODE_I32
);
1361 reg
= DREG(insn
, 0);
1362 gen_op_and32(src1
, reg
, gen_im32(0xf));
1363 gen_op_logic_cc(src1
);
1364 gen_op_shr32(src1
, reg
, gen_im32(4));
1365 gen_op_and32(src1
, src1
, gen_im32(1));
1366 gen_op_update_xflag_tst(src1
);
1368 gen_op_and32(QREG_SR
, reg
, gen_im32(0xff00));
1371 else if ((insn
& 0x3f) == 0x3c)
1374 val
= lduw_code(s
->pc
);
1376 gen_set_sr_im(s
, val
, ccr_only
);
1379 disas_undef(s
, insn
);
1382 DISAS_INSN(move_to_ccr
)
1384 gen_set_sr(s
, insn
, 1);
1391 reg
= DREG(insn
, 0);
1392 gen_op_not32(reg
, reg
);
1393 gen_logic_cc(s
, reg
);
1403 dest
= gen_new_qreg(QMODE_I32
);
1404 src1
= gen_new_qreg(QMODE_I32
);
1405 src2
= gen_new_qreg(QMODE_I32
);
1406 reg
= DREG(insn
, 0);
1407 gen_op_shl32(src1
, reg
, gen_im32(16));
1408 gen_op_shr32(src2
, reg
, gen_im32(16));
1409 gen_op_or32(dest
, src1
, src2
);
1410 gen_op_mov32(reg
, dest
);
1411 gen_logic_cc(s
, dest
);
1418 tmp
= gen_lea(s
, insn
, OS_LONG
);
1432 reg
= DREG(insn
, 0);
1433 op
= (insn
>> 6) & 7;
1434 tmp
= gen_new_qreg(QMODE_I32
);
1436 gen_op_ext16s32(tmp
, reg
);
1438 gen_op_ext8s32(tmp
, reg
);
1440 gen_partset_reg(OS_WORD
, reg
, tmp
);
1442 gen_op_mov32(reg
, tmp
);
1443 gen_logic_cc(s
, tmp
);
1451 switch ((insn
>> 6) & 3) {
1464 SRC_EA(tmp
, opsize
, -1, NULL
);
1465 gen_logic_cc(s
, tmp
);
1470 /* Implemented as a NOP. */
1475 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1478 /* ??? This should be atomic. */
1485 dest
= gen_new_qreg(QMODE_I32
);
1486 SRC_EA(src1
, OS_BYTE
, -1, &addr
);
1487 gen_logic_cc(s
, src1
);
1488 gen_op_or32(dest
, src1
, gen_im32(0x80));
1489 DEST_EA(insn
, OS_BYTE
, dest
, &addr
);
1499 /* The upper 32 bits of the product are discarded, so
1500 muls.l and mulu.l are functionally equivalent. */
1501 ext
= lduw_code(s
->pc
);
1504 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1507 reg
= DREG(ext
, 12);
1508 SRC_EA(src1
, OS_LONG
, 0, NULL
);
1509 dest
= gen_new_qreg(QMODE_I32
);
1510 gen_op_mul32(dest
, src1
, reg
);
1511 gen_op_mov32(reg
, dest
);
1512 /* Unlike m68k, coldfire always clears the overflow bit. */
1513 gen_logic_cc(s
, dest
);
1522 offset
= ldsw_code(s
->pc
);
1524 reg
= AREG(insn
, 0);
1525 tmp
= gen_new_qreg(QMODE_I32
);
1526 gen_op_sub32(tmp
, QREG_SP
, gen_im32(4));
1527 gen_store(s
, OS_LONG
, tmp
, reg
);
1529 gen_op_mov32(reg
, tmp
);
1530 gen_op_add32(QREG_SP
, tmp
, gen_im32(offset
));
1539 src
= gen_new_qreg(QMODE_I32
);
1540 reg
= AREG(insn
, 0);
1541 gen_op_mov32(src
, reg
);
1542 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1543 gen_op_mov32(reg
, tmp
);
1544 gen_op_add32(QREG_SP
, src
, gen_im32(4));
1555 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1556 gen_op_add32(QREG_SP
, QREG_SP
, gen_im32(4));
1564 /* Load the target address first to ensure correct exception
1566 tmp
= gen_lea(s
, insn
, OS_LONG
);
1571 if ((insn
& 0x40) == 0) {
1573 gen_push(s
, gen_im32(s
->pc
));
1586 SRC_EA(src1
, OS_LONG
, 0, &addr
);
1587 val
= (insn
>> 9) & 7;
1590 src2
= gen_im32(val
);
1591 dest
= gen_new_qreg(QMODE_I32
);
1592 gen_op_mov32(dest
, src1
);
1593 if ((insn
& 0x38) == 0x08) {
1594 /* Don't update condition codes if the destination is an
1595 address register. */
1596 if (insn
& 0x0100) {
1597 gen_op_sub32(dest
, dest
, src2
);
1599 gen_op_add32(dest
, dest
, src2
);
1602 if (insn
& 0x0100) {
1603 gen_op_update_xflag_lt(dest
, src2
);
1604 gen_op_sub32(dest
, dest
, src2
);
1605 s
->cc_op
= CC_OP_SUB
;
1607 gen_op_add32(dest
, dest
, src2
);
1608 gen_op_update_xflag_lt(dest
, src2
);
1609 s
->cc_op
= CC_OP_ADD
;
1611 gen_op_update_cc_add(dest
, src2
);
1613 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
1619 case 2: /* One extension word. */
1622 case 3: /* Two extension words. */
1625 case 4: /* No extension words. */
1628 disas_undef(s
, insn
);
1640 op
= (insn
>> 8) & 0xf;
1641 offset
= (int8_t)insn
;
1643 offset
= ldsw_code(s
->pc
);
1645 } else if (offset
== -1) {
1646 offset
= read_im32(s
);
1650 gen_push(s
, gen_im32(s
->pc
));
1655 l1
= gen_new_label();
1656 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1657 gen_jmp_tb(s
, 1, base
+ offset
);
1659 gen_jmp_tb(s
, 0, s
->pc
);
1661 /* Unconditional branch. */
1662 gen_jmp_tb(s
, 0, base
+ offset
);
1670 tmp
= gen_im32((int8_t)insn
);
1671 gen_op_mov32(DREG(insn
, 9), tmp
);
1672 gen_logic_cc(s
, tmp
);
1685 SRC_EA(src
, opsize
, (insn
& 0x80) ? 0 : -1, NULL
);
1686 reg
= DREG(insn
, 9);
1687 gen_op_mov32(reg
, src
);
1688 gen_logic_cc(s
, src
);
1698 reg
= DREG(insn
, 9);
1699 dest
= gen_new_qreg(QMODE_I32
);
1701 SRC_EA(src
, OS_LONG
, 0, &addr
);
1702 gen_op_or32(dest
, src
, reg
);
1703 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
1705 SRC_EA(src
, OS_LONG
, 0, NULL
);
1706 gen_op_or32(dest
, src
, reg
);
1707 gen_op_mov32(reg
, dest
);
1709 gen_logic_cc(s
, dest
);
1717 SRC_EA(src
, OS_LONG
, 0, NULL
);
1718 reg
= AREG(insn
, 9);
1719 gen_op_sub32(reg
, reg
, src
);
1730 reg
= DREG(insn
, 9);
1731 src
= DREG(insn
, 0);
1732 dest
= gen_new_qreg(QMODE_I32
);
1733 gen_op_mov32 (dest
, reg
);
1734 gen_op_subx_cc(dest
, src
);
1736 tmp
= gen_new_qreg(QMODE_I32
);
1737 gen_op_mov32 (tmp
, QREG_CC_DEST
);
1738 gen_op_update_cc_add(dest
, src
);
1739 gen_op_mov32(reg
, dest
);
1740 s
->cc_op
= CC_OP_DYNAMIC
;
1742 gen_op_or32(tmp
, tmp
, gen_im32(~CCF_Z
));
1743 gen_op_and32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1744 s
->cc_op
= CC_OP_FLAGS
;
1752 val
= (insn
>> 9) & 7;
1755 src
= gen_im32(val
);
1756 gen_logic_cc(s
, src
);
1757 DEST_EA(insn
, OS_LONG
, src
, NULL
);
1768 op
= (insn
>> 6) & 3;
1772 s
->cc_op
= CC_OP_CMPB
;
1776 s
->cc_op
= CC_OP_CMPW
;
1780 s
->cc_op
= CC_OP_SUB
;
1785 SRC_EA(src
, opsize
, -1, NULL
);
1786 reg
= DREG(insn
, 9);
1787 dest
= gen_new_qreg(QMODE_I32
);
1788 gen_op_sub32(dest
, reg
, src
);
1789 gen_op_update_cc_add(dest
, src
);
1804 SRC_EA(src
, opsize
, -1, NULL
);
1805 reg
= AREG(insn
, 9);
1806 dest
= gen_new_qreg(QMODE_I32
);
1807 gen_op_sub32(dest
, reg
, src
);
1808 gen_op_update_cc_add(dest
, src
);
1809 s
->cc_op
= CC_OP_SUB
;
1819 SRC_EA(src
, OS_LONG
, 0, &addr
);
1820 reg
= DREG(insn
, 9);
1821 dest
= gen_new_qreg(QMODE_I32
);
1822 gen_op_xor32(dest
, src
, reg
);
1823 gen_logic_cc(s
, dest
);
1824 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
1834 reg
= DREG(insn
, 9);
1835 dest
= gen_new_qreg(QMODE_I32
);
1837 SRC_EA(src
, OS_LONG
, 0, &addr
);
1838 gen_op_and32(dest
, src
, reg
);
1839 DEST_EA(insn
, OS_LONG
, dest
, &addr
);
1841 SRC_EA(src
, OS_LONG
, 0, NULL
);
1842 gen_op_and32(dest
, src
, reg
);
1843 gen_op_mov32(reg
, dest
);
1845 gen_logic_cc(s
, dest
);
1853 SRC_EA(src
, OS_LONG
, 0, NULL
);
1854 reg
= AREG(insn
, 9);
1855 gen_op_add32(reg
, reg
, src
);
1866 reg
= DREG(insn
, 9);
1867 src
= DREG(insn
, 0);
1868 dest
= gen_new_qreg(QMODE_I32
);
1869 gen_op_mov32 (dest
, reg
);
1870 gen_op_addx_cc(dest
, src
);
1872 tmp
= gen_new_qreg(QMODE_I32
);
1873 gen_op_mov32 (tmp
, QREG_CC_DEST
);
1874 gen_op_update_cc_add(dest
, src
);
1875 gen_op_mov32(reg
, dest
);
1876 s
->cc_op
= CC_OP_DYNAMIC
;
1878 gen_op_or32(tmp
, tmp
, gen_im32(~CCF_Z
));
1879 gen_op_and32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1880 s
->cc_op
= CC_OP_FLAGS
;
1883 DISAS_INSN(shift_im
)
1888 reg
= DREG(insn
, 0);
1889 tmp
= (insn
>> 9) & 7;
1893 gen_op_shl_im_cc(reg
, tmp
);
1894 s
->cc_op
= CC_OP_SHL
;
1897 gen_op_shr_im_cc(reg
, tmp
);
1898 s
->cc_op
= CC_OP_SHR
;
1900 gen_op_sar_im_cc(reg
, tmp
);
1901 s
->cc_op
= CC_OP_SAR
;
1906 DISAS_INSN(shift_reg
)
1912 reg
= DREG(insn
, 0);
1913 src
= DREG(insn
, 9);
1914 tmp
= gen_new_qreg(QMODE_I32
);
1915 gen_op_and32(tmp
, src
, gen_im32(63));
1917 gen_op_shl_cc(reg
, tmp
);
1918 s
->cc_op
= CC_OP_SHL
;
1921 gen_op_shr_cc(reg
, tmp
);
1922 s
->cc_op
= CC_OP_SHR
;
1924 gen_op_sar_cc(reg
, tmp
);
1925 s
->cc_op
= CC_OP_SAR
;
1933 reg
= DREG(insn
, 0);
1934 gen_logic_cc(s
, reg
);
1935 gen_op_ff1(reg
, reg
);
1938 static int gen_get_sr(DisasContext
*s
)
1943 ccr
= gen_get_ccr(s
);
1944 sr
= gen_new_qreg(QMODE_I32
);
1945 gen_op_and32(sr
, QREG_SR
, gen_im32(0xffe0));
1946 gen_op_or32(sr
, sr
, ccr
);
1956 ext
= lduw_code(s
->pc
);
1958 if (ext
!= 0x46FC) {
1959 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
1962 ext
= lduw_code(s
->pc
);
1964 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
1965 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
1968 gen_push(s
, gen_get_sr(s
));
1969 gen_set_sr_im(s
, ext
, 0);
1972 DISAS_INSN(move_from_sr
)
1978 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1982 reg
= DREG(insn
, 0);
1983 gen_partset_reg(OS_WORD
, reg
, sr
);
1986 DISAS_INSN(move_to_sr
)
1989 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1992 gen_set_sr(s
, insn
, 0);
1996 DISAS_INSN(move_from_usp
)
1999 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2002 /* TODO: Implement USP. */
2003 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
2006 DISAS_INSN(move_to_usp
)
2009 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2012 /* TODO: Implement USP. */
2013 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
2018 gen_jmp(s
, gen_im32(s
->pc
));
2027 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2031 ext
= lduw_code(s
->pc
);
2034 gen_set_sr_im(s
, ext
, 0);
2035 gen_jmp(s
, gen_im32(s
->pc
));
2042 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2045 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2054 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2058 ext
= lduw_code(s
->pc
);
2062 reg
= AREG(ext
, 12);
2064 reg
= DREG(ext
, 12);
2066 gen_op_movec(gen_im32(ext
& 0xfff), reg
);
2073 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2076 /* ICache fetch. Implement as no-op. */
2082 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2085 /* Cache push/invalidate. Implement as no-op. */
2090 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2096 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2099 /* TODO: Implement wdebug. */
2100 qemu_assert(0, "WDEBUG not implemented");
2105 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2108 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2109 immediately before the next FP instruction is executed. */
2120 ext
= lduw_code(s
->pc
);
2122 opmode
= ext
& 0x7f;
2123 switch ((ext
>> 13) & 7) {
2128 case 3: /* fmove out */
2131 /* ??? TODO: Proper behavior on overflow. */
2132 switch ((ext
>> 10) & 7) {
2135 res
= gen_new_qreg(QMODE_I32
);
2136 gen_op_f64_to_i32(res
, src
);
2140 res
= gen_new_qreg(QMODE_F32
);
2141 gen_op_f64_to_f32(res
, src
);
2145 res
= gen_new_qreg(QMODE_I32
);
2146 gen_op_f64_to_i32(res
, src
);
2154 res
= gen_new_qreg(QMODE_I32
);
2155 gen_op_f64_to_i32(res
, src
);
2160 DEST_EA(insn
, opsize
, res
, NULL
);
2162 case 4: /* fmove to control register. */
2163 switch ((ext
>> 10) & 7) {
2165 /* Not implemented. Ignore writes. */
2170 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2174 case 5: /* fmove from control register. */
2175 switch ((ext
>> 10) & 7) {
2177 /* Not implemented. Always return zero. */
2183 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2187 DEST_EA(insn
, OS_LONG
, res
, NULL
);
2189 case 6: /* fmovem */
2194 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2196 src
= gen_lea(s
, insn
, OS_LONG
);
2201 addr
= gen_new_qreg(QMODE_I32
);
2202 gen_op_mov32(addr
, src
);
2207 if (ext
& (1 << 13)) {
2209 gen_st(s
, f64
, addr
, dest
);
2212 gen_ld(s
, f64
, dest
, addr
);
2214 if (ext
& (mask
- 1))
2215 gen_op_add32(addr
, addr
, gen_im32(8));
2223 if (ext
& (1 << 14)) {
2226 /* Source effective address. */
2227 switch ((ext
>> 10) & 7) {
2228 case 0: opsize
= OS_LONG
; break;
2229 case 1: opsize
= OS_SINGLE
; break;
2230 case 4: opsize
= OS_WORD
; break;
2231 case 5: opsize
= OS_DOUBLE
; break;
2232 case 6: opsize
= OS_BYTE
; break;
2236 SRC_EA(tmp
, opsize
, -1, NULL
);
2237 if (opsize
== OS_DOUBLE
) {
2240 src
= gen_new_qreg(QMODE_F64
);
2245 gen_op_i32_to_f64(src
, tmp
);
2248 gen_op_f32_to_f64(src
, tmp
);
2253 /* Source register. */
2254 src
= FREG(ext
, 10);
2256 dest
= FREG(ext
, 7);
2257 res
= gen_new_qreg(QMODE_F64
);
2259 gen_op_movf64(res
, dest
);
2262 case 0: case 0x40: case 0x44: /* fmove */
2263 gen_op_movf64(res
, src
);
2266 gen_op_iround_f64(res
, src
);
2269 case 3: /* fintrz */
2270 gen_op_itrunc_f64(res
, src
);
2273 case 4: case 0x41: case 0x45: /* fsqrt */
2274 gen_op_sqrtf64(res
, src
);
2276 case 0x18: case 0x58: case 0x5c: /* fabs */
2277 gen_op_absf64(res
, src
);
2279 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2280 gen_op_chsf64(res
, src
);
2282 case 0x20: case 0x60: case 0x64: /* fdiv */
2283 gen_op_divf64(res
, res
, src
);
2285 case 0x22: case 0x62: case 0x66: /* fadd */
2286 gen_op_addf64(res
, res
, src
);
2288 case 0x23: case 0x63: case 0x67: /* fmul */
2289 gen_op_mulf64(res
, res
, src
);
2291 case 0x28: case 0x68: case 0x6c: /* fsub */
2292 gen_op_subf64(res
, res
, src
);
2294 case 0x38: /* fcmp */
2295 gen_op_sub_cmpf64(res
, res
, src
);
2299 case 0x3a: /* ftst */
2300 gen_op_movf64(res
, src
);
2308 if (opmode
& 0x40) {
2309 if ((opmode
& 0x4) != 0)
2311 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2318 tmp
= gen_new_qreg(QMODE_F32
);
2319 gen_op_f64_to_f32(tmp
, res
);
2320 gen_op_f32_to_f64(res
, tmp
);
2322 gen_op_fp_result(res
);
2324 gen_op_movf64(dest
, res
);
2329 disas_undef_fpu(s
, insn
);
2341 offset
= ldsw_code(s
->pc
);
2343 if (insn
& (1 << 6)) {
2344 offset
= (offset
<< 16) | lduw_code(s
->pc
);
2348 l1
= gen_new_label();
2349 /* TODO: Raise BSUN exception. */
2350 flag
= gen_new_qreg(QMODE_I32
);
2351 zero
= gen_new_qreg(QMODE_F64
);
2352 gen_op_zerof64(zero
);
2353 gen_op_compare_quietf64(flag
, QREG_FP_RESULT
, zero
);
2354 /* Jump to l1 if condition is true. */
2355 switch (insn
& 0xf) {
2358 case 1: /* eq (=0) */
2359 gen_op_jmp_z32(flag
, l1
);
2361 case 2: /* ogt (=1) */
2362 gen_op_sub32(flag
, flag
, gen_im32(1));
2363 gen_op_jmp_z32(flag
, l1
);
2365 case 3: /* oge (=0 or =1) */
2366 gen_op_jmp_z32(flag
, l1
);
2367 gen_op_sub32(flag
, flag
, gen_im32(1));
2368 gen_op_jmp_z32(flag
, l1
);
2370 case 4: /* olt (=-1) */
2371 gen_op_jmp_s32(flag
, l1
);
2373 case 5: /* ole (=-1 or =0) */
2374 gen_op_jmp_s32(flag
, l1
);
2375 gen_op_jmp_z32(flag
, l1
);
2377 case 6: /* ogl (=-1 or =1) */
2378 gen_op_jmp_s32(flag
, l1
);
2379 gen_op_sub32(flag
, flag
, gen_im32(1));
2380 gen_op_jmp_z32(flag
, l1
);
2382 case 7: /* or (=2) */
2383 gen_op_sub32(flag
, flag
, gen_im32(2));
2384 gen_op_jmp_z32(flag
, l1
);
2386 case 8: /* un (<2) */
2387 gen_op_sub32(flag
, flag
, gen_im32(2));
2388 gen_op_jmp_s32(flag
, l1
);
2390 case 9: /* ueq (=0 or =2) */
2391 gen_op_jmp_z32(flag
, l1
);
2392 gen_op_sub32(flag
, flag
, gen_im32(2));
2393 gen_op_jmp_z32(flag
, l1
);
2395 case 10: /* ugt (>0) */
2396 /* ??? Add jmp_gtu. */
2397 gen_op_sub32(flag
, flag
, gen_im32(1));
2398 gen_op_jmp_ns32(flag
, l1
);
2400 case 11: /* uge (>=0) */
2401 gen_op_jmp_ns32(flag
, l1
);
2403 case 12: /* ult (=-1 or =2) */
2404 gen_op_jmp_s32(flag
, l1
);
2405 gen_op_sub32(flag
, flag
, gen_im32(2));
2406 gen_op_jmp_z32(flag
, l1
);
2408 case 13: /* ule (!=1) */
2409 gen_op_sub32(flag
, flag
, gen_im32(1));
2410 gen_op_jmp_nz32(flag
, l1
);
2412 case 14: /* ne (!=0) */
2413 gen_op_jmp_nz32(flag
, l1
);
2416 gen_op_mov32(flag
, gen_im32(1));
2419 gen_jmp_tb(s
, 0, s
->pc
);
2421 gen_jmp_tb(s
, 1, addr
+ offset
);
2424 DISAS_INSN(frestore
)
2426 /* TODO: Implement frestore. */
2427 qemu_assert(0, "FRESTORE not implemented");
2432 /* TODO: Implement fsave. */
2433 qemu_assert(0, "FSAVE not implemented");
2436 static disas_proc opcode_table
[65536];
2439 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
2445 /* Sanity check. All set bits must be included in the mask. */
2446 if (opcode
& ~mask
) {
2448 "qemu internal error: bogus opcode definition %04x/%04x\n",
2452 /* This could probably be cleverer. For now just optimize the case where
2453 the top bits are known. */
2454 /* Find the first zero bit in the mask. */
2456 while ((i
& mask
) != 0)
2458 /* Iterate over all combinations of this and lower bits. */
2463 from
= opcode
& ~(i
- 1);
2465 for (i
= from
; i
< to
; i
++) {
2466 if ((i
& mask
) == opcode
)
2467 opcode_table
[i
] = proc
;
2471 /* Register m68k opcode handlers. Order is important.
2472 Later insn override earlier ones. */
2473 void register_m68k_insns (CPUM68KState
*env
)
2475 #define INSN(name, opcode, mask, feature) \
2476 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2477 register_opcode(disas_##name, 0x##opcode, 0x##mask)
2478 INSN(undef
, 0000, 0000, CF_ISA_A
);
2479 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
2480 INSN(bitrev
, 00c0
, fff8
, CF_ISA_C
);
2481 INSN(bitop_reg
, 0100, f1c0
, CF_ISA_A
);
2482 INSN(bitop_reg
, 0140, f1c0
, CF_ISA_A
);
2483 INSN(bitop_reg
, 0180, f1c0
, CF_ISA_A
);
2484 INSN(bitop_reg
, 01c0
, f1c0
, CF_ISA_A
);
2485 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
2486 INSN(byterev
, 02c0
, fff8
, CF_ISA_A
);
2487 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
2488 INSN(ff1
, 04c0
, fff8
, CF_ISA_C
);
2489 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
2490 INSN(bitop_im
, 0800, ffc0
, CF_ISA_A
);
2491 INSN(bitop_im
, 0840, ffc0
, CF_ISA_A
);
2492 INSN(bitop_im
, 0880, ffc0
, CF_ISA_A
);
2493 INSN(bitop_im
, 08c0
, ffc0
, CF_ISA_A
);
2494 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
2495 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
2496 INSN(move
, 1000, f000
, CF_ISA_A
);
2497 INSN(move
, 2000, f000
, CF_ISA_A
);
2498 INSN(move
, 3000, f000
, CF_ISA_A
);
2499 INSN(strldsr
, 40e7
, ffff
, CF_ISA_A
);
2500 INSN(negx
, 4080, fff8
, CF_ISA_A
);
2501 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
2502 INSN(lea
, 41c0
, f1c0
, CF_ISA_A
);
2503 INSN(clr
, 4200, ff00
, CF_ISA_A
);
2504 INSN(undef
, 42c0
, ffc0
, CF_ISA_A
);
2505 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
2506 INSN(neg
, 4480, fff8
, CF_ISA_A
);
2507 INSN(move_to_ccr
, 44c0
, ffc0
, CF_ISA_A
);
2508 INSN(not, 4680, fff8
, CF_ISA_A
);
2509 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
2510 INSN(pea
, 4840, ffc0
, CF_ISA_A
);
2511 INSN(swap
, 4840, fff8
, CF_ISA_A
);
2512 INSN(movem
, 48c0
, fbc0
, CF_ISA_A
);
2513 INSN(ext
, 4880, fff8
, CF_ISA_A
);
2514 INSN(ext
, 48c0
, fff8
, CF_ISA_A
);
2515 INSN(ext
, 49c0
, fff8
, CF_ISA_A
);
2516 INSN(tst
, 4a00
, ff00
, CF_ISA_A
);
2517 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
2518 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
2519 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
2520 INSN(illegal
, 4afc
, ffff
, CF_ISA_A
);
2521 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
2522 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
2523 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
2524 INSN(trap
, 4e40
, fff0
, CF_ISA_A
);
2525 INSN(link
, 4e50
, fff8
, CF_ISA_A
);
2526 INSN(unlk
, 4e58
, fff8
, CF_ISA_A
);
2527 INSN(move_to_usp
, 4e60
, fff8
, CF_ISA_B
);
2528 INSN(move_from_usp
, 4e68
, fff8
, CF_ISA_B
);
2529 INSN(nop
, 4e71
, ffff
, CF_ISA_A
);
2530 INSN(stop
, 4e72
, ffff
, CF_ISA_A
);
2531 INSN(rte
, 4e73
, ffff
, CF_ISA_A
);
2532 INSN(rts
, 4e75
, ffff
, CF_ISA_A
);
2533 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
2534 INSN(jump
, 4e80
, ffc0
, CF_ISA_A
);
2535 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
2536 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
2537 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
);
2538 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
2539 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
2540 INSN(branch
, 6000, f000
, CF_ISA_A
);
2541 INSN(moveq
, 7000, f100
, CF_ISA_A
);
2542 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
2543 INSN(or, 8000, f000
, CF_ISA_A
);
2544 INSN(divw
, 80c0
, f0c0
, CF_ISA_A
);
2545 INSN(addsub
, 9000, f000
, CF_ISA_A
);
2546 INSN(subx
, 9180, f1f8
, CF_ISA_A
);
2547 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
2548 INSN(undef_mac
, a000
, f000
, CF_ISA_A
);
2549 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
2550 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
2551 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
2552 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
2553 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
2554 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
2555 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
2556 INSN(and, c000
, f000
, CF_ISA_A
);
2557 INSN(mulw
, c0c0
, f0c0
, CF_ISA_A
);
2558 INSN(addsub
, d000
, f000
, CF_ISA_A
);
2559 INSN(addx
, d180
, f1f8
, CF_ISA_A
);
2560 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
2561 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
2562 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
2563 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
2564 INSN(fpu
, f200
, ffc0
, CF_FPU
);
2565 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
2566 INSN(frestore
, f340
, ffc0
, CF_FPU
);
2567 INSN(fsave
, f340
, ffc0
, CF_FPU
);
2568 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
2569 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
2570 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
2571 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
2575 /* ??? Some of this implementation is not exception safe. We should always
2576 write back the result to memory before setting the condition codes. */
2577 static void disas_m68k_insn(CPUState
* env
, DisasContext
*s
)
2581 insn
= lduw_code(s
->pc
);
2584 opcode_table
[insn
](s
, insn
);
2588 /* Save the result of a floating point operation. */
2589 static void expand_op_fp_result(qOP
*qop
)
2591 gen_op_movf64(QREG_FP_RESULT
, qop
->args
[0]);
2594 /* Dummy op to indicate that the flags have been set. */
2595 static void expand_op_flags_set(qOP
*qop
)
2599 /* Convert the confition codes into CC_OP_FLAGS format. */
2600 static void expand_op_flush_flags(qOP
*qop
)
2604 if (qop
->args
[0] == CC_OP_DYNAMIC
)
2605 cc_opreg
= QREG_CC_OP
;
2607 cc_opreg
= gen_im32(qop
->args
[0]);
2608 gen_op_helper32(QREG_NULL
, cc_opreg
, HELPER_flush_flags
);
2611 /* Set CC_DEST after a logical or direct flag setting operation. */
2612 static void expand_op_logic_cc(qOP
*qop
)
2614 gen_op_mov32(QREG_CC_DEST
, qop
->args
[0]);
2617 /* Set CC_SRC and CC_DEST after an arithmetic operation. */
2618 static void expand_op_update_cc_add(qOP
*qop
)
2620 gen_op_mov32(QREG_CC_DEST
, qop
->args
[0]);
2621 gen_op_mov32(QREG_CC_SRC
, qop
->args
[1]);
2624 /* Update the X flag. */
2625 static void expand_op_update_xflag(qOP
*qop
)
2630 arg0
= qop
->args
[0];
2631 arg1
= qop
->args
[1];
2632 if (arg1
== QREG_NULL
) {
2634 gen_op_mov32(QREG_CC_X
, arg0
);
2636 /* CC_X = arg0 < (unsigned)arg1. */
2637 gen_op_set_ltu32(QREG_CC_X
, arg0
, arg1
);
2641 /* Set arg0 to the contents of the X flag. */
2642 static void expand_op_get_xflag(qOP
*qop
)
2644 gen_op_mov32(qop
->args
[0], QREG_CC_X
);
2647 /* Expand a shift by immediate. The ISA only allows shifts by 1-8, so we
2648 already know the shift is within range. */
2649 static inline void expand_shift_im(qOP
*qop
, int right
, int arith
)
2659 val
= gen_new_qreg(QMODE_I32
);
2660 gen_op_mov32(val
, reg
);
2661 gen_op_mov32(QREG_CC_DEST
, val
);
2662 gen_op_mov32(QREG_CC_SRC
, tmp
);
2665 gen_op_sar32(reg
, val
, tmp
);
2667 gen_op_shr32(reg
, val
, tmp
);
2672 tmp
= gen_im32(im
- 1);
2674 gen_op_shl32(reg
, val
, tmp
);
2675 tmp
= gen_im32(32 - im
);
2677 if (tmp
!= QREG_NULL
)
2678 gen_op_shr32(val
, val
, tmp
);
2679 gen_op_and32(QREG_CC_X
, val
, gen_im32(1));
2682 static void expand_op_shl_im_cc(qOP
*qop
)
2684 expand_shift_im(qop
, 0, 0);
2687 static void expand_op_shr_im_cc(qOP
*qop
)
2689 expand_shift_im(qop
, 1, 0);
2692 static void expand_op_sar_im_cc(qOP
*qop
)
2694 expand_shift_im(qop
, 1, 1);
2697 /* Expand a shift by register. */
2698 /* ??? This gives incorrect answers for shifts by 0 or >= 32 */
2699 static inline void expand_shift_reg(qOP
*qop
, int right
, int arith
)
2707 shift
= qop
->args
[1];
2708 val
= gen_new_qreg(QMODE_I32
);
2709 gen_op_mov32(val
, reg
);
2710 gen_op_mov32(QREG_CC_DEST
, val
);
2711 gen_op_mov32(QREG_CC_SRC
, shift
);
2712 tmp
= gen_new_qreg(QMODE_I32
);
2715 gen_op_sar32(reg
, val
, shift
);
2717 gen_op_shr32(reg
, val
, shift
);
2719 gen_op_sub32(tmp
, shift
, gen_im32(1));
2721 gen_op_shl32(reg
, val
, shift
);
2722 gen_op_sub32(tmp
, gen_im32(31), shift
);
2724 gen_op_shl32(val
, val
, tmp
);
2725 gen_op_and32(QREG_CC_X
, val
, gen_im32(1));
2728 static void expand_op_shl_cc(qOP
*qop
)
2730 expand_shift_reg(qop
, 0, 0);
2733 static void expand_op_shr_cc(qOP
*qop
)
2735 expand_shift_reg(qop
, 1, 0);
2738 static void expand_op_sar_cc(qOP
*qop
)
2740 expand_shift_reg(qop
, 1, 1);
2743 /* Set the Z flag to (arg0 & arg1) == 0. */
2744 static void expand_op_btest(qOP
*qop
)
2749 l1
= gen_new_label();
2750 tmp
= gen_new_qreg(QMODE_I32
);
2751 gen_op_and32(tmp
, qop
->args
[0], qop
->args
[1]);
2752 gen_op_and32(QREG_CC_DEST
, QREG_CC_DEST
, gen_im32(~(uint32_t)CCF_Z
));
2753 gen_op_jmp_nz32(tmp
, l1
);
2754 gen_op_or32(QREG_CC_DEST
, QREG_CC_DEST
, gen_im32(CCF_Z
));
2758 /* arg0 += arg1 + CC_X */
2759 static void expand_op_addx_cc(qOP
*qop
)
2761 int arg0
= qop
->args
[0];
2762 int arg1
= qop
->args
[1];
2765 gen_op_add32 (arg0
, arg0
, arg1
);
2766 l1
= gen_new_label();
2767 l2
= gen_new_label();
2768 gen_op_jmp_z32(QREG_CC_X
, l1
);
2769 gen_op_add32(arg0
, arg0
, gen_im32(1));
2770 gen_op_mov32(QREG_CC_OP
, gen_im32(CC_OP_ADDX
));
2771 gen_op_set_leu32(QREG_CC_X
, arg0
, arg1
);
2774 gen_op_mov32(QREG_CC_OP
, gen_im32(CC_OP_ADD
));
2775 gen_op_set_ltu32(QREG_CC_X
, arg0
, arg1
);
2779 /* arg0 -= arg1 + CC_X */
2780 static void expand_op_subx_cc(qOP
*qop
)
2782 int arg0
= qop
->args
[0];
2783 int arg1
= qop
->args
[1];
2786 l1
= gen_new_label();
2787 l2
= gen_new_label();
2788 gen_op_jmp_z32(QREG_CC_X
, l1
);
2789 gen_op_set_leu32(QREG_CC_X
, arg0
, arg1
);
2790 gen_op_sub32(arg0
, arg0
, gen_im32(1));
2791 gen_op_mov32(QREG_CC_OP
, gen_im32(CC_OP_SUBX
));
2794 gen_op_set_ltu32(QREG_CC_X
, arg0
, arg1
);
2795 gen_op_mov32(QREG_CC_OP
, gen_im32(CC_OP_SUB
));
2797 gen_op_sub32 (arg0
, arg0
, arg1
);
2800 /* Expand target specific ops to generic qops. */
2801 static void expand_target_qops(void)
2807 /* Copy the list of qops, expanding target specific ops as we go. */
2808 qop
= gen_first_qop
;
2809 gen_first_qop
= NULL
;
2810 gen_last_qop
= NULL
;
2811 for (; qop
; qop
= next
) {
2814 if (c
< FIRST_TARGET_OP
) {
2815 qop
->prev
= gen_last_qop
;
2818 gen_last_qop
->next
= qop
;
2820 gen_first_qop
= qop
;
2825 #define DEF(name, nargs, barrier) \
2826 case INDEX_op_##name: \
2827 expand_op_##name(qop); \
2829 #include "qop-target.def"
2832 cpu_abort(NULL
, "Unexpanded target qop");
2837 /* ??? Implement this. */
2839 optimize_flags(void)
2844 /* generate intermediate code for basic block 'tb'. */
2846 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
2849 DisasContext dc1
, *dc
= &dc1
;
2850 uint16_t *gen_opc_end
;
2852 target_ulong pc_start
;
2856 /* generate intermediate code */
2861 gen_opc_ptr
= gen_opc_buf
;
2862 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2863 gen_opparam_ptr
= gen_opparam_buf
;
2866 dc
->is_jmp
= DISAS_NEXT
;
2868 dc
->cc_op
= CC_OP_DYNAMIC
;
2869 dc
->singlestep_enabled
= env
->singlestep_enabled
;
2870 dc
->fpcr
= env
->fpcr
;
2871 dc
->user
= (env
->sr
& SR_S
) == 0;
2876 pc_offset
= dc
->pc
- pc_start
;
2877 gen_throws_exception
= NULL
;
2878 if (env
->nb_breakpoints
> 0) {
2879 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2880 if (env
->breakpoints
[j
] == dc
->pc
) {
2881 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
2882 dc
->is_jmp
= DISAS_JUMP
;
2890 j
= gen_opc_ptr
- gen_opc_buf
;
2894 gen_opc_instr_start
[lj
++] = 0;
2896 gen_opc_pc
[lj
] = dc
->pc
;
2897 gen_opc_instr_start
[lj
] = 1;
2899 last_cc_op
= dc
->cc_op
;
2900 dc
->insn_pc
= dc
->pc
;
2901 disas_m68k_insn(env
, dc
);
2902 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
2903 !env
->singlestep_enabled
&&
2904 (pc_offset
) < (TARGET_PAGE_SIZE
- 32));
2906 if (__builtin_expect(env
->singlestep_enabled
, 0)) {
2907 /* Make sure the pc is updated, and raise a debug exception. */
2909 gen_flush_cc_op(dc
);
2910 gen_op_mov32(QREG_PC
, gen_im32((long)dc
->pc
));
2912 gen_op_raise_exception(EXCP_DEBUG
);
2914 switch(dc
->is_jmp
) {
2916 gen_flush_cc_op(dc
);
2917 gen_jmp_tb(dc
, 0, dc
->pc
);
2922 gen_flush_cc_op(dc
);
2923 /* indicate that the hash table must be used to find the next TB */
2924 gen_op_mov32(QREG_T0
, gen_im32(0));
2928 /* nothing more to generate */
2932 *gen_opc_ptr
= INDEX_op_end
;
2935 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2936 fprintf(logfile
, "----------------\n");
2937 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2938 target_disas(logfile
, pc_start
, dc
->pc
- pc_start
, 0);
2939 fprintf(logfile
, "\n");
2940 if (loglevel
& (CPU_LOG_TB_OP
)) {
2941 fprintf(logfile
, "OP:\n");
2942 dump_ops(gen_opc_buf
, gen_opparam_buf
);
2943 fprintf(logfile
, "\n");
2948 j
= gen_opc_ptr
- gen_opc_buf
;
2951 gen_opc_instr_start
[lj
++] = 0;
2954 tb
->size
= dc
->pc
- pc_start
;
2958 //expand_target_qops();
2962 int gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
2964 return gen_intermediate_code_internal(env
, tb
, 0);
2967 int gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
2969 return gen_intermediate_code_internal(env
, tb
, 1);
2972 void cpu_reset(CPUM68KState
*env
)
2974 memset(env
, 0, offsetof(CPUM68KState
, breakpoints
));
2975 #if !defined (CONFIG_USER_ONLY)
2978 /* ??? FP regs should be initialized to NaN. */
2979 env
->cc_op
= CC_OP_FLAGS
;
2980 /* TODO: We should set PC from the interrupt vector. */
2985 CPUM68KState
*cpu_m68k_init(void)
2989 env
= malloc(sizeof(CPUM68KState
));
2998 void cpu_m68k_close(CPUM68KState
*env
)
3003 void cpu_dump_state(CPUState
*env
, FILE *f
,
3004 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
3010 for (i
= 0; i
< 8; i
++)
3012 u
.d
= env
->fregs
[i
];
3013 cpu_fprintf (f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3014 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3015 i
, u
.l
.upper
, u
.l
.lower
, u
.d
);
3017 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3019 cpu_fprintf (f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& 0x10) ? 'X' : '-',
3020 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3021 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3022 cpu_fprintf (f
, "FPRESULT = %12g\n", env
->fp_result
);