tcg/hppa/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  26     "%r0",
  27     "%r1",
  28     "%rp",
  29     "%r3",
  30     "%r4",
  31     "%r5",
  32     "%r6",
  33     "%r7",
  34     "%r8",
  35     "%r9",
  36     "%r10",
  37     "%r11",
  38     "%r12",
  39     "%r13",
  40     "%r14",
  41     "%r15",
  42     "%r16",
  43     "%r17",
  44     "%r18",
  45     "%r19",
  46     "%r20",
  47     "%r21",
  48     "%r22",
  49     "%r23",
  50     "%r24",
  51     "%r25",
  52     "%r26",
  53     "%dp",
  54     "%ret0",
  55     "%ret1",
  56     "%sp",
  57     "%r31",
  58 };
  59
  60 static const int tcg_target_reg_alloc_order[] = {
  61     TCG_REG_R4,
  62     TCG_REG_R5,
  63     TCG_REG_R6,
  64     TCG_REG_R7,
  65     TCG_REG_R8,
  66     TCG_REG_R9,
  67     TCG_REG_R10,
  68     TCG_REG_R11,
  69     TCG_REG_R12,
  70     TCG_REG_R13,
  71
  72     TCG_REG_R17,
  73     TCG_REG_R14,
  74     TCG_REG_R15,
  75     TCG_REG_R16,
  76 };
  77
  78 static const int tcg_target_call_iarg_regs[4] = {
  79     TCG_REG_R26,
  80     TCG_REG_R25,
  81     TCG_REG_R24,
  82     TCG_REG_R23,
  83 };
  84
  85 static const int tcg_target_call_oarg_regs[2] = {
  86     TCG_REG_RET0,
  87     TCG_REG_RET1,
  88 };
  89
  90 static void patch_reloc(uint8_t *code_ptr, int type,
  91                         tcg_target_long value, tcg_target_long addend)
  92 {
  93     switch (type) {
  94     case R_PARISC_PCREL17F:
  95         hppa_patch17f((uint32_t *)code_ptr, value, addend);
  96         break;
  97     default:
  98         tcg_abort();
  99     }
 100 }
 101
 102 /* maximum number of register used for input function arguments */
 103 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 104 {
 105     return 4;
 106 }
 107
 108 /* parse target specific constraints */
 109 int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 110 {
 111     const char *ct_str;
 112
 113     ct_str = *pct_str;
 114     switch (ct_str[0]) {
 115     case 'r':
 116         ct->ct |= TCG_CT_REG;
 117         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 118         break;
 119     case 'L': /* qemu_ld/st constraint */
 120         ct->ct |= TCG_CT_REG;
 121         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 122         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R26);
 123         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R25);
 124         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R24);
 125         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R23);
 126         break;
 127     default:
 128         return -1;
 129     }
 130     ct_str++;
 131     *pct_str = ct_str;
 132     return 0;
 133 }
 134
 135 /* test if a constant matches the constraint */
 136 static inline int tcg_target_const_match(tcg_target_long val,
 137                                          const TCGArgConstraint *arg_ct)
 138 {
 139     int ct;
 140
 141     ct = arg_ct->ct;
 142
 143     /* TODO */
 144
 145     return 0;
 146 }
 147
 148 #define INSN_OP(x)       ((x) << 26)
 149 #define INSN_EXT3BR(x)   ((x) << 13)
 150 #define INSN_EXT3SH(x)   ((x) << 10)
 151 #define INSN_EXT4(x)     ((x) << 6)
 152 #define INSN_EXT5(x)     (x)
 153 #define INSN_EXT6(x)     ((x) << 6)
 154 #define INSN_EXT7(x)     ((x) << 6)
 155 #define INSN_EXT8A(x)    ((x) << 6)
 156 #define INSN_EXT8B(x)    ((x) << 5)
 157 #define INSN_T(x)        (x)
 158 #define INSN_R1(x)       ((x) << 16)
 159 #define INSN_R2(x)       ((x) << 21)
 160 #define INSN_DEP_LEN(x)  (32 - (x))
 161 #define INSN_SHDEP_CP(x) ((31 - (x)) << 5)
 162 #define INSN_SHDEP_P(x)  ((x) << 5)
 163 #define INSN_COND(x)     ((x) << 13)
 164
 165 #define COND_NEVER 0
 166 #define COND_EQUAL 1
 167 #define COND_LT    2
 168 #define COND_LTEQ  3
 169 #define COND_LTU   4
 170 #define COND_LTUEQ 5
 171 #define COND_SV    6
 172 #define COND_OD    7
 173
 174
 175 /* Logical ADD */
 176 #define ARITH_ADD  (INSN_OP(0x02) | INSN_EXT6(0x28))
 177 #define ARITH_AND  (INSN_OP(0x02) | INSN_EXT6(0x08))
 178 #define ARITH_OR   (INSN_OP(0x02) | INSN_EXT6(0x09))
 179 #define ARITH_XOR  (INSN_OP(0x02) | INSN_EXT6(0x0a))
 180 #define ARITH_SUB  (INSN_OP(0x02) | INSN_EXT6(0x10))
 181
 182 #define SHD        (INSN_OP(0x34) | INSN_EXT3SH(2))
 183 #define VSHD       (INSN_OP(0x34) | INSN_EXT3SH(0))
 184 #define DEP        (INSN_OP(0x35) | INSN_EXT3SH(3))
 185 #define ZDEP       (INSN_OP(0x35) | INSN_EXT3SH(2))
 186 #define ZVDEP      (INSN_OP(0x35) | INSN_EXT3SH(0))
 187 #define EXTRU      (INSN_OP(0x34) | INSN_EXT3SH(6))
 188 #define EXTRS      (INSN_OP(0x34) | INSN_EXT3SH(7))
 189 #define VEXTRS     (INSN_OP(0x34) | INSN_EXT3SH(5))
 190
 191 #define SUBI       (INSN_OP(0x25))
 192 #define MTCTL      (INSN_OP(0x00) | INSN_EXT8B(0xc2))
 193
 194 #define BL         (INSN_OP(0x3a) | INSN_EXT3BR(0))
 195 #define BLE_SR4    (INSN_OP(0x39) | (1 << 13))
 196 #define BV         (INSN_OP(0x3a) | INSN_EXT3BR(6))
 197 #define BV_N       (INSN_OP(0x3a) | INSN_EXT3BR(6) | 2)
 198 #define LDIL       (INSN_OP(0x08))
 199 #define LDO        (INSN_OP(0x0d))
 200
 201 #define LDB        (INSN_OP(0x10))
 202 #define LDH        (INSN_OP(0x11))
 203 #define LDW        (INSN_OP(0x12))
 204 #define LDWM       (INSN_OP(0x13))
 205
 206 #define STB        (INSN_OP(0x18))
 207 #define STH        (INSN_OP(0x19))
 208 #define STW        (INSN_OP(0x1a))
 209 #define STWM       (INSN_OP(0x1b))
 210
 211 #define COMBT      (INSN_OP(0x20))
 212 #define COMBF      (INSN_OP(0x22))
 213
 214 static int lowsignext(uint32_t val, int start, int length)
 215 {
 216     return (((val << 1) & ~(~0 << length)) |
 217             ((val >> (length - 1)) & 1)) << start;
 218 }
 219
 220 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
 221 {
 222     /* PA1.1 defines COPY as OR r,0,t */
 223     tcg_out32(s, ARITH_OR | INSN_T(ret) | INSN_R1(arg) | INSN_R2(TCG_REG_R0));
 224
 225     /* PA2.0 defines COPY as LDO 0(r),t
 226      * but hppa-dis.c is unaware of this definition */
 227     /* tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(arg) | reassemble_14(0)); */
 228 }
 229
 230 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 231                                 int ret, tcg_target_long arg)
 232 {
 233     if (arg == (arg & 0x1fff)) {
 234         tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(TCG_REG_R0) |
 235                      reassemble_14(arg));
 236     } else {
 237         tcg_out32(s, LDIL | INSN_R2(ret) |
 238                      reassemble_21(lrsel((uint32_t)arg, 0)));
 239         if (arg & 0x7ff)
 240             tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(ret) |
 241                          reassemble_14(rrsel((uint32_t)arg, 0)));
 242     }
 243 }
 244
 245 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 246                                   tcg_target_long arg)
 247 {
 248     tcg_out32(s, LDIL | INSN_R2(ret) |
 249                  reassemble_21(lrsel((uint32_t)arg, 0)));
 250     tcg_out32(s, LDW | INSN_R1(ret) | INSN_R2(ret) |
 251                  reassemble_14(rrsel((uint32_t)arg, 0)));
 252 }
 253
 254 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 255                                   tcg_target_long arg)
 256 {
 257     tcg_out_ld_raw(s, ret, arg);
 258 }
 259
 260 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset,
 261                                 int op)
 262 {
 263     if (offset == (offset & 0xfff))
 264         tcg_out32(s, op | INSN_R1(ret) | INSN_R2(addr) |
 265                  reassemble_14(offset));
 266     else {
 267         fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
 268         tcg_abort();
 269     }
 270 }
 271
 272 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
 273                               int arg1, tcg_target_long arg2)
 274 {
 275     fprintf(stderr, "unimplemented %s\n", __func__);
 276     tcg_abort();
 277 }
 278
 279 static inline void tcg_out_st(TCGContext *s, TCGType type, int ret,
 280                               int arg1, tcg_target_long arg2)
 281 {
 282     fprintf(stderr, "unimplemented %s\n", __func__);
 283     tcg_abort();
 284 }
 285
 286 static inline void tcg_out_arith(TCGContext *s, int t, int r1, int r2, int op)
 287 {
 288     tcg_out32(s, op | INSN_T(t) | INSN_R1(r1) | INSN_R2(r2));
 289 }
 290
 291 static inline void tcg_out_arithi(TCGContext *s, int t, int r1,
 292                                   tcg_target_long val, int op)
 293 {
 294     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, val);
 295     tcg_out_arith(s, t, r1, TCG_REG_R20, op);
 296 }
 297
 298 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 299 {
 300     tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 301 }
 302
 303 static inline void tcg_out_nop(TCGContext *s)
 304 {
 305     tcg_out32(s, ARITH_OR | INSN_T(TCG_REG_R0) | INSN_R1(TCG_REG_R0) |
 306                  INSN_R2(TCG_REG_R0));
 307 }
 308
 309 static inline void tcg_out_ext8s(TCGContext *s, int ret, int arg) {
 310     tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) |
 311                  INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
 312 }
 313
 314 static inline void tcg_out_ext16s(TCGContext *s, int ret, int arg) {
 315     tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) |
 316                  INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
 317 }
 318
 319 static inline void tcg_out_bswap16(TCGContext *s, int ret, int arg) {
 320     if(ret != arg)
 321         tcg_out_mov(s, ret, arg);
 322     tcg_out32(s, DEP | INSN_R2(ret) | INSN_R1(ret) |
 323                  INSN_SHDEP_CP(15) | INSN_DEP_LEN(8));
 324     tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(TCG_REG_R0) |
 325                  INSN_R2(ret) | INSN_SHDEP_CP(8));
 326 }
 327
 328 static inline void tcg_out_bswap32(TCGContext *s, int ret, int arg, int temp) {
 329     tcg_out32(s, SHD | INSN_T(temp) | INSN_R1(arg) |
 330                  INSN_R2(arg) | INSN_SHDEP_CP(16));
 331     tcg_out32(s, DEP | INSN_R2(temp) | INSN_R1(temp) |
 332                  INSN_SHDEP_CP(15) | INSN_DEP_LEN(8));
 333     tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(arg) |
 334                  INSN_R2(temp) | INSN_SHDEP_CP(8));
 335 }
 336
 337 static inline void tcg_out_call(TCGContext *s, void *func)
 338 {
 339     uint32_t val = (uint32_t)__canonicalize_funcptr_for_compare(func);
 340     tcg_out32(s, LDIL | INSN_R2(TCG_REG_R20) |
 341                  reassemble_21(lrsel(val, 0)));
 342     tcg_out32(s, BLE_SR4 | INSN_R2(TCG_REG_R20) |
 343                  reassemble_17(rrsel(val, 0) >> 2));
 344     tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
 345 }
 346
 347 #if defined(CONFIG_SOFTMMU)
 348 extern void __ldb_mmu(void);
 349 extern void __ldw_mmu(void);
 350 extern void __ldl_mmu(void);
 351 extern void __ldq_mmu(void);
 352
 353 extern void __stb_mmu(void);
 354 extern void __stw_mmu(void);
 355 extern void __stl_mmu(void);
 356 extern void __stq_mmu(void);
 357
 358 static void *qemu_ld_helpers[4] = {
 359     __ldb_mmu,
 360     __ldw_mmu,
 361     __ldl_mmu,
 362     __ldq_mmu,
 363 };
 364
 365 static void *qemu_st_helpers[4] = {
 366     __stb_mmu,
 367     __stw_mmu,
 368     __stl_mmu,
 369     __stq_mmu,
 370 };
 371 #endif
 372
 373 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
 374 {
 375     int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
 376 #if defined(CONFIG_SOFTMMU)
 377     uint32_t *label1_ptr, *label2_ptr;
 378 #endif
 379 #if TARGET_LONG_BITS == 64
 380 #if defined(CONFIG_SOFTMMU)
 381     uint32_t *label3_ptr;
 382 #endif
 383     int addr_reg2;
 384 #endif
 385
 386     data_reg = *args++;
 387     if (opc == 3)
 388         data_reg2 = *args++;
 389     else
 390         data_reg2 = 0; /* surpress warning */
 391     addr_reg = *args++;
 392 #if TARGET_LONG_BITS == 64
 393     addr_reg2 = *args++;
 394 #endif
 395     mem_index = *args;
 396     s_bits = opc & 3;
 397
 398     r0 = TCG_REG_R26;
 399     r1 = TCG_REG_R25;
 400
 401 #if defined(CONFIG_SOFTMMU)
 402     tcg_out_mov(s, r1, addr_reg);
 403
 404     tcg_out_mov(s, r0, addr_reg);
 405
 406     tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) |
 407                  INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
 408
 409     tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 410                    ARITH_AND);
 411
 412     tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
 413                    ARITH_AND);
 414
 415     tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD);
 416     tcg_out_arithi(s, r1, r1,
 417                    offsetof(CPUState, tlb_table[mem_index][0].addr_read),
 418                    ARITH_ADD);
 419
 420     tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
 421
 422 #if TARGET_LONG_BITS == 32
 423     /* if equal, jump to label1 */
 424     label1_ptr = (uint32_t *)s->code_ptr;
 425     tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
 426                  INSN_COND(COND_EQUAL));
 427     tcg_out_mov(s, r0, addr_reg); /* delay slot */
 428 #else
 429     /* if not equal, jump to label3 */
 430     label3_ptr = (uint32_t *)s->code_ptr;
 431     tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
 432                  INSN_COND(COND_EQUAL));
 433     tcg_out_mov(s, r0, addr_reg); /* delay slot */
 434
 435     tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
 436
 437     /* if equal, jump to label1 */
 438     label1_ptr = (uint32_t *)s->code_ptr;
 439     tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) |
 440                  INSN_COND(COND_EQUAL));
 441     tcg_out_nop(s); /* delay slot */
 442
 443     /* label3: */
 444     *label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
 445 #endif
 446
 447 #if TARGET_LONG_BITS == 32
 448     tcg_out_mov(s, TCG_REG_R26, addr_reg);
 449     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R25, mem_index);
 450 #else
 451     tcg_out_mov(s, TCG_REG_R26, addr_reg);
 452     tcg_out_mov(s, TCG_REG_R25, addr_reg2);
 453     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index);
 454 #endif
 455
 456     tcg_out_call(s, qemu_ld_helpers[s_bits]);
 457
 458     switch(opc) {
 459         case 0 | 4:
 460             tcg_out_ext8s(s, data_reg, TCG_REG_RET0);
 461             break;
 462         case 1 | 4:
 463             tcg_out_ext16s(s, data_reg, TCG_REG_RET0);
 464             break;
 465         case 0:
 466         case 1:
 467         case 2:
 468         default:
 469             tcg_out_mov(s, data_reg, TCG_REG_RET0);
 470             break;
 471         case 3:
 472             tcg_abort();
 473             tcg_out_mov(s, data_reg, TCG_REG_RET0);
 474             tcg_out_mov(s, data_reg2, TCG_REG_RET1);
 475             break;
 476     }
 477
 478     /* jump to label2 */
 479     label2_ptr = (uint32_t *)s->code_ptr;
 480     tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
 481
 482     /* label1: */
 483     *label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
 484
 485     tcg_out_arithi(s, TCG_REG_R20, r1,
 486                    offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_read),
 487                    ARITH_ADD);
 488     tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
 489     tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD);
 490 #else
 491     r0 = addr_reg;
 492 #endif
 493
 494 #ifdef TARGET_WORDS_BIGENDIAN
 495     bswap = 0;
 496 #else
 497     bswap = 1;
 498 #endif
 499     switch (opc) {
 500         case 0:
 501             tcg_out_ldst(s, data_reg, r0, 0, LDB);
 502             break;
 503         case 0 | 4:
 504             tcg_out_ldst(s, data_reg, r0, 0, LDB);
 505             tcg_out_ext8s(s, data_reg, data_reg);
 506             break;
 507         case 1:
 508             tcg_out_ldst(s, data_reg, r0, 0, LDH);
 509             if (bswap)
 510                 tcg_out_bswap16(s, data_reg, data_reg);
 511             break;
 512         case 1 | 4:
 513             tcg_out_ldst(s, data_reg, r0, 0, LDH);
 514             if (bswap)
 515                 tcg_out_bswap16(s, data_reg, data_reg);
 516             tcg_out_ext16s(s, data_reg, data_reg);
 517             break;
 518         case 2:
 519             tcg_out_ldst(s, data_reg, r0, 0, LDW);
 520             if (bswap)
 521                 tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20);
 522             break;
 523         case 3:
 524             tcg_abort();
 525             if (!bswap) {
 526                 tcg_out_ldst(s, data_reg, r0, 0, LDW);
 527                 tcg_out_ldst(s, data_reg2, r0, 4, LDW);
 528             } else {
 529                 tcg_out_ldst(s, data_reg, r0, 4, LDW);
 530                 tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20);
 531                 tcg_out_ldst(s, data_reg2, r0, 0, LDW);
 532                 tcg_out_bswap32(s, data_reg2, data_reg2, TCG_REG_R20);
 533             }
 534             break;
 535         default:
 536             tcg_abort();
 537     }
 538
 539 #if defined(CONFIG_SOFTMMU)
 540     /* label2: */
 541     *label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
 542 #endif
 543 }
 544
 545 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
 546 {
 547     int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
 548 #if defined(CONFIG_SOFTMMU)
 549     uint32_t *label1_ptr, *label2_ptr;
 550 #endif
 551 #if TARGET_LONG_BITS == 64
 552 #if defined(CONFIG_SOFTMMU)
 553     uint32_t *label3_ptr;
 554 #endif
 555     int addr_reg2;
 556 #endif
 557
 558     data_reg = *args++;
 559     if (opc == 3)
 560         data_reg2 = *args++;
 561     else
 562         data_reg2 = 0; /* surpress warning */
 563     addr_reg = *args++;
 564 #if TARGET_LONG_BITS == 64
 565     addr_reg2 = *args++;
 566 #endif
 567     mem_index = *args;
 568
 569     s_bits = opc;
 570
 571     r0 = TCG_REG_R26;
 572     r1 = TCG_REG_R25;
 573
 574 #if defined(CONFIG_SOFTMMU)
 575     tcg_out_mov(s, r1, addr_reg);
 576
 577     tcg_out_mov(s, r0, addr_reg);
 578
 579     tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) |
 580                  INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
 581
 582     tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 583                    ARITH_AND);
 584
 585     tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
 586                    ARITH_AND);
 587
 588     tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD);
 589     tcg_out_arithi(s, r1, r1,
 590                    offsetof(CPUState, tlb_table[mem_index][0].addr_write),
 591                    ARITH_ADD);
 592
 593     tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
 594
 595 #if TARGET_LONG_BITS == 32
 596     /* if equal, jump to label1 */
 597     label1_ptr = (uint32_t *)s->code_ptr;
 598     tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
 599                  INSN_COND(COND_EQUAL));
 600     tcg_out_mov(s, r0, addr_reg); /* delay slot */
 601 #else
 602     /* if not equal, jump to label3 */
 603     label3_ptr = (uint32_t *)s->code_ptr;
 604     tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
 605                  INSN_COND(COND_EQUAL));
 606     tcg_out_mov(s, r0, addr_reg); /* delay slot */
 607
 608     tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
 609
 610     /* if equal, jump to label1 */
 611     label1_ptr = (uint32_t *)s->code_ptr;
 612     tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) |
 613                  INSN_COND(COND_EQUAL));
 614     tcg_out_nop(s); /* delay slot */
 615
 616     /* label3: */
 617     *label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
 618 #endif
 619
 620     tcg_out_mov(s, TCG_REG_R26, addr_reg);
 621 #if TARGET_LONG_BITS == 64
 622     tcg_out_mov(s, TCG_REG_R25, addr_reg2);
 623     if (opc == 3) {
 624         tcg_abort();
 625         tcg_out_mov(s, TCG_REG_R24, data_reg);
 626         tcg_out_mov(s, TCG_REG_R23, data_reg2);
 627         /* TODO: push mem_index */
 628         tcg_abort();
 629     } else {
 630         switch(opc) {
 631         case 0:
 632             tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) |
 633                          INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
 634             break;
 635         case 1:
 636             tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) |
 637                          INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
 638             break;
 639         case 2:
 640             tcg_out_mov(s, TCG_REG_R24, data_reg);
 641             break;
 642         }
 643         tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index);
 644     }
 645 #else
 646     if (opc == 3) {
 647         tcg_abort();
 648         tcg_out_mov(s, TCG_REG_R25, data_reg);
 649         tcg_out_mov(s, TCG_REG_R24, data_reg2);
 650         tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index);
 651     } else {
 652         switch(opc) {
 653         case 0:
 654             tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) |
 655                          INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
 656             break;
 657         case 1:
 658             tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) |
 659                          INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
 660             break;
 661         case 2:
 662             tcg_out_mov(s, TCG_REG_R25, data_reg);
 663             break;
 664         }
 665         tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index);
 666     }
 667 #endif
 668     tcg_out_call(s, qemu_st_helpers[s_bits]);
 669
 670     /* jump to label2 */
 671     label2_ptr = (uint32_t *)s->code_ptr;
 672     tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
 673
 674     /* label1: */
 675     *label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
 676
 677     tcg_out_arithi(s, TCG_REG_R20, r1,
 678                    offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_write),
 679                    ARITH_ADD);
 680     tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
 681     tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD);
 682 #else
 683     r0 = addr_reg;
 684 #endif
 685
 686 #ifdef TARGET_WORDS_BIGENDIAN
 687     bswap = 0;
 688 #else
 689     bswap = 1;
 690 #endif
 691     switch (opc) {
 692     case 0:
 693         tcg_out_ldst(s, data_reg, r0, 0, STB);
 694         break;
 695     case 1:
 696         if (bswap) {
 697             tcg_out_bswap16(s, TCG_REG_R20, data_reg);
 698             data_reg = TCG_REG_R20;
 699         }
 700         tcg_out_ldst(s, data_reg, r0, 0, STH);
 701         break;
 702     case 2:
 703         if (bswap) {
 704             tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20);
 705             data_reg = TCG_REG_R20;
 706         }
 707         tcg_out_ldst(s, data_reg, r0, 0, STW);
 708         break;
 709     case 3:
 710         tcg_abort();
 711         if (!bswap) {
 712             tcg_out_ldst(s, data_reg, r0, 0, STW);
 713             tcg_out_ldst(s, data_reg2, r0, 4, STW);
 714         } else {
 715             tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20);
 716             tcg_out_ldst(s, TCG_REG_R20, r0, 4, STW);
 717             tcg_out_bswap32(s, TCG_REG_R20, data_reg2, TCG_REG_R20);
 718             tcg_out_ldst(s, TCG_REG_R20, r0, 0, STW);
 719         }
 720         break;
 721     default:
 722         tcg_abort();
 723     }
 724
 725 #if defined(CONFIG_SOFTMMU)
 726     /* label2: */
 727     *label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
 728 #endif
 729 }
 730
 731 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
 732                               const int *const_args)
 733 {
 734     int c;
 735
 736     switch (opc) {
 737     case INDEX_op_exit_tb:
 738         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RET0, args[0]);
 739         tcg_out32(s, BV_N | INSN_R2(TCG_REG_R18));
 740         break;
 741     case INDEX_op_goto_tb:
 742         if (s->tb_jmp_offset) {
 743             /* direct jump method */
 744             fprintf(stderr, "goto_tb direct\n");
 745             tcg_abort();
 746             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, args[0]);
 747             tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20));
 748             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
 749         } else {
 750             /* indirect jump method */
 751             tcg_out_ld_ptr(s, TCG_REG_R20,
 752                            (tcg_target_long)(s->tb_next + args[0]));
 753             tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20));
 754         }
 755         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
 756         break;
 757     case INDEX_op_call:
 758         tcg_out32(s, BLE_SR4 | INSN_R2(args[0]));
 759         tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
 760         break;
 761     case INDEX_op_jmp:
 762         fprintf(stderr, "unimplemented jmp\n");
 763         tcg_abort();
 764         break;
 765     case INDEX_op_br:
 766         fprintf(stderr, "unimplemented br\n");
 767         tcg_abort();
 768         break;
 769     case INDEX_op_movi_i32:
 770         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
 771         break;
 772
 773     case INDEX_op_ld8u_i32:
 774         tcg_out_ldst(s, args[0], args[1], args[2], LDB);
 775         break;
 776     case INDEX_op_ld8s_i32:
 777         tcg_out_ldst(s, args[0], args[1], args[2], LDB);
 778         tcg_out_ext8s(s, args[0], args[0]);
 779         break;
 780     case INDEX_op_ld16u_i32:
 781         tcg_out_ldst(s, args[0], args[1], args[2], LDH);
 782         break;
 783     case INDEX_op_ld16s_i32:
 784         tcg_out_ldst(s, args[0], args[1], args[2], LDH);
 785         tcg_out_ext16s(s, args[0], args[0]);
 786         break;
 787     case INDEX_op_ld_i32:
 788         tcg_out_ldst(s, args[0], args[1], args[2], LDW);
 789         break;
 790
 791     case INDEX_op_st8_i32:
 792         tcg_out_ldst(s, args[0], args[1], args[2], STB);
 793         break;
 794     case INDEX_op_st16_i32:
 795         tcg_out_ldst(s, args[0], args[1], args[2], STH);
 796         break;
 797     case INDEX_op_st_i32:
 798         tcg_out_ldst(s, args[0], args[1], args[2], STW);
 799         break;
 800
 801     case INDEX_op_sub_i32:
 802         c = ARITH_SUB;
 803         goto gen_arith;
 804     case INDEX_op_and_i32:
 805         c = ARITH_AND;
 806         goto gen_arith;
 807     case INDEX_op_or_i32:
 808         c = ARITH_OR;
 809         goto gen_arith;
 810     case INDEX_op_xor_i32:
 811         c = ARITH_XOR;
 812         goto gen_arith;
 813     case INDEX_op_add_i32:
 814         c = ARITH_ADD;
 815         goto gen_arith;
 816
 817     case INDEX_op_shl_i32:
 818         tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
 819                      lowsignext(0x1f, 0, 11));
 820         tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
 821         tcg_out32(s, ZVDEP | INSN_R2(args[0]) | INSN_R1(args[1]) |
 822                      INSN_DEP_LEN(32));
 823         break;
 824     case INDEX_op_shr_i32:
 825         tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(args[2]));
 826         tcg_out32(s, VSHD | INSN_T(args[0]) | INSN_R1(TCG_REG_R0) |
 827                      INSN_R2(args[1]));
 828         break;
 829     case INDEX_op_sar_i32:
 830         tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
 831                      lowsignext(0x1f, 0, 11));
 832         tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
 833         tcg_out32(s, VEXTRS | INSN_R1(args[0]) | INSN_R2(args[1]) |
 834                      INSN_DEP_LEN(32));
 835         break;
 836
 837     case INDEX_op_mul_i32:
 838         fprintf(stderr, "unimplemented mul\n");
 839         tcg_abort();
 840         break;
 841     case INDEX_op_mulu2_i32:
 842         fprintf(stderr, "unimplemented mulu2\n");
 843         tcg_abort();
 844         break;
 845     case INDEX_op_div2_i32:
 846         fprintf(stderr, "unimplemented div2\n");
 847         tcg_abort();
 848         break;
 849     case INDEX_op_divu2_i32:
 850         fprintf(stderr, "unimplemented divu2\n");
 851         tcg_abort();
 852         break;
 853
 854     case INDEX_op_brcond_i32:
 855         fprintf(stderr, "unimplemented brcond\n");
 856         tcg_abort();
 857         break;
 858
 859     case INDEX_op_qemu_ld8u:
 860         tcg_out_qemu_ld(s, args, 0);
 861         break;
 862     case INDEX_op_qemu_ld8s:
 863         tcg_out_qemu_ld(s, args, 0 | 4);
 864         break;
 865     case INDEX_op_qemu_ld16u:
 866         tcg_out_qemu_ld(s, args, 1);
 867         break;
 868     case INDEX_op_qemu_ld16s:
 869         tcg_out_qemu_ld(s, args, 1 | 4);
 870         break;
 871     case INDEX_op_qemu_ld32u:
 872         tcg_out_qemu_ld(s, args, 2);
 873         break;
 874
 875     case INDEX_op_qemu_st8:
 876         tcg_out_qemu_st(s, args, 0);
 877         break;
 878     case INDEX_op_qemu_st16:
 879         tcg_out_qemu_st(s, args, 1);
 880         break;
 881     case INDEX_op_qemu_st32:
 882         tcg_out_qemu_st(s, args, 2);
 883         break;
 884
 885     default:
 886         fprintf(stderr, "unknown opcode 0x%x\n", opc);
 887         tcg_abort();
 888     }
 889     return;
 890
 891 gen_arith:
 892     tcg_out_arith(s, args[0], args[1], args[2], c);
 893 }
 894
 895 static const TCGTargetOpDef hppa_op_defs[] = {
 896     { INDEX_op_exit_tb, { } },
 897     { INDEX_op_goto_tb, { } },
 898
 899     { INDEX_op_call, { "r" } },
 900     { INDEX_op_jmp, { "r" } },
 901     { INDEX_op_br, { } },
 902
 903     { INDEX_op_mov_i32, { "r", "r" } },
 904     { INDEX_op_movi_i32, { "r" } },
 905     { INDEX_op_ld8u_i32, { "r", "r" } },
 906     { INDEX_op_ld8s_i32, { "r", "r" } },
 907     { INDEX_op_ld16u_i32, { "r", "r" } },
 908     { INDEX_op_ld16s_i32, { "r", "r" } },
 909     { INDEX_op_ld_i32, { "r", "r" } },
 910     { INDEX_op_st8_i32, { "r", "r" } },
 911     { INDEX_op_st16_i32, { "r", "r" } },
 912     { INDEX_op_st_i32, { "r", "r" } },
 913
 914     { INDEX_op_add_i32, { "r", "r", "r" } },
 915     { INDEX_op_sub_i32, { "r", "r", "r" } },
 916     { INDEX_op_and_i32, { "r", "r", "r" } },
 917     { INDEX_op_or_i32, { "r", "r", "r" } },
 918     { INDEX_op_xor_i32, { "r", "r", "r" } },
 919
 920     { INDEX_op_shl_i32, { "r", "r", "r" } },
 921     { INDEX_op_shr_i32, { "r", "r", "r" } },
 922     { INDEX_op_sar_i32, { "r", "r", "r" } },
 923
 924     { INDEX_op_brcond_i32, { "r", "r" } },
 925
 926 #if TARGET_LONG_BITS == 32
 927     { INDEX_op_qemu_ld8u, { "r", "L" } },
 928     { INDEX_op_qemu_ld8s, { "r", "L" } },
 929     { INDEX_op_qemu_ld16u, { "r", "L" } },
 930     { INDEX_op_qemu_ld16s, { "r", "L" } },
 931     { INDEX_op_qemu_ld32u, { "r", "L" } },
 932     { INDEX_op_qemu_ld64, { "r", "r", "L" } },
 933
 934     { INDEX_op_qemu_st8, { "L", "L" } },
 935     { INDEX_op_qemu_st16, { "L", "L" } },
 936     { INDEX_op_qemu_st32, { "L", "L" } },
 937     { INDEX_op_qemu_st64, { "L", "L", "L" } },
 938 #else
 939     { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
 940     { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
 941     { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
 942     { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
 943     { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
 944     { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
 945     { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
 946
 947     { INDEX_op_qemu_st8, { "L", "L", "L" } },
 948     { INDEX_op_qemu_st16, { "L", "L", "L" } },
 949     { INDEX_op_qemu_st32, { "L", "L", "L" } },
 950     { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
 951 #endif
 952     { -1 },
 953 };
 954
 955 void tcg_target_init(TCGContext *s)
 956 {
 957     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
 958     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 959                      (1 << TCG_REG_R20) |
 960                      (1 << TCG_REG_R21) |
 961                      (1 << TCG_REG_R22) |
 962                      (1 << TCG_REG_R23) |
 963                      (1 << TCG_REG_R24) |
 964                      (1 << TCG_REG_R25) |
 965                      (1 << TCG_REG_R26));
 966
 967     tcg_regset_clear(s->reserved_regs);
 968     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);  /* hardwired to zero */
 969     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);  /* addil target */
 970     tcg_regset_set_reg(s->reserved_regs, TCG_REG_RP);  /* link register */
 971     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3);  /* frame pointer */
 972     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R18); /* return pointer */
 973     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R19); /* clobbered w/o pic */
 974     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R20); /* reserved */
 975     tcg_regset_set_reg(s->reserved_regs, TCG_REG_DP);  /* data pointer */
 976     tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);  /* stack pointer */
 977     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
 978
 979     tcg_add_target_add_op_defs(hppa_op_defs);
 980 }