hw/sun4u.c

   1 /*
   2  * QEMU Sun4u System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34
  35 #define KERNEL_LOAD_ADDR     0x00404000
  36 #define CMDLINE_ADDR         0x003ff000
  37 #define INITRD_LOAD_ADDR     0x00300000
  38 #define PROM_SIZE_MAX        (512 * 1024)
  39 #define PROM_ADDR            0x1fff0000000ULL
  40 #define PROM_VADDR           0x000ffd00000ULL
  41 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  42 #define APB_MEM_BASE         0x1ff00000000ULL
  43 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  44 #define PROM_FILENAME        "openbios-sparc64"
  45 #define NVRAM_SIZE           0x2000
  46
  47 /* TSC handling */
  48
  49 uint64_t cpu_get_tsc()
  50 {
  51     return qemu_get_clock(vm_clock);
  52 }
  53
  54 int DMA_get_channel_mode (int nchan)
  55 {
  56     return 0;
  57 }
  58 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  59 {
  60     return 0;
  61 }
  62 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  63 {
  64     return 0;
  65 }
  66 void DMA_hold_DREQ (int nchan) {}
  67 void DMA_release_DREQ (int nchan) {}
  68 void DMA_schedule(int nchan) {}
  69 void DMA_run (void) {}
  70 void DMA_init (int high_page_enable) {}
  71 void DMA_register_channel (int nchan,
  72                            DMA_transfer_handler transfer_handler,
  73                            void *opaque)
  74 {
  75 }
  76
  77 extern int nographic;
  78
  79 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
  80                                    const unsigned char *arch,
  81                                    uint32_t RAM_size, const char *boot_devices,
  82                                    uint32_t kernel_image, uint32_t kernel_size,
  83                                    const char *cmdline,
  84                                    uint32_t initrd_image, uint32_t initrd_size,
  85                                    uint32_t NVRAM_image,
  86                                    int width, int height, int depth)
  87 {
  88     unsigned int i;
  89     uint32_t start, end;
  90     uint8_t image[0x1ff0];
  91     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  92     struct sparc_arch_cfg *sparc_header;
  93     struct OpenBIOS_nvpart_v1 *part_header;
  94
  95     memset(image, '\0', sizeof(image));
  96
  97     // Try to match PPC NVRAM
  98     strcpy(header->struct_ident, "QEMU_BIOS");
  99     header->struct_version = cpu_to_be32(3); /* structure v3 */
 100
 101     header->nvram_size = cpu_to_be16(NVRAM_size);
 102     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 103     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 104     strcpy(header->arch, arch);
 105     header->nb_cpus = smp_cpus & 0xff;
 106     header->RAM0_base = 0;
 107     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 108     strcpy(header->boot_devices, boot_devices);
 109     header->nboot_devices = strlen(boot_devices) & 0xff;
 110     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 111     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 112     if (cmdline) {
 113         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 114         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 115         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 116     }
 117     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 118     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 119     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 120
 121     header->width = cpu_to_be16(width);
 122     header->height = cpu_to_be16(height);
 123     header->depth = cpu_to_be16(depth);
 124     if (nographic)
 125         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 126
 127     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 128
 129     // Architecture specific header
 130     start = sizeof(ohwcfg_v3_t);
 131     sparc_header = (struct sparc_arch_cfg *)&image[start];
 132     sparc_header->valid = 0;
 133     start += sizeof(struct sparc_arch_cfg);
 134
 135     // OpenBIOS nvram variables
 136     // Variable partition
 137     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 138     part_header->signature = OPENBIOS_PART_SYSTEM;
 139     strcpy(part_header->name, "system");
 140
 141     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 142     for (i = 0; i < nb_prom_envs; i++)
 143         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 144
 145     // End marker
 146     image[end++] = '\0';
 147
 148     end = start + ((end - start + 15) & ~15);
 149     OpenBIOS_finish_partition(part_header, end - start);
 150
 151     // free partition
 152     start = end;
 153     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 154     part_header->signature = OPENBIOS_PART_FREE;
 155     strcpy(part_header->name, "free");
 156
 157     end = 0x1fd0;
 158     OpenBIOS_finish_partition(part_header, end - start);
 159
 160     for (i = 0; i < sizeof(image); i++)
 161         m48t59_write(nvram, i, image[i]);
 162
 163     return 0;
 164 }
 165
 166 void pic_info()
 167 {
 168 }
 169
 170 void irq_info()
 171 {
 172 }
 173
 174 void qemu_system_powerdown(void)
 175 {
 176 }
 177
 178 static void main_cpu_reset(void *opaque)
 179 {
 180     CPUState *env = opaque;
 181
 182     cpu_reset(env);
 183     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 184     ptimer_run(env->tick, 0);
 185     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 186     ptimer_run(env->stick, 0);
 187     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 188     ptimer_run(env->hstick, 0);
 189 }
 190
 191 void tick_irq(void *opaque)
 192 {
 193     CPUState *env = opaque;
 194
 195     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 196 }
 197
 198 void stick_irq(void *opaque)
 199 {
 200     CPUState *env = opaque;
 201
 202     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 203 }
 204
 205 void hstick_irq(void *opaque)
 206 {
 207     CPUState *env = opaque;
 208
 209     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 210 }
 211
 212 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 213 {
 214 }
 215
 216 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 217 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 218 static const int ide_irq[2] = { 14, 15 };
 219
 220 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 221 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 222
 223 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 224 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 225
 226 static fdctrl_t *floppy_controller;
 227
 228 /* Sun4u hardware initialisation */
 229 static void sun4u_init(int ram_size, int vga_ram_size,
 230                        const char *boot_devices, DisplayState *ds,
 231                        const char *kernel_filename, const char *kernel_cmdline,
 232                        const char *initrd_filename, const char *cpu_model)
 233 {
 234     CPUState *env;
 235     char buf[1024];
 236     m48t59_t *nvram;
 237     int ret, linux_boot;
 238     unsigned int i;
 239     long prom_offset, initrd_size, kernel_size;
 240     PCIBus *pci_bus;
 241     QEMUBH *bh;
 242     qemu_irq *irq;
 243
 244     linux_boot = (kernel_filename != NULL);
 245
 246     /* init CPUs */
 247     if (cpu_model == NULL)
 248         cpu_model = "TI UltraSparc II";
 249     env = cpu_init(cpu_model);
 250     if (!env) {
 251         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 252         exit(1);
 253     }
 254     bh = qemu_bh_new(tick_irq, env);
 255     env->tick = ptimer_init(bh);
 256     ptimer_set_period(env->tick, 1ULL);
 257
 258     bh = qemu_bh_new(stick_irq, env);
 259     env->stick = ptimer_init(bh);
 260     ptimer_set_period(env->stick, 1ULL);
 261
 262     bh = qemu_bh_new(hstick_irq, env);
 263     env->hstick = ptimer_init(bh);
 264     ptimer_set_period(env->hstick, 1ULL);
 265     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 266     qemu_register_reset(main_cpu_reset, env);
 267     main_cpu_reset(env);
 268
 269     /* allocate RAM */
 270     cpu_register_physical_memory(0, ram_size, 0);
 271
 272     prom_offset = ram_size + vga_ram_size;
 273     cpu_register_physical_memory(PROM_ADDR,
 274                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
 275                                  prom_offset | IO_MEM_ROM);
 276
 277     if (bios_name == NULL)
 278         bios_name = PROM_FILENAME;
 279     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 280     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 281     if (ret < 0) {
 282         fprintf(stderr, "qemu: could not load prom '%s'\n",
 283                 buf);
 284         exit(1);
 285     }
 286
 287     kernel_size = 0;
 288     initrd_size = 0;
 289     if (linux_boot) {
 290         /* XXX: put correct offset */
 291         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 292         if (kernel_size < 0)
 293             kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 294         if (kernel_size < 0)
 295             kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 296         if (kernel_size < 0) {
 297             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 298                     kernel_filename);
 299             exit(1);
 300         }
 301
 302         /* load initrd */
 303         if (initrd_filename) {
 304             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 305             if (initrd_size < 0) {
 306                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 307                         initrd_filename);
 308                 exit(1);
 309             }
 310         }
 311         if (initrd_size > 0) {
 312             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 313                 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
 314                     == 0x48647253) { // HdrS
 315                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 316                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
 317                     break;
 318                 }
 319             }
 320         }
 321     }
 322     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 323     isa_mem_base = VGA_BASE;
 324     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
 325
 326     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 327         if (serial_hds[i]) {
 328             serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
 329         }
 330     }
 331
 332     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 333         if (parallel_hds[i]) {
 334             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
 335         }
 336     }
 337
 338     for(i = 0; i < nb_nics; i++) {
 339         if (!nd_table[i].model)
 340             nd_table[i].model = "ne2k_pci";
 341         pci_nic_init(pci_bus, &nd_table[i], -1);
 342     }
 343
 344     irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
 345     // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
 346     pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
 347     /* FIXME: wire up interrupts.  */
 348     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 349     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
 350     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 351     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
 352                          KERNEL_LOAD_ADDR, kernel_size,
 353                          kernel_cmdline,
 354                          INITRD_LOAD_ADDR, initrd_size,
 355                          /* XXX: need an option to load a NVRAM image */
 356                          0,
 357                          graphic_width, graphic_height, graphic_depth);
 358
 359 }
 360
 361 QEMUMachine sun4u_machine = {
 362     "sun4u",
 363     "Sun4u platform",
 364     sun4u_init,
 365 };