hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27
  28 //#define DEBUG_TIMER
  29
  30 #ifdef DEBUG_TIMER
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("TIMER: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /*
  38  * Registers of hardware timer in sun4m.
  39  *
  40  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  41  * produced as NCR89C105. See
  42  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  43  *
  44  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  45  * are zero. Bit 31 is 1 when count has been reached.
  46  *
  47  * Per-CPU timers interrupt local CPU, system timer uses normal
  48  * interrupt routing.
  49  *
  50  */
  51
  52 #define MAX_CPUS 16
  53
  54 typedef struct SLAVIO_TIMERState {
  55     qemu_irq irq;
  56     ptimer_state *timer;
  57     uint32_t count, counthigh, reached;
  58     uint64_t limit;
  59     // processor only
  60     int running;
  61     struct SLAVIO_TIMERState *master;
  62     int slave_index;
  63     // system only
  64     struct SLAVIO_TIMERState *slave[MAX_CPUS];
  65     uint32_t slave_mode;
  66 } SLAVIO_TIMERState;
  67
  68 #define TIMER_MAXADDR 0x1f
  69 #define SYS_TIMER_SIZE 0x14
  70 #define CPU_TIMER_SIZE 0x10
  71
  72 static int slavio_timer_is_user(SLAVIO_TIMERState *s)
  73 {
  74     return s->master && (s->master->slave_mode & (1 << s->slave_index));
  75 }
  76
  77 // Update count, set irq, update expire_time
  78 // Convert from ptimer countdown units
  79 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
  80 {
  81     uint64_t count;
  82
  83     count = s->limit - (ptimer_get_count(s->timer) << 9);
  84     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
  85             s->count);
  86     s->count = count & 0xfffffe00;
  87     s->counthigh = count >> 32;
  88 }
  89
  90 // timer callback
  91 static void slavio_timer_irq(void *opaque)
  92 {
  93     SLAVIO_TIMERState *s = opaque;
  94
  95     slavio_timer_get_out(s);
  96     DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
  97     if (!slavio_timer_is_user(s)) {
  98         s->reached = 0x80000000;
  99         qemu_irq_raise(s->irq);
 100     }
 101 }
 102
 103 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
 104 {
 105     SLAVIO_TIMERState *s = opaque;
 106     uint32_t saddr, ret;
 107
 108     saddr = (addr & TIMER_MAXADDR) >> 2;
 109     switch (saddr) {
 110     case 0:
 111         // read limit (system counter mode) or read most signifying
 112         // part of counter (user mode)
 113         if (slavio_timer_is_user(s)) {
 114             // read user timer MSW
 115             slavio_timer_get_out(s);
 116             ret = s->counthigh;
 117         } else {
 118             // read limit
 119             // clear irq
 120             qemu_irq_lower(s->irq);
 121             s->reached = 0;
 122             ret = s->limit & 0x7fffffff;
 123         }
 124         break;
 125     case 1:
 126         // read counter and reached bit (system mode) or read lsbits
 127         // of counter (user mode)
 128         slavio_timer_get_out(s);
 129         if (slavio_timer_is_user(s)) // read user timer LSW
 130             ret = s->count & 0xfffffe00;
 131         else // read limit
 132             ret = (s->count & 0x7ffffe00) | s->reached;
 133         break;
 134     case 3:
 135         // only available in processor counter/timer
 136         // read start/stop status
 137         ret = s->running;
 138         break;
 139     case 4:
 140         // only available in system counter
 141         // read user/system mode
 142         ret = s->slave_mode;
 143         break;
 144     default:
 145         DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
 146         ret = 0;
 147         break;
 148     }
 149     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 150
 151     return ret;
 152 }
 153
 154 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 155 {
 156     SLAVIO_TIMERState *s = opaque;
 157     uint32_t saddr;
 158     int reload = 0;
 159
 160     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 161     saddr = (addr & TIMER_MAXADDR) >> 2;
 162     switch (saddr) {
 163     case 0:
 164         if (slavio_timer_is_user(s)) {
 165             // set user counter MSW, reset counter
 166             qemu_irq_lower(s->irq);
 167             s->limit = 0x7ffffffffffffe00ULL;
 168             DPRINTF("processor %d user timer reset\n", s->slave_index);
 169             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 170         } else {
 171             // set limit, reset counter
 172             qemu_irq_lower(s->irq);
 173             s->limit = val & 0x7ffffe00ULL;
 174             if (!s->limit)
 175                 s->limit = 0x7ffffe00ULL;
 176             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 177         }
 178         break;
 179     case 1:
 180         if (slavio_timer_is_user(s)) {
 181             // set user counter LSW, reset counter
 182             qemu_irq_lower(s->irq);
 183             s->limit = 0x7ffffffffffffe00ULL;
 184             DPRINTF("processor %d user timer reset\n", s->slave_index);
 185             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 186         } else
 187             DPRINTF("not user timer\n");
 188         break;
 189     case 2:
 190         // set limit without resetting counter
 191         s->limit = val & 0x7ffffe00ULL;
 192         if (!s->limit)
 193             s->limit = 0x7ffffe00ULL;
 194         ptimer_set_limit(s->timer, s->limit >> 9, reload);
 195         break;
 196     case 3:
 197         if (slavio_timer_is_user(s)) {
 198             // start/stop user counter
 199             if ((val & 1) && !s->running) {
 200                 DPRINTF("processor %d user timer started\n", s->slave_index);
 201                 ptimer_run(s->timer, 0);
 202                 s->running = 1;
 203             } else if (!(val & 1) && s->running) {
 204                 DPRINTF("processor %d user timer stopped\n", s->slave_index);
 205                 ptimer_stop(s->timer);
 206                 s->running = 0;
 207             }
 208         }
 209         break;
 210     case 4:
 211         if (s->master == NULL) {
 212             unsigned int i;
 213
 214             for (i = 0; i < MAX_CPUS; i++) {
 215                 if (val & (1 << i)) {
 216                     qemu_irq_lower(s->slave[i]->irq);
 217                     s->slave[i]->limit = -1ULL;
 218                 }
 219                 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
 220                     ptimer_stop(s->slave[i]->timer);
 221                     ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1);
 222                     DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
 223                     ptimer_run(s->slave[i]->timer, 0);
 224                 }
 225             }
 226             s->slave_mode = val & ((1 << MAX_CPUS) - 1);
 227         } else
 228             DPRINTF("not system timer\n");
 229         break;
 230     default:
 231         DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
 232         break;
 233     }
 234 }
 235
 236 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
 237     slavio_timer_mem_readl,
 238     slavio_timer_mem_readl,
 239     slavio_timer_mem_readl,
 240 };
 241
 242 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
 243     slavio_timer_mem_writel,
 244     slavio_timer_mem_writel,
 245     slavio_timer_mem_writel,
 246 };
 247
 248 static void slavio_timer_save(QEMUFile *f, void *opaque)
 249 {
 250     SLAVIO_TIMERState *s = opaque;
 251
 252     qemu_put_be64s(f, &s->limit);
 253     qemu_put_be32s(f, &s->count);
 254     qemu_put_be32s(f, &s->counthigh);
 255     qemu_put_be32(f, 0); // Was irq
 256     qemu_put_be32s(f, &s->reached);
 257     qemu_put_be32s(f, &s->running);
 258     qemu_put_be32s(f, 0); // Was mode
 259     qemu_put_ptimer(f, s->timer);
 260 }
 261
 262 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 263 {
 264     SLAVIO_TIMERState *s = opaque;
 265     uint32_t tmp;
 266
 267     if (version_id != 2)
 268         return -EINVAL;
 269
 270     qemu_get_be64s(f, &s->limit);
 271     qemu_get_be32s(f, &s->count);
 272     qemu_get_be32s(f, &s->counthigh);
 273     qemu_get_be32s(f, &tmp); // Was irq
 274     qemu_get_be32s(f, &s->reached);
 275     qemu_get_be32s(f, &s->running);
 276     qemu_get_be32s(f, &tmp); // Was mode
 277     qemu_get_ptimer(f, s->timer);
 278
 279     return 0;
 280 }
 281
 282 static void slavio_timer_reset(void *opaque)
 283 {
 284     SLAVIO_TIMERState *s = opaque;
 285
 286     if (slavio_timer_is_user(s))
 287         s->limit = 0x7ffffffffffffe00ULL;
 288     else
 289         s->limit = 0x7ffffe00ULL;
 290     s->count = 0;
 291     s->reached = 0;
 292     ptimer_set_limit(s->timer, s->limit >> 9, 1);
 293     ptimer_run(s->timer, 0);
 294     s->running = 1;
 295     qemu_irq_lower(s->irq);
 296 }
 297
 298 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
 299                                             qemu_irq irq,
 300                                             SLAVIO_TIMERState *master,
 301                                             int slave_index)
 302 {
 303     int slavio_timer_io_memory;
 304     SLAVIO_TIMERState *s;
 305     QEMUBH *bh;
 306
 307     s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
 308     if (!s)
 309         return s;
 310     s->irq = irq;
 311     s->master = master;
 312     s->slave_index = slave_index;
 313     bh = qemu_bh_new(slavio_timer_irq, s);
 314     s->timer = ptimer_init(bh);
 315     ptimer_set_period(s->timer, 500ULL);
 316
 317     slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
 318                                                     slavio_timer_mem_write, s);
 319     if (master)
 320         cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
 321     else
 322         cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory);
 323     register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
 324     qemu_register_reset(slavio_timer_reset, s);
 325     slavio_timer_reset(s);
 326
 327     return s;
 328 }
 329
 330 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
 331                            qemu_irq *cpu_irqs)
 332 {
 333     SLAVIO_TIMERState *master;
 334     unsigned int i;
 335
 336     master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0);
 337
 338     for (i = 0; i < MAX_CPUS; i++) {
 339         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
 340                                              (i * TARGET_PAGE_SIZE),
 341                                              cpu_irqs[i], master, i);
 342     }
 343 }