hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "ppc.h"
  33 #include "boards.h"
  34
  35 //#define HARD_DEBUG_PPC_IO
  36 //#define DEBUG_PPC_IO
  37
  38 /* SMP is not enabled, for now */
  39 #define MAX_CPUS 1
  40
  41 #define BIOS_FILENAME "ppc_rom.bin"
  42 #define KERNEL_LOAD_ADDR 0x01000000
  43 #define INITRD_LOAD_ADDR 0x01800000
  44
  45 extern int loglevel;
  46 extern FILE *logfile;
  47
  48 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  49 #define DEBUG_PPC_IO
  50 #endif
  51
  52 #if defined (HARD_DEBUG_PPC_IO)
  53 #define PPC_IO_DPRINTF(fmt, args...)                     \
  54 do {                                                     \
  55     if (loglevel & CPU_LOG_IOPORT) {                     \
  56         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  57     } else {                                             \
  58         printf("%s : " fmt, __func__ , ##args);          \
  59     }                                                    \
  60 } while (0)
  61 #elif defined (DEBUG_PPC_IO)
  62 #define PPC_IO_DPRINTF(fmt, args...)                     \
  63 do {                                                     \
  64     if (loglevel & CPU_LOG_IOPORT) {                     \
  65         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  66     }                                                    \
  67 } while (0)
  68 #else
  69 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
  70 #endif
  71
  72 /* Constants for devices init */
  73 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  74 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  75 static const int ide_irq[2] = { 13, 13 };
  76
  77 #define NE2000_NB_MAX 6
  78
  79 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  80 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  81
  82 //static PITState *pit;
  83
  84 /* ISA IO ports bridge */
  85 #define PPC_IO_BASE 0x80000000
  86
  87 /* Speaker port 0x61 */
  88 int speaker_data_on;
  89 int dummy_refresh_clock;
  90
  91 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  92 {
  93 #if 0
  94     speaker_data_on = (val >> 1) & 1;
  95     pit_set_gate(pit, 2, val & 1);
  96 #endif
  97 }
  98
  99 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 100 {
 101 #if 0
 102     int out;
 103     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 104     dummy_refresh_clock ^= 1;
 105     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 106         (dummy_refresh_clock << 4);
 107 #endif
 108     return 0;
 109 }
 110
 111 /* PCI intack register */
 112 /* Read-only register (?) */
 113 static void _PPC_intack_write (void *opaque,
 114                                target_phys_addr_t addr, uint32_t value)
 115 {
 116 //    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 117 }
 118
 119 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
 120 {
 121     uint32_t retval = 0;
 122
 123     if (addr == 0xBFFFFFF0)
 124         retval = pic_intack_read(isa_pic);
 125 //   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 126
 127     return retval;
 128 }
 129
 130 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 131 {
 132     return _PPC_intack_read(addr);
 133 }
 134
 135 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 136 {
 137 #ifdef TARGET_WORDS_BIGENDIAN
 138     return bswap16(_PPC_intack_read(addr));
 139 #else
 140     return _PPC_intack_read(addr);
 141 #endif
 142 }
 143
 144 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 145 {
 146 #ifdef TARGET_WORDS_BIGENDIAN
 147     return bswap32(_PPC_intack_read(addr));
 148 #else
 149     return _PPC_intack_read(addr);
 150 #endif
 151 }
 152
 153 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 154     &_PPC_intack_write,
 155     &_PPC_intack_write,
 156     &_PPC_intack_write,
 157 };
 158
 159 static CPUReadMemoryFunc *PPC_intack_read[] = {
 160     &PPC_intack_readb,
 161     &PPC_intack_readw,
 162     &PPC_intack_readl,
 163 };
 164
 165 /* PowerPC control and status registers */
 166 #if 0 // Not used
 167 static struct {
 168     /* IDs */
 169     uint32_t veni_devi;
 170     uint32_t revi;
 171     /* Control and status */
 172     uint32_t gcsr;
 173     uint32_t xcfr;
 174     uint32_t ct32;
 175     uint32_t mcsr;
 176     /* General purpose registers */
 177     uint32_t gprg[6];
 178     /* Exceptions */
 179     uint32_t feen;
 180     uint32_t fest;
 181     uint32_t fema;
 182     uint32_t fecl;
 183     uint32_t eeen;
 184     uint32_t eest;
 185     uint32_t eecl;
 186     uint32_t eeint;
 187     uint32_t eemck0;
 188     uint32_t eemck1;
 189     /* Error diagnostic */
 190 } XCSR;
 191
 192 static void PPC_XCSR_writeb (void *opaque,
 193                              target_phys_addr_t addr, uint32_t value)
 194 {
 195     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 196 }
 197
 198 static void PPC_XCSR_writew (void *opaque,
 199                              target_phys_addr_t addr, uint32_t value)
 200 {
 201 #ifdef TARGET_WORDS_BIGENDIAN
 202     value = bswap16(value);
 203 #endif
 204     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 205 }
 206
 207 static void PPC_XCSR_writel (void *opaque,
 208                              target_phys_addr_t addr, uint32_t value)
 209 {
 210 #ifdef TARGET_WORDS_BIGENDIAN
 211     value = bswap32(value);
 212 #endif
 213     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 214 }
 215
 216 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 217 {
 218     uint32_t retval = 0;
 219
 220     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 221
 222     return retval;
 223 }
 224
 225 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 226 {
 227     uint32_t retval = 0;
 228
 229     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 230 #ifdef TARGET_WORDS_BIGENDIAN
 231     retval = bswap16(retval);
 232 #endif
 233
 234     return retval;
 235 }
 236
 237 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 238 {
 239     uint32_t retval = 0;
 240
 241     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 242 #ifdef TARGET_WORDS_BIGENDIAN
 243     retval = bswap32(retval);
 244 #endif
 245
 246     return retval;
 247 }
 248
 249 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 250     &PPC_XCSR_writeb,
 251     &PPC_XCSR_writew,
 252     &PPC_XCSR_writel,
 253 };
 254
 255 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 256     &PPC_XCSR_readb,
 257     &PPC_XCSR_readw,
 258     &PPC_XCSR_readl,
 259 };
 260 #endif
 261
 262 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 263 typedef struct sysctrl_t {
 264     qemu_irq reset_irq;
 265     m48t59_t *nvram;
 266     uint8_t state;
 267     uint8_t syscontrol;
 268     uint8_t fake_io[2];
 269     int contiguous_map;
 270     int endian;
 271 } sysctrl_t;
 272
 273 enum {
 274     STATE_HARDFILE = 0x01,
 275 };
 276
 277 static sysctrl_t *sysctrl;
 278
 279 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 280 {
 281     sysctrl_t *sysctrl = opaque;
 282
 283     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 284                    val);
 285     sysctrl->fake_io[addr - 0x0398] = val;
 286 }
 287
 288 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 289 {
 290     sysctrl_t *sysctrl = opaque;
 291
 292     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 293                    sysctrl->fake_io[addr - 0x0398]);
 294     return sysctrl->fake_io[addr - 0x0398];
 295 }
 296
 297 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 298 {
 299     sysctrl_t *sysctrl = opaque;
 300
 301     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 302                    addr - PPC_IO_BASE, val);
 303     switch (addr) {
 304     case 0x0092:
 305         /* Special port 92 */
 306         /* Check soft reset asked */
 307         if (val & 0x01) {
 308             qemu_irq_raise(sysctrl->reset_irq);
 309         } else {
 310             qemu_irq_lower(sysctrl->reset_irq);
 311         }
 312         /* Check LE mode */
 313         if (val & 0x02) {
 314             sysctrl->endian = 1;
 315         } else {
 316             sysctrl->endian = 0;
 317         }
 318         break;
 319     case 0x0800:
 320         /* Motorola CPU configuration register : read-only */
 321         break;
 322     case 0x0802:
 323         /* Motorola base module feature register : read-only */
 324         break;
 325     case 0x0803:
 326         /* Motorola base module status register : read-only */
 327         break;
 328     case 0x0808:
 329         /* Hardfile light register */
 330         if (val & 1)
 331             sysctrl->state |= STATE_HARDFILE;
 332         else
 333             sysctrl->state &= ~STATE_HARDFILE;
 334         break;
 335     case 0x0810:
 336         /* Password protect 1 register */
 337         if (sysctrl->nvram != NULL)
 338             m48t59_toggle_lock(sysctrl->nvram, 1);
 339         break;
 340     case 0x0812:
 341         /* Password protect 2 register */
 342         if (sysctrl->nvram != NULL)
 343             m48t59_toggle_lock(sysctrl->nvram, 2);
 344         break;
 345     case 0x0814:
 346         /* L2 invalidate register */
 347         //        tlb_flush(first_cpu, 1);
 348         break;
 349     case 0x081C:
 350         /* system control register */
 351         sysctrl->syscontrol = val & 0x0F;
 352         break;
 353     case 0x0850:
 354         /* I/O map type register */
 355         sysctrl->contiguous_map = val & 0x01;
 356         break;
 357     default:
 358         printf("ERROR: unaffected IO port write: %04" PRIx32
 359                " => %02" PRIx32"\n", addr, val);
 360         break;
 361     }
 362 }
 363
 364 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 365 {
 366     sysctrl_t *sysctrl = opaque;
 367     uint32_t retval = 0xFF;
 368
 369     switch (addr) {
 370     case 0x0092:
 371         /* Special port 92 */
 372         retval = 0x00;
 373         break;
 374     case 0x0800:
 375         /* Motorola CPU configuration register */
 376         retval = 0xEF; /* MPC750 */
 377         break;
 378     case 0x0802:
 379         /* Motorola Base module feature register */
 380         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 381         break;
 382     case 0x0803:
 383         /* Motorola base module status register */
 384         retval = 0xE0; /* Standard MPC750 */
 385         break;
 386     case 0x080C:
 387         /* Equipment present register:
 388          *  no L2 cache
 389          *  no upgrade processor
 390          *  no cards in PCI slots
 391          *  SCSI fuse is bad
 392          */
 393         retval = 0x3C;
 394         break;
 395     case 0x0810:
 396         /* Motorola base module extended feature register */
 397         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 398         break;
 399     case 0x0814:
 400         /* L2 invalidate: don't care */
 401         break;
 402     case 0x0818:
 403         /* Keylock */
 404         retval = 0x00;
 405         break;
 406     case 0x081C:
 407         /* system control register
 408          * 7 - 6 / 1 - 0: L2 cache enable
 409          */
 410         retval = sysctrl->syscontrol;
 411         break;
 412     case 0x0823:
 413         /* */
 414         retval = 0x03; /* no L2 cache */
 415         break;
 416     case 0x0850:
 417         /* I/O map type register */
 418         retval = sysctrl->contiguous_map;
 419         break;
 420     default:
 421         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 422         break;
 423     }
 424     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 425                    addr - PPC_IO_BASE, retval);
 426
 427     return retval;
 428 }
 429
 430 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
 431                                                          target_phys_addr_t
 432                                                          addr)
 433 {
 434     if (sysctrl->contiguous_map == 0) {
 435         /* 64 KB contiguous space for IOs */
 436         addr &= 0xFFFF;
 437     } else {
 438         /* 8 MB non-contiguous space for IOs */
 439         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 440     }
 441
 442     return addr;
 443 }
 444
 445 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 446                                 uint32_t value)
 447 {
 448     sysctrl_t *sysctrl = opaque;
 449
 450     addr = prep_IO_address(sysctrl, addr);
 451     cpu_outb(NULL, addr, value);
 452 }
 453
 454 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 455 {
 456     sysctrl_t *sysctrl = opaque;
 457     uint32_t ret;
 458
 459     addr = prep_IO_address(sysctrl, addr);
 460     ret = cpu_inb(NULL, addr);
 461
 462     return ret;
 463 }
 464
 465 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 466                                 uint32_t value)
 467 {
 468     sysctrl_t *sysctrl = opaque;
 469
 470     addr = prep_IO_address(sysctrl, addr);
 471 #ifdef TARGET_WORDS_BIGENDIAN
 472     value = bswap16(value);
 473 #endif
 474     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 475     cpu_outw(NULL, addr, value);
 476 }
 477
 478 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 479 {
 480     sysctrl_t *sysctrl = opaque;
 481     uint32_t ret;
 482
 483     addr = prep_IO_address(sysctrl, addr);
 484     ret = cpu_inw(NULL, addr);
 485 #ifdef TARGET_WORDS_BIGENDIAN
 486     ret = bswap16(ret);
 487 #endif
 488     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 489
 490     return ret;
 491 }
 492
 493 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 494                                 uint32_t value)
 495 {
 496     sysctrl_t *sysctrl = opaque;
 497
 498     addr = prep_IO_address(sysctrl, addr);
 499 #ifdef TARGET_WORDS_BIGENDIAN
 500     value = bswap32(value);
 501 #endif
 502     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 503     cpu_outl(NULL, addr, value);
 504 }
 505
 506 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 507 {
 508     sysctrl_t *sysctrl = opaque;
 509     uint32_t ret;
 510
 511     addr = prep_IO_address(sysctrl, addr);
 512     ret = cpu_inl(NULL, addr);
 513 #ifdef TARGET_WORDS_BIGENDIAN
 514     ret = bswap32(ret);
 515 #endif
 516     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 517
 518     return ret;
 519 }
 520
 521 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 522     &PPC_prep_io_writeb,
 523     &PPC_prep_io_writew,
 524     &PPC_prep_io_writel,
 525 };
 526
 527 CPUReadMemoryFunc *PPC_prep_io_read[] = {
 528     &PPC_prep_io_readb,
 529     &PPC_prep_io_readw,
 530     &PPC_prep_io_readl,
 531 };
 532
 533 #define NVRAM_SIZE        0x2000
 534
 535 /* PowerPC PREP hardware initialisation */
 536 static void ppc_prep_init (int ram_size, int vga_ram_size,
 537                            const char *boot_device, DisplayState *ds,
 538                            const char *kernel_filename,
 539                            const char *kernel_cmdline,
 540                            const char *initrd_filename,
 541                            const char *cpu_model)
 542 {
 543     CPUState *env = NULL, *envs[MAX_CPUS];
 544     char buf[1024];
 545     nvram_t nvram;
 546     m48t59_t *m48t59;
 547     int PPC_io_memory;
 548     int linux_boot, i, nb_nics1, bios_size;
 549     unsigned long bios_offset;
 550     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 551     PCIBus *pci_bus;
 552     qemu_irq *i8259;
 553     int ppc_boot_device;
 554
 555     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 556     if (sysctrl == NULL)
 557         return;
 558
 559     linux_boot = (kernel_filename != NULL);
 560
 561     /* init CPUs */
 562     if (cpu_model == NULL)
 563         cpu_model = "default";
 564     for (i = 0; i < smp_cpus; i++) {
 565         env = cpu_init(cpu_model);
 566         if (!env) {
 567             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 568             exit(1);
 569         }
 570         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 571             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 572             cpu_ppc_tb_init(env, 7812500UL);
 573         } else {
 574             /* Set time-base frequency to 100 Mhz */
 575             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 576         }
 577         qemu_register_reset(&cpu_ppc_reset, env);
 578         register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 579         envs[i] = env;
 580     }
 581
 582     /* allocate RAM */
 583     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 584
 585     /* allocate and load BIOS */
 586     bios_offset = ram_size + vga_ram_size;
 587     if (bios_name == NULL)
 588         bios_name = BIOS_FILENAME;
 589     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 590     bios_size = load_image(buf, phys_ram_base + bios_offset);
 591     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 592         cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
 593         exit(1);
 594     }
 595     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 596         cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 597     }
 598     bios_size = (bios_size + 0xfff) & ~0xfff;
 599     cpu_register_physical_memory((uint32_t)(-bios_size),
 600                                  bios_size, bios_offset | IO_MEM_ROM);
 601
 602     if (linux_boot) {
 603         kernel_base = KERNEL_LOAD_ADDR;
 604         /* now we can load the kernel */
 605         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 606         if (kernel_size < 0) {
 607             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 608                       kernel_filename);
 609             exit(1);
 610         }
 611         /* load initrd */
 612         if (initrd_filename) {
 613             initrd_base = INITRD_LOAD_ADDR;
 614             initrd_size = load_image(initrd_filename,
 615                                      phys_ram_base + initrd_base);
 616             if (initrd_size < 0) {
 617                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 618                           initrd_filename);
 619                 exit(1);
 620             }
 621         } else {
 622             initrd_base = 0;
 623             initrd_size = 0;
 624         }
 625         ppc_boot_device = 'm';
 626     } else {
 627         kernel_base = 0;
 628         kernel_size = 0;
 629         initrd_base = 0;
 630         initrd_size = 0;
 631         ppc_boot_device = '\0';
 632         /* For now, OHW cannot boot from the network. */
 633         for (i = 0; boot_device[i] != '\0'; i++) {
 634             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 635                 ppc_boot_device = boot_device[i];
 636                 break;
 637             }
 638         }
 639         if (ppc_boot_device == '\0') {
 640             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 641             exit(1);
 642         }
 643     }
 644
 645     isa_mem_base = 0xc0000000;
 646     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 647         cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
 648         exit(1);
 649     }
 650     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 651     pci_bus = pci_prep_init(i8259);
 652     //    pci_bus = i440fx_init();
 653     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 654     PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
 655                                            PPC_prep_io_write, sysctrl);
 656     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 657
 658     /* init basic PC hardware */
 659     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
 660                  vga_ram_size, 0, 0);
 661     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 662     //    pit = pit_init(0x40, i8259[0]);
 663     rtc_init(0x70, i8259[8]);
 664
 665     serial_init(0x3f8, i8259[4], serial_hds[0]);
 666     nb_nics1 = nb_nics;
 667     if (nb_nics1 > NE2000_NB_MAX)
 668         nb_nics1 = NE2000_NB_MAX;
 669     for(i = 0; i < nb_nics1; i++) {
 670         if (nd_table[i].model == NULL
 671             || strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 672             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 673         } else {
 674             pci_nic_init(pci_bus, &nd_table[i], -1);
 675         }
 676     }
 677
 678     for(i = 0; i < 2; i++) {
 679         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 680                      bs_table[2 * i], bs_table[2 * i + 1]);
 681     }
 682     i8042_init(i8259[1], i8259[12], 0x60);
 683     DMA_init(1);
 684     //    AUD_init();
 685     //    SB16_init();
 686
 687     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
 688
 689     /* Register speaker port */
 690     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 691     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 692     /* Register fake IO ports for PREP */
 693     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 694     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 695     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 696     /* System control ports */
 697     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 698     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 699     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 700     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 701     /* PCI intack location */
 702     PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
 703                                            PPC_intack_write, NULL);
 704     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 705     /* PowerPC control and status register group */
 706 #if 0
 707     PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
 708                                            NULL);
 709     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 710 #endif
 711
 712     if (usb_enabled) {
 713         usb_ohci_init_pci(pci_bus, 3, -1);
 714     }
 715
 716     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 717     if (m48t59 == NULL)
 718         return;
 719     sysctrl->nvram = m48t59;
 720
 721     /* Initialise NVRAM */
 722     nvram.opaque = m48t59;
 723     nvram.read_fn = &m48t59_read;
 724     nvram.write_fn = &m48t59_write;
 725     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 726                          kernel_base, kernel_size,
 727                          kernel_cmdline,
 728                          initrd_base, initrd_size,
 729                          /* XXX: need an option to load a NVRAM image */
 730                          0,
 731                          graphic_width, graphic_height, graphic_depth);
 732
 733     /* Special port to get debug messages from Open-Firmware */
 734     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 735 }
 736
 737 QEMUMachine prep_machine = {
 738     "prep",
 739     "PowerPC PREP platform",
 740     ppc_prep_init,
 741 };