hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "console.h"
  27 #include "net.h"
  28
  29 //#define DEBUG_PCI
  30
  31 struct PCIBus {
  32     int bus_num;
  33     int devfn_min;
  34     pci_set_irq_fn set_irq;
  35     pci_map_irq_fn map_irq;
  36     uint32_t config_reg; /* XXX: suppress */
  37     /* low level pic */
  38     SetIRQFunc *low_set_irq;
  39     qemu_irq *irq_opaque;
  40     PCIDevice *devices[256];
  41     PCIDevice *parent_dev;
  42     PCIBus *next;
  43     /* The bus IRQ state is the logical OR of the connected devices.
  44        Keep a count of the number of devices with raised IRQs.  */
  45     int irq_count[];
  46 };
  47
  48 static void pci_update_mappings(PCIDevice *d);
  49 static void pci_set_irq(void *opaque, int irq_num, int level);
  50
  51 target_phys_addr_t pci_mem_base;
  52 static int pci_irq_index;
  53 static PCIBus *first_bus;
  54
  55 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  56                          qemu_irq *pic, int devfn_min, int nirq)
  57 {
  58     PCIBus *bus;
  59     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  60     bus->set_irq = set_irq;
  61     bus->map_irq = map_irq;
  62     bus->irq_opaque = pic;
  63     bus->devfn_min = devfn_min;
  64     first_bus = bus;
  65     return bus;
  66 }
  67
  68 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
  69 {
  70     PCIBus *bus;
  71     bus = qemu_mallocz(sizeof(PCIBus));
  72     bus->map_irq = map_irq;
  73     bus->parent_dev = dev;
  74     bus->next = dev->bus->next;
  75     dev->bus->next = bus;
  76     return bus;
  77 }
  78
  79 int pci_bus_num(PCIBus *s)
  80 {
  81     return s->bus_num;
  82 }
  83
  84 void pci_device_save(PCIDevice *s, QEMUFile *f)
  85 {
  86     qemu_put_be32(f, 1); /* PCI device version */
  87     qemu_put_buffer(f, s->config, 256);
  88 }
  89
  90 int pci_device_load(PCIDevice *s, QEMUFile *f)
  91 {
  92     uint32_t version_id;
  93     version_id = qemu_get_be32(f);
  94     if (version_id != 1)
  95         return -EINVAL;
  96     qemu_get_buffer(f, s->config, 256);
  97     pci_update_mappings(s);
  98     return 0;
  99 }
 100
 101 /* -1 for devfn means auto assign */
 102 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 103                                int instance_size, int devfn,
 104                                PCIConfigReadFunc *config_read,
 105                                PCIConfigWriteFunc *config_write)
 106 {
 107     PCIDevice *pci_dev;
 108
 109     if (pci_irq_index >= PCI_DEVICES_MAX)
 110         return NULL;
 111
 112     if (devfn < 0) {
 113         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 114             if (!bus->devices[devfn])
 115                 goto found;
 116         }
 117         return NULL;
 118     found: ;
 119     }
 120     pci_dev = qemu_mallocz(instance_size);
 121     if (!pci_dev)
 122         return NULL;
 123     pci_dev->bus = bus;
 124     pci_dev->devfn = devfn;
 125     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 126     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 127
 128     if (!config_read)
 129         config_read = pci_default_read_config;
 130     if (!config_write)
 131         config_write = pci_default_write_config;
 132     pci_dev->config_read = config_read;
 133     pci_dev->config_write = config_write;
 134     pci_dev->irq_index = pci_irq_index++;
 135     bus->devices[devfn] = pci_dev;
 136     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 137     return pci_dev;
 138 }
 139
 140 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 141                             uint32_t size, int type,
 142                             PCIMapIORegionFunc *map_func)
 143 {
 144     PCIIORegion *r;
 145     uint32_t addr;
 146
 147     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 148         return;
 149     r = &pci_dev->io_regions[region_num];
 150     r->addr = -1;
 151     r->size = size;
 152     r->type = type;
 153     r->map_func = map_func;
 154     if (region_num == PCI_ROM_SLOT) {
 155         addr = 0x30;
 156     } else {
 157         addr = 0x10 + region_num * 4;
 158     }
 159     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 160 }
 161
 162 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 163 {
 164     return addr + pci_mem_base;
 165 }
 166
 167 static void pci_update_mappings(PCIDevice *d)
 168 {
 169     PCIIORegion *r;
 170     int cmd, i;
 171     uint32_t last_addr, new_addr, config_ofs;
 172
 173     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 174     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 175         r = &d->io_regions[i];
 176         if (i == PCI_ROM_SLOT) {
 177             config_ofs = 0x30;
 178         } else {
 179             config_ofs = 0x10 + i * 4;
 180         }
 181         if (r->size != 0) {
 182             if (r->type & PCI_ADDRESS_SPACE_IO) {
 183                 if (cmd & PCI_COMMAND_IO) {
 184                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 185                                                          config_ofs));
 186                     new_addr = new_addr & ~(r->size - 1);
 187                     last_addr = new_addr + r->size - 1;
 188                     /* NOTE: we have only 64K ioports on PC */
 189                     if (last_addr <= new_addr || new_addr == 0 ||
 190                         last_addr >= 0x10000) {
 191                         new_addr = -1;
 192                     }
 193                 } else {
 194                     new_addr = -1;
 195                 }
 196             } else {
 197                 if (cmd & PCI_COMMAND_MEMORY) {
 198                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 199                                                          config_ofs));
 200                     /* the ROM slot has a specific enable bit */
 201                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 202                         goto no_mem_map;
 203                     new_addr = new_addr & ~(r->size - 1);
 204                     last_addr = new_addr + r->size - 1;
 205                     /* NOTE: we do not support wrapping */
 206                     /* XXX: as we cannot support really dynamic
 207                        mappings, we handle specific values as invalid
 208                        mappings. */
 209                     if (last_addr <= new_addr || new_addr == 0 ||
 210                         last_addr == -1) {
 211                         new_addr = -1;
 212                     }
 213                 } else {
 214                 no_mem_map:
 215                     new_addr = -1;
 216                 }
 217             }
 218             /* now do the real mapping */
 219             if (new_addr != r->addr) {
 220                 if (r->addr != -1) {
 221                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 222                         int class;
 223                         /* NOTE: specific hack for IDE in PC case:
 224                            only one byte must be mapped. */
 225                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 226                         if (class == 0x0101 && r->size == 4) {
 227                             isa_unassign_ioport(r->addr + 2, 1);
 228                         } else {
 229                             isa_unassign_ioport(r->addr, r->size);
 230                         }
 231                     } else {
 232                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 233                                                      r->size,
 234                                                      IO_MEM_UNASSIGNED);
 235                     }
 236                 }
 237                 r->addr = new_addr;
 238                 if (r->addr != -1) {
 239                     r->map_func(d, i, r->addr, r->size, r->type);
 240                 }
 241             }
 242         }
 243     }
 244 }
 245
 246 uint32_t pci_default_read_config(PCIDevice *d,
 247                                  uint32_t address, int len)
 248 {
 249     uint32_t val;
 250
 251     switch(len) {
 252     default:
 253     case 4:
 254         if (address <= 0xfc) {
 255             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 256             break;
 257         }
 258         /* fall through */
 259     case 2:
 260         if (address <= 0xfe) {
 261             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 262             break;
 263         }
 264         /* fall through */
 265     case 1:
 266         val = d->config[address];
 267         break;
 268     }
 269     return val;
 270 }
 271
 272 void pci_default_write_config(PCIDevice *d,
 273                               uint32_t address, uint32_t val, int len)
 274 {
 275     int can_write, i;
 276     uint32_t end, addr;
 277
 278     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 279                      (address >= 0x30 && address < 0x34))) {
 280         PCIIORegion *r;
 281         int reg;
 282
 283         if ( address >= 0x30 ) {
 284             reg = PCI_ROM_SLOT;
 285         }else{
 286             reg = (address - 0x10) >> 2;
 287         }
 288         r = &d->io_regions[reg];
 289         if (r->size == 0)
 290             goto default_config;
 291         /* compute the stored value */
 292         if (reg == PCI_ROM_SLOT) {
 293             /* keep ROM enable bit */
 294             val &= (~(r->size - 1)) | 1;
 295         } else {
 296             val &= ~(r->size - 1);
 297             val |= r->type;
 298         }
 299         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 300         pci_update_mappings(d);
 301         return;
 302     }
 303  default_config:
 304     /* not efficient, but simple */
 305     addr = address;
 306     for(i = 0; i < len; i++) {
 307         /* default read/write accesses */
 308         switch(d->config[0x0e]) {
 309         case 0x00:
 310         case 0x80:
 311             switch(addr) {
 312             case 0x00:
 313             case 0x01:
 314             case 0x02:
 315             case 0x03:
 316             case 0x08:
 317             case 0x09:
 318             case 0x0a:
 319             case 0x0b:
 320             case 0x0e:
 321             case 0x10 ... 0x27: /* base */
 322             case 0x30 ... 0x33: /* rom */
 323             case 0x3d:
 324                 can_write = 0;
 325                 break;
 326             default:
 327                 can_write = 1;
 328                 break;
 329             }
 330             break;
 331         default:
 332         case 0x01:
 333             switch(addr) {
 334             case 0x00:
 335             case 0x01:
 336             case 0x02:
 337             case 0x03:
 338             case 0x08:
 339             case 0x09:
 340             case 0x0a:
 341             case 0x0b:
 342             case 0x0e:
 343             case 0x38 ... 0x3b: /* rom */
 344             case 0x3d:
 345                 can_write = 0;
 346                 break;
 347             default:
 348                 can_write = 1;
 349                 break;
 350             }
 351             break;
 352         }
 353         if (can_write) {
 354             d->config[addr] = val;
 355         }
 356         if (++addr > 0xff)
 357                 break;
 358         val >>= 8;
 359     }
 360
 361     end = address + len;
 362     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 363         /* if the command register is modified, we must modify the mappings */
 364         pci_update_mappings(d);
 365     }
 366 }
 367
 368 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 369 {
 370     PCIBus *s = opaque;
 371     PCIDevice *pci_dev;
 372     int config_addr, bus_num;
 373
 374 #if defined(DEBUG_PCI) && 0
 375     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 376            addr, val, len);
 377 #endif
 378     bus_num = (addr >> 16) & 0xff;
 379     while (s && s->bus_num != bus_num)
 380         s = s->next;
 381     if (!s)
 382         return;
 383     pci_dev = s->devices[(addr >> 8) & 0xff];
 384     if (!pci_dev)
 385         return;
 386     config_addr = addr & 0xff;
 387 #if defined(DEBUG_PCI)
 388     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 389            pci_dev->name, config_addr, val, len);
 390 #endif
 391     pci_dev->config_write(pci_dev, config_addr, val, len);
 392 }
 393
 394 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 395 {
 396     PCIBus *s = opaque;
 397     PCIDevice *pci_dev;
 398     int config_addr, bus_num;
 399     uint32_t val;
 400
 401     bus_num = (addr >> 16) & 0xff;
 402     while (s && s->bus_num != bus_num)
 403         s= s->next;
 404     if (!s)
 405         goto fail;
 406     pci_dev = s->devices[(addr >> 8) & 0xff];
 407     if (!pci_dev) {
 408     fail:
 409         switch(len) {
 410         case 1:
 411             val = 0xff;
 412             break;
 413         case 2:
 414             val = 0xffff;
 415             break;
 416         default:
 417         case 4:
 418             val = 0xffffffff;
 419             break;
 420         }
 421         goto the_end;
 422     }
 423     config_addr = addr & 0xff;
 424     val = pci_dev->config_read(pci_dev, config_addr, len);
 425 #if defined(DEBUG_PCI)
 426     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 427            pci_dev->name, config_addr, val, len);
 428 #endif
 429  the_end:
 430 #if defined(DEBUG_PCI) && 0
 431     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 432            addr, val, len);
 433 #endif
 434     return val;
 435 }
 436
 437 /***********************************************************/
 438 /* generic PCI irq support */
 439
 440 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 441 static void pci_set_irq(void *opaque, int irq_num, int level)
 442 {
 443     PCIDevice *pci_dev = (PCIDevice *)opaque;
 444     PCIBus *bus;
 445     int change;
 446
 447     change = level - pci_dev->irq_state[irq_num];
 448     if (!change)
 449         return;
 450
 451     pci_dev->irq_state[irq_num] = level;
 452     for (;;) {
 453         bus = pci_dev->bus;
 454         irq_num = bus->map_irq(pci_dev, irq_num);
 455         if (bus->set_irq)
 456             break;
 457         pci_dev = bus->parent_dev;
 458     }
 459     bus->irq_count[irq_num] += change;
 460     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 461 }
 462
 463 /***********************************************************/
 464 /* monitor info on PCI */
 465
 466 typedef struct {
 467     uint16_t class;
 468     const char *desc;
 469 } pci_class_desc;
 470
 471 static pci_class_desc pci_class_descriptions[] =
 472 {
 473     { 0x0100, "SCSI controller"},
 474     { 0x0101, "IDE controller"},
 475     { 0x0102, "Floppy controller"},
 476     { 0x0103, "IPI controller"},
 477     { 0x0104, "RAID controller"},
 478     { 0x0106, "SATA controller"},
 479     { 0x0107, "SAS controller"},
 480     { 0x0180, "Storage controller"},
 481     { 0x0200, "Ethernet controller"},
 482     { 0x0201, "Token Ring controller"},
 483     { 0x0202, "FDDI controller"},
 484     { 0x0203, "ATM controller"},
 485     { 0x0280, "Network controller"},
 486     { 0x0300, "VGA controller"},
 487     { 0x0301, "XGA controller"},
 488     { 0x0302, "3D controller"},
 489     { 0x0380, "Display controller"},
 490     { 0x0400, "Video controller"},
 491     { 0x0401, "Audio controller"},
 492     { 0x0402, "Phone"},
 493     { 0x0480, "Multimedia controller"},
 494     { 0x0500, "RAM controller"},
 495     { 0x0501, "Flash controller"},
 496     { 0x0580, "Memory controller"},
 497     { 0x0600, "Host bridge"},
 498     { 0x0601, "ISA bridge"},
 499     { 0x0602, "EISA bridge"},
 500     { 0x0603, "MC bridge"},
 501     { 0x0604, "PCI bridge"},
 502     { 0x0605, "PCMCIA bridge"},
 503     { 0x0606, "NUBUS bridge"},
 504     { 0x0607, "CARDBUS bridge"},
 505     { 0x0608, "RACEWAY bridge"},
 506     { 0x0680, "Bridge"},
 507     { 0x0c03, "USB controller"},
 508     { 0, NULL}
 509 };
 510
 511 static void pci_info_device(PCIDevice *d)
 512 {
 513     int i, class;
 514     PCIIORegion *r;
 515     pci_class_desc *desc;
 516
 517     term_printf("  Bus %2d, device %3d, function %d:\n",
 518            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 519     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 520     term_printf("    ");
 521     desc = pci_class_descriptions;
 522     while (desc->desc && class != desc->class)
 523         desc++;
 524     if (desc->desc) {
 525         term_printf("%s", desc->desc);
 526     } else {
 527         term_printf("Class %04x", class);
 528     }
 529     term_printf(": PCI device %04x:%04x\n",
 530            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 531            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 532
 533     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 534         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 535     }
 536     if (class == 0x0604) {
 537         term_printf("      BUS %d.\n", d->config[0x19]);
 538     }
 539     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 540         r = &d->io_regions[i];
 541         if (r->size != 0) {
 542             term_printf("      BAR%d: ", i);
 543             if (r->type & PCI_ADDRESS_SPACE_IO) {
 544                 term_printf("I/O at 0x%04x [0x%04x].\n",
 545                        r->addr, r->addr + r->size - 1);
 546             } else {
 547                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 548                        r->addr, r->addr + r->size - 1);
 549             }
 550         }
 551     }
 552     if (class == 0x0604 && d->config[0x19] != 0) {
 553         pci_for_each_device(d->config[0x19], pci_info_device);
 554     }
 555 }
 556
 557 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 558 {
 559     PCIBus *bus = first_bus;
 560     PCIDevice *d;
 561     int devfn;
 562
 563     while (bus && bus->bus_num != bus_num)
 564         bus = bus->next;
 565     if (bus) {
 566         for(devfn = 0; devfn < 256; devfn++) {
 567             d = bus->devices[devfn];
 568             if (d)
 569                 fn(d);
 570         }
 571     }
 572 }
 573
 574 void pci_info(void)
 575 {
 576     pci_for_each_device(0, pci_info_device);
 577 }
 578
 579 /* Initialize a PCI NIC.  */
 580 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
 581 {
 582     if (strcmp(nd->model, "ne2k_pci") == 0) {
 583         pci_ne2000_init(bus, nd, devfn);
 584     } else if (strcmp(nd->model, "i82551") == 0) {
 585         pci_i82551_init(bus, nd, devfn);
 586     } else if (strcmp(nd->model, "i82557b") == 0) {
 587         pci_i82557b_init(bus, nd, devfn);
 588     } else if (strcmp(nd->model, "i82559er") == 0) {
 589         pci_i82559er_init(bus, nd, devfn);
 590     } else if (strcmp(nd->model, "rtl8139") == 0) {
 591         pci_rtl8139_init(bus, nd, devfn);
 592     } else if (strcmp(nd->model, "pcnet") == 0) {
 593         pci_pcnet_init(bus, nd, devfn);
 594     } else if (strcmp(nd->model, "?") == 0) {
 595         fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
 596                         " ne2k_pci pcnet rtl8139\n");
 597         exit (1);
 598     } else {
 599         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 600         exit (1);
 601     }
 602 }
 603
 604 typedef struct {
 605     PCIDevice dev;
 606     PCIBus *bus;
 607 } PCIBridge;
 608
 609 static void pci_bridge_write_config(PCIDevice *d,
 610                              uint32_t address, uint32_t val, int len)
 611 {
 612     PCIBridge *s = (PCIBridge *)d;
 613
 614     if (address == 0x19 || (address == 0x18 && len > 1)) {
 615         if (address == 0x19)
 616             s->bus->bus_num = val & 0xff;
 617         else
 618             s->bus->bus_num = (val >> 8) & 0xff;
 619 #if defined(DEBUG_PCI)
 620         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 621 #endif
 622     }
 623     pci_default_write_config(d, address, val, len);
 624 }
 625
 626 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 627                         pci_map_irq_fn map_irq, const char *name)
 628 {
 629     PCIBridge *s;
 630     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 631                                          devfn, NULL, pci_bridge_write_config);
 632     s->dev.config[0x00] = id >> 16;
 633     s->dev.config[0x01] = id >> 24;
 634     s->dev.config[0x02] = id; // device_id
 635     s->dev.config[0x03] = id >> 8;
 636     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 637     s->dev.config[0x05] = 0x00;
 638     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 639     s->dev.config[0x07] = 0x00; // status = fast devsel
 640     s->dev.config[0x08] = 0x00; // revision
 641     s->dev.config[0x09] = 0x00; // programming i/f
 642     s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
 643     s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
 644     s->dev.config[0x0D] = 0x10; // latency_timer
 645     s->dev.config[0x0E] = 0x81; // header_type
 646     s->dev.config[0x1E] = 0xa0; // secondary status
 647
 648     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 649     return s->bus;
 650 }