hw/iommu.c

   1 /*
   2  * QEMU SPARC iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26
  27 /* debug iommu */
  28 //#define DEBUG_IOMMU
  29
  30 #ifdef DEBUG_IOMMU
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IOMMU: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 #define IOMMU_NREGS (3*4096/4)
  38 #define IOMMU_CTRL          (0x0000 >> 2)
  39 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  40 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  41 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  42 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  43 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  50 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  51 #define IOMMU_CTRL_MASK     0x0000001d
  52
  53 #define IOMMU_BASE          (0x0004 >> 2)
  54 #define IOMMU_BASE_MASK     0x07fffc00
  55
  56 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  58
  59 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  60 #define IOMMU_PGFLUSH_MASK  0xffffffff
  61
  62 #define IOMMU_AFSR          (0x1000 >> 2)
  63 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  64 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after transaction */
  65 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than 12.8 us. */
  66 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error acknowledge */
  67 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  68 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  69 #define IOMMU_AFSR_RESV     0x00f00000 /* Reserved, forced to 0x8 by hardware */
  70 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  71 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  72 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  73
  74 #define IOMMU_AFAR          (0x1004 >> 2)
  75
  76 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  77 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  78 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  79 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  80 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
  81 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
  82 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
  83 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
  84                                           produced by this device as pure
  85                                           physical. */
  86 #define IOMMU_SBCFG_MASK    0x00010003
  87
  88 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
  89 #define IOMMU_ARBEN_MASK    0x001f0000
  90 #define IOMMU_MID           0x00000008
  91
  92 /* The format of an iopte in the page tables */
  93 #define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
  94 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
  95 #define IOPTE_WRITE         0x00000004 /* Writeable */
  96 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
  97 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
  98
  99 #define PAGE_SHIFT      12
 100 #define PAGE_SIZE       (1 << PAGE_SHIFT)
 101 #define PAGE_MASK       (PAGE_SIZE - 1)
 102
 103 typedef struct IOMMUState {
 104     target_phys_addr_t addr;
 105     uint32_t regs[IOMMU_NREGS];
 106     target_phys_addr_t iostart;
 107     uint32_t version;
 108 } IOMMUState;
 109
 110 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
 111 {
 112     IOMMUState *s = opaque;
 113     target_phys_addr_t saddr;
 114
 115     saddr = (addr - s->addr) >> 2;
 116     switch (saddr) {
 117     default:
 118         DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
 119         return s->regs[saddr];
 120         break;
 121     }
 122     return 0;
 123 }
 124
 125 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 126 {
 127     IOMMUState *s = opaque;
 128     target_phys_addr_t saddr;
 129
 130     saddr = (addr - s->addr) >> 2;
 131     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
 132     switch (saddr) {
 133     case IOMMU_CTRL:
 134         switch (val & IOMMU_CTRL_RNGE) {
 135         case IOMMU_RNGE_16MB:
 136             s->iostart = 0xffffffffff000000ULL;
 137             break;
 138         case IOMMU_RNGE_32MB:
 139             s->iostart = 0xfffffffffe000000ULL;
 140             break;
 141         case IOMMU_RNGE_64MB:
 142             s->iostart = 0xfffffffffc000000ULL;
 143             break;
 144         case IOMMU_RNGE_128MB:
 145             s->iostart = 0xfffffffff8000000ULL;
 146             break;
 147         case IOMMU_RNGE_256MB:
 148             s->iostart = 0xfffffffff0000000ULL;
 149             break;
 150         case IOMMU_RNGE_512MB:
 151             s->iostart = 0xffffffffe0000000ULL;
 152             break;
 153         case IOMMU_RNGE_1GB:
 154             s->iostart = 0xffffffffc0000000ULL;
 155             break;
 156         default:
 157         case IOMMU_RNGE_2GB:
 158             s->iostart = 0xffffffff80000000ULL;
 159             break;
 160         }
 161         DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
 162         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 163         break;
 164     case IOMMU_BASE:
 165         s->regs[saddr] = val & IOMMU_BASE_MASK;
 166         break;
 167     case IOMMU_TLBFLUSH:
 168         DPRINTF("tlb flush %x\n", val);
 169         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 170         break;
 171     case IOMMU_PGFLUSH:
 172         DPRINTF("page flush %x\n", val);
 173         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 174         break;
 175     case IOMMU_SBCFG0:
 176     case IOMMU_SBCFG1:
 177     case IOMMU_SBCFG2:
 178     case IOMMU_SBCFG3:
 179         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 180         break;
 181     case IOMMU_ARBEN:
 182         // XXX implement SBus probing: fault when reading unmapped
 183         // addresses, fault cause and address stored to MMU/IOMMU
 184         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 185         break;
 186     default:
 187         s->regs[saddr] = val;
 188         break;
 189     }
 190 }
 191
 192 static CPUReadMemoryFunc *iommu_mem_read[3] = {
 193     iommu_mem_readw,
 194     iommu_mem_readw,
 195     iommu_mem_readw,
 196 };
 197
 198 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 199     iommu_mem_writew,
 200     iommu_mem_writew,
 201     iommu_mem_writew,
 202 };
 203
 204 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 205 {
 206     uint32_t ret;
 207     target_phys_addr_t iopte;
 208 #ifdef DEBUG_IOMMU
 209     target_phys_addr_t pa = addr;
 210 #endif
 211
 212     iopte = s->regs[IOMMU_BASE] << 4;
 213     addr &= ~s->iostart;
 214     iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
 215     cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
 216     tswap32s(&ret);
 217     DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
 218             ", *pte = %x\n", pa, iopte, ret);
 219
 220     return ret;
 221 }
 222
 223 static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
 224                                              target_phys_addr_t addr,
 225                                              uint32_t pte)
 226 {
 227     uint32_t tmppte;
 228     target_phys_addr_t pa;
 229
 230     tmppte = pte;
 231     pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
 232     DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
 233             " (iopte = %x)\n", addr, pa, tmppte);
 234
 235     return pa;
 236 }
 237
 238 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
 239 {
 240     DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
 241     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
 242         IOMMU_AFSR_FAV;
 243     if (!is_write)
 244         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 245     s->regs[IOMMU_AFAR] = addr;
 246 }
 247
 248 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
 249                            uint8_t *buf, int len, int is_write)
 250 {
 251     int l;
 252     uint32_t flags;
 253     target_phys_addr_t page, phys_addr;
 254
 255     while (len > 0) {
 256         page = addr & TARGET_PAGE_MASK;
 257         l = (page + TARGET_PAGE_SIZE) - addr;
 258         if (l > len)
 259             l = len;
 260         flags = iommu_page_get_flags(opaque, page);
 261         if (!(flags & IOPTE_VALID)) {
 262             iommu_bad_addr(opaque, page, is_write);
 263             return;
 264         }
 265         phys_addr = iommu_translate_pa(opaque, addr, flags);
 266         if (is_write) {
 267             if (!(flags & IOPTE_WRITE)) {
 268                 iommu_bad_addr(opaque, page, is_write);
 269                 return;
 270             }
 271             cpu_physical_memory_write(phys_addr, buf, len);
 272         } else {
 273             cpu_physical_memory_read(phys_addr, buf, len);
 274         }
 275         len -= l;
 276         buf += l;
 277         addr += l;
 278     }
 279 }
 280
 281 static void iommu_save(QEMUFile *f, void *opaque)
 282 {
 283     IOMMUState *s = opaque;
 284     int i;
 285
 286     for (i = 0; i < IOMMU_NREGS; i++)
 287         qemu_put_be32s(f, &s->regs[i]);
 288     qemu_put_be64s(f, &s->iostart);
 289 }
 290
 291 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 292 {
 293     IOMMUState *s = opaque;
 294     int i;
 295
 296     if (version_id != 2)
 297         return -EINVAL;
 298
 299     for (i = 0; i < IOMMU_NREGS; i++)
 300         qemu_get_be32s(f, &s->regs[i]);
 301     qemu_get_be64s(f, &s->iostart);
 302
 303     return 0;
 304 }
 305
 306 static void iommu_reset(void *opaque)
 307 {
 308     IOMMUState *s = opaque;
 309
 310     memset(s->regs, 0, IOMMU_NREGS * 4);
 311     s->iostart = 0;
 312     s->regs[IOMMU_CTRL] = s->version;
 313     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 314 }
 315
 316 void *iommu_init(target_phys_addr_t addr, uint32_t version)
 317 {
 318     IOMMUState *s;
 319     int iommu_io_memory;
 320
 321     s = qemu_mallocz(sizeof(IOMMUState));
 322     if (!s)
 323         return NULL;
 324
 325     s->addr = addr;
 326     s->version = version;
 327
 328     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
 329     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
 330
 331     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
 332     qemu_register_reset(iommu_reset, s);
 333     iommu_reset(s);
 334     return s;
 335 }
 336