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configure: also switch ppc64abi32 and ppcemb to CONFIG_SOFTFLOAT
[qemu/mini2440.git] / target-arm / translate.c
blob0650bc3a21693e1b0b4ceaf6446c5b7a5aa70e90
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <stdarg.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <string.h>
26 #include <inttypes.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "disas.h"
31 #include "tcg-op.h"
32 #include "qemu-log.h"
33
34 #include "helpers.h"
35 #define GEN_HELPER 1
36 #include "helpers.h"
37
38 #define ENABLE_ARCH_5J 0
39 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
40 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
41 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
42 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
43
44 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
45
46 /* internal defines */
47 typedef struct DisasContext {
48 target_ulong pc;
49 int is_jmp;
50 /* Nonzero if this instruction has been conditionally skipped. */
51 int condjmp;
52 /* The label that will be jumped to when the instruction is skipped. */
53 int condlabel;
54 /* Thumb-2 condtional execution bits. */
55 int condexec_mask;
56 int condexec_cond;
57 struct TranslationBlock *tb;
58 int singlestep_enabled;
59 int thumb;
60 #if !defined(CONFIG_USER_ONLY)
61 int user;
62 #endif
63 } DisasContext;
64
65 #if defined(CONFIG_USER_ONLY)
66 #define IS_USER(s) 1
67 #else
68 #define IS_USER(s) (s->user)
69 #endif
70
71 /* These instructions trap after executing, so defer them until after the
72 conditional executions state has been updated. */
73 #define DISAS_WFI 4
74 #define DISAS_SWI 5
75
76 static TCGv_ptr cpu_env;
77 /* We reuse the same 64-bit temporaries for efficiency. */
78 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
79
80 /* FIXME: These should be removed. */
81 static TCGv cpu_T[2];
82 static TCGv cpu_F0s, cpu_F1s;
83 static TCGv_i64 cpu_F0d, cpu_F1d;
84
85 #define ICOUNT_TEMP cpu_T[0]
86 #include "gen-icount.h"
87
88 /* initialize TCG globals. */
89 void arm_translate_init(void)
90 {
91 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
92
93 cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0");
94 cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1");
95
96 #define GEN_HELPER 2
97 #include "helpers.h"
98 }
99
100 /* The code generator doesn't like lots of temporaries, so maintain our own
101 cache for reuse within a function. */
102 #define MAX_TEMPS 8
103 static int num_temps;
104 static TCGv temps[MAX_TEMPS];
105
106 /* Allocate a temporary variable. */
107 static TCGv_i32 new_tmp(void)
108 {
109 TCGv tmp;
110 if (num_temps == MAX_TEMPS)
111 abort();
112
113 if (GET_TCGV_I32(temps[num_temps]))
114 return temps[num_temps++];
115
116 tmp = tcg_temp_new_i32();
117 temps[num_temps++] = tmp;
118 return tmp;
119 }
120
121 /* Release a temporary variable. */
122 static void dead_tmp(TCGv tmp)
123 {
124 int i;
125 num_temps--;
126 i = num_temps;
127 if (TCGV_EQUAL(temps[i], tmp))
128 return;
129
130 /* Shuffle this temp to the last slot. */
131 while (!TCGV_EQUAL(temps[i], tmp))
132 i--;
133 while (i < num_temps) {
134 temps[i] = temps[i + 1];
135 i++;
136 }
137 temps[i] = tmp;
138 }
139
140 static inline TCGv load_cpu_offset(int offset)
141 {
142 TCGv tmp = new_tmp();
143 tcg_gen_ld_i32(tmp, cpu_env, offset);
144 return tmp;
145 }
146
147 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
148
149 static inline void store_cpu_offset(TCGv var, int offset)
150 {
151 tcg_gen_st_i32(var, cpu_env, offset);
152 dead_tmp(var);
153 }
154
155 #define store_cpu_field(var, name) \
156 store_cpu_offset(var, offsetof(CPUState, name))
157
158 /* Set a variable to the value of a CPU register. */
159 static void load_reg_var(DisasContext *s, TCGv var, int reg)
160 {
161 if (reg == 15) {
162 uint32_t addr;
163 /* normaly, since we updated PC, we need only to add one insn */
164 if (s->thumb)
165 addr = (long)s->pc + 2;
166 else
167 addr = (long)s->pc + 4;
168 tcg_gen_movi_i32(var, addr);
169 } else {
170 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
171 }
172 }
173
174 /* Create a new temporary and set it to the value of a CPU register. */
175 static inline TCGv load_reg(DisasContext *s, int reg)
176 {
177 TCGv tmp = new_tmp();
178 load_reg_var(s, tmp, reg);
179 return tmp;
180 }
181
182 /* Set a CPU register. The source must be a temporary and will be
183 marked as dead. */
184 static void store_reg(DisasContext *s, int reg, TCGv var)
185 {
186 if (reg == 15) {
187 tcg_gen_andi_i32(var, var, ~1);
188 s->is_jmp = DISAS_JUMP;
189 }
190 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
191 dead_tmp(var);
192 }
193
194
195 /* Basic operations. */
196 #define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1])
197 #define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im)
198 #define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)
199
200 #define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im)
201 #define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1])
202 #define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1])
203 #define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0])
204
205 #define gen_op_addl_T0_T1_cc() gen_helper_add_cc(cpu_T[0], cpu_T[0], cpu_T[1])
206 #define gen_op_adcl_T0_T1_cc() gen_helper_adc_cc(cpu_T[0], cpu_T[0], cpu_T[1])
207 #define gen_op_subl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1])
208 #define gen_op_sbcl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[0], cpu_T[1])
209 #define gen_op_rsbl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[1], cpu_T[0])
210 #define gen_op_rscl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[1], cpu_T[0])
211
212 #define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1])
213 #define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1])
214 #define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1])
215 #define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0])
216 #define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1])
217 #define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);
218 #define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);
219
220 #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)
221 #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)
222
223 /* Value extensions. */
224 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
225 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
226 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
227 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
228
229 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
230 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
231
232 #define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1])
233
234 #define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask))
235 /* Set NZCV flags from the high 4 bits of var. */
236 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
237
238 static void gen_exception(int excp)
239 {
240 TCGv tmp = new_tmp();
241 tcg_gen_movi_i32(tmp, excp);
242 gen_helper_exception(tmp);
243 dead_tmp(tmp);
244 }
245
246 static void gen_smul_dual(TCGv a, TCGv b)
247 {
248 TCGv tmp1 = new_tmp();
249 TCGv tmp2 = new_tmp();
250 tcg_gen_ext16s_i32(tmp1, a);
251 tcg_gen_ext16s_i32(tmp2, b);
252 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
253 dead_tmp(tmp2);
254 tcg_gen_sari_i32(a, a, 16);
255 tcg_gen_sari_i32(b, b, 16);
256 tcg_gen_mul_i32(b, b, a);
257 tcg_gen_mov_i32(a, tmp1);
258 dead_tmp(tmp1);
259 }
260
261 /* Byteswap each halfword. */
262 static void gen_rev16(TCGv var)
263 {
264 TCGv tmp = new_tmp();
265 tcg_gen_shri_i32(tmp, var, 8);
266 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
267 tcg_gen_shli_i32(var, var, 8);
268 tcg_gen_andi_i32(var, var, 0xff00ff00);
269 tcg_gen_or_i32(var, var, tmp);
270 dead_tmp(tmp);
271 }
272
273 /* Byteswap low halfword and sign extend. */
274 static void gen_revsh(TCGv var)
275 {
276 TCGv tmp = new_tmp();
277 tcg_gen_shri_i32(tmp, var, 8);
278 tcg_gen_andi_i32(tmp, tmp, 0x00ff);
279 tcg_gen_shli_i32(var, var, 8);
280 tcg_gen_ext8s_i32(var, var);
281 tcg_gen_or_i32(var, var, tmp);
282 dead_tmp(tmp);
283 }
284
285 /* Unsigned bitfield extract. */
286 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
287 {
288 if (shift)
289 tcg_gen_shri_i32(var, var, shift);
290 tcg_gen_andi_i32(var, var, mask);
291 }
292
293 /* Signed bitfield extract. */
294 static void gen_sbfx(TCGv var, int shift, int width)
295 {
296 uint32_t signbit;
297
298 if (shift)
299 tcg_gen_sari_i32(var, var, shift);
300 if (shift + width < 32) {
301 signbit = 1u << (width - 1);
302 tcg_gen_andi_i32(var, var, (1u << width) - 1);
303 tcg_gen_xori_i32(var, var, signbit);
304 tcg_gen_subi_i32(var, var, signbit);
305 }
306 }
307
308 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
309 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
310 {
311 tcg_gen_andi_i32(val, val, mask);
312 tcg_gen_shli_i32(val, val, shift);
313 tcg_gen_andi_i32(base, base, ~(mask << shift));
314 tcg_gen_or_i32(dest, base, val);
315 }
316
317 /* Round the top 32 bits of a 64-bit value. */
318 static void gen_roundqd(TCGv a, TCGv b)
319 {
320 tcg_gen_shri_i32(a, a, 31);
321 tcg_gen_add_i32(a, a, b);
322 }
323
324 /* FIXME: Most targets have native widening multiplication.
325 It would be good to use that instead of a full wide multiply. */
326 /* 32x32->64 multiply. Marks inputs as dead. */
327 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
328 {
329 TCGv_i64 tmp1 = tcg_temp_new_i64();
330 TCGv_i64 tmp2 = tcg_temp_new_i64();
331
332 tcg_gen_extu_i32_i64(tmp1, a);
333 dead_tmp(a);
334 tcg_gen_extu_i32_i64(tmp2, b);
335 dead_tmp(b);
336 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
337 return tmp1;
338 }
339
340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
341 {
342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 return tmp1;
351 }
352
353 /* Unsigned 32x32->64 multiply. */
354 static void gen_op_mull_T0_T1(void)
355 {
356 TCGv_i64 tmp1 = tcg_temp_new_i64();
357 TCGv_i64 tmp2 = tcg_temp_new_i64();
358
359 tcg_gen_extu_i32_i64(tmp1, cpu_T[0]);
360 tcg_gen_extu_i32_i64(tmp2, cpu_T[1]);
361 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
362 tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);
363 tcg_gen_shri_i64(tmp1, tmp1, 32);
364 tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);
365 }
366
367 /* Signed 32x32->64 multiply. */
368 static void gen_imull(TCGv a, TCGv b)
369 {
370 TCGv_i64 tmp1 = tcg_temp_new_i64();
371 TCGv_i64 tmp2 = tcg_temp_new_i64();
372
373 tcg_gen_ext_i32_i64(tmp1, a);
374 tcg_gen_ext_i32_i64(tmp2, b);
375 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
376 tcg_gen_trunc_i64_i32(a, tmp1);
377 tcg_gen_shri_i64(tmp1, tmp1, 32);
378 tcg_gen_trunc_i64_i32(b, tmp1);
379 }
380
381 /* Swap low and high halfwords. */
382 static void gen_swap_half(TCGv var)
383 {
384 TCGv tmp = new_tmp();
385 tcg_gen_shri_i32(tmp, var, 16);
386 tcg_gen_shli_i32(var, var, 16);
387 tcg_gen_or_i32(var, var, tmp);
388 dead_tmp(tmp);
389 }
390
391 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
392 tmp = (t0 ^ t1) & 0x8000;
393 t0 &= ~0x8000;
394 t1 &= ~0x8000;
395 t0 = (t0 + t1) ^ tmp;
396 */
397
398 static void gen_add16(TCGv t0, TCGv t1)
399 {
400 TCGv tmp = new_tmp();
401 tcg_gen_xor_i32(tmp, t0, t1);
402 tcg_gen_andi_i32(tmp, tmp, 0x8000);
403 tcg_gen_andi_i32(t0, t0, ~0x8000);
404 tcg_gen_andi_i32(t1, t1, ~0x8000);
405 tcg_gen_add_i32(t0, t0, t1);
406 tcg_gen_xor_i32(t0, t0, tmp);
407 dead_tmp(tmp);
408 dead_tmp(t1);
409 }
410
411 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
412
413 /* Set CF to the top bit of var. */
414 static void gen_set_CF_bit31(TCGv var)
415 {
416 TCGv tmp = new_tmp();
417 tcg_gen_shri_i32(tmp, var, 31);
418 gen_set_CF(tmp);
419 dead_tmp(tmp);
420 }
421
422 /* Set N and Z flags from var. */
423 static inline void gen_logic_CC(TCGv var)
424 {
425 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
426 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
427 }
428
429 /* T0 += T1 + CF. */
430 static void gen_adc_T0_T1(void)
431 {
432 TCGv tmp;
433 gen_op_addl_T0_T1();
434 tmp = load_cpu_field(CF);
435 tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp);
436 dead_tmp(tmp);
437 }
438
439 /* dest = T0 - T1 + CF - 1. */
440 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
441 {
442 TCGv tmp;
443 tcg_gen_sub_i32(dest, t0, t1);
444 tmp = load_cpu_field(CF);
445 tcg_gen_add_i32(dest, dest, tmp);
446 tcg_gen_subi_i32(dest, dest, 1);
447 dead_tmp(tmp);
448 }
449
450 #define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1])
451 #define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0])
452
453 /* T0 &= ~T1. Clobbers T1. */
454 /* FIXME: Implement bic natively. */
455 static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
456 {
457 TCGv tmp = new_tmp();
458 tcg_gen_not_i32(tmp, t1);
459 tcg_gen_and_i32(dest, t0, tmp);
460 dead_tmp(tmp);
461 }
462 static inline void gen_op_bicl_T0_T1(void)
463 {
464 gen_op_notl_T1();
465 gen_op_andl_T0_T1();
466 }
467
468 /* FIXME: Implement this natively. */
469 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
470
471 /* FIXME: Implement this natively. */
472 static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i)
473 {
474 TCGv tmp;
475
476 if (i == 0)
477 return;
478
479 tmp = new_tmp();
480 tcg_gen_shri_i32(tmp, t1, i);
481 tcg_gen_shli_i32(t1, t1, 32 - i);
482 tcg_gen_or_i32(t0, t1, tmp);
483 dead_tmp(tmp);
484 }
485
486 static void shifter_out_im(TCGv var, int shift)
487 {
488 TCGv tmp = new_tmp();
489 if (shift == 0) {
490 tcg_gen_andi_i32(tmp, var, 1);
491 } else {
492 tcg_gen_shri_i32(tmp, var, shift);
493 if (shift != 31)
494 tcg_gen_andi_i32(tmp, tmp, 1);
495 }
496 gen_set_CF(tmp);
497 dead_tmp(tmp);
498 }
499
500 /* Shift by immediate. Includes special handling for shift == 0. */
501 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
502 {
503 switch (shiftop) {
504 case 0: /* LSL */
505 if (shift != 0) {
506 if (flags)
507 shifter_out_im(var, 32 - shift);
508 tcg_gen_shli_i32(var, var, shift);
509 }
510 break;
511 case 1: /* LSR */
512 if (shift == 0) {
513 if (flags) {
514 tcg_gen_shri_i32(var, var, 31);
515 gen_set_CF(var);
516 }
517 tcg_gen_movi_i32(var, 0);
518 } else {
519 if (flags)
520 shifter_out_im(var, shift - 1);
521 tcg_gen_shri_i32(var, var, shift);
522 }
523 break;
524 case 2: /* ASR */
525 if (shift == 0)
526 shift = 32;
527 if (flags)
528 shifter_out_im(var, shift - 1);
529 if (shift == 32)
530 shift = 31;
531 tcg_gen_sari_i32(var, var, shift);
532 break;
533 case 3: /* ROR/RRX */
534 if (shift != 0) {
535 if (flags)
536 shifter_out_im(var, shift - 1);
537 tcg_gen_rori_i32(var, var, shift); break;
538 } else {
539 TCGv tmp = load_cpu_field(CF);
540 if (flags)
541 shifter_out_im(var, 0);
542 tcg_gen_shri_i32(var, var, 1);
543 tcg_gen_shli_i32(tmp, tmp, 31);
544 tcg_gen_or_i32(var, var, tmp);
545 dead_tmp(tmp);
546 }
547 }
548 };
549
550 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
551 TCGv shift, int flags)
552 {
553 if (flags) {
554 switch (shiftop) {
555 case 0: gen_helper_shl_cc(var, var, shift); break;
556 case 1: gen_helper_shr_cc(var, var, shift); break;
557 case 2: gen_helper_sar_cc(var, var, shift); break;
558 case 3: gen_helper_ror_cc(var, var, shift); break;
559 }
560 } else {
561 switch (shiftop) {
562 case 0: gen_helper_shl(var, var, shift); break;
563 case 1: gen_helper_shr(var, var, shift); break;
564 case 2: gen_helper_sar(var, var, shift); break;
565 case 3: gen_helper_ror(var, var, shift); break;
566 }
567 }
568 dead_tmp(shift);
569 }
570
571 #define PAS_OP(pfx) \
572 switch (op2) { \
573 case 0: gen_pas_helper(glue(pfx,add16)); break; \
574 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
575 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
576 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
577 case 4: gen_pas_helper(glue(pfx,add8)); break; \
578 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
579 }
580 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
581 {
582 TCGv_ptr tmp;
583
584 switch (op1) {
585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
586 case 1:
587 tmp = tcg_temp_new_ptr();
588 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
589 PAS_OP(s)
590 break;
591 case 5:
592 tmp = tcg_temp_new_ptr();
593 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
594 PAS_OP(u)
595 break;
596 #undef gen_pas_helper
597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 2:
599 PAS_OP(q);
600 break;
601 case 3:
602 PAS_OP(sh);
603 break;
604 case 6:
605 PAS_OP(uq);
606 break;
607 case 7:
608 PAS_OP(uh);
609 break;
610 #undef gen_pas_helper
611 }
612 }
613 #undef PAS_OP
614
615 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
616 #define PAS_OP(pfx) \
617 switch (op2) { \
618 case 0: gen_pas_helper(glue(pfx,add8)); break; \
619 case 1: gen_pas_helper(glue(pfx,add16)); break; \
620 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
621 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
622 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
623 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
624 }
625 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
626 {
627 TCGv_ptr tmp;
628
629 switch (op1) {
630 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
631 case 0:
632 tmp = tcg_temp_new_ptr();
633 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
634 PAS_OP(s)
635 break;
636 case 4:
637 tmp = tcg_temp_new_ptr();
638 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
639 PAS_OP(u)
640 break;
641 #undef gen_pas_helper
642 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
643 case 1:
644 PAS_OP(q);
645 break;
646 case 2:
647 PAS_OP(sh);
648 break;
649 case 5:
650 PAS_OP(uq);
651 break;
652 case 6:
653 PAS_OP(uh);
654 break;
655 #undef gen_pas_helper
656 }
657 }
658 #undef PAS_OP
659
660 static void gen_test_cc(int cc, int label)
661 {
662 TCGv tmp;
663 TCGv tmp2;
664 int inv;
665
666 switch (cc) {
667 case 0: /* eq: Z */
668 tmp = load_cpu_field(ZF);
669 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
670 break;
671 case 1: /* ne: !Z */
672 tmp = load_cpu_field(ZF);
673 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
674 break;
675 case 2: /* cs: C */
676 tmp = load_cpu_field(CF);
677 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
678 break;
679 case 3: /* cc: !C */
680 tmp = load_cpu_field(CF);
681 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
682 break;
683 case 4: /* mi: N */
684 tmp = load_cpu_field(NF);
685 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
686 break;
687 case 5: /* pl: !N */
688 tmp = load_cpu_field(NF);
689 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
690 break;
691 case 6: /* vs: V */
692 tmp = load_cpu_field(VF);
693 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
694 break;
695 case 7: /* vc: !V */
696 tmp = load_cpu_field(VF);
697 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
698 break;
699 case 8: /* hi: C && !Z */
700 inv = gen_new_label();
701 tmp = load_cpu_field(CF);
702 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
703 dead_tmp(tmp);
704 tmp = load_cpu_field(ZF);
705 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
706 gen_set_label(inv);
707 break;
708 case 9: /* ls: !C || Z */
709 tmp = load_cpu_field(CF);
710 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
711 dead_tmp(tmp);
712 tmp = load_cpu_field(ZF);
713 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
714 break;
715 case 10: /* ge: N == V -> N ^ V == 0 */
716 tmp = load_cpu_field(VF);
717 tmp2 = load_cpu_field(NF);
718 tcg_gen_xor_i32(tmp, tmp, tmp2);
719 dead_tmp(tmp2);
720 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
721 break;
722 case 11: /* lt: N != V -> N ^ V != 0 */
723 tmp = load_cpu_field(VF);
724 tmp2 = load_cpu_field(NF);
725 tcg_gen_xor_i32(tmp, tmp, tmp2);
726 dead_tmp(tmp2);
727 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
728 break;
729 case 12: /* gt: !Z && N == V */
730 inv = gen_new_label();
731 tmp = load_cpu_field(ZF);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
733 dead_tmp(tmp);
734 tmp = load_cpu_field(VF);
735 tmp2 = load_cpu_field(NF);
736 tcg_gen_xor_i32(tmp, tmp, tmp2);
737 dead_tmp(tmp2);
738 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
739 gen_set_label(inv);
740 break;
741 case 13: /* le: Z || N != V */
742 tmp = load_cpu_field(ZF);
743 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
744 dead_tmp(tmp);
745 tmp = load_cpu_field(VF);
746 tmp2 = load_cpu_field(NF);
747 tcg_gen_xor_i32(tmp, tmp, tmp2);
748 dead_tmp(tmp2);
749 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
750 break;
751 default:
752 fprintf(stderr, "Bad condition code 0x%x\n", cc);
753 abort();
754 }
755 dead_tmp(tmp);
756 }
757
758 static const uint8_t table_logic_cc[16] = {
759 1, /* and */
760 1, /* xor */
761 0, /* sub */
762 0, /* rsb */
763 0, /* add */
764 0, /* adc */
765 0, /* sbc */
766 0, /* rsc */
767 1, /* andl */
768 1, /* xorl */
769 0, /* cmp */
770 0, /* cmn */
771 1, /* orr */
772 1, /* mov */
773 1, /* bic */
774 1, /* mvn */
775 };
776
777 /* Set PC and Thumb state from an immediate address. */
778 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
779 {
780 TCGv tmp;
781
782 s->is_jmp = DISAS_UPDATE;
783 tmp = new_tmp();
784 if (s->thumb != (addr & 1)) {
785 tcg_gen_movi_i32(tmp, addr & 1);
786 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
787 }
788 tcg_gen_movi_i32(tmp, addr & ~1);
789 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15]));
790 dead_tmp(tmp);
791 }
792
793 /* Set PC and Thumb state from var. var is marked as dead. */
794 static inline void gen_bx(DisasContext *s, TCGv var)
795 {
796 TCGv tmp;
797
798 s->is_jmp = DISAS_UPDATE;
799 tmp = new_tmp();
800 tcg_gen_andi_i32(tmp, var, 1);
801 store_cpu_field(tmp, thumb);
802 tcg_gen_andi_i32(var, var, ~1);
803 store_cpu_field(var, regs[15]);
804 }
805
806 /* TODO: This should be removed. Use gen_bx instead. */
807 static inline void gen_bx_T0(DisasContext *s)
808 {
809 TCGv tmp = new_tmp();
810 tcg_gen_mov_i32(tmp, cpu_T[0]);
811 gen_bx(s, tmp);
812 }
813
814 static inline TCGv gen_ld8s(TCGv addr, int index)
815 {
816 TCGv tmp = new_tmp();
817 tcg_gen_qemu_ld8s(tmp, addr, index);
818 return tmp;
819 }
820 static inline TCGv gen_ld8u(TCGv addr, int index)
821 {
822 TCGv tmp = new_tmp();
823 tcg_gen_qemu_ld8u(tmp, addr, index);
824 return tmp;
825 }
826 static inline TCGv gen_ld16s(TCGv addr, int index)
827 {
828 TCGv tmp = new_tmp();
829 tcg_gen_qemu_ld16s(tmp, addr, index);
830 return tmp;
831 }
832 static inline TCGv gen_ld16u(TCGv addr, int index)
833 {
834 TCGv tmp = new_tmp();
835 tcg_gen_qemu_ld16u(tmp, addr, index);
836 return tmp;
837 }
838 static inline TCGv gen_ld32(TCGv addr, int index)
839 {
840 TCGv tmp = new_tmp();
841 tcg_gen_qemu_ld32u(tmp, addr, index);
842 return tmp;
843 }
844 static inline void gen_st8(TCGv val, TCGv addr, int index)
845 {
846 tcg_gen_qemu_st8(val, addr, index);
847 dead_tmp(val);
848 }
849 static inline void gen_st16(TCGv val, TCGv addr, int index)
850 {
851 tcg_gen_qemu_st16(val, addr, index);
852 dead_tmp(val);
853 }
854 static inline void gen_st32(TCGv val, TCGv addr, int index)
855 {
856 tcg_gen_qemu_st32(val, addr, index);
857 dead_tmp(val);
858 }
859
860 static inline void gen_movl_T0_reg(DisasContext *s, int reg)
861 {
862 load_reg_var(s, cpu_T[0], reg);
863 }
864
865 static inline void gen_movl_T1_reg(DisasContext *s, int reg)
866 {
867 load_reg_var(s, cpu_T[1], reg);
868 }
869
870 static inline void gen_movl_T2_reg(DisasContext *s, int reg)
871 {
872 load_reg_var(s, cpu_T[2], reg);
873 }
874
875 static inline void gen_set_pc_im(uint32_t val)
876 {
877 TCGv tmp = new_tmp();
878 tcg_gen_movi_i32(tmp, val);
879 store_cpu_field(tmp, regs[15]);
880 }
881
882 static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)
883 {
884 TCGv tmp;
885 if (reg == 15) {
886 tmp = new_tmp();
887 tcg_gen_andi_i32(tmp, cpu_T[t], ~1);
888 } else {
889 tmp = cpu_T[t];
890 }
891 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg]));
892 if (reg == 15) {
893 dead_tmp(tmp);
894 s->is_jmp = DISAS_JUMP;
895 }
896 }
897
898 static inline void gen_movl_reg_T0(DisasContext *s, int reg)
899 {
900 gen_movl_reg_TN(s, reg, 0);
901 }
902
903 static inline void gen_movl_reg_T1(DisasContext *s, int reg)
904 {
905 gen_movl_reg_TN(s, reg, 1);
906 }
907
908 /* Force a TB lookup after an instruction that changes the CPU state. */
909 static inline void gen_lookup_tb(DisasContext *s)
910 {
911 gen_op_movl_T0_im(s->pc);
912 gen_movl_reg_T0(s, 15);
913 s->is_jmp = DISAS_UPDATE;
914 }
915
916 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
917 TCGv var)
918 {
919 int val, rm, shift, shiftop;
920 TCGv offset;
921
922 if (!(insn & (1 << 25))) {
923 /* immediate */
924 val = insn & 0xfff;
925 if (!(insn & (1 << 23)))
926 val = -val;
927 if (val != 0)
928 tcg_gen_addi_i32(var, var, val);
929 } else {
930 /* shift/register */
931 rm = (insn) & 0xf;
932 shift = (insn >> 7) & 0x1f;
933 shiftop = (insn >> 5) & 3;
934 offset = load_reg(s, rm);
935 gen_arm_shift_im(offset, shiftop, shift, 0);
936 if (!(insn & (1 << 23)))
937 tcg_gen_sub_i32(var, var, offset);
938 else
939 tcg_gen_add_i32(var, var, offset);
940 dead_tmp(offset);
941 }
942 }
943
944 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
945 int extra, TCGv var)
946 {
947 int val, rm;
948 TCGv offset;
949
950 if (insn & (1 << 22)) {
951 /* immediate */
952 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
953 if (!(insn & (1 << 23)))
954 val = -val;
955 val += extra;
956 if (val != 0)
957 tcg_gen_addi_i32(var, var, val);
958 } else {
959 /* register */
960 if (extra)
961 tcg_gen_addi_i32(var, var, extra);
962 rm = (insn) & 0xf;
963 offset = load_reg(s, rm);
964 if (!(insn & (1 << 23)))
965 tcg_gen_sub_i32(var, var, offset);
966 else
967 tcg_gen_add_i32(var, var, offset);
968 dead_tmp(offset);
969 }
970 }
971
972 #define VFP_OP2(name) \
973 static inline void gen_vfp_##name(int dp) \
974 { \
975 if (dp) \
976 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
977 else \
978 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
979 }
980
981 VFP_OP2(add)
982 VFP_OP2(sub)
983 VFP_OP2(mul)
984 VFP_OP2(div)
985
986 #undef VFP_OP2
987
988 static inline void gen_vfp_abs(int dp)
989 {
990 if (dp)
991 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
992 else
993 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
994 }
995
996 static inline void gen_vfp_neg(int dp)
997 {
998 if (dp)
999 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
1000 else
1001 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
1002 }
1003
1004 static inline void gen_vfp_sqrt(int dp)
1005 {
1006 if (dp)
1007 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
1008 else
1009 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
1010 }
1011
1012 static inline void gen_vfp_cmp(int dp)
1013 {
1014 if (dp)
1015 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
1016 else
1017 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
1018 }
1019
1020 static inline void gen_vfp_cmpe(int dp)
1021 {
1022 if (dp)
1023 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
1024 else
1025 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
1026 }
1027
1028 static inline void gen_vfp_F1_ld0(int dp)
1029 {
1030 if (dp)
1031 tcg_gen_movi_i64(cpu_F1d, 0);
1032 else
1033 tcg_gen_movi_i32(cpu_F1s, 0);
1034 }
1035
1036 static inline void gen_vfp_uito(int dp)
1037 {
1038 if (dp)
1039 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
1040 else
1041 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
1042 }
1043
1044 static inline void gen_vfp_sito(int dp)
1045 {
1046 if (dp)
1047 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
1048 else
1049 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
1050 }
1051
1052 static inline void gen_vfp_toui(int dp)
1053 {
1054 if (dp)
1055 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
1056 else
1057 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
1058 }
1059
1060 static inline void gen_vfp_touiz(int dp)
1061 {
1062 if (dp)
1063 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
1064 else
1065 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
1066 }
1067
1068 static inline void gen_vfp_tosi(int dp)
1069 {
1070 if (dp)
1071 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
1072 else
1073 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
1074 }
1075
1076 static inline void gen_vfp_tosiz(int dp)
1077 {
1078 if (dp)
1079 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1080 else
1081 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1082 }
1083
1084 #define VFP_GEN_FIX(name) \
1085 static inline void gen_vfp_##name(int dp, int shift) \
1086 { \
1087 if (dp) \
1088 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tcg_const_i32(shift), cpu_env);\
1089 else \
1090 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tcg_const_i32(shift), cpu_env);\
1091 }
1092 VFP_GEN_FIX(tosh)
1093 VFP_GEN_FIX(tosl)
1094 VFP_GEN_FIX(touh)
1095 VFP_GEN_FIX(toul)
1096 VFP_GEN_FIX(shto)
1097 VFP_GEN_FIX(slto)
1098 VFP_GEN_FIX(uhto)
1099 VFP_GEN_FIX(ulto)
1100 #undef VFP_GEN_FIX
1101
1102 static inline void gen_vfp_ld(DisasContext *s, int dp)
1103 {
1104 if (dp)
1105 tcg_gen_qemu_ld64(cpu_F0d, cpu_T[1], IS_USER(s));
1106 else
1107 tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s));
1108 }
1109
1110 static inline void gen_vfp_st(DisasContext *s, int dp)
1111 {
1112 if (dp)
1113 tcg_gen_qemu_st64(cpu_F0d, cpu_T[1], IS_USER(s));
1114 else
1115 tcg_gen_qemu_st32(cpu_F0s, cpu_T[1], IS_USER(s));
1116 }
1117
1118 static inline long
1119 vfp_reg_offset (int dp, int reg)
1120 {
1121 if (dp)
1122 return offsetof(CPUARMState, vfp.regs[reg]);
1123 else if (reg & 1) {
1124 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1125 + offsetof(CPU_DoubleU, l.upper);
1126 } else {
1127 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1128 + offsetof(CPU_DoubleU, l.lower);
1129 }
1130 }
1131
1132 /* Return the offset of a 32-bit piece of a NEON register.
1133 zero is the least significant end of the register. */
1134 static inline long
1135 neon_reg_offset (int reg, int n)
1136 {
1137 int sreg;
1138 sreg = reg * 2 + n;
1139 return vfp_reg_offset(0, sreg);
1140 }
1141
1142 /* FIXME: Remove these. */
1143 #define neon_T0 cpu_T[0]
1144 #define neon_T1 cpu_T[1]
1145 #define NEON_GET_REG(T, reg, n) \
1146 tcg_gen_ld_i32(neon_##T, cpu_env, neon_reg_offset(reg, n))
1147 #define NEON_SET_REG(T, reg, n) \
1148 tcg_gen_st_i32(neon_##T, cpu_env, neon_reg_offset(reg, n))
1149
1150 static TCGv neon_load_reg(int reg, int pass)
1151 {
1152 TCGv tmp = new_tmp();
1153 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1154 return tmp;
1155 }
1156
1157 static void neon_store_reg(int reg, int pass, TCGv var)
1158 {
1159 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1160 dead_tmp(var);
1161 }
1162
1163 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1164 {
1165 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1166 }
1167
1168 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1169 {
1170 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1171 }
1172
1173 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1174 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1175 #define tcg_gen_st_f32 tcg_gen_st_i32
1176 #define tcg_gen_st_f64 tcg_gen_st_i64
1177
1178 static inline void gen_mov_F0_vreg(int dp, int reg)
1179 {
1180 if (dp)
1181 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1182 else
1183 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1184 }
1185
1186 static inline void gen_mov_F1_vreg(int dp, int reg)
1187 {
1188 if (dp)
1189 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1190 else
1191 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1192 }
1193
1194 static inline void gen_mov_vreg_F0(int dp, int reg)
1195 {
1196 if (dp)
1197 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1198 else
1199 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1200 }
1201
1202 #define ARM_CP_RW_BIT (1 << 20)
1203
1204 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1205 {
1206 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1207 }
1208
1209 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1210 {
1211 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1212 }
1213
1214 static inline void gen_op_iwmmxt_movl_wCx_T0(int reg)
1215 {
1216 tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1217 }
1218
1219 static inline void gen_op_iwmmxt_movl_T0_wCx(int reg)
1220 {
1221 tcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1222 }
1223
1224 static inline void gen_op_iwmmxt_movl_T1_wCx(int reg)
1225 {
1226 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1227 }
1228
1229 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1230 {
1231 iwmmxt_store_reg(cpu_M0, rn);
1232 }
1233
1234 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1235 {
1236 iwmmxt_load_reg(cpu_M0, rn);
1237 }
1238
1239 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1240 {
1241 iwmmxt_load_reg(cpu_V1, rn);
1242 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1243 }
1244
1245 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1246 {
1247 iwmmxt_load_reg(cpu_V1, rn);
1248 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1249 }
1250
1251 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1252 {
1253 iwmmxt_load_reg(cpu_V1, rn);
1254 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1255 }
1256
1257 #define IWMMXT_OP(name) \
1258 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1259 { \
1260 iwmmxt_load_reg(cpu_V1, rn); \
1261 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1262 }
1263
1264 #define IWMMXT_OP_ENV(name) \
1265 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1266 { \
1267 iwmmxt_load_reg(cpu_V1, rn); \
1268 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1269 }
1270
1271 #define IWMMXT_OP_ENV_SIZE(name) \
1272 IWMMXT_OP_ENV(name##b) \
1273 IWMMXT_OP_ENV(name##w) \
1274 IWMMXT_OP_ENV(name##l)
1275
1276 #define IWMMXT_OP_ENV1(name) \
1277 static inline void gen_op_iwmmxt_##name##_M0(void) \
1278 { \
1279 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1280 }
1281
1282 IWMMXT_OP(maddsq)
1283 IWMMXT_OP(madduq)
1284 IWMMXT_OP(sadb)
1285 IWMMXT_OP(sadw)
1286 IWMMXT_OP(mulslw)
1287 IWMMXT_OP(mulshw)
1288 IWMMXT_OP(mululw)
1289 IWMMXT_OP(muluhw)
1290 IWMMXT_OP(macsw)
1291 IWMMXT_OP(macuw)
1292
1293 IWMMXT_OP_ENV_SIZE(unpackl)
1294 IWMMXT_OP_ENV_SIZE(unpackh)
1295
1296 IWMMXT_OP_ENV1(unpacklub)
1297 IWMMXT_OP_ENV1(unpackluw)
1298 IWMMXT_OP_ENV1(unpacklul)
1299 IWMMXT_OP_ENV1(unpackhub)
1300 IWMMXT_OP_ENV1(unpackhuw)
1301 IWMMXT_OP_ENV1(unpackhul)
1302 IWMMXT_OP_ENV1(unpacklsb)
1303 IWMMXT_OP_ENV1(unpacklsw)
1304 IWMMXT_OP_ENV1(unpacklsl)
1305 IWMMXT_OP_ENV1(unpackhsb)
1306 IWMMXT_OP_ENV1(unpackhsw)
1307 IWMMXT_OP_ENV1(unpackhsl)
1308
1309 IWMMXT_OP_ENV_SIZE(cmpeq)
1310 IWMMXT_OP_ENV_SIZE(cmpgtu)
1311 IWMMXT_OP_ENV_SIZE(cmpgts)
1312
1313 IWMMXT_OP_ENV_SIZE(mins)
1314 IWMMXT_OP_ENV_SIZE(minu)
1315 IWMMXT_OP_ENV_SIZE(maxs)
1316 IWMMXT_OP_ENV_SIZE(maxu)
1317
1318 IWMMXT_OP_ENV_SIZE(subn)
1319 IWMMXT_OP_ENV_SIZE(addn)
1320 IWMMXT_OP_ENV_SIZE(subu)
1321 IWMMXT_OP_ENV_SIZE(addu)
1322 IWMMXT_OP_ENV_SIZE(subs)
1323 IWMMXT_OP_ENV_SIZE(adds)
1324
1325 IWMMXT_OP_ENV(avgb0)
1326 IWMMXT_OP_ENV(avgb1)
1327 IWMMXT_OP_ENV(avgw0)
1328 IWMMXT_OP_ENV(avgw1)
1329
1330 IWMMXT_OP(msadb)
1331
1332 IWMMXT_OP_ENV(packuw)
1333 IWMMXT_OP_ENV(packul)
1334 IWMMXT_OP_ENV(packuq)
1335 IWMMXT_OP_ENV(packsw)
1336 IWMMXT_OP_ENV(packsl)
1337 IWMMXT_OP_ENV(packsq)
1338
1339 static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void)
1340 {
1341 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1342 }
1343
1344 static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void)
1345 {
1346 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1347 }
1348
1349 static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void)
1350 {
1351 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1352 }
1353
1354 static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn)
1355 {
1356 iwmmxt_load_reg(cpu_V1, rn);
1357 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, cpu_T[0]);
1358 }
1359
1360 static inline void gen_op_iwmmxt_insr_M0_T0_T1(int shift)
1361 {
1362 TCGv tmp = tcg_const_i32(shift);
1363 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1], tmp);
1364 }
1365
1366 static inline void gen_op_iwmmxt_extrsb_T0_M0(int shift)
1367 {
1368 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1369 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1370 tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
1371 }
1372
1373 static inline void gen_op_iwmmxt_extrsw_T0_M0(int shift)
1374 {
1375 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1376 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1377 tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
1378 }
1379
1380 static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask)
1381 {
1382 tcg_gen_shri_i64(cpu_M0, cpu_M0, shift);
1383 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0);
1384 if (mask != ~0u)
1385 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
1386 }
1387
1388 static void gen_op_iwmmxt_set_mup(void)
1389 {
1390 TCGv tmp;
1391 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1392 tcg_gen_ori_i32(tmp, tmp, 2);
1393 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1394 }
1395
1396 static void gen_op_iwmmxt_set_cup(void)
1397 {
1398 TCGv tmp;
1399 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1400 tcg_gen_ori_i32(tmp, tmp, 1);
1401 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1402 }
1403
1404 static void gen_op_iwmmxt_setpsr_nz(void)
1405 {
1406 TCGv tmp = new_tmp();
1407 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1408 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1409 }
1410
1411 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1412 {
1413 iwmmxt_load_reg(cpu_V1, rn);
1414 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1415 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1416 }
1417
1418
1419 static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
1420 {
1421 iwmmxt_load_reg(cpu_V0, rn);
1422 tcg_gen_trunc_i64_i32(cpu_T[0], cpu_V0);
1423 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1424 tcg_gen_trunc_i64_i32(cpu_T[1], cpu_V0);
1425 }
1426
1427 static void gen_iwmmxt_movl_wRn_T0_T1(int rn)
1428 {
1429 tcg_gen_concat_i32_i64(cpu_V0, cpu_T[0], cpu_T[1]);
1430 iwmmxt_store_reg(cpu_V0, rn);
1431 }
1432
1433 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)
1434 {
1435 int rd;
1436 uint32_t offset;
1437
1438 rd = (insn >> 16) & 0xf;
1439 gen_movl_T1_reg(s, rd);
1440
1441 offset = (insn & 0xff) << ((insn >> 7) & 2);
1442 if (insn & (1 << 24)) {
1443 /* Pre indexed */
1444 if (insn & (1 << 23))
1445 gen_op_addl_T1_im(offset);
1446 else
1447 gen_op_addl_T1_im(-offset);
1448
1449 if (insn & (1 << 21))
1450 gen_movl_reg_T1(s, rd);
1451 } else if (insn & (1 << 21)) {
1452 /* Post indexed */
1453 if (insn & (1 << 23))
1454 gen_op_movl_T0_im(offset);
1455 else
1456 gen_op_movl_T0_im(- offset);
1457 gen_op_addl_T0_T1();
1458 gen_movl_reg_T0(s, rd);
1459 } else if (!(insn & (1 << 23)))
1460 return 1;
1461 return 0;
1462 }
1463
1464 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
1465 {
1466 int rd = (insn >> 0) & 0xf;
1467
1468 if (insn & (1 << 8))
1469 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3)
1470 return 1;
1471 else
1472 gen_op_iwmmxt_movl_T0_wCx(rd);
1473 else
1474 gen_iwmmxt_movl_T0_T1_wRn(rd);
1475
1476 gen_op_movl_T1_im(mask);
1477 gen_op_andl_T0_T1();
1478 return 0;
1479 }
1480
1481 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1482 (ie. an undefined instruction). */
1483 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1484 {
1485 int rd, wrd;
1486 int rdhi, rdlo, rd0, rd1, i;
1487 TCGv tmp;
1488
1489 if ((insn & 0x0e000e00) == 0x0c000000) {
1490 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1491 wrd = insn & 0xf;
1492 rdlo = (insn >> 12) & 0xf;
1493 rdhi = (insn >> 16) & 0xf;
1494 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1495 gen_iwmmxt_movl_T0_T1_wRn(wrd);
1496 gen_movl_reg_T0(s, rdlo);
1497 gen_movl_reg_T1(s, rdhi);
1498 } else { /* TMCRR */
1499 gen_movl_T0_reg(s, rdlo);
1500 gen_movl_T1_reg(s, rdhi);
1501 gen_iwmmxt_movl_wRn_T0_T1(wrd);
1502 gen_op_iwmmxt_set_mup();
1503 }
1504 return 0;
1505 }
1506
1507 wrd = (insn >> 12) & 0xf;
1508 if (gen_iwmmxt_address(s, insn))
1509 return 1;
1510 if (insn & ARM_CP_RW_BIT) {
1511 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1512 tmp = gen_ld32(cpu_T[1], IS_USER(s));
1513 tcg_gen_mov_i32(cpu_T[0], tmp);
1514 dead_tmp(tmp);
1515 gen_op_iwmmxt_movl_wCx_T0(wrd);
1516 } else {
1517 i = 1;
1518 if (insn & (1 << 8)) {
1519 if (insn & (1 << 22)) { /* WLDRD */
1520 tcg_gen_qemu_ld64(cpu_M0, cpu_T[1], IS_USER(s));
1521 i = 0;
1522 } else { /* WLDRW wRd */
1523 tmp = gen_ld32(cpu_T[1], IS_USER(s));
1524 }
1525 } else {
1526 if (insn & (1 << 22)) { /* WLDRH */
1527 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
1528 } else { /* WLDRB */
1529 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
1530 }
1531 }
1532 if (i) {
1533 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1534 dead_tmp(tmp);
1535 }
1536 gen_op_iwmmxt_movq_wRn_M0(wrd);
1537 }
1538 } else {
1539 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1540 gen_op_iwmmxt_movl_T0_wCx(wrd);
1541 tmp = new_tmp();
1542 tcg_gen_mov_i32(tmp, cpu_T[0]);
1543 gen_st32(tmp, cpu_T[1], IS_USER(s));
1544 } else {
1545 gen_op_iwmmxt_movq_M0_wRn(wrd);
1546 tmp = new_tmp();
1547 if (insn & (1 << 8)) {
1548 if (insn & (1 << 22)) { /* WSTRD */
1549 dead_tmp(tmp);
1550 tcg_gen_qemu_st64(cpu_M0, cpu_T[1], IS_USER(s));
1551 } else { /* WSTRW wRd */
1552 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1553 gen_st32(tmp, cpu_T[1], IS_USER(s));
1554 }
1555 } else {
1556 if (insn & (1 << 22)) { /* WSTRH */
1557 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1558 gen_st16(tmp, cpu_T[1], IS_USER(s));
1559 } else { /* WSTRB */
1560 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1561 gen_st8(tmp, cpu_T[1], IS_USER(s));
1562 }
1563 }
1564 }
1565 }
1566 return 0;
1567 }
1568
1569 if ((insn & 0x0f000000) != 0x0e000000)
1570 return 1;
1571
1572 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1573 case 0x000: /* WOR */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 0) & 0xf;
1576 rd1 = (insn >> 16) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 gen_op_iwmmxt_orq_M0_wRn(rd1);
1579 gen_op_iwmmxt_setpsr_nz();
1580 gen_op_iwmmxt_movq_wRn_M0(wrd);
1581 gen_op_iwmmxt_set_mup();
1582 gen_op_iwmmxt_set_cup();
1583 break;
1584 case 0x011: /* TMCR */
1585 if (insn & 0xf)
1586 return 1;
1587 rd = (insn >> 12) & 0xf;
1588 wrd = (insn >> 16) & 0xf;
1589 switch (wrd) {
1590 case ARM_IWMMXT_wCID:
1591 case ARM_IWMMXT_wCASF:
1592 break;
1593 case ARM_IWMMXT_wCon:
1594 gen_op_iwmmxt_set_cup();
1595 /* Fall through. */
1596 case ARM_IWMMXT_wCSSF:
1597 gen_op_iwmmxt_movl_T0_wCx(wrd);
1598 gen_movl_T1_reg(s, rd);
1599 gen_op_bicl_T0_T1();
1600 gen_op_iwmmxt_movl_wCx_T0(wrd);
1601 break;
1602 case ARM_IWMMXT_wCGR0:
1603 case ARM_IWMMXT_wCGR1:
1604 case ARM_IWMMXT_wCGR2:
1605 case ARM_IWMMXT_wCGR3:
1606 gen_op_iwmmxt_set_cup();
1607 gen_movl_reg_T0(s, rd);
1608 gen_op_iwmmxt_movl_wCx_T0(wrd);
1609 break;
1610 default:
1611 return 1;
1612 }
1613 break;
1614 case 0x100: /* WXOR */
1615 wrd = (insn >> 12) & 0xf;
1616 rd0 = (insn >> 0) & 0xf;
1617 rd1 = (insn >> 16) & 0xf;
1618 gen_op_iwmmxt_movq_M0_wRn(rd0);
1619 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1620 gen_op_iwmmxt_setpsr_nz();
1621 gen_op_iwmmxt_movq_wRn_M0(wrd);
1622 gen_op_iwmmxt_set_mup();
1623 gen_op_iwmmxt_set_cup();
1624 break;
1625 case 0x111: /* TMRC */
1626 if (insn & 0xf)
1627 return 1;
1628 rd = (insn >> 12) & 0xf;
1629 wrd = (insn >> 16) & 0xf;
1630 gen_op_iwmmxt_movl_T0_wCx(wrd);
1631 gen_movl_reg_T0(s, rd);
1632 break;
1633 case 0x300: /* WANDN */
1634 wrd = (insn >> 12) & 0xf;
1635 rd0 = (insn >> 0) & 0xf;
1636 rd1 = (insn >> 16) & 0xf;
1637 gen_op_iwmmxt_movq_M0_wRn(rd0);
1638 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1639 gen_op_iwmmxt_andq_M0_wRn(rd1);
1640 gen_op_iwmmxt_setpsr_nz();
1641 gen_op_iwmmxt_movq_wRn_M0(wrd);
1642 gen_op_iwmmxt_set_mup();
1643 gen_op_iwmmxt_set_cup();
1644 break;
1645 case 0x200: /* WAND */
1646 wrd = (insn >> 12) & 0xf;
1647 rd0 = (insn >> 0) & 0xf;
1648 rd1 = (insn >> 16) & 0xf;
1649 gen_op_iwmmxt_movq_M0_wRn(rd0);
1650 gen_op_iwmmxt_andq_M0_wRn(rd1);
1651 gen_op_iwmmxt_setpsr_nz();
1652 gen_op_iwmmxt_movq_wRn_M0(wrd);
1653 gen_op_iwmmxt_set_mup();
1654 gen_op_iwmmxt_set_cup();
1655 break;
1656 case 0x810: case 0xa10: /* WMADD */
1657 wrd = (insn >> 12) & 0xf;
1658 rd0 = (insn >> 0) & 0xf;
1659 rd1 = (insn >> 16) & 0xf;
1660 gen_op_iwmmxt_movq_M0_wRn(rd0);
1661 if (insn & (1 << 21))
1662 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1663 else
1664 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1665 gen_op_iwmmxt_movq_wRn_M0(wrd);
1666 gen_op_iwmmxt_set_mup();
1667 break;
1668 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1669 wrd = (insn >> 12) & 0xf;
1670 rd0 = (insn >> 16) & 0xf;
1671 rd1 = (insn >> 0) & 0xf;
1672 gen_op_iwmmxt_movq_M0_wRn(rd0);
1673 switch ((insn >> 22) & 3) {
1674 case 0:
1675 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1676 break;
1677 case 1:
1678 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1679 break;
1680 case 2:
1681 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1682 break;
1683 case 3:
1684 return 1;
1685 }
1686 gen_op_iwmmxt_movq_wRn_M0(wrd);
1687 gen_op_iwmmxt_set_mup();
1688 gen_op_iwmmxt_set_cup();
1689 break;
1690 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1691 wrd = (insn >> 12) & 0xf;
1692 rd0 = (insn >> 16) & 0xf;
1693 rd1 = (insn >> 0) & 0xf;
1694 gen_op_iwmmxt_movq_M0_wRn(rd0);
1695 switch ((insn >> 22) & 3) {
1696 case 0:
1697 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1698 break;
1699 case 1:
1700 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1701 break;
1702 case 2:
1703 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1704 break;
1705 case 3:
1706 return 1;
1707 }
1708 gen_op_iwmmxt_movq_wRn_M0(wrd);
1709 gen_op_iwmmxt_set_mup();
1710 gen_op_iwmmxt_set_cup();
1711 break;
1712 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1713 wrd = (insn >> 12) & 0xf;
1714 rd0 = (insn >> 16) & 0xf;
1715 rd1 = (insn >> 0) & 0xf;
1716 gen_op_iwmmxt_movq_M0_wRn(rd0);
1717 if (insn & (1 << 22))
1718 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1719 else
1720 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1721 if (!(insn & (1 << 20)))
1722 gen_op_iwmmxt_addl_M0_wRn(wrd);
1723 gen_op_iwmmxt_movq_wRn_M0(wrd);
1724 gen_op_iwmmxt_set_mup();
1725 break;
1726 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1727 wrd = (insn >> 12) & 0xf;
1728 rd0 = (insn >> 16) & 0xf;
1729 rd1 = (insn >> 0) & 0xf;
1730 gen_op_iwmmxt_movq_M0_wRn(rd0);
1731 if (insn & (1 << 21)) {
1732 if (insn & (1 << 20))
1733 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1734 else
1735 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1736 } else {
1737 if (insn & (1 << 20))
1738 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1739 else
1740 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1741 }
1742 gen_op_iwmmxt_movq_wRn_M0(wrd);
1743 gen_op_iwmmxt_set_mup();
1744 break;
1745 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1746 wrd = (insn >> 12) & 0xf;
1747 rd0 = (insn >> 16) & 0xf;
1748 rd1 = (insn >> 0) & 0xf;
1749 gen_op_iwmmxt_movq_M0_wRn(rd0);
1750 if (insn & (1 << 21))
1751 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1752 else
1753 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1754 if (!(insn & (1 << 20))) {
1755 iwmmxt_load_reg(cpu_V1, wrd);
1756 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1757 }
1758 gen_op_iwmmxt_movq_wRn_M0(wrd);
1759 gen_op_iwmmxt_set_mup();
1760 break;
1761 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1762 wrd = (insn >> 12) & 0xf;
1763 rd0 = (insn >> 16) & 0xf;
1764 rd1 = (insn >> 0) & 0xf;
1765 gen_op_iwmmxt_movq_M0_wRn(rd0);
1766 switch ((insn >> 22) & 3) {
1767 case 0:
1768 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1769 break;
1770 case 1:
1771 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1772 break;
1773 case 2:
1774 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1775 break;
1776 case 3:
1777 return 1;
1778 }
1779 gen_op_iwmmxt_movq_wRn_M0(wrd);
1780 gen_op_iwmmxt_set_mup();
1781 gen_op_iwmmxt_set_cup();
1782 break;
1783 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1784 wrd = (insn >> 12) & 0xf;
1785 rd0 = (insn >> 16) & 0xf;
1786 rd1 = (insn >> 0) & 0xf;
1787 gen_op_iwmmxt_movq_M0_wRn(rd0);
1788 if (insn & (1 << 22)) {
1789 if (insn & (1 << 20))
1790 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1791 else
1792 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1793 } else {
1794 if (insn & (1 << 20))
1795 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1796 else
1797 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1798 }
1799 gen_op_iwmmxt_movq_wRn_M0(wrd);
1800 gen_op_iwmmxt_set_mup();
1801 gen_op_iwmmxt_set_cup();
1802 break;
1803 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1804 wrd = (insn >> 12) & 0xf;
1805 rd0 = (insn >> 16) & 0xf;
1806 rd1 = (insn >> 0) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0);
1808 gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1809 gen_op_movl_T1_im(7);
1810 gen_op_andl_T0_T1();
1811 gen_op_iwmmxt_align_M0_T0_wRn(rd1);
1812 gen_op_iwmmxt_movq_wRn_M0(wrd);
1813 gen_op_iwmmxt_set_mup();
1814 break;
1815 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1816 rd = (insn >> 12) & 0xf;
1817 wrd = (insn >> 16) & 0xf;
1818 gen_movl_T0_reg(s, rd);
1819 gen_op_iwmmxt_movq_M0_wRn(wrd);
1820 switch ((insn >> 6) & 3) {
1821 case 0:
1822 gen_op_movl_T1_im(0xff);
1823 gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3);
1824 break;
1825 case 1:
1826 gen_op_movl_T1_im(0xffff);
1827 gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4);
1828 break;
1829 case 2:
1830 gen_op_movl_T1_im(0xffffffff);
1831 gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5);
1832 break;
1833 case 3:
1834 return 1;
1835 }
1836 gen_op_iwmmxt_movq_wRn_M0(wrd);
1837 gen_op_iwmmxt_set_mup();
1838 break;
1839 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1840 rd = (insn >> 12) & 0xf;
1841 wrd = (insn >> 16) & 0xf;
1842 if (rd == 15)
1843 return 1;
1844 gen_op_iwmmxt_movq_M0_wRn(wrd);
1845 switch ((insn >> 22) & 3) {
1846 case 0:
1847 if (insn & 8)
1848 gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3);
1849 else {
1850 gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff);
1851 }
1852 break;
1853 case 1:
1854 if (insn & 8)
1855 gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4);
1856 else {
1857 gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff);
1858 }
1859 break;
1860 case 2:
1861 gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u);
1862 break;
1863 case 3:
1864 return 1;
1865 }
1866 gen_movl_reg_T0(s, rd);
1867 break;
1868 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1869 if ((insn & 0x000ff008) != 0x0003f000)
1870 return 1;
1871 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
1872 switch ((insn >> 22) & 3) {
1873 case 0:
1874 gen_op_shrl_T1_im(((insn & 7) << 2) + 0);
1875 break;
1876 case 1:
1877 gen_op_shrl_T1_im(((insn & 3) << 3) + 4);
1878 break;
1879 case 2:
1880 gen_op_shrl_T1_im(((insn & 1) << 4) + 12);
1881 break;
1882 case 3:
1883 return 1;
1884 }
1885 gen_op_shll_T1_im(28);
1886 gen_set_nzcv(cpu_T[1]);
1887 break;
1888 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1889 rd = (insn >> 12) & 0xf;
1890 wrd = (insn >> 16) & 0xf;
1891 gen_movl_T0_reg(s, rd);
1892 switch ((insn >> 6) & 3) {
1893 case 0:
1894 gen_helper_iwmmxt_bcstb(cpu_M0, cpu_T[0]);
1895 break;
1896 case 1:
1897 gen_helper_iwmmxt_bcstw(cpu_M0, cpu_T[0]);
1898 break;
1899 case 2:
1900 gen_helper_iwmmxt_bcstl(cpu_M0, cpu_T[0]);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 break;
1908 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1909 if ((insn & 0x000ff00f) != 0x0003f000)
1910 return 1;
1911 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
1912 switch ((insn >> 22) & 3) {
1913 case 0:
1914 for (i = 0; i < 7; i ++) {
1915 gen_op_shll_T1_im(4);
1916 gen_op_andl_T0_T1();
1917 }
1918 break;
1919 case 1:
1920 for (i = 0; i < 3; i ++) {
1921 gen_op_shll_T1_im(8);
1922 gen_op_andl_T0_T1();
1923 }
1924 break;
1925 case 2:
1926 gen_op_shll_T1_im(16);
1927 gen_op_andl_T0_T1();
1928 break;
1929 case 3:
1930 return 1;
1931 }
1932 gen_set_nzcv(cpu_T[0]);
1933 break;
1934 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1935 wrd = (insn >> 12) & 0xf;
1936 rd0 = (insn >> 16) & 0xf;
1937 gen_op_iwmmxt_movq_M0_wRn(rd0);
1938 switch ((insn >> 22) & 3) {
1939 case 0:
1940 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1941 break;
1942 case 1:
1943 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1944 break;
1945 case 2:
1946 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1947 break;
1948 case 3:
1949 return 1;
1950 }
1951 gen_op_iwmmxt_movq_wRn_M0(wrd);
1952 gen_op_iwmmxt_set_mup();
1953 break;
1954 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1955 if ((insn & 0x000ff00f) != 0x0003f000)
1956 return 1;
1957 gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
1958 switch ((insn >> 22) & 3) {
1959 case 0:
1960 for (i = 0; i < 7; i ++) {
1961 gen_op_shll_T1_im(4);
1962 gen_op_orl_T0_T1();
1963 }
1964 break;
1965 case 1:
1966 for (i = 0; i < 3; i ++) {
1967 gen_op_shll_T1_im(8);
1968 gen_op_orl_T0_T1();
1969 }
1970 break;
1971 case 2:
1972 gen_op_shll_T1_im(16);
1973 gen_op_orl_T0_T1();
1974 break;
1975 case 3:
1976 return 1;
1977 }
1978 gen_set_nzcv(cpu_T[0]);
1979 break;
1980 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1981 rd = (insn >> 12) & 0xf;
1982 rd0 = (insn >> 16) & 0xf;
1983 if ((insn & 0xf) != 0)
1984 return 1;
1985 gen_op_iwmmxt_movq_M0_wRn(rd0);
1986 switch ((insn >> 22) & 3) {
1987 case 0:
1988 gen_helper_iwmmxt_msbb(cpu_T[0], cpu_M0);
1989 break;
1990 case 1:
1991 gen_helper_iwmmxt_msbw(cpu_T[0], cpu_M0);
1992 break;
1993 case 2:
1994 gen_helper_iwmmxt_msbl(cpu_T[0], cpu_M0);
1995 break;
1996 case 3:
1997 return 1;
1998 }
1999 gen_movl_reg_T0(s, rd);
2000 break;
2001 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2002 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 rd1 = (insn >> 0) & 0xf;
2006 gen_op_iwmmxt_movq_M0_wRn(rd0);
2007 switch ((insn >> 22) & 3) {
2008 case 0:
2009 if (insn & (1 << 21))
2010 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
2011 else
2012 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
2013 break;
2014 case 1:
2015 if (insn & (1 << 21))
2016 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
2017 else
2018 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
2019 break;
2020 case 2:
2021 if (insn & (1 << 21))
2022 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
2023 else
2024 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
2025 break;
2026 case 3:
2027 return 1;
2028 }
2029 gen_op_iwmmxt_movq_wRn_M0(wrd);
2030 gen_op_iwmmxt_set_mup();
2031 gen_op_iwmmxt_set_cup();
2032 break;
2033 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2034 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2035 wrd = (insn >> 12) & 0xf;
2036 rd0 = (insn >> 16) & 0xf;
2037 gen_op_iwmmxt_movq_M0_wRn(rd0);
2038 switch ((insn >> 22) & 3) {
2039 case 0:
2040 if (insn & (1 << 21))
2041 gen_op_iwmmxt_unpacklsb_M0();
2042 else
2043 gen_op_iwmmxt_unpacklub_M0();
2044 break;
2045 case 1:
2046 if (insn & (1 << 21))
2047 gen_op_iwmmxt_unpacklsw_M0();
2048 else
2049 gen_op_iwmmxt_unpackluw_M0();
2050 break;
2051 case 2:
2052 if (insn & (1 << 21))
2053 gen_op_iwmmxt_unpacklsl_M0();
2054 else
2055 gen_op_iwmmxt_unpacklul_M0();
2056 break;
2057 case 3:
2058 return 1;
2059 }
2060 gen_op_iwmmxt_movq_wRn_M0(wrd);
2061 gen_op_iwmmxt_set_mup();
2062 gen_op_iwmmxt_set_cup();
2063 break;
2064 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2065 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2066 wrd = (insn >> 12) & 0xf;
2067 rd0 = (insn >> 16) & 0xf;
2068 gen_op_iwmmxt_movq_M0_wRn(rd0);
2069 switch ((insn >> 22) & 3) {
2070 case 0:
2071 if (insn & (1 << 21))
2072 gen_op_iwmmxt_unpackhsb_M0();
2073 else
2074 gen_op_iwmmxt_unpackhub_M0();
2075 break;
2076 case 1:
2077 if (insn & (1 << 21))
2078 gen_op_iwmmxt_unpackhsw_M0();
2079 else
2080 gen_op_iwmmxt_unpackhuw_M0();
2081 break;
2082 case 2:
2083 if (insn & (1 << 21))
2084 gen_op_iwmmxt_unpackhsl_M0();
2085 else
2086 gen_op_iwmmxt_unpackhul_M0();
2087 break;
2088 case 3:
2089 return 1;
2090 }
2091 gen_op_iwmmxt_movq_wRn_M0(wrd);
2092 gen_op_iwmmxt_set_mup();
2093 gen_op_iwmmxt_set_cup();
2094 break;
2095 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2096 case 0x214: case 0x614: case 0xa14: case 0xe14:
2097 wrd = (insn >> 12) & 0xf;
2098 rd0 = (insn >> 16) & 0xf;
2099 gen_op_iwmmxt_movq_M0_wRn(rd0);
2100 if (gen_iwmmxt_shift(insn, 0xff))
2101 return 1;
2102 switch ((insn >> 22) & 3) {
2103 case 0:
2104 return 1;
2105 case 1:
2106 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2107 break;
2108 case 2:
2109 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2110 break;
2111 case 3:
2112 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2113 break;
2114 }
2115 gen_op_iwmmxt_movq_wRn_M0(wrd);
2116 gen_op_iwmmxt_set_mup();
2117 gen_op_iwmmxt_set_cup();
2118 break;
2119 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2120 case 0x014: case 0x414: case 0x814: case 0xc14:
2121 wrd = (insn >> 12) & 0xf;
2122 rd0 = (insn >> 16) & 0xf;
2123 gen_op_iwmmxt_movq_M0_wRn(rd0);
2124 if (gen_iwmmxt_shift(insn, 0xff))
2125 return 1;
2126 switch ((insn >> 22) & 3) {
2127 case 0:
2128 return 1;
2129 case 1:
2130 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2131 break;
2132 case 2:
2133 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2134 break;
2135 case 3:
2136 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2137 break;
2138 }
2139 gen_op_iwmmxt_movq_wRn_M0(wrd);
2140 gen_op_iwmmxt_set_mup();
2141 gen_op_iwmmxt_set_cup();
2142 break;
2143 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2144 case 0x114: case 0x514: case 0x914: case 0xd14:
2145 wrd = (insn >> 12) & 0xf;
2146 rd0 = (insn >> 16) & 0xf;
2147 gen_op_iwmmxt_movq_M0_wRn(rd0);
2148 if (gen_iwmmxt_shift(insn, 0xff))
2149 return 1;
2150 switch ((insn >> 22) & 3) {
2151 case 0:
2152 return 1;
2153 case 1:
2154 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2155 break;
2156 case 2:
2157 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2158 break;
2159 case 3:
2160 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2161 break;
2162 }
2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 gen_op_iwmmxt_set_cup();
2166 break;
2167 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2168 case 0x314: case 0x714: case 0xb14: case 0xf14:
2169 wrd = (insn >> 12) & 0xf;
2170 rd0 = (insn >> 16) & 0xf;
2171 gen_op_iwmmxt_movq_M0_wRn(rd0);
2172 switch ((insn >> 22) & 3) {
2173 case 0:
2174 return 1;
2175 case 1:
2176 if (gen_iwmmxt_shift(insn, 0xf))
2177 return 1;
2178 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2179 break;
2180 case 2:
2181 if (gen_iwmmxt_shift(insn, 0x1f))
2182 return 1;
2183 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2184 break;
2185 case 3:
2186 if (gen_iwmmxt_shift(insn, 0x3f))
2187 return 1;
2188 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2189 break;
2190 }
2191 gen_op_iwmmxt_movq_wRn_M0(wrd);
2192 gen_op_iwmmxt_set_mup();
2193 gen_op_iwmmxt_set_cup();
2194 break;
2195 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2196 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2197 wrd = (insn >> 12) & 0xf;
2198 rd0 = (insn >> 16) & 0xf;
2199 rd1 = (insn >> 0) & 0xf;
2200 gen_op_iwmmxt_movq_M0_wRn(rd0);
2201 switch ((insn >> 22) & 3) {
2202 case 0:
2203 if (insn & (1 << 21))
2204 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2205 else
2206 gen_op_iwmmxt_minub_M0_wRn(rd1);
2207 break;
2208 case 1:
2209 if (insn & (1 << 21))
2210 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2211 else
2212 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2213 break;
2214 case 2:
2215 if (insn & (1 << 21))
2216 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2217 else
2218 gen_op_iwmmxt_minul_M0_wRn(rd1);
2219 break;
2220 case 3:
2221 return 1;
2222 }
2223 gen_op_iwmmxt_movq_wRn_M0(wrd);
2224 gen_op_iwmmxt_set_mup();
2225 break;
2226 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2227 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2228 wrd = (insn >> 12) & 0xf;
2229 rd0 = (insn >> 16) & 0xf;
2230 rd1 = (insn >> 0) & 0xf;
2231 gen_op_iwmmxt_movq_M0_wRn(rd0);
2232 switch ((insn >> 22) & 3) {
2233 case 0:
2234 if (insn & (1 << 21))
2235 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2236 else
2237 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2238 break;
2239 case 1:
2240 if (insn & (1 << 21))
2241 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2242 else
2243 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2244 break;
2245 case 2:
2246 if (insn & (1 << 21))
2247 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2248 else
2249 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2250 break;
2251 case 3:
2252 return 1;
2253 }
2254 gen_op_iwmmxt_movq_wRn_M0(wrd);
2255 gen_op_iwmmxt_set_mup();
2256 break;
2257 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2258 case 0x402: case 0x502: case 0x602: case 0x702:
2259 wrd = (insn >> 12) & 0xf;
2260 rd0 = (insn >> 16) & 0xf;
2261 rd1 = (insn >> 0) & 0xf;
2262 gen_op_iwmmxt_movq_M0_wRn(rd0);
2263 gen_op_movl_T0_im((insn >> 20) & 3);
2264 gen_op_iwmmxt_align_M0_T0_wRn(rd1);
2265 gen_op_iwmmxt_movq_wRn_M0(wrd);
2266 gen_op_iwmmxt_set_mup();
2267 break;
2268 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2269 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2270 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2271 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
2276 switch ((insn >> 20) & 0xf) {
2277 case 0x0:
2278 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2279 break;
2280 case 0x1:
2281 gen_op_iwmmxt_subub_M0_wRn(rd1);
2282 break;
2283 case 0x3:
2284 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2285 break;
2286 case 0x4:
2287 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2288 break;
2289 case 0x5:
2290 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2291 break;
2292 case 0x7:
2293 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2294 break;
2295 case 0x8:
2296 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2297 break;
2298 case 0x9:
2299 gen_op_iwmmxt_subul_M0_wRn(rd1);
2300 break;
2301 case 0xb:
2302 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2303 break;
2304 default:
2305 return 1;
2306 }
2307 gen_op_iwmmxt_movq_wRn_M0(wrd);
2308 gen_op_iwmmxt_set_mup();
2309 gen_op_iwmmxt_set_cup();
2310 break;
2311 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2312 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2313 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2314 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2315 wrd = (insn >> 12) & 0xf;
2316 rd0 = (insn >> 16) & 0xf;
2317 gen_op_iwmmxt_movq_M0_wRn(rd0);
2318 gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));
2319 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
2320 gen_op_iwmmxt_movq_wRn_M0(wrd);
2321 gen_op_iwmmxt_set_mup();
2322 gen_op_iwmmxt_set_cup();
2323 break;
2324 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2325 case 0x418: case 0x518: case 0x618: case 0x718:
2326 case 0x818: case 0x918: case 0xa18: case 0xb18:
2327 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2328 wrd = (insn >> 12) & 0xf;
2329 rd0 = (insn >> 16) & 0xf;
2330 rd1 = (insn >> 0) & 0xf;
2331 gen_op_iwmmxt_movq_M0_wRn(rd0);
2332 switch ((insn >> 20) & 0xf) {
2333 case 0x0:
2334 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2335 break;
2336 case 0x1:
2337 gen_op_iwmmxt_addub_M0_wRn(rd1);
2338 break;
2339 case 0x3:
2340 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2341 break;
2342 case 0x4:
2343 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2344 break;
2345 case 0x5:
2346 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2347 break;
2348 case 0x7:
2349 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2350 break;
2351 case 0x8:
2352 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2353 break;
2354 case 0x9:
2355 gen_op_iwmmxt_addul_M0_wRn(rd1);
2356 break;
2357 case 0xb:
2358 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2359 break;
2360 default:
2361 return 1;
2362 }
2363 gen_op_iwmmxt_movq_wRn_M0(wrd);
2364 gen_op_iwmmxt_set_mup();
2365 gen_op_iwmmxt_set_cup();
2366 break;
2367 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2368 case 0x408: case 0x508: case 0x608: case 0x708:
2369 case 0x808: case 0x908: case 0xa08: case 0xb08:
2370 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2371 wrd = (insn >> 12) & 0xf;
2372 rd0 = (insn >> 16) & 0xf;
2373 rd1 = (insn >> 0) & 0xf;
2374 gen_op_iwmmxt_movq_M0_wRn(rd0);
2375 if (!(insn & (1 << 20)))
2376 return 1;
2377 switch ((insn >> 22) & 3) {
2378 case 0:
2379 return 1;
2380 case 1:
2381 if (insn & (1 << 21))
2382 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2383 else
2384 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2385 break;
2386 case 2:
2387 if (insn & (1 << 21))
2388 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2389 else
2390 gen_op_iwmmxt_packul_M0_wRn(rd1);
2391 break;
2392 case 3:
2393 if (insn & (1 << 21))
2394 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2395 else
2396 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2397 break;
2398 }
2399 gen_op_iwmmxt_movq_wRn_M0(wrd);
2400 gen_op_iwmmxt_set_mup();
2401 gen_op_iwmmxt_set_cup();
2402 break;
2403 case 0x201: case 0x203: case 0x205: case 0x207:
2404 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2405 case 0x211: case 0x213: case 0x215: case 0x217:
2406 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2407 wrd = (insn >> 5) & 0xf;
2408 rd0 = (insn >> 12) & 0xf;
2409 rd1 = (insn >> 0) & 0xf;
2410 if (rd0 == 0xf || rd1 == 0xf)
2411 return 1;
2412 gen_op_iwmmxt_movq_M0_wRn(wrd);
2413 switch ((insn >> 16) & 0xf) {
2414 case 0x0: /* TMIA */
2415 gen_movl_T0_reg(s, rd0);
2416 gen_movl_T1_reg(s, rd1);
2417 gen_op_iwmmxt_muladdsl_M0_T0_T1();
2418 break;
2419 case 0x8: /* TMIAPH */
2420 gen_movl_T0_reg(s, rd0);
2421 gen_movl_T1_reg(s, rd1);
2422 gen_op_iwmmxt_muladdsw_M0_T0_T1();
2423 break;
2424 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2425 gen_movl_T1_reg(s, rd0);
2426 if (insn & (1 << 16))
2427 gen_op_shrl_T1_im(16);
2428 gen_op_movl_T0_T1();
2429 gen_movl_T1_reg(s, rd1);
2430 if (insn & (1 << 17))
2431 gen_op_shrl_T1_im(16);
2432 gen_op_iwmmxt_muladdswl_M0_T0_T1();
2433 break;
2434 default:
2435 return 1;
2436 }
2437 gen_op_iwmmxt_movq_wRn_M0(wrd);
2438 gen_op_iwmmxt_set_mup();
2439 break;
2440 default:
2441 return 1;
2442 }
2443
2444 return 0;
2445 }
2446
2447 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2448 (ie. an undefined instruction). */
2449 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2450 {
2451 int acc, rd0, rd1, rdhi, rdlo;
2452
2453 if ((insn & 0x0ff00f10) == 0x0e200010) {
2454 /* Multiply with Internal Accumulate Format */
2455 rd0 = (insn >> 12) & 0xf;
2456 rd1 = insn & 0xf;
2457 acc = (insn >> 5) & 7;
2458
2459 if (acc != 0)
2460 return 1;
2461
2462 switch ((insn >> 16) & 0xf) {
2463 case 0x0: /* MIA */
2464 gen_movl_T0_reg(s, rd0);
2465 gen_movl_T1_reg(s, rd1);
2466 gen_op_iwmmxt_muladdsl_M0_T0_T1();
2467 break;
2468 case 0x8: /* MIAPH */
2469 gen_movl_T0_reg(s, rd0);
2470 gen_movl_T1_reg(s, rd1);
2471 gen_op_iwmmxt_muladdsw_M0_T0_T1();
2472 break;
2473 case 0xc: /* MIABB */
2474 case 0xd: /* MIABT */
2475 case 0xe: /* MIATB */
2476 case 0xf: /* MIATT */
2477 gen_movl_T1_reg(s, rd0);
2478 if (insn & (1 << 16))
2479 gen_op_shrl_T1_im(16);
2480 gen_op_movl_T0_T1();
2481 gen_movl_T1_reg(s, rd1);
2482 if (insn & (1 << 17))
2483 gen_op_shrl_T1_im(16);
2484 gen_op_iwmmxt_muladdswl_M0_T0_T1();
2485 break;
2486 default:
2487 return 1;
2488 }
2489
2490 gen_op_iwmmxt_movq_wRn_M0(acc);
2491 return 0;
2492 }
2493
2494 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2495 /* Internal Accumulator Access Format */
2496 rdhi = (insn >> 16) & 0xf;
2497 rdlo = (insn >> 12) & 0xf;
2498 acc = insn & 7;
2499
2500 if (acc != 0)
2501 return 1;
2502
2503 if (insn & ARM_CP_RW_BIT) { /* MRA */
2504 gen_iwmmxt_movl_T0_T1_wRn(acc);
2505 gen_movl_reg_T0(s, rdlo);
2506 gen_op_movl_T0_im((1 << (40 - 32)) - 1);
2507 gen_op_andl_T0_T1();
2508 gen_movl_reg_T0(s, rdhi);
2509 } else { /* MAR */
2510 gen_movl_T0_reg(s, rdlo);
2511 gen_movl_T1_reg(s, rdhi);
2512 gen_iwmmxt_movl_wRn_T0_T1(acc);
2513 }
2514 return 0;
2515 }
2516
2517 return 1;
2518 }
2519
2520 /* Disassemble system coprocessor instruction. Return nonzero if
2521 instruction is not defined. */
2522 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2523 {
2524 TCGv tmp;
2525 uint32_t rd = (insn >> 12) & 0xf;
2526 uint32_t cp = (insn >> 8) & 0xf;
2527 if (IS_USER(s)) {
2528 return 1;
2529 }
2530
2531 if (insn & ARM_CP_RW_BIT) {
2532 if (!env->cp[cp].cp_read)
2533 return 1;
2534 gen_set_pc_im(s->pc);
2535 tmp = new_tmp();
2536 gen_helper_get_cp(tmp, cpu_env, tcg_const_i32(insn));
2537 store_reg(s, rd, tmp);
2538 } else {
2539 if (!env->cp[cp].cp_write)
2540 return 1;
2541 gen_set_pc_im(s->pc);
2542 tmp = load_reg(s, rd);
2543 gen_helper_set_cp(cpu_env, tcg_const_i32(insn), tmp);
2544 dead_tmp(tmp);
2545 }
2546 return 0;
2547 }
2548
2549 static int cp15_user_ok(uint32_t insn)
2550 {
2551 int cpn = (insn >> 16) & 0xf;
2552 int cpm = insn & 0xf;
2553 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2554
2555 if (cpn == 13 && cpm == 0) {
2556 /* TLS register. */
2557 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2558 return 1;
2559 }
2560 if (cpn == 7) {
2561 /* ISB, DSB, DMB. */
2562 if ((cpm == 5 && op == 4)
2563 || (cpm == 10 && (op == 4 || op == 5)))
2564 return 1;
2565 }
2566 return 0;
2567 }
2568
2569 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2570 instruction is not defined. */
2571 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2572 {
2573 uint32_t rd;
2574 TCGv tmp;
2575
2576 /* M profile cores use memory mapped registers instead of cp15. */
2577 if (arm_feature(env, ARM_FEATURE_M))
2578 return 1;
2579
2580 if ((insn & (1 << 25)) == 0) {
2581 if (insn & (1 << 20)) {
2582 /* mrrc */
2583 return 1;
2584 }
2585 /* mcrr. Used for block cache operations, so implement as no-op. */
2586 return 0;
2587 }
2588 if ((insn & (1 << 4)) == 0) {
2589 /* cdp */
2590 return 1;
2591 }
2592 if (IS_USER(s) && !cp15_user_ok(insn)) {
2593 return 1;
2594 }
2595 if ((insn & 0x0fff0fff) == 0x0e070f90
2596 || (insn & 0x0fff0fff) == 0x0e070f58) {
2597 /* Wait for interrupt. */
2598 gen_set_pc_im(s->pc);
2599 s->is_jmp = DISAS_WFI;
2600 return 0;
2601 }
2602 rd = (insn >> 12) & 0xf;
2603 if (insn & ARM_CP_RW_BIT) {
2604 tmp = new_tmp();
2605 gen_helper_get_cp15(tmp, cpu_env, tcg_const_i32(insn));
2606 /* If the destination register is r15 then sets condition codes. */
2607 if (rd != 15)
2608 store_reg(s, rd, tmp);
2609 else
2610 dead_tmp(tmp);
2611 } else {
2612 tmp = load_reg(s, rd);
2613 gen_helper_set_cp15(cpu_env, tcg_const_i32(insn), tmp);
2614 dead_tmp(tmp);
2615 /* Normally we would always end the TB here, but Linux
2616 * arch/arm/mach-pxa/sleep.S expects two instructions following
2617 * an MMU enable to execute from cache. Imitate this behaviour. */
2618 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2619 (insn & 0x0fff0fff) != 0x0e010f10)
2620 gen_lookup_tb(s);
2621 }
2622 return 0;
2623 }
2624
2625 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2626 #define VFP_SREG(insn, bigbit, smallbit) \
2627 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2628 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2629 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2630 reg = (((insn) >> (bigbit)) & 0x0f) \
2631 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2632 } else { \
2633 if (insn & (1 << (smallbit))) \
2634 return 1; \
2635 reg = ((insn) >> (bigbit)) & 0x0f; \
2636 }} while (0)
2637
2638 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2639 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2640 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2641 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2642 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2643 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2644
2645 /* Move between integer and VFP cores. */
2646 static TCGv gen_vfp_mrs(void)
2647 {
2648 TCGv tmp = new_tmp();
2649 tcg_gen_mov_i32(tmp, cpu_F0s);
2650 return tmp;
2651 }
2652
2653 static void gen_vfp_msr(TCGv tmp)
2654 {
2655 tcg_gen_mov_i32(cpu_F0s, tmp);
2656 dead_tmp(tmp);
2657 }
2658
2659 static inline int
2660 vfp_enabled(CPUState * env)
2661 {
2662 return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
2663 }
2664
2665 static void gen_neon_dup_u8(TCGv var, int shift)
2666 {
2667 TCGv tmp = new_tmp();
2668 if (shift)
2669 tcg_gen_shri_i32(var, var, shift);
2670 tcg_gen_ext8u_i32(var, var);
2671 tcg_gen_shli_i32(tmp, var, 8);
2672 tcg_gen_or_i32(var, var, tmp);
2673 tcg_gen_shli_i32(tmp, var, 16);
2674 tcg_gen_or_i32(var, var, tmp);
2675 dead_tmp(tmp);
2676 }
2677
2678 static void gen_neon_dup_low16(TCGv var)
2679 {
2680 TCGv tmp = new_tmp();
2681 tcg_gen_ext16u_i32(var, var);
2682 tcg_gen_shli_i32(tmp, var, 16);
2683 tcg_gen_or_i32(var, var, tmp);
2684 dead_tmp(tmp);
2685 }
2686
2687 static void gen_neon_dup_high16(TCGv var)
2688 {
2689 TCGv tmp = new_tmp();
2690 tcg_gen_andi_i32(var, var, 0xffff0000);
2691 tcg_gen_shri_i32(tmp, var, 16);
2692 tcg_gen_or_i32(var, var, tmp);
2693 dead_tmp(tmp);
2694 }
2695
2696 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2697 (ie. an undefined instruction). */
2698 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2699 {
2700 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2701 int dp, veclen;
2702 TCGv tmp;
2703 TCGv tmp2;
2704
2705 if (!arm_feature(env, ARM_FEATURE_VFP))
2706 return 1;
2707
2708 if (!vfp_enabled(env)) {
2709 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2710 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2711 return 1;
2712 rn = (insn >> 16) & 0xf;
2713 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2714 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2715 return 1;
2716 }
2717 dp = ((insn & 0xf00) == 0xb00);
2718 switch ((insn >> 24) & 0xf) {
2719 case 0xe:
2720 if (insn & (1 << 4)) {
2721 /* single register transfer */
2722 rd = (insn >> 12) & 0xf;
2723 if (dp) {
2724 int size;
2725 int pass;
2726
2727 VFP_DREG_N(rn, insn);
2728 if (insn & 0xf)
2729 return 1;
2730 if (insn & 0x00c00060
2731 && !arm_feature(env, ARM_FEATURE_NEON))
2732 return 1;
2733
2734 pass = (insn >> 21) & 1;
2735 if (insn & (1 << 22)) {
2736 size = 0;
2737 offset = ((insn >> 5) & 3) * 8;
2738 } else if (insn & (1 << 5)) {
2739 size = 1;
2740 offset = (insn & (1 << 6)) ? 16 : 0;
2741 } else {
2742 size = 2;
2743 offset = 0;
2744 }
2745 if (insn & ARM_CP_RW_BIT) {
2746 /* vfp->arm */
2747 tmp = neon_load_reg(rn, pass);
2748 switch (size) {
2749 case 0:
2750 if (offset)
2751 tcg_gen_shri_i32(tmp, tmp, offset);
2752 if (insn & (1 << 23))
2753 gen_uxtb(tmp);
2754 else
2755 gen_sxtb(tmp);
2756 break;
2757 case 1:
2758 if (insn & (1 << 23)) {
2759 if (offset) {
2760 tcg_gen_shri_i32(tmp, tmp, 16);
2761 } else {
2762 gen_uxth(tmp);
2763 }
2764 } else {
2765 if (offset) {
2766 tcg_gen_sari_i32(tmp, tmp, 16);
2767 } else {
2768 gen_sxth(tmp);
2769 }
2770 }
2771 break;
2772 case 2:
2773 break;
2774 }
2775 store_reg(s, rd, tmp);
2776 } else {
2777 /* arm->vfp */
2778 tmp = load_reg(s, rd);
2779 if (insn & (1 << 23)) {
2780 /* VDUP */
2781 if (size == 0) {
2782 gen_neon_dup_u8(tmp, 0);
2783 } else if (size == 1) {
2784 gen_neon_dup_low16(tmp);
2785 }
2786 tmp2 = new_tmp();
2787 tcg_gen_mov_i32(tmp2, tmp);
2788 neon_store_reg(rn, 0, tmp2);
2789 neon_store_reg(rn, 1, tmp);
2790 } else {
2791 /* VMOV */
2792 switch (size) {
2793 case 0:
2794 tmp2 = neon_load_reg(rn, pass);
2795 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2796 dead_tmp(tmp2);
2797 break;
2798 case 1:
2799 tmp2 = neon_load_reg(rn, pass);
2800 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2801 dead_tmp(tmp2);
2802 break;
2803 case 2:
2804 break;
2805 }
2806 neon_store_reg(rn, pass, tmp);
2807 }
2808 }
2809 } else { /* !dp */
2810 if ((insn & 0x6f) != 0x00)
2811 return 1;
2812 rn = VFP_SREG_N(insn);
2813 if (insn & ARM_CP_RW_BIT) {
2814 /* vfp->arm */
2815 if (insn & (1 << 21)) {
2816 /* system register */
2817 rn >>= 1;
2818
2819 switch (rn) {
2820 case ARM_VFP_FPSID:
2821 /* VFP2 allows access to FSID from userspace.
2822 VFP3 restricts all id registers to privileged
2823 accesses. */
2824 if (IS_USER(s)
2825 && arm_feature(env, ARM_FEATURE_VFP3))
2826 return 1;
2827 tmp = load_cpu_field(vfp.xregs[rn]);
2828 break;
2829 case ARM_VFP_FPEXC:
2830 if (IS_USER(s))
2831 return 1;
2832 tmp = load_cpu_field(vfp.xregs[rn]);
2833 break;
2834 case ARM_VFP_FPINST:
2835 case ARM_VFP_FPINST2:
2836 /* Not present in VFP3. */
2837 if (IS_USER(s)
2838 || arm_feature(env, ARM_FEATURE_VFP3))
2839 return 1;
2840 tmp = load_cpu_field(vfp.xregs[rn]);
2841 break;
2842 case ARM_VFP_FPSCR:
2843 if (rd == 15) {
2844 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2845 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2846 } else {
2847 tmp = new_tmp();
2848 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2849 }
2850 break;
2851 case ARM_VFP_MVFR0:
2852 case ARM_VFP_MVFR1:
2853 if (IS_USER(s)
2854 || !arm_feature(env, ARM_FEATURE_VFP3))
2855 return 1;
2856 tmp = load_cpu_field(vfp.xregs[rn]);
2857 break;
2858 default:
2859 return 1;
2860 }
2861 } else {
2862 gen_mov_F0_vreg(0, rn);
2863 tmp = gen_vfp_mrs();
2864 }
2865 if (rd == 15) {
2866 /* Set the 4 flag bits in the CPSR. */
2867 gen_set_nzcv(tmp);
2868 dead_tmp(tmp);
2869 } else {
2870 store_reg(s, rd, tmp);
2871 }
2872 } else {
2873 /* arm->vfp */
2874 tmp = load_reg(s, rd);
2875 if (insn & (1 << 21)) {
2876 rn >>= 1;
2877 /* system register */
2878 switch (rn) {
2879 case ARM_VFP_FPSID:
2880 case ARM_VFP_MVFR0:
2881 case ARM_VFP_MVFR1:
2882 /* Writes are ignored. */
2883 break;
2884 case ARM_VFP_FPSCR:
2885 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2886 dead_tmp(tmp);
2887 gen_lookup_tb(s);
2888 break;
2889 case ARM_VFP_FPEXC:
2890 if (IS_USER(s))
2891 return 1;
2892 store_cpu_field(tmp, vfp.xregs[rn]);
2893 gen_lookup_tb(s);
2894 break;
2895 case ARM_VFP_FPINST:
2896 case ARM_VFP_FPINST2:
2897 store_cpu_field(tmp, vfp.xregs[rn]);
2898 break;
2899 default:
2900 return 1;
2901 }
2902 } else {
2903 gen_vfp_msr(tmp);
2904 gen_mov_vreg_F0(0, rn);
2905 }
2906 }
2907 }
2908 } else {
2909 /* data processing */
2910 /* The opcode is in bits 23, 21, 20 and 6. */
2911 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2912 if (dp) {
2913 if (op == 15) {
2914 /* rn is opcode */
2915 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2916 } else {
2917 /* rn is register number */
2918 VFP_DREG_N(rn, insn);
2919 }
2920
2921 if (op == 15 && (rn == 15 || rn > 17)) {
2922 /* Integer or single precision destination. */
2923 rd = VFP_SREG_D(insn);
2924 } else {
2925 VFP_DREG_D(rd, insn);
2926 }
2927
2928 if (op == 15 && (rn == 16 || rn == 17)) {
2929 /* Integer source. */
2930 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
2931 } else {
2932 VFP_DREG_M(rm, insn);
2933 }
2934 } else {
2935 rn = VFP_SREG_N(insn);
2936 if (op == 15 && rn == 15) {
2937 /* Double precision destination. */
2938 VFP_DREG_D(rd, insn);
2939 } else {
2940 rd = VFP_SREG_D(insn);
2941 }
2942 rm = VFP_SREG_M(insn);
2943 }
2944
2945 veclen = env->vfp.vec_len;
2946 if (op == 15 && rn > 3)
2947 veclen = 0;
2948
2949 /* Shut up compiler warnings. */
2950 delta_m = 0;
2951 delta_d = 0;
2952 bank_mask = 0;
2953
2954 if (veclen > 0) {
2955 if (dp)
2956 bank_mask = 0xc;
2957 else
2958 bank_mask = 0x18;
2959
2960 /* Figure out what type of vector operation this is. */
2961 if ((rd & bank_mask) == 0) {
2962 /* scalar */
2963 veclen = 0;
2964 } else {
2965 if (dp)
2966 delta_d = (env->vfp.vec_stride >> 1) + 1;
2967 else
2968 delta_d = env->vfp.vec_stride + 1;
2969
2970 if ((rm & bank_mask) == 0) {
2971 /* mixed scalar/vector */
2972 delta_m = 0;
2973 } else {
2974 /* vector */
2975 delta_m = delta_d;
2976 }
2977 }
2978 }
2979
2980 /* Load the initial operands. */
2981 if (op == 15) {
2982 switch (rn) {
2983 case 16:
2984 case 17:
2985 /* Integer source */
2986 gen_mov_F0_vreg(0, rm);
2987 break;
2988 case 8:
2989 case 9:
2990 /* Compare */
2991 gen_mov_F0_vreg(dp, rd);
2992 gen_mov_F1_vreg(dp, rm);
2993 break;
2994 case 10:
2995 case 11:
2996 /* Compare with zero */
2997 gen_mov_F0_vreg(dp, rd);
2998 gen_vfp_F1_ld0(dp);
2999 break;
3000 case 20:
3001 case 21:
3002 case 22:
3003 case 23:
3004 /* Source and destination the same. */
3005 gen_mov_F0_vreg(dp, rd);
3006 break;
3007 default:
3008 /* One source operand. */
3009 gen_mov_F0_vreg(dp, rm);
3010 break;
3011 }
3012 } else {
3013 /* Two source operands. */
3014 gen_mov_F0_vreg(dp, rn);
3015 gen_mov_F1_vreg(dp, rm);
3016 }
3017
3018 for (;;) {
3019 /* Perform the calculation. */
3020 switch (op) {
3021 case 0: /* mac: fd + (fn * fm) */
3022 gen_vfp_mul(dp);
3023 gen_mov_F1_vreg(dp, rd);
3024 gen_vfp_add(dp);
3025 break;
3026 case 1: /* nmac: fd - (fn * fm) */
3027 gen_vfp_mul(dp);
3028 gen_vfp_neg(dp);
3029 gen_mov_F1_vreg(dp, rd);
3030 gen_vfp_add(dp);
3031 break;
3032 case 2: /* msc: -fd + (fn * fm) */
3033 gen_vfp_mul(dp);
3034 gen_mov_F1_vreg(dp, rd);
3035 gen_vfp_sub(dp);
3036 break;
3037 case 3: /* nmsc: -fd - (fn * fm) */
3038 gen_vfp_mul(dp);
3039 gen_vfp_neg(dp);
3040 gen_mov_F1_vreg(dp, rd);
3041 gen_vfp_sub(dp);
3042 break;
3043 case 4: /* mul: fn * fm */
3044 gen_vfp_mul(dp);
3045 break;
3046 case 5: /* nmul: -(fn * fm) */
3047 gen_vfp_mul(dp);
3048 gen_vfp_neg(dp);
3049 break;
3050 case 6: /* add: fn + fm */
3051 gen_vfp_add(dp);
3052 break;
3053 case 7: /* sub: fn - fm */
3054 gen_vfp_sub(dp);
3055 break;
3056 case 8: /* div: fn / fm */
3057 gen_vfp_div(dp);
3058 break;
3059 case 14: /* fconst */
3060 if (!arm_feature(env, ARM_FEATURE_VFP3))
3061 return 1;
3062
3063 n = (insn << 12) & 0x80000000;
3064 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3065 if (dp) {
3066 if (i & 0x40)
3067 i |= 0x3f80;
3068 else
3069 i |= 0x4000;
3070 n |= i << 16;
3071 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3072 } else {
3073 if (i & 0x40)
3074 i |= 0x780;
3075 else
3076 i |= 0x800;
3077 n |= i << 19;
3078 tcg_gen_movi_i32(cpu_F0s, n);
3079 }
3080 break;
3081 case 15: /* extension space */
3082 switch (rn) {
3083 case 0: /* cpy */
3084 /* no-op */
3085 break;
3086 case 1: /* abs */
3087 gen_vfp_abs(dp);
3088 break;
3089 case 2: /* neg */
3090 gen_vfp_neg(dp);
3091 break;
3092 case 3: /* sqrt */
3093 gen_vfp_sqrt(dp);
3094 break;
3095 case 8: /* cmp */
3096 gen_vfp_cmp(dp);
3097 break;
3098 case 9: /* cmpe */
3099 gen_vfp_cmpe(dp);
3100 break;
3101 case 10: /* cmpz */
3102 gen_vfp_cmp(dp);
3103 break;
3104 case 11: /* cmpez */
3105 gen_vfp_F1_ld0(dp);
3106 gen_vfp_cmpe(dp);
3107 break;
3108 case 15: /* single<->double conversion */
3109 if (dp)
3110 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3111 else
3112 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3113 break;
3114 case 16: /* fuito */
3115 gen_vfp_uito(dp);
3116 break;
3117 case 17: /* fsito */
3118 gen_vfp_sito(dp);
3119 break;
3120 case 20: /* fshto */
3121 if (!arm_feature(env, ARM_FEATURE_VFP3))
3122 return 1;
3123 gen_vfp_shto(dp, rm);
3124 break;
3125 case 21: /* fslto */
3126 if (!arm_feature(env, ARM_FEATURE_VFP3))
3127 return 1;
3128 gen_vfp_slto(dp, rm);
3129 break;
3130 case 22: /* fuhto */
3131 if (!arm_feature(env, ARM_FEATURE_VFP3))
3132 return 1;
3133 gen_vfp_uhto(dp, rm);
3134 break;
3135 case 23: /* fulto */
3136 if (!arm_feature(env, ARM_FEATURE_VFP3))
3137 return 1;
3138 gen_vfp_ulto(dp, rm);
3139 break;
3140 case 24: /* ftoui */
3141 gen_vfp_toui(dp);
3142 break;
3143 case 25: /* ftouiz */
3144 gen_vfp_touiz(dp);
3145 break;
3146 case 26: /* ftosi */
3147 gen_vfp_tosi(dp);
3148 break;
3149 case 27: /* ftosiz */
3150 gen_vfp_tosiz(dp);
3151 break;
3152 case 28: /* ftosh */
3153 if (!arm_feature(env, ARM_FEATURE_VFP3))
3154 return 1;
3155 gen_vfp_tosh(dp, rm);
3156 break;
3157 case 29: /* ftosl */
3158 if (!arm_feature(env, ARM_FEATURE_VFP3))
3159 return 1;
3160 gen_vfp_tosl(dp, rm);
3161 break;
3162 case 30: /* ftouh */
3163 if (!arm_feature(env, ARM_FEATURE_VFP3))
3164 return 1;
3165 gen_vfp_touh(dp, rm);
3166 break;
3167 case 31: /* ftoul */
3168 if (!arm_feature(env, ARM_FEATURE_VFP3))
3169 return 1;
3170 gen_vfp_toul(dp, rm);
3171 break;
3172 default: /* undefined */
3173 printf ("rn:%d\n", rn);
3174 return 1;
3175 }
3176 break;
3177 default: /* undefined */
3178 printf ("op:%d\n", op);
3179 return 1;
3180 }
3181
3182 /* Write back the result. */
3183 if (op == 15 && (rn >= 8 && rn <= 11))
3184 ; /* Comparison, do nothing. */
3185 else if (op == 15 && rn > 17)
3186 /* Integer result. */
3187 gen_mov_vreg_F0(0, rd);
3188 else if (op == 15 && rn == 15)
3189 /* conversion */
3190 gen_mov_vreg_F0(!dp, rd);
3191 else
3192 gen_mov_vreg_F0(dp, rd);
3193
3194 /* break out of the loop if we have finished */
3195 if (veclen == 0)
3196 break;
3197
3198 if (op == 15 && delta_m == 0) {
3199 /* single source one-many */
3200 while (veclen--) {
3201 rd = ((rd + delta_d) & (bank_mask - 1))
3202 | (rd & bank_mask);
3203 gen_mov_vreg_F0(dp, rd);
3204 }
3205 break;
3206 }
3207 /* Setup the next operands. */
3208 veclen--;
3209 rd = ((rd + delta_d) & (bank_mask - 1))
3210 | (rd & bank_mask);
3211
3212 if (op == 15) {
3213 /* One source operand. */
3214 rm = ((rm + delta_m) & (bank_mask - 1))
3215 | (rm & bank_mask);
3216 gen_mov_F0_vreg(dp, rm);
3217 } else {
3218 /* Two source operands. */
3219 rn = ((rn + delta_d) & (bank_mask - 1))
3220 | (rn & bank_mask);
3221 gen_mov_F0_vreg(dp, rn);
3222 if (delta_m) {
3223 rm = ((rm + delta_m) & (bank_mask - 1))
3224 | (rm & bank_mask);
3225 gen_mov_F1_vreg(dp, rm);
3226 }
3227 }
3228 }
3229 }
3230 break;
3231 case 0xc:
3232 case 0xd:
3233 if (dp && (insn & 0x03e00000) == 0x00400000) {
3234 /* two-register transfer */
3235 rn = (insn >> 16) & 0xf;
3236 rd = (insn >> 12) & 0xf;
3237 if (dp) {
3238 VFP_DREG_M(rm, insn);
3239 } else {
3240 rm = VFP_SREG_M(insn);
3241 }
3242
3243 if (insn & ARM_CP_RW_BIT) {
3244 /* vfp->arm */
3245 if (dp) {
3246 gen_mov_F0_vreg(0, rm * 2);
3247 tmp = gen_vfp_mrs();
3248 store_reg(s, rd, tmp);
3249 gen_mov_F0_vreg(0, rm * 2 + 1);
3250 tmp = gen_vfp_mrs();
3251 store_reg(s, rn, tmp);
3252 } else {
3253 gen_mov_F0_vreg(0, rm);
3254 tmp = gen_vfp_mrs();
3255 store_reg(s, rn, tmp);
3256 gen_mov_F0_vreg(0, rm + 1);
3257 tmp = gen_vfp_mrs();
3258 store_reg(s, rd, tmp);
3259 }
3260 } else {
3261 /* arm->vfp */
3262 if (dp) {
3263 tmp = load_reg(s, rd);
3264 gen_vfp_msr(tmp);
3265 gen_mov_vreg_F0(0, rm * 2);
3266 tmp = load_reg(s, rn);
3267 gen_vfp_msr(tmp);
3268 gen_mov_vreg_F0(0, rm * 2 + 1);
3269 } else {
3270 tmp = load_reg(s, rn);
3271 gen_vfp_msr(tmp);
3272 gen_mov_vreg_F0(0, rm);
3273 tmp = load_reg(s, rd);
3274 gen_vfp_msr(tmp);
3275 gen_mov_vreg_F0(0, rm + 1);
3276 }
3277 }
3278 } else {
3279 /* Load/store */
3280 rn = (insn >> 16) & 0xf;
3281 if (dp)
3282 VFP_DREG_D(rd, insn);
3283 else
3284 rd = VFP_SREG_D(insn);
3285 if (s->thumb && rn == 15) {
3286 gen_op_movl_T1_im(s->pc & ~2);
3287 } else {
3288 gen_movl_T1_reg(s, rn);
3289 }
3290 if ((insn & 0x01200000) == 0x01000000) {
3291 /* Single load/store */
3292 offset = (insn & 0xff) << 2;
3293 if ((insn & (1 << 23)) == 0)
3294 offset = -offset;
3295 gen_op_addl_T1_im(offset);
3296 if (insn & (1 << 20)) {
3297 gen_vfp_ld(s, dp);
3298 gen_mov_vreg_F0(dp, rd);
3299 } else {
3300 gen_mov_F0_vreg(dp, rd);
3301 gen_vfp_st(s, dp);
3302 }
3303 } else {
3304 /* load/store multiple */
3305 if (dp)
3306 n = (insn >> 1) & 0x7f;
3307 else
3308 n = insn & 0xff;
3309
3310 if (insn & (1 << 24)) /* pre-decrement */
3311 gen_op_addl_T1_im(-((insn & 0xff) << 2));
3312
3313 if (dp)
3314 offset = 8;
3315 else
3316 offset = 4;
3317 for (i = 0; i < n; i++) {
3318 if (insn & ARM_CP_RW_BIT) {
3319 /* load */
3320 gen_vfp_ld(s, dp);
3321 gen_mov_vreg_F0(dp, rd + i);
3322 } else {
3323 /* store */
3324 gen_mov_F0_vreg(dp, rd + i);
3325 gen_vfp_st(s, dp);
3326 }
3327 gen_op_addl_T1_im(offset);
3328 }
3329 if (insn & (1 << 21)) {
3330 /* writeback */
3331 if (insn & (1 << 24))
3332 offset = -offset * n;
3333 else if (dp && (insn & 1))
3334 offset = 4;
3335 else
3336 offset = 0;
3337
3338 if (offset != 0)
3339 gen_op_addl_T1_im(offset);
3340 gen_movl_reg_T1(s, rn);
3341 }
3342 }
3343 }
3344 break;
3345 default:
3346 /* Should never happen. */
3347 return 1;
3348 }
3349 return 0;
3350 }
3351
3352 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3353 {
3354 TranslationBlock *tb;
3355
3356 tb = s->tb;
3357 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3358 tcg_gen_goto_tb(n);
3359 gen_set_pc_im(dest);
3360 tcg_gen_exit_tb((long)tb + n);
3361 } else {
3362 gen_set_pc_im(dest);
3363 tcg_gen_exit_tb(0);
3364 }
3365 }
3366
3367 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3368 {
3369 if (unlikely(s->singlestep_enabled)) {
3370 /* An indirect jump so that we still trigger the debug exception. */
3371 if (s->thumb)
3372 dest |= 1;
3373 gen_bx_im(s, dest);
3374 } else {
3375 gen_goto_tb(s, 0, dest);
3376 s->is_jmp = DISAS_TB_JUMP;
3377 }
3378 }
3379
3380 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3381 {
3382 if (x)
3383 tcg_gen_sari_i32(t0, t0, 16);
3384 else
3385 gen_sxth(t0);
3386 if (y)
3387 tcg_gen_sari_i32(t1, t1, 16);
3388 else
3389 gen_sxth(t1);
3390 tcg_gen_mul_i32(t0, t0, t1);
3391 }
3392
3393 /* Return the mask of PSR bits set by a MSR instruction. */
3394 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3395 uint32_t mask;
3396
3397 mask = 0;
3398 if (flags & (1 << 0))
3399 mask |= 0xff;
3400 if (flags & (1 << 1))
3401 mask |= 0xff00;
3402 if (flags & (1 << 2))
3403 mask |= 0xff0000;
3404 if (flags & (1 << 3))
3405 mask |= 0xff000000;
3406
3407 /* Mask out undefined bits. */
3408 mask &= ~CPSR_RESERVED;
3409 if (!arm_feature(env, ARM_FEATURE_V6))
3410 mask &= ~(CPSR_E | CPSR_GE);
3411 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3412 mask &= ~CPSR_IT;
3413 /* Mask out execution state bits. */
3414 if (!spsr)
3415 mask &= ~CPSR_EXEC;
3416 /* Mask out privileged bits. */
3417 if (IS_USER(s))
3418 mask &= CPSR_USER;
3419 return mask;
3420 }
3421
3422 /* Returns nonzero if access to the PSR is not permitted. */
3423 static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr)
3424 {
3425 TCGv tmp;
3426 if (spsr) {
3427 /* ??? This is also undefined in system mode. */
3428 if (IS_USER(s))
3429 return 1;
3430
3431 tmp = load_cpu_field(spsr);
3432 tcg_gen_andi_i32(tmp, tmp, ~mask);
3433 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
3434 tcg_gen_or_i32(tmp, tmp, cpu_T[0]);
3435 store_cpu_field(tmp, spsr);
3436 } else {
3437 gen_set_cpsr(cpu_T[0], mask);
3438 }
3439 gen_lookup_tb(s);
3440 return 0;
3441 }
3442
3443 /* Generate an old-style exception return. */
3444 static void gen_exception_return(DisasContext *s)
3445 {
3446 TCGv tmp;
3447 gen_movl_reg_T0(s, 15);
3448 tmp = load_cpu_field(spsr);
3449 gen_set_cpsr(tmp, 0xffffffff);
3450 dead_tmp(tmp);
3451 s->is_jmp = DISAS_UPDATE;
3452 }
3453
3454 /* Generate a v6 exception return. Marks both values as dead. */
3455 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3456 {
3457 gen_set_cpsr(cpsr, 0xffffffff);
3458 dead_tmp(cpsr);
3459 store_reg(s, 15, pc);
3460 s->is_jmp = DISAS_UPDATE;
3461 }
3462
3463 static inline void
3464 gen_set_condexec (DisasContext *s)
3465 {
3466 if (s->condexec_mask) {
3467 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3468 TCGv tmp = new_tmp();
3469 tcg_gen_movi_i32(tmp, val);
3470 store_cpu_field(tmp, condexec_bits);
3471 }
3472 }
3473
3474 static void gen_nop_hint(DisasContext *s, int val)
3475 {
3476 switch (val) {
3477 case 3: /* wfi */
3478 gen_set_pc_im(s->pc);
3479 s->is_jmp = DISAS_WFI;
3480 break;
3481 case 2: /* wfe */
3482 case 4: /* sev */
3483 /* TODO: Implement SEV and WFE. May help SMP performance. */
3484 default: /* nop */
3485 break;
3486 }
3487 }
3488
3489 /* These macros help make the code more readable when migrating from the
3490 old dyngen helpers. They should probably be removed when
3491 T0/T1 are removed. */
3492 #define CPU_T001 cpu_T[0], cpu_T[0], cpu_T[1]
3493 #define CPU_T0E01 cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]
3494
3495 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3496
3497 static inline int gen_neon_add(int size)
3498 {
3499 switch (size) {
3500 case 0: gen_helper_neon_add_u8(CPU_T001); break;
3501 case 1: gen_helper_neon_add_u16(CPU_T001); break;
3502 case 2: gen_op_addl_T0_T1(); break;
3503 default: return 1;
3504 }
3505 return 0;
3506 }
3507
3508 static inline void gen_neon_rsb(int size)
3509 {
3510 switch (size) {
3511 case 0: gen_helper_neon_sub_u8(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3512 case 1: gen_helper_neon_sub_u16(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3513 case 2: gen_op_rsbl_T0_T1(); break;
3514 default: return;
3515 }
3516 }
3517
3518 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3519 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3520 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3521 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3522 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3523
3524 /* FIXME: This is wrong. They set the wrong overflow bit. */
3525 #define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3526 #define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3527 #define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3528 #define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3529
3530 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3531 switch ((size << 1) | u) { \
3532 case 0: \
3533 gen_helper_neon_##name##_s8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3534 break; \
3535 case 1: \
3536 gen_helper_neon_##name##_u8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3537 break; \
3538 case 2: \
3539 gen_helper_neon_##name##_s16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3540 break; \
3541 case 3: \
3542 gen_helper_neon_##name##_u16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3543 break; \
3544 case 4: \
3545 gen_helper_neon_##name##_s32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3546 break; \
3547 case 5: \
3548 gen_helper_neon_##name##_u32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \
3549 break; \
3550 default: return 1; \
3551 }} while (0)
3552
3553 #define GEN_NEON_INTEGER_OP(name) do { \
3554 switch ((size << 1) | u) { \
3555 case 0: \
3556 gen_helper_neon_##name##_s8(cpu_T[0], cpu_T[0], cpu_T[1]); \
3557 break; \
3558 case 1: \
3559 gen_helper_neon_##name##_u8(cpu_T[0], cpu_T[0], cpu_T[1]); \
3560 break; \
3561 case 2: \
3562 gen_helper_neon_##name##_s16(cpu_T[0], cpu_T[0], cpu_T[1]); \
3563 break; \
3564 case 3: \
3565 gen_helper_neon_##name##_u16(cpu_T[0], cpu_T[0], cpu_T[1]); \
3566 break; \
3567 case 4: \
3568 gen_helper_neon_##name##_s32(cpu_T[0], cpu_T[0], cpu_T[1]); \
3569 break; \
3570 case 5: \
3571 gen_helper_neon_##name##_u32(cpu_T[0], cpu_T[0], cpu_T[1]); \
3572 break; \
3573 default: return 1; \
3574 }} while (0)
3575
3576 static inline void
3577 gen_neon_movl_scratch_T0(int scratch)
3578 {
3579 uint32_t offset;
3580
3581 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
3582 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
3583 }
3584
3585 static inline void
3586 gen_neon_movl_scratch_T1(int scratch)
3587 {
3588 uint32_t offset;
3589
3590 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
3591 tcg_gen_st_i32(cpu_T[1], cpu_env, offset);
3592 }
3593
3594 static inline void
3595 gen_neon_movl_T0_scratch(int scratch)
3596 {
3597 uint32_t offset;
3598
3599 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
3600 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
3601 }
3602
3603 static inline void
3604 gen_neon_movl_T1_scratch(int scratch)
3605 {
3606 uint32_t offset;
3607
3608 offset = offsetof(CPUARMState, vfp.scratch[scratch]);
3609 tcg_gen_ld_i32(cpu_T[1], cpu_env, offset);
3610 }
3611
3612 static inline void gen_neon_get_scalar(int size, int reg)
3613 {
3614 if (size == 1) {
3615 NEON_GET_REG(T0, reg >> 1, reg & 1);
3616 } else {
3617 NEON_GET_REG(T0, reg >> 2, (reg >> 1) & 1);
3618 if (reg & 1)
3619 gen_neon_dup_low16(cpu_T[0]);
3620 else
3621 gen_neon_dup_high16(cpu_T[0]);
3622 }
3623 }
3624
3625 static void gen_neon_unzip(int reg, int q, int tmp, int size)
3626 {
3627 int n;
3628
3629 for (n = 0; n < q + 1; n += 2) {
3630 NEON_GET_REG(T0, reg, n);
3631 NEON_GET_REG(T0, reg, n + n);
3632 switch (size) {
3633 case 0: gen_helper_neon_unzip_u8(); break;
3634 case 1: gen_helper_neon_zip_u16(); break; /* zip and unzip are the same. */
3635 case 2: /* no-op */; break;
3636 default: abort();
3637 }
3638 gen_neon_movl_scratch_T0(tmp + n);
3639 gen_neon_movl_scratch_T1(tmp + n + 1);
3640 }
3641 }
3642
3643 static struct {
3644 int nregs;
3645 int interleave;
3646 int spacing;
3647 } neon_ls_element_type[11] = {
3648 {4, 4, 1},
3649 {4, 4, 2},
3650 {4, 1, 1},
3651 {4, 2, 1},
3652 {3, 3, 1},
3653 {3, 3, 2},
3654 {3, 1, 1},
3655 {1, 1, 1},
3656 {2, 2, 1},
3657 {2, 2, 2},
3658 {2, 1, 1}
3659 };
3660
3661 /* Translate a NEON load/store element instruction. Return nonzero if the
3662 instruction is invalid. */
3663 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3664 {
3665 int rd, rn, rm;
3666 int op;
3667 int nregs;
3668 int interleave;
3669 int stride;
3670 int size;
3671 int reg;
3672 int pass;
3673 int load;
3674 int shift;
3675 int n;
3676 TCGv tmp;
3677 TCGv tmp2;
3678
3679 if (!vfp_enabled(env))
3680 return 1;
3681 VFP_DREG_D(rd, insn);
3682 rn = (insn >> 16) & 0xf;
3683 rm = insn & 0xf;
3684 load = (insn & (1 << 21)) != 0;
3685 if ((insn & (1 << 23)) == 0) {
3686 /* Load store all elements. */
3687 op = (insn >> 8) & 0xf;
3688 size = (insn >> 6) & 3;
3689 if (op > 10 || size == 3)
3690 return 1;
3691 nregs = neon_ls_element_type[op].nregs;
3692 interleave = neon_ls_element_type[op].interleave;
3693 gen_movl_T1_reg(s, rn);
3694 stride = (1 << size) * interleave;
3695 for (reg = 0; reg < nregs; reg++) {
3696 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3697 gen_movl_T1_reg(s, rn);
3698 gen_op_addl_T1_im((1 << size) * reg);
3699 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3700 gen_movl_T1_reg(s, rn);
3701 gen_op_addl_T1_im(1 << size);
3702 }
3703 for (pass = 0; pass < 2; pass++) {
3704 if (size == 2) {
3705 if (load) {
3706 tmp = gen_ld32(cpu_T[1], IS_USER(s));
3707 neon_store_reg(rd, pass, tmp);
3708 } else {
3709 tmp = neon_load_reg(rd, pass);
3710 gen_st32(tmp, cpu_T[1], IS_USER(s));
3711 }
3712 gen_op_addl_T1_im(stride);
3713 } else if (size == 1) {
3714 if (load) {
3715 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
3716 gen_op_addl_T1_im(stride);
3717 tmp2 = gen_ld16u(cpu_T[1], IS_USER(s));
3718 gen_op_addl_T1_im(stride);
3719 gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
3720 dead_tmp(tmp2);
3721 neon_store_reg(rd, pass, tmp);
3722 } else {
3723 tmp = neon_load_reg(rd, pass);
3724 tmp2 = new_tmp();
3725 tcg_gen_shri_i32(tmp2, tmp, 16);
3726 gen_st16(tmp, cpu_T[1], IS_USER(s));
3727 gen_op_addl_T1_im(stride);
3728 gen_st16(tmp2, cpu_T[1], IS_USER(s));
3729 gen_op_addl_T1_im(stride);
3730 }
3731 } else /* size == 0 */ {
3732 if (load) {
3733 TCGV_UNUSED(tmp2);
3734 for (n = 0; n < 4; n++) {
3735 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
3736 gen_op_addl_T1_im(stride);
3737 if (n == 0) {
3738 tmp2 = tmp;
3739 } else {
3740 gen_bfi(tmp2, tmp2, tmp, n * 8, 0xff);
3741 dead_tmp(tmp);
3742 }
3743 }
3744 neon_store_reg(rd, pass, tmp2);
3745 } else {
3746 tmp2 = neon_load_reg(rd, pass);
3747 for (n = 0; n < 4; n++) {
3748 tmp = new_tmp();
3749 if (n == 0) {
3750 tcg_gen_mov_i32(tmp, tmp2);
3751 } else {
3752 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3753 }
3754 gen_st8(tmp, cpu_T[1], IS_USER(s));
3755 gen_op_addl_T1_im(stride);
3756 }
3757 dead_tmp(tmp2);
3758 }
3759 }
3760 }
3761 rd += neon_ls_element_type[op].spacing;
3762 }
3763 stride = nregs * 8;
3764 } else {
3765 size = (insn >> 10) & 3;
3766 if (size == 3) {
3767 /* Load single element to all lanes. */
3768 if (!load)
3769 return 1;
3770 size = (insn >> 6) & 3;
3771 nregs = ((insn >> 8) & 3) + 1;
3772 stride = (insn & (1 << 5)) ? 2 : 1;
3773 gen_movl_T1_reg(s, rn);
3774 for (reg = 0; reg < nregs; reg++) {
3775 switch (size) {
3776 case 0:
3777 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
3778 gen_neon_dup_u8(tmp, 0);
3779 break;
3780 case 1:
3781 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
3782 gen_neon_dup_low16(tmp);
3783 break;
3784 case 2:
3785 tmp = gen_ld32(cpu_T[0], IS_USER(s));
3786 break;
3787 case 3:
3788 return 1;
3789 default: /* Avoid compiler warnings. */
3790 abort();
3791 }
3792 gen_op_addl_T1_im(1 << size);
3793 tmp2 = new_tmp();
3794 tcg_gen_mov_i32(tmp2, tmp);
3795 neon_store_reg(rd, 0, tmp2);
3796 neon_store_reg(rd, 1, tmp);
3797 rd += stride;
3798 }
3799 stride = (1 << size) * nregs;
3800 } else {
3801 /* Single element. */
3802 pass = (insn >> 7) & 1;
3803 switch (size) {
3804 case 0:
3805 shift = ((insn >> 5) & 3) * 8;
3806 stride = 1;
3807 break;
3808 case 1:
3809 shift = ((insn >> 6) & 1) * 16;
3810 stride = (insn & (1 << 5)) ? 2 : 1;
3811 break;
3812 case 2:
3813 shift = 0;
3814 stride = (insn & (1 << 6)) ? 2 : 1;
3815 break;
3816 default:
3817 abort();
3818 }
3819 nregs = ((insn >> 8) & 3) + 1;
3820 gen_movl_T1_reg(s, rn);
3821 for (reg = 0; reg < nregs; reg++) {
3822 if (load) {
3823 switch (size) {
3824 case 0:
3825 tmp = gen_ld8u(cpu_T[1], IS_USER(s));
3826 break;
3827 case 1:
3828 tmp = gen_ld16u(cpu_T[1], IS_USER(s));
3829 break;
3830 case 2:
3831 tmp = gen_ld32(cpu_T[1], IS_USER(s));
3832 break;
3833 default: /* Avoid compiler warnings. */
3834 abort();
3835 }
3836 if (size != 2) {
3837 tmp2 = neon_load_reg(rd, pass);
3838 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3839 dead_tmp(tmp2);
3840 }
3841 neon_store_reg(rd, pass, tmp);
3842 } else { /* Store */
3843 tmp = neon_load_reg(rd, pass);
3844 if (shift)
3845 tcg_gen_shri_i32(tmp, tmp, shift);
3846 switch (size) {
3847 case 0:
3848 gen_st8(tmp, cpu_T[1], IS_USER(s));
3849 break;
3850 case 1:
3851 gen_st16(tmp, cpu_T[1], IS_USER(s));
3852 break;
3853 case 2:
3854 gen_st32(tmp, cpu_T[1], IS_USER(s));
3855 break;
3856 }
3857 }
3858 rd += stride;
3859 gen_op_addl_T1_im(1 << size);
3860 }
3861 stride = nregs * (1 << size);
3862 }
3863 }
3864 if (rm != 15) {
3865 TCGv base;
3866
3867 base = load_reg(s, rn);
3868 if (rm == 13) {
3869 tcg_gen_addi_i32(base, base, stride);
3870 } else {
3871 TCGv index;
3872 index = load_reg(s, rm);
3873 tcg_gen_add_i32(base, base, index);
3874 dead_tmp(index);
3875 }
3876 store_reg(s, rn, base);
3877 }
3878 return 0;
3879 }
3880
3881 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
3882 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
3883 {
3884 tcg_gen_and_i32(t, t, c);
3885 tcg_gen_bic_i32(f, f, c);
3886 tcg_gen_or_i32(dest, t, f);
3887 }
3888
3889 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
3890 {
3891 switch (size) {
3892 case 0: gen_helper_neon_narrow_u8(dest, src); break;
3893 case 1: gen_helper_neon_narrow_u16(dest, src); break;
3894 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
3895 default: abort();
3896 }
3897 }
3898
3899 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
3900 {
3901 switch (size) {
3902 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
3903 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
3904 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
3905 default: abort();
3906 }
3907 }
3908
3909 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
3910 {
3911 switch (size) {
3912 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
3913 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
3914 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
3915 default: abort();
3916 }
3917 }
3918
3919 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
3920 int q, int u)
3921 {
3922 if (q) {
3923 if (u) {
3924 switch (size) {
3925 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
3926 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
3927 default: abort();
3928 }
3929 } else {
3930 switch (size) {
3931 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
3932 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
3933 default: abort();
3934 }
3935 }
3936 } else {
3937 if (u) {
3938 switch (size) {
3939 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
3940 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
3941 default: abort();
3942 }
3943 } else {
3944 switch (size) {
3945 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
3946 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
3947 default: abort();
3948 }
3949 }
3950 }
3951 }
3952
3953 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
3954 {
3955 if (u) {
3956 switch (size) {
3957 case 0: gen_helper_neon_widen_u8(dest, src); break;
3958 case 1: gen_helper_neon_widen_u16(dest, src); break;
3959 case 2: tcg_gen_extu_i32_i64(dest, src); break;
3960 default: abort();
3961 }
3962 } else {
3963 switch (size) {
3964 case 0: gen_helper_neon_widen_s8(dest, src); break;
3965 case 1: gen_helper_neon_widen_s16(dest, src); break;
3966 case 2: tcg_gen_ext_i32_i64(dest, src); break;
3967 default: abort();
3968 }
3969 }
3970 dead_tmp(src);
3971 }
3972
3973 static inline void gen_neon_addl(int size)
3974 {
3975 switch (size) {
3976 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
3977 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
3978 case 2: tcg_gen_add_i64(CPU_V001); break;
3979 default: abort();
3980 }
3981 }
3982
3983 static inline void gen_neon_subl(int size)
3984 {
3985 switch (size) {
3986 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
3987 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
3988 case 2: tcg_gen_sub_i64(CPU_V001); break;
3989 default: abort();
3990 }
3991 }
3992
3993 static inline void gen_neon_negl(TCGv_i64 var, int size)
3994 {
3995 switch (size) {
3996 case 0: gen_helper_neon_negl_u16(var, var); break;
3997 case 1: gen_helper_neon_negl_u32(var, var); break;
3998 case 2: gen_helper_neon_negl_u64(var, var); break;
3999 default: abort();
4000 }
4001 }
4002
4003 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4004 {
4005 switch (size) {
4006 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4007 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4008 default: abort();
4009 }
4010 }
4011
4012 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4013 {
4014 TCGv_i64 tmp;
4015
4016 switch ((size << 1) | u) {
4017 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4018 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4019 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4020 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4021 case 4:
4022 tmp = gen_muls_i64_i32(a, b);
4023 tcg_gen_mov_i64(dest, tmp);
4024 break;
4025 case 5:
4026 tmp = gen_mulu_i64_i32(a, b);
4027 tcg_gen_mov_i64(dest, tmp);
4028 break;
4029 default: abort();
4030 }
4031 if (size < 2) {
4032 dead_tmp(b);
4033 dead_tmp(a);
4034 }
4035 }
4036
4037 /* Translate a NEON data processing instruction. Return nonzero if the
4038 instruction is invalid.
4039 We process data in a mixture of 32-bit and 64-bit chunks.
4040 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4041
4042 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4043 {
4044 int op;
4045 int q;
4046 int rd, rn, rm;
4047 int size;
4048 int shift;
4049 int pass;
4050 int count;
4051 int pairwise;
4052 int u;
4053 int n;
4054 uint32_t imm;
4055 TCGv tmp;
4056 TCGv tmp2;
4057 TCGv tmp3;
4058 TCGv_i64 tmp64;
4059
4060 if (!vfp_enabled(env))
4061 return 1;
4062 q = (insn & (1 << 6)) != 0;
4063 u = (insn >> 24) & 1;
4064 VFP_DREG_D(rd, insn);
4065 VFP_DREG_N(rn, insn);
4066 VFP_DREG_M(rm, insn);
4067 size = (insn >> 20) & 3;
4068 if ((insn & (1 << 23)) == 0) {
4069 /* Three register same length. */
4070 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4071 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4072 || op == 10 || op == 11 || op == 16)) {
4073 /* 64-bit element instructions. */
4074 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4075 neon_load_reg64(cpu_V0, rn + pass);
4076 neon_load_reg64(cpu_V1, rm + pass);
4077 switch (op) {
4078 case 1: /* VQADD */
4079 if (u) {
4080 gen_helper_neon_add_saturate_u64(CPU_V001);
4081 } else {
4082 gen_helper_neon_add_saturate_s64(CPU_V001);
4083 }
4084 break;
4085 case 5: /* VQSUB */
4086 if (u) {
4087 gen_helper_neon_sub_saturate_u64(CPU_V001);
4088 } else {
4089 gen_helper_neon_sub_saturate_s64(CPU_V001);
4090 }
4091 break;
4092 case 8: /* VSHL */
4093 if (u) {
4094 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4095 } else {
4096 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4097 }
4098 break;
4099 case 9: /* VQSHL */
4100 if (u) {
4101 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4102 cpu_V0, cpu_V0);
4103 } else {
4104 gen_helper_neon_qshl_s64(cpu_V1, cpu_env,
4105 cpu_V1, cpu_V0);
4106 }
4107 break;
4108 case 10: /* VRSHL */
4109 if (u) {
4110 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4111 } else {
4112 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4113 }
4114 break;
4115 case 11: /* VQRSHL */
4116 if (u) {
4117 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4118 cpu_V1, cpu_V0);
4119 } else {
4120 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4121 cpu_V1, cpu_V0);
4122 }
4123 break;
4124 case 16:
4125 if (u) {
4126 tcg_gen_sub_i64(CPU_V001);
4127 } else {
4128 tcg_gen_add_i64(CPU_V001);
4129 }
4130 break;
4131 default:
4132 abort();
4133 }
4134 neon_store_reg64(cpu_V0, rd + pass);
4135 }
4136 return 0;
4137 }
4138 switch (op) {
4139 case 8: /* VSHL */
4140 case 9: /* VQSHL */
4141 case 10: /* VRSHL */
4142 case 11: /* VQRSHL */
4143 {
4144 int rtmp;
4145 /* Shift instruction operands are reversed. */
4146 rtmp = rn;
4147 rn = rm;
4148 rm = rtmp;
4149 pairwise = 0;
4150 }
4151 break;
4152 case 20: /* VPMAX */
4153 case 21: /* VPMIN */
4154 case 23: /* VPADD */
4155 pairwise = 1;
4156 break;
4157 case 26: /* VPADD (float) */
4158 pairwise = (u && size < 2);
4159 break;
4160 case 30: /* VPMIN/VPMAX (float) */
4161 pairwise = u;
4162 break;
4163 default:
4164 pairwise = 0;
4165 break;
4166 }
4167 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4168
4169 if (pairwise) {
4170 /* Pairwise. */
4171 if (q)
4172 n = (pass & 1) * 2;
4173 else
4174 n = 0;
4175 if (pass < q + 1) {
4176 NEON_GET_REG(T0, rn, n);
4177 NEON_GET_REG(T1, rn, n + 1);
4178 } else {
4179 NEON_GET_REG(T0, rm, n);
4180 NEON_GET_REG(T1, rm, n + 1);
4181 }
4182 } else {
4183 /* Elementwise. */
4184 NEON_GET_REG(T0, rn, pass);
4185 NEON_GET_REG(T1, rm, pass);
4186 }
4187 switch (op) {
4188 case 0: /* VHADD */
4189 GEN_NEON_INTEGER_OP(hadd);
4190 break;
4191 case 1: /* VQADD */
4192 GEN_NEON_INTEGER_OP_ENV(qadd);
4193 break;
4194 case 2: /* VRHADD */
4195 GEN_NEON_INTEGER_OP(rhadd);
4196 break;
4197 case 3: /* Logic ops. */
4198 switch ((u << 2) | size) {
4199 case 0: /* VAND */
4200 gen_op_andl_T0_T1();
4201 break;
4202 case 1: /* BIC */
4203 gen_op_bicl_T0_T1();
4204 break;
4205 case 2: /* VORR */
4206 gen_op_orl_T0_T1();
4207 break;
4208 case 3: /* VORN */
4209 gen_op_notl_T1();
4210 gen_op_orl_T0_T1();
4211 break;
4212 case 4: /* VEOR */
4213 gen_op_xorl_T0_T1();
4214 break;
4215 case 5: /* VBSL */
4216 tmp = neon_load_reg(rd, pass);
4217 gen_neon_bsl(cpu_T[0], cpu_T[0], cpu_T[1], tmp);
4218 dead_tmp(tmp);
4219 break;
4220 case 6: /* VBIT */
4221 tmp = neon_load_reg(rd, pass);
4222 gen_neon_bsl(cpu_T[0], cpu_T[0], tmp, cpu_T[1]);
4223 dead_tmp(tmp);
4224 break;
4225 case 7: /* VBIF */
4226 tmp = neon_load_reg(rd, pass);
4227 gen_neon_bsl(cpu_T[0], tmp, cpu_T[0], cpu_T[1]);
4228 dead_tmp(tmp);
4229 break;
4230 }
4231 break;
4232 case 4: /* VHSUB */
4233 GEN_NEON_INTEGER_OP(hsub);
4234 break;
4235 case 5: /* VQSUB */
4236 GEN_NEON_INTEGER_OP_ENV(qsub);
4237 break;
4238 case 6: /* VCGT */
4239 GEN_NEON_INTEGER_OP(cgt);
4240 break;
4241 case 7: /* VCGE */
4242 GEN_NEON_INTEGER_OP(cge);
4243 break;
4244 case 8: /* VSHL */
4245 GEN_NEON_INTEGER_OP(shl);
4246 break;
4247 case 9: /* VQSHL */
4248 GEN_NEON_INTEGER_OP_ENV(qshl);
4249 break;
4250 case 10: /* VRSHL */
4251 GEN_NEON_INTEGER_OP(rshl);
4252 break;
4253 case 11: /* VQRSHL */
4254 GEN_NEON_INTEGER_OP_ENV(qrshl);
4255 break;
4256 case 12: /* VMAX */
4257 GEN_NEON_INTEGER_OP(max);
4258 break;
4259 case 13: /* VMIN */
4260 GEN_NEON_INTEGER_OP(min);
4261 break;
4262 case 14: /* VABD */
4263 GEN_NEON_INTEGER_OP(abd);
4264 break;
4265 case 15: /* VABA */
4266 GEN_NEON_INTEGER_OP(abd);
4267 NEON_GET_REG(T1, rd, pass);
4268 gen_neon_add(size);
4269 break;
4270 case 16:
4271 if (!u) { /* VADD */
4272 if (gen_neon_add(size))
4273 return 1;
4274 } else { /* VSUB */
4275 switch (size) {
4276 case 0: gen_helper_neon_sub_u8(CPU_T001); break;
4277 case 1: gen_helper_neon_sub_u16(CPU_T001); break;
4278 case 2: gen_op_subl_T0_T1(); break;
4279 default: return 1;
4280 }
4281 }
4282 break;
4283 case 17:
4284 if (!u) { /* VTST */
4285 switch (size) {
4286 case 0: gen_helper_neon_tst_u8(CPU_T001); break;
4287 case 1: gen_helper_neon_tst_u16(CPU_T001); break;
4288 case 2: gen_helper_neon_tst_u32(CPU_T001); break;
4289 default: return 1;
4290 }
4291 } else { /* VCEQ */
4292 switch (size) {
4293 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
4294 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
4295 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
4296 default: return 1;
4297 }
4298 }
4299 break;
4300 case 18: /* Multiply. */
4301 switch (size) {
4302 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4303 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
4304 case 2: gen_op_mul_T0_T1(); break;
4305 default: return 1;
4306 }
4307 NEON_GET_REG(T1, rd, pass);
4308 if (u) { /* VMLS */
4309 gen_neon_rsb(size);
4310 } else { /* VMLA */
4311 gen_neon_add(size);
4312 }
4313 break;
4314 case 19: /* VMUL */
4315 if (u) { /* polynomial */
4316 gen_helper_neon_mul_p8(CPU_T001);
4317 } else { /* Integer */
4318 switch (size) {
4319 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4320 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
4321 case 2: gen_op_mul_T0_T1(); break;
4322 default: return 1;
4323 }
4324 }
4325 break;
4326 case 20: /* VPMAX */
4327 GEN_NEON_INTEGER_OP(pmax);
4328 break;
4329 case 21: /* VPMIN */
4330 GEN_NEON_INTEGER_OP(pmin);
4331 break;
4332 case 22: /* Hultiply high. */
4333 if (!u) { /* VQDMULH */
4334 switch (size) {
4335 case 1: gen_helper_neon_qdmulh_s16(CPU_T0E01); break;
4336 case 2: gen_helper_neon_qdmulh_s32(CPU_T0E01); break;
4337 default: return 1;
4338 }
4339 } else { /* VQRDHMUL */
4340 switch (size) {
4341 case 1: gen_helper_neon_qrdmulh_s16(CPU_T0E01); break;
4342 case 2: gen_helper_neon_qrdmulh_s32(CPU_T0E01); break;
4343 default: return 1;
4344 }
4345 }
4346 break;
4347 case 23: /* VPADD */
4348 if (u)
4349 return 1;
4350 switch (size) {
4351 case 0: gen_helper_neon_padd_u8(CPU_T001); break;
4352 case 1: gen_helper_neon_padd_u16(CPU_T001); break;
4353 case 2: gen_op_addl_T0_T1(); break;
4354 default: return 1;
4355 }
4356 break;
4357 case 26: /* Floating point arithnetic. */
4358 switch ((u << 2) | size) {
4359 case 0: /* VADD */
4360 gen_helper_neon_add_f32(CPU_T001);
4361 break;
4362 case 2: /* VSUB */
4363 gen_helper_neon_sub_f32(CPU_T001);
4364 break;
4365 case 4: /* VPADD */
4366 gen_helper_neon_add_f32(CPU_T001);
4367 break;
4368 case 6: /* VABD */
4369 gen_helper_neon_abd_f32(CPU_T001);
4370 break;
4371 default:
4372 return 1;
4373 }
4374 break;
4375 case 27: /* Float multiply. */
4376 gen_helper_neon_mul_f32(CPU_T001);
4377 if (!u) {
4378 NEON_GET_REG(T1, rd, pass);
4379 if (size == 0) {
4380 gen_helper_neon_add_f32(CPU_T001);
4381 } else {
4382 gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]);
4383 }
4384 }
4385 break;
4386 case 28: /* Float compare. */
4387 if (!u) {
4388 gen_helper_neon_ceq_f32(CPU_T001);
4389 } else {
4390 if (size == 0)
4391 gen_helper_neon_cge_f32(CPU_T001);
4392 else
4393 gen_helper_neon_cgt_f32(CPU_T001);
4394 }
4395 break;
4396 case 29: /* Float compare absolute. */
4397 if (!u)
4398 return 1;
4399 if (size == 0)
4400 gen_helper_neon_acge_f32(CPU_T001);
4401 else
4402 gen_helper_neon_acgt_f32(CPU_T001);
4403 break;
4404 case 30: /* Float min/max. */
4405 if (size == 0)
4406 gen_helper_neon_max_f32(CPU_T001);
4407 else
4408 gen_helper_neon_min_f32(CPU_T001);
4409 break;
4410 case 31:
4411 if (size == 0)
4412 gen_helper_recps_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env);
4413 else
4414 gen_helper_rsqrts_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env);
4415 break;
4416 default:
4417 abort();
4418 }
4419 /* Save the result. For elementwise operations we can put it
4420 straight into the destination register. For pairwise operations
4421 we have to be careful to avoid clobbering the source operands. */
4422 if (pairwise && rd == rm) {
4423 gen_neon_movl_scratch_T0(pass);
4424 } else {
4425 NEON_SET_REG(T0, rd, pass);
4426 }
4427
4428 } /* for pass */
4429 if (pairwise && rd == rm) {
4430 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4431 gen_neon_movl_T0_scratch(pass);
4432 NEON_SET_REG(T0, rd, pass);
4433 }
4434 }
4435 /* End of 3 register same size operations. */
4436 } else if (insn & (1 << 4)) {
4437 if ((insn & 0x00380080) != 0) {
4438 /* Two registers and shift. */
4439 op = (insn >> 8) & 0xf;
4440 if (insn & (1 << 7)) {
4441 /* 64-bit shift. */
4442 size = 3;
4443 } else {
4444 size = 2;
4445 while ((insn & (1 << (size + 19))) == 0)
4446 size--;
4447 }
4448 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4449 /* To avoid excessive dumplication of ops we implement shift
4450 by immediate using the variable shift operations. */
4451 if (op < 8) {
4452 /* Shift by immediate:
4453 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4454 /* Right shifts are encoded as N - shift, where N is the
4455 element size in bits. */
4456 if (op <= 4)
4457 shift = shift - (1 << (size + 3));
4458 if (size == 3) {
4459 count = q + 1;
4460 } else {
4461 count = q ? 4: 2;
4462 }
4463 switch (size) {
4464 case 0:
4465 imm = (uint8_t) shift;
4466 imm |= imm << 8;
4467 imm |= imm << 16;
4468 break;
4469 case 1:
4470 imm = (uint16_t) shift;
4471 imm |= imm << 16;
4472 break;
4473 case 2:
4474 case 3:
4475 imm = shift;
4476 break;
4477 default:
4478 abort();
4479 }
4480
4481 for (pass = 0; pass < count; pass++) {
4482 if (size == 3) {
4483 neon_load_reg64(cpu_V0, rm + pass);
4484 tcg_gen_movi_i64(cpu_V1, imm);
4485 switch (op) {
4486 case 0: /* VSHR */
4487 case 1: /* VSRA */
4488 if (u)
4489 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4490 else
4491 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4492 break;
4493 case 2: /* VRSHR */
4494 case 3: /* VRSRA */
4495 if (u)
4496 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4497 else
4498 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4499 break;
4500 case 4: /* VSRI */
4501 if (!u)
4502 return 1;
4503 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4504 break;
4505 case 5: /* VSHL, VSLI */
4506 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4507 break;
4508 case 6: /* VQSHL */
4509 if (u)
4510 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4511 else
4512 gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4513 break;
4514 case 7: /* VQSHLU */
4515 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4516 break;
4517 }
4518 if (op == 1 || op == 3) {
4519 /* Accumulate. */
4520 neon_load_reg64(cpu_V0, rd + pass);
4521 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4522 } else if (op == 4 || (op == 5 && u)) {
4523 /* Insert */
4524 cpu_abort(env, "VS[LR]I.64 not implemented");
4525 }
4526 neon_store_reg64(cpu_V0, rd + pass);
4527 } else { /* size < 3 */
4528 /* Operands in T0 and T1. */
4529 gen_op_movl_T1_im(imm);
4530 NEON_GET_REG(T0, rm, pass);
4531 switch (op) {
4532 case 0: /* VSHR */
4533 case 1: /* VSRA */
4534 GEN_NEON_INTEGER_OP(shl);
4535 break;
4536 case 2: /* VRSHR */
4537 case 3: /* VRSRA */
4538 GEN_NEON_INTEGER_OP(rshl);
4539 break;
4540 case 4: /* VSRI */
4541 if (!u)
4542 return 1;
4543 GEN_NEON_INTEGER_OP(shl);
4544 break;
4545 case 5: /* VSHL, VSLI */
4546 switch (size) {
4547 case 0: gen_helper_neon_shl_u8(CPU_T001); break;
4548 case 1: gen_helper_neon_shl_u16(CPU_T001); break;
4549 case 2: gen_helper_neon_shl_u32(CPU_T001); break;
4550 default: return 1;
4551 }
4552 break;
4553 case 6: /* VQSHL */
4554 GEN_NEON_INTEGER_OP_ENV(qshl);
4555 break;
4556 case 7: /* VQSHLU */
4557 switch (size) {
4558 case 0: gen_helper_neon_qshl_u8(CPU_T0E01); break;
4559 case 1: gen_helper_neon_qshl_u16(CPU_T0E01); break;
4560 case 2: gen_helper_neon_qshl_u32(CPU_T0E01); break;
4561 default: return 1;
4562 }
4563 break;
4564 }
4565
4566 if (op == 1 || op == 3) {
4567 /* Accumulate. */
4568 NEON_GET_REG(T1, rd, pass);
4569 gen_neon_add(size);
4570 } else if (op == 4 || (op == 5 && u)) {
4571 /* Insert */
4572 switch (size) {
4573 case 0:
4574 if (op == 4)
4575 imm = 0xff >> -shift;
4576 else
4577 imm = (uint8_t)(0xff << shift);
4578 imm |= imm << 8;
4579 imm |= imm << 16;
4580 break;
4581 case 1:
4582 if (op == 4)
4583 imm = 0xffff >> -shift;
4584 else
4585 imm = (uint16_t)(0xffff << shift);
4586 imm |= imm << 16;
4587 break;
4588 case 2:
4589 if (op == 4)
4590 imm = 0xffffffffu >> -shift;
4591 else
4592 imm = 0xffffffffu << shift;
4593 break;
4594 default:
4595 abort();
4596 }
4597 tmp = neon_load_reg(rd, pass);
4598 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], imm);
4599 tcg_gen_andi_i32(tmp, tmp, ~imm);
4600 tcg_gen_or_i32(cpu_T[0], cpu_T[0], tmp);
4601 }
4602 NEON_SET_REG(T0, rd, pass);
4603 }
4604 } /* for pass */
4605 } else if (op < 10) {
4606 /* Shift by immediate and narrow:
4607 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4608 shift = shift - (1 << (size + 3));
4609 size++;
4610 switch (size) {
4611 case 1:
4612 imm = (uint16_t)shift;
4613 imm |= imm << 16;
4614 tmp2 = tcg_const_i32(imm);
4615 TCGV_UNUSED_I64(tmp64);
4616 break;
4617 case 2:
4618 imm = (uint32_t)shift;
4619 tmp2 = tcg_const_i32(imm);
4620 TCGV_UNUSED_I64(tmp64);
4621 break;
4622 case 3:
4623 tmp64 = tcg_const_i64(shift);
4624 TCGV_UNUSED(tmp2);
4625 break;
4626 default:
4627 abort();
4628 }
4629
4630 for (pass = 0; pass < 2; pass++) {
4631 if (size == 3) {
4632 neon_load_reg64(cpu_V0, rm + pass);
4633 if (q) {
4634 if (u)
4635 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
4636 else
4637 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
4638 } else {
4639 if (u)
4640 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
4641 else
4642 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
4643 }
4644 } else {
4645 tmp = neon_load_reg(rm + pass, 0);
4646 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4647 tmp3 = neon_load_reg(rm + pass, 1);
4648 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4649 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4650 dead_tmp(tmp);
4651 dead_tmp(tmp3);
4652 }
4653 tmp = new_tmp();
4654 if (op == 8 && !u) {
4655 gen_neon_narrow(size - 1, tmp, cpu_V0);
4656 } else {
4657 if (op == 8)
4658 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4659 else
4660 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4661 }
4662 if (pass == 0) {
4663 tmp2 = tmp;
4664 } else {
4665 neon_store_reg(rd, 0, tmp2);
4666 neon_store_reg(rd, 1, tmp);
4667 }
4668 } /* for pass */
4669 } else if (op == 10) {
4670 /* VSHLL */
4671 if (q || size == 3)
4672 return 1;
4673 tmp = neon_load_reg(rm, 0);
4674 tmp2 = neon_load_reg(rm, 1);
4675 for (pass = 0; pass < 2; pass++) {
4676 if (pass == 1)
4677 tmp = tmp2;
4678
4679 gen_neon_widen(cpu_V0, tmp, size, u);
4680
4681 if (shift != 0) {
4682 /* The shift is less than the width of the source
4683 type, so we can just shift the whole register. */
4684 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4685 if (size < 2 || !u) {
4686 uint64_t imm64;
4687 if (size == 0) {
4688 imm = (0xffu >> (8 - shift));
4689 imm |= imm << 16;
4690 } else {
4691 imm = 0xffff >> (16 - shift);
4692 }
4693 imm64 = imm | (((uint64_t)imm) << 32);
4694 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
4695 }
4696 }
4697 neon_store_reg64(cpu_V0, rd + pass);
4698 }
4699 } else if (op == 15 || op == 16) {
4700 /* VCVT fixed-point. */
4701 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4702 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4703 if (op & 1) {
4704 if (u)
4705 gen_vfp_ulto(0, shift);
4706 else
4707 gen_vfp_slto(0, shift);
4708 } else {
4709 if (u)
4710 gen_vfp_toul(0, shift);
4711 else
4712 gen_vfp_tosl(0, shift);
4713 }
4714 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
4715 }
4716 } else {
4717 return 1;
4718 }
4719 } else { /* (insn & 0x00380080) == 0 */
4720 int invert;
4721
4722 op = (insn >> 8) & 0xf;
4723 /* One register and immediate. */
4724 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4725 invert = (insn & (1 << 5)) != 0;
4726 switch (op) {
4727 case 0: case 1:
4728 /* no-op */
4729 break;
4730 case 2: case 3:
4731 imm <<= 8;
4732 break;
4733 case 4: case 5:
4734 imm <<= 16;
4735 break;
4736 case 6: case 7:
4737 imm <<= 24;
4738 break;
4739 case 8: case 9:
4740 imm |= imm << 16;
4741 break;
4742 case 10: case 11:
4743 imm = (imm << 8) | (imm << 24);
4744 break;
4745 case 12:
4746 imm = (imm < 8) | 0xff;
4747 break;
4748 case 13:
4749 imm = (imm << 16) | 0xffff;
4750 break;
4751 case 14:
4752 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4753 if (invert)
4754 imm = ~imm;
4755 break;
4756 case 15:
4757 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4758 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4759 break;
4760 }
4761 if (invert)
4762 imm = ~imm;
4763
4764 if (op != 14 || !invert)
4765 gen_op_movl_T1_im(imm);
4766
4767 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4768 if (op & 1 && op < 12) {
4769 tmp = neon_load_reg(rd, pass);
4770 if (invert) {
4771 /* The immediate value has already been inverted, so
4772 BIC becomes AND. */
4773 tcg_gen_andi_i32(tmp, tmp, imm);
4774 } else {
4775 tcg_gen_ori_i32(tmp, tmp, imm);
4776 }
4777 } else {
4778 /* VMOV, VMVN. */
4779 tmp = new_tmp();
4780 if (op == 14 && invert) {
4781 uint32_t val;
4782 val = 0;
4783 for (n = 0; n < 4; n++) {
4784 if (imm & (1 << (n + (pass & 1) * 4)))
4785 val |= 0xff << (n * 8);
4786 }
4787 tcg_gen_movi_i32(tmp, val);
4788 } else {
4789 tcg_gen_movi_i32(tmp, imm);
4790 }
4791 }
4792 neon_store_reg(rd, pass, tmp);
4793 }
4794 }
4795 } else { /* (insn & 0x00800010 == 0x00800000) */
4796 if (size != 3) {
4797 op = (insn >> 8) & 0xf;
4798 if ((insn & (1 << 6)) == 0) {
4799 /* Three registers of different lengths. */
4800 int src1_wide;
4801 int src2_wide;
4802 int prewiden;
4803 /* prewiden, src1_wide, src2_wide */
4804 static const int neon_3reg_wide[16][3] = {
4805 {1, 0, 0}, /* VADDL */
4806 {1, 1, 0}, /* VADDW */
4807 {1, 0, 0}, /* VSUBL */
4808 {1, 1, 0}, /* VSUBW */
4809 {0, 1, 1}, /* VADDHN */
4810 {0, 0, 0}, /* VABAL */
4811 {0, 1, 1}, /* VSUBHN */
4812 {0, 0, 0}, /* VABDL */
4813 {0, 0, 0}, /* VMLAL */
4814 {0, 0, 0}, /* VQDMLAL */
4815 {0, 0, 0}, /* VMLSL */
4816 {0, 0, 0}, /* VQDMLSL */
4817 {0, 0, 0}, /* Integer VMULL */
4818 {0, 0, 0}, /* VQDMULL */
4819 {0, 0, 0} /* Polynomial VMULL */
4820 };
4821
4822 prewiden = neon_3reg_wide[op][0];
4823 src1_wide = neon_3reg_wide[op][1];
4824 src2_wide = neon_3reg_wide[op][2];
4825
4826 if (size == 0 && (op == 9 || op == 11 || op == 13))
4827 return 1;
4828
4829 /* Avoid overlapping operands. Wide source operands are
4830 always aligned so will never overlap with wide
4831 destinations in problematic ways. */
4832 if (rd == rm && !src2_wide) {
4833 NEON_GET_REG(T0, rm, 1);
4834 gen_neon_movl_scratch_T0(2);
4835 } else if (rd == rn && !src1_wide) {
4836 NEON_GET_REG(T0, rn, 1);
4837 gen_neon_movl_scratch_T0(2);
4838 }
4839 TCGV_UNUSED(tmp3);
4840 for (pass = 0; pass < 2; pass++) {
4841 if (src1_wide) {
4842 neon_load_reg64(cpu_V0, rn + pass);
4843 TCGV_UNUSED(tmp);
4844 } else {
4845 if (pass == 1 && rd == rn) {
4846 gen_neon_movl_T0_scratch(2);
4847 tmp = new_tmp();
4848 tcg_gen_mov_i32(tmp, cpu_T[0]);
4849 } else {
4850 tmp = neon_load_reg(rn, pass);
4851 }
4852 if (prewiden) {
4853 gen_neon_widen(cpu_V0, tmp, size, u);
4854 }
4855 }
4856 if (src2_wide) {
4857 neon_load_reg64(cpu_V1, rm + pass);
4858 TCGV_UNUSED(tmp2);
4859 } else {
4860 if (pass == 1 && rd == rm) {
4861 gen_neon_movl_T0_scratch(2);
4862 tmp2 = new_tmp();
4863 tcg_gen_mov_i32(tmp2, cpu_T[0]);
4864 } else {
4865 tmp2 = neon_load_reg(rm, pass);
4866 }
4867 if (prewiden) {
4868 gen_neon_widen(cpu_V1, tmp2, size, u);
4869 }
4870 }
4871 switch (op) {
4872 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
4873 gen_neon_addl(size);
4874 break;
4875 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */
4876 gen_neon_subl(size);
4877 break;
4878 case 5: case 7: /* VABAL, VABDL */
4879 switch ((size << 1) | u) {
4880 case 0:
4881 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
4882 break;
4883 case 1:
4884 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
4885 break;
4886 case 2:
4887 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
4888 break;
4889 case 3:
4890 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
4891 break;
4892 case 4:
4893 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
4894 break;
4895 case 5:
4896 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
4897 break;
4898 default: abort();
4899 }
4900 dead_tmp(tmp2);
4901 dead_tmp(tmp);
4902 break;
4903 case 8: case 9: case 10: case 11: case 12: case 13:
4904 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
4905 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
4906 break;
4907 case 14: /* Polynomial VMULL */
4908 cpu_abort(env, "Polynomial VMULL not implemented");
4909
4910 default: /* 15 is RESERVED. */
4911 return 1;
4912 }
4913 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
4914 /* Accumulate. */
4915 if (op == 10 || op == 11) {
4916 gen_neon_negl(cpu_V0, size);
4917 }
4918
4919 if (op != 13) {
4920 neon_load_reg64(cpu_V1, rd + pass);
4921 }
4922
4923 switch (op) {
4924 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
4925 gen_neon_addl(size);
4926 break;
4927 case 9: case 11: /* VQDMLAL, VQDMLSL */
4928 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4929 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
4930 break;
4931 /* Fall through. */
4932 case 13: /* VQDMULL */
4933 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4934 break;
4935 default:
4936 abort();
4937 }
4938 neon_store_reg64(cpu_V0, rd + pass);
4939 } else if (op == 4 || op == 6) {
4940 /* Narrowing operation. */
4941 tmp = new_tmp();
4942 if (u) {
4943 switch (size) {
4944 case 0:
4945 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
4946 break;
4947 case 1:
4948 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
4949 break;
4950 case 2:
4951 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
4952 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
4953 break;
4954 default: abort();
4955 }
4956 } else {
4957 switch (size) {
4958 case 0:
4959 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
4960 break;
4961 case 1:
4962 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
4963 break;
4964 case 2:
4965 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
4966 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
4967 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
4968 break;
4969 default: abort();
4970 }
4971 }
4972 if (pass == 0) {
4973 tmp3 = tmp;
4974 } else {
4975 neon_store_reg(rd, 0, tmp3);
4976 neon_store_reg(rd, 1, tmp);
4977 }
4978 } else {
4979 /* Write back the result. */
4980 neon_store_reg64(cpu_V0, rd + pass);
4981 }
4982 }
4983 } else {
4984 /* Two registers and a scalar. */
4985 switch (op) {
4986 case 0: /* Integer VMLA scalar */
4987 case 1: /* Float VMLA scalar */
4988 case 4: /* Integer VMLS scalar */
4989 case 5: /* Floating point VMLS scalar */
4990 case 8: /* Integer VMUL scalar */
4991 case 9: /* Floating point VMUL scalar */
4992 case 12: /* VQDMULH scalar */
4993 case 13: /* VQRDMULH scalar */
4994 gen_neon_get_scalar(size, rm);
4995 gen_neon_movl_scratch_T0(0);
4996 for (pass = 0; pass < (u ? 4 : 2); pass++) {
4997 if (pass != 0)
4998 gen_neon_movl_T0_scratch(0);
4999 NEON_GET_REG(T1, rn, pass);
5000 if (op == 12) {
5001 if (size == 1) {
5002 gen_helper_neon_qdmulh_s16(CPU_T0E01);
5003 } else {
5004 gen_helper_neon_qdmulh_s32(CPU_T0E01);
5005 }
5006 } else if (op == 13) {
5007 if (size == 1) {
5008 gen_helper_neon_qrdmulh_s16(CPU_T0E01);
5009 } else {
5010 gen_helper_neon_qrdmulh_s32(CPU_T0E01);
5011 }
5012 } else if (op & 1) {
5013 gen_helper_neon_mul_f32(CPU_T001);
5014 } else {
5015 switch (size) {
5016 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
5017 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
5018 case 2: gen_op_mul_T0_T1(); break;
5019 default: return 1;
5020 }
5021 }
5022 if (op < 8) {
5023 /* Accumulate. */
5024 NEON_GET_REG(T1, rd, pass);
5025 switch (op) {
5026 case 0:
5027 gen_neon_add(size);
5028 break;
5029 case 1:
5030 gen_helper_neon_add_f32(CPU_T001);
5031 break;
5032 case 4:
5033 gen_neon_rsb(size);
5034 break;
5035 case 5:
5036 gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]);
5037 break;
5038 default:
5039 abort();
5040 }
5041 }
5042 NEON_SET_REG(T0, rd, pass);
5043 }
5044 break;
5045 case 2: /* VMLAL sclar */
5046 case 3: /* VQDMLAL scalar */
5047 case 6: /* VMLSL scalar */
5048 case 7: /* VQDMLSL scalar */
5049 case 10: /* VMULL scalar */
5050 case 11: /* VQDMULL scalar */
5051 if (size == 0 && (op == 3 || op == 7 || op == 11))
5052 return 1;
5053
5054 gen_neon_get_scalar(size, rm);
5055 NEON_GET_REG(T1, rn, 1);
5056
5057 for (pass = 0; pass < 2; pass++) {
5058 if (pass == 0) {
5059 tmp = neon_load_reg(rn, 0);
5060 } else {
5061 tmp = new_tmp();
5062 tcg_gen_mov_i32(tmp, cpu_T[1]);
5063 }
5064 tmp2 = new_tmp();
5065 tcg_gen_mov_i32(tmp2, cpu_T[0]);
5066 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5067 if (op == 6 || op == 7) {
5068 gen_neon_negl(cpu_V0, size);
5069 }
5070 if (op != 11) {
5071 neon_load_reg64(cpu_V1, rd + pass);
5072 }
5073 switch (op) {
5074 case 2: case 6:
5075 gen_neon_addl(size);
5076 break;
5077 case 3: case 7:
5078 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5079 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5080 break;
5081 case 10:
5082 /* no-op */
5083 break;
5084 case 11:
5085 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5086 break;
5087 default:
5088 abort();
5089 }
5090 neon_store_reg64(cpu_V0, rd + pass);
5091 }
5092 break;
5093 default: /* 14 and 15 are RESERVED */
5094 return 1;
5095 }
5096 }
5097 } else { /* size == 3 */
5098 if (!u) {
5099 /* Extract. */
5100 imm = (insn >> 8) & 0xf;
5101 count = q + 1;
5102
5103 if (imm > 7 && !q)
5104 return 1;
5105
5106 if (imm == 0) {
5107 neon_load_reg64(cpu_V0, rn);
5108 if (q) {
5109 neon_load_reg64(cpu_V1, rn + 1);
5110 }
5111 } else if (imm == 8) {
5112 neon_load_reg64(cpu_V0, rn + 1);
5113 if (q) {
5114 neon_load_reg64(cpu_V1, rm);
5115 }
5116 } else if (q) {
5117 tmp64 = tcg_temp_new_i64();
5118 if (imm < 8) {
5119 neon_load_reg64(cpu_V0, rn);
5120 neon_load_reg64(tmp64, rn + 1);
5121 } else {
5122 neon_load_reg64(cpu_V0, rn + 1);
5123 neon_load_reg64(tmp64, rm);
5124 }
5125 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5126 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5127 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5128 if (imm < 8) {
5129 neon_load_reg64(cpu_V1, rm);
5130 } else {
5131 neon_load_reg64(cpu_V1, rm + 1);
5132 imm -= 8;
5133 }
5134 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5135 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5136 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5137 } else {
5138 /* BUGFIX */
5139 neon_load_reg64(cpu_V0, rn);
5140 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5141 neon_load_reg64(cpu_V1, rm);
5142 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5143 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5144 }
5145 neon_store_reg64(cpu_V0, rd);
5146 if (q) {
5147 neon_store_reg64(cpu_V1, rd + 1);
5148 }
5149 } else if ((insn & (1 << 11)) == 0) {
5150 /* Two register misc. */
5151 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5152 size = (insn >> 18) & 3;
5153 switch (op) {
5154 case 0: /* VREV64 */
5155 if (size == 3)
5156 return 1;
5157 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5158 NEON_GET_REG(T0, rm, pass * 2);
5159 NEON_GET_REG(T1, rm, pass * 2 + 1);
5160 switch (size) {
5161 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
5162 case 1: gen_swap_half(cpu_T[0]); break;
5163 case 2: /* no-op */ break;
5164 default: abort();
5165 }
5166 NEON_SET_REG(T0, rd, pass * 2 + 1);
5167 if (size == 2) {
5168 NEON_SET_REG(T1, rd, pass * 2);
5169 } else {
5170 gen_op_movl_T0_T1();
5171 switch (size) {
5172 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
5173 case 1: gen_swap_half(cpu_T[0]); break;
5174 default: abort();
5175 }
5176 NEON_SET_REG(T0, rd, pass * 2);
5177 }
5178 }
5179 break;
5180 case 4: case 5: /* VPADDL */
5181 case 12: case 13: /* VPADAL */
5182 if (size == 3)
5183 return 1;
5184 for (pass = 0; pass < q + 1; pass++) {
5185 tmp = neon_load_reg(rm, pass * 2);
5186 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5187 tmp = neon_load_reg(rm, pass * 2 + 1);
5188 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5189 switch (size) {
5190 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5191 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5192 case 2: tcg_gen_add_i64(CPU_V001); break;
5193 default: abort();
5194 }
5195 if (op >= 12) {
5196 /* Accumulate. */
5197 neon_load_reg64(cpu_V1, rd + pass);
5198 gen_neon_addl(size);
5199 }
5200 neon_store_reg64(cpu_V0, rd + pass);
5201 }
5202 break;
5203 case 33: /* VTRN */
5204 if (size == 2) {
5205 for (n = 0; n < (q ? 4 : 2); n += 2) {
5206 NEON_GET_REG(T0, rm, n);
5207 NEON_GET_REG(T1, rd, n + 1);
5208 NEON_SET_REG(T1, rm, n);
5209 NEON_SET_REG(T0, rd, n + 1);
5210 }
5211 } else {
5212 goto elementwise;
5213 }
5214 break;
5215 case 34: /* VUZP */
5216 /* Reg Before After
5217 Rd A3 A2 A1 A0 B2 B0 A2 A0
5218 Rm B3 B2 B1 B0 B3 B1 A3 A1
5219 */
5220 if (size == 3)
5221 return 1;
5222 gen_neon_unzip(rd, q, 0, size);
5223 gen_neon_unzip(rm, q, 4, size);
5224 if (q) {
5225 static int unzip_order_q[8] =
5226 {0, 2, 4, 6, 1, 3, 5, 7};
5227 for (n = 0; n < 8; n++) {
5228 int reg = (n < 4) ? rd : rm;
5229 gen_neon_movl_T0_scratch(unzip_order_q[n]);
5230 NEON_SET_REG(T0, reg, n % 4);
5231 }
5232 } else {
5233 static int unzip_order[4] =
5234 {0, 4, 1, 5};
5235 for (n = 0; n < 4; n++) {
5236 int reg = (n < 2) ? rd : rm;
5237 gen_neon_movl_T0_scratch(unzip_order[n]);
5238 NEON_SET_REG(T0, reg, n % 2);
5239 }
5240 }
5241 break;
5242 case 35: /* VZIP */
5243 /* Reg Before After
5244 Rd A3 A2 A1 A0 B1 A1 B0 A0
5245 Rm B3 B2 B1 B0 B3 A3 B2 A2
5246 */
5247 if (size == 3)
5248 return 1;
5249 count = (q ? 4 : 2);
5250 for (n = 0; n < count; n++) {
5251 NEON_GET_REG(T0, rd, n);
5252 NEON_GET_REG(T1, rd, n);
5253 switch (size) {
5254 case 0: gen_helper_neon_zip_u8(); break;
5255 case 1: gen_helper_neon_zip_u16(); break;
5256 case 2: /* no-op */; break;
5257 default: abort();
5258 }
5259 gen_neon_movl_scratch_T0(n * 2);
5260 gen_neon_movl_scratch_T1(n * 2 + 1);
5261 }
5262 for (n = 0; n < count * 2; n++) {
5263 int reg = (n < count) ? rd : rm;
5264 gen_neon_movl_T0_scratch(n);
5265 NEON_SET_REG(T0, reg, n % count);
5266 }
5267 break;
5268 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5269 if (size == 3)
5270 return 1;
5271 TCGV_UNUSED(tmp2);
5272 for (pass = 0; pass < 2; pass++) {
5273 neon_load_reg64(cpu_V0, rm + pass);
5274 tmp = new_tmp();
5275 if (op == 36 && q == 0) {
5276 gen_neon_narrow(size, tmp, cpu_V0);
5277 } else if (q) {
5278 gen_neon_narrow_satu(size, tmp, cpu_V0);
5279 } else {
5280 gen_neon_narrow_sats(size, tmp, cpu_V0);
5281 }
5282 if (pass == 0) {
5283 tmp2 = tmp;
5284 } else {
5285 neon_store_reg(rd, 0, tmp2);
5286 neon_store_reg(rd, 1, tmp);
5287 }
5288 }
5289 break;
5290 case 38: /* VSHLL */
5291 if (q || size == 3)
5292 return 1;
5293 tmp = neon_load_reg(rm, 0);
5294 tmp2 = neon_load_reg(rm, 1);
5295 for (pass = 0; pass < 2; pass++) {
5296 if (pass == 1)
5297 tmp = tmp2;
5298 gen_neon_widen(cpu_V0, tmp, size, 1);
5299 neon_store_reg64(cpu_V0, rd + pass);
5300 }
5301 break;
5302 default:
5303 elementwise:
5304 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5305 if (op == 30 || op == 31 || op >= 58) {
5306 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5307 neon_reg_offset(rm, pass));
5308 } else {
5309 NEON_GET_REG(T0, rm, pass);
5310 }
5311 switch (op) {
5312 case 1: /* VREV32 */
5313 switch (size) {
5314 case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
5315 case 1: gen_swap_half(cpu_T[0]); break;
5316 default: return 1;
5317 }
5318 break;
5319 case 2: /* VREV16 */
5320 if (size != 0)
5321 return 1;
5322 gen_rev16(cpu_T[0]);
5323 break;
5324 case 8: /* CLS */
5325 switch (size) {
5326 case 0: gen_helper_neon_cls_s8(cpu_T[0], cpu_T[0]); break;
5327 case 1: gen_helper_neon_cls_s16(cpu_T[0], cpu_T[0]); break;
5328 case 2: gen_helper_neon_cls_s32(cpu_T[0], cpu_T[0]); break;
5329 default: return 1;
5330 }
5331 break;
5332 case 9: /* CLZ */
5333 switch (size) {
5334 case 0: gen_helper_neon_clz_u8(cpu_T[0], cpu_T[0]); break;
5335 case 1: gen_helper_neon_clz_u16(cpu_T[0], cpu_T[0]); break;
5336 case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break;
5337 default: return 1;
5338 }
5339 break;
5340 case 10: /* CNT */
5341 if (size != 0)
5342 return 1;
5343 gen_helper_neon_cnt_u8(cpu_T[0], cpu_T[0]);
5344 break;
5345 case 11: /* VNOT */
5346 if (size != 0)
5347 return 1;
5348 gen_op_notl_T0();
5349 break;
5350 case 14: /* VQABS */
5351 switch (size) {
5352 case 0: gen_helper_neon_qabs_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5353 case 1: gen_helper_neon_qabs_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5354 case 2: gen_helper_neon_qabs_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
5355 default: return 1;
5356 }
5357 break;
5358 case 15: /* VQNEG */
5359 switch (size) {
5360 case 0: gen_helper_neon_qneg_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5361 case 1: gen_helper_neon_qneg_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5362 case 2: gen_helper_neon_qneg_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
5363 default: return 1;
5364 }
5365 break;
5366 case 16: case 19: /* VCGT #0, VCLE #0 */
5367 gen_op_movl_T1_im(0);
5368 switch(size) {
5369 case 0: gen_helper_neon_cgt_s8(CPU_T001); break;
5370 case 1: gen_helper_neon_cgt_s16(CPU_T001); break;
5371 case 2: gen_helper_neon_cgt_s32(CPU_T001); break;
5372 default: return 1;
5373 }
5374 if (op == 19)
5375 gen_op_notl_T0();
5376 break;
5377 case 17: case 20: /* VCGE #0, VCLT #0 */
5378 gen_op_movl_T1_im(0);
5379 switch(size) {
5380 case 0: gen_helper_neon_cge_s8(CPU_T001); break;
5381 case 1: gen_helper_neon_cge_s16(CPU_T001); break;
5382 case 2: gen_helper_neon_cge_s32(CPU_T001); break;
5383 default: return 1;
5384 }
5385 if (op == 20)
5386 gen_op_notl_T0();
5387 break;
5388 case 18: /* VCEQ #0 */
5389 gen_op_movl_T1_im(0);
5390 switch(size) {
5391 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
5392 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
5393 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
5394 default: return 1;
5395 }
5396 break;
5397 case 22: /* VABS */
5398 switch(size) {
5399 case 0: gen_helper_neon_abs_s8(cpu_T[0], cpu_T[0]); break;
5400 case 1: gen_helper_neon_abs_s16(cpu_T[0], cpu_T[0]); break;
5401 case 2: tcg_gen_abs_i32(cpu_T[0], cpu_T[0]); break;
5402 default: return 1;
5403 }
5404 break;
5405 case 23: /* VNEG */
5406 gen_op_movl_T1_im(0);
5407 if (size == 3)
5408 return 1;
5409 gen_neon_rsb(size);
5410 break;
5411 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5412 gen_op_movl_T1_im(0);
5413 gen_helper_neon_cgt_f32(CPU_T001);
5414 if (op == 27)
5415 gen_op_notl_T0();
5416 break;
5417 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5418 gen_op_movl_T1_im(0);
5419 gen_helper_neon_cge_f32(CPU_T001);
5420 if (op == 28)
5421 gen_op_notl_T0();
5422 break;
5423 case 26: /* Float VCEQ #0 */
5424 gen_op_movl_T1_im(0);
5425 gen_helper_neon_ceq_f32(CPU_T001);
5426 break;
5427 case 30: /* Float VABS */
5428 gen_vfp_abs(0);
5429 break;
5430 case 31: /* Float VNEG */
5431 gen_vfp_neg(0);
5432 break;
5433 case 32: /* VSWP */
5434 NEON_GET_REG(T1, rd, pass);
5435 NEON_SET_REG(T1, rm, pass);
5436 break;
5437 case 33: /* VTRN */
5438 NEON_GET_REG(T1, rd, pass);
5439 switch (size) {
5440 case 0: gen_helper_neon_trn_u8(); break;
5441 case 1: gen_helper_neon_trn_u16(); break;
5442 case 2: abort();
5443 default: return 1;
5444 }
5445 NEON_SET_REG(T1, rm, pass);
5446 break;
5447 case 56: /* Integer VRECPE */
5448 gen_helper_recpe_u32(cpu_T[0], cpu_T[0], cpu_env);
5449 break;
5450 case 57: /* Integer VRSQRTE */
5451 gen_helper_rsqrte_u32(cpu_T[0], cpu_T[0], cpu_env);
5452 break;
5453 case 58: /* Float VRECPE */
5454 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5455 break;
5456 case 59: /* Float VRSQRTE */
5457 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5458 break;
5459 case 60: /* VCVT.F32.S32 */
5460 gen_vfp_tosiz(0);
5461 break;
5462 case 61: /* VCVT.F32.U32 */
5463 gen_vfp_touiz(0);
5464 break;
5465 case 62: /* VCVT.S32.F32 */
5466 gen_vfp_sito(0);
5467 break;
5468 case 63: /* VCVT.U32.F32 */
5469 gen_vfp_uito(0);
5470 break;
5471 default:
5472 /* Reserved: 21, 29, 39-56 */
5473 return 1;
5474 }
5475 if (op == 30 || op == 31 || op >= 58) {
5476 tcg_gen_st_f32(cpu_F0s, cpu_env,
5477 neon_reg_offset(rd, pass));
5478 } else {
5479 NEON_SET_REG(T0, rd, pass);
5480 }
5481 }
5482 break;
5483 }
5484 } else if ((insn & (1 << 10)) == 0) {
5485 /* VTBL, VTBX. */
5486 n = ((insn >> 5) & 0x18) + 8;
5487 if (insn & (1 << 6)) {
5488 tmp = neon_load_reg(rd, 0);
5489 } else {
5490 tmp = new_tmp();
5491 tcg_gen_movi_i32(tmp, 0);
5492 }
5493 tmp2 = neon_load_reg(rm, 0);
5494 gen_helper_neon_tbl(tmp2, tmp2, tmp, tcg_const_i32(rn),
5495 tcg_const_i32(n));
5496 dead_tmp(tmp);
5497 if (insn & (1 << 6)) {
5498 tmp = neon_load_reg(rd, 1);
5499 } else {
5500 tmp = new_tmp();
5501 tcg_gen_movi_i32(tmp, 0);
5502 }
5503 tmp3 = neon_load_reg(rm, 1);
5504 gen_helper_neon_tbl(tmp3, tmp3, tmp, tcg_const_i32(rn),
5505 tcg_const_i32(n));
5506 neon_store_reg(rd, 0, tmp2);
5507 neon_store_reg(rd, 1, tmp3);
5508 dead_tmp(tmp);
5509 } else if ((insn & 0x380) == 0) {
5510 /* VDUP */
5511 if (insn & (1 << 19)) {
5512 NEON_SET_REG(T0, rm, 1);
5513 } else {
5514 NEON_SET_REG(T0, rm, 0);
5515 }
5516 if (insn & (1 << 16)) {
5517 gen_neon_dup_u8(cpu_T[0], ((insn >> 17) & 3) * 8);
5518 } else if (insn & (1 << 17)) {
5519 if ((insn >> 18) & 1)
5520 gen_neon_dup_high16(cpu_T[0]);
5521 else
5522 gen_neon_dup_low16(cpu_T[0]);
5523 }
5524 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5525 NEON_SET_REG(T0, rd, pass);
5526 }
5527 } else {
5528 return 1;
5529 }
5530 }
5531 }
5532 return 0;
5533 }
5534
5535 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5536 {
5537 int cpnum;
5538
5539 cpnum = (insn >> 8) & 0xf;
5540 if (arm_feature(env, ARM_FEATURE_XSCALE)
5541 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5542 return 1;
5543
5544 switch (cpnum) {
5545 case 0:
5546 case 1:
5547 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5548 return disas_iwmmxt_insn(env, s, insn);
5549 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5550 return disas_dsp_insn(env, s, insn);
5551 }
5552 return 1;
5553 case 10:
5554 case 11:
5555 return disas_vfp_insn (env, s, insn);
5556 case 15:
5557 return disas_cp15_insn (env, s, insn);
5558 default:
5559 /* Unknown coprocessor. See if the board has hooked it. */
5560 return disas_cp_insn (env, s, insn);
5561 }
5562 }
5563
5564
5565 /* Store a 64-bit value to a register pair. Clobbers val. */
5566 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5567 {
5568 TCGv tmp;
5569 tmp = new_tmp();
5570 tcg_gen_trunc_i64_i32(tmp, val);
5571 store_reg(s, rlow, tmp);
5572 tmp = new_tmp();
5573 tcg_gen_shri_i64(val, val, 32);
5574 tcg_gen_trunc_i64_i32(tmp, val);
5575 store_reg(s, rhigh, tmp);
5576 }
5577
5578 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5579 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5580 {
5581 TCGv_i64 tmp;
5582 TCGv tmp2;
5583
5584 /* Load value and extend to 64 bits. */
5585 tmp = tcg_temp_new_i64();
5586 tmp2 = load_reg(s, rlow);
5587 tcg_gen_extu_i32_i64(tmp, tmp2);
5588 dead_tmp(tmp2);
5589 tcg_gen_add_i64(val, val, tmp);
5590 }
5591
5592 /* load and add a 64-bit value from a register pair. */
5593 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5594 {
5595 TCGv_i64 tmp;
5596 TCGv tmpl;
5597 TCGv tmph;
5598
5599 /* Load 64-bit value rd:rn. */
5600 tmpl = load_reg(s, rlow);
5601 tmph = load_reg(s, rhigh);
5602 tmp = tcg_temp_new_i64();
5603 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5604 dead_tmp(tmpl);
5605 dead_tmp(tmph);
5606 tcg_gen_add_i64(val, val, tmp);
5607 }
5608
5609 /* Set N and Z flags from a 64-bit value. */
5610 static void gen_logicq_cc(TCGv_i64 val)
5611 {
5612 TCGv tmp = new_tmp();
5613 gen_helper_logicq_cc(tmp, val);
5614 gen_logic_CC(tmp);
5615 dead_tmp(tmp);
5616 }
5617
5618 static void disas_arm_insn(CPUState * env, DisasContext *s)
5619 {
5620 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
5621 TCGv tmp;
5622 TCGv tmp2;
5623 TCGv tmp3;
5624 TCGv addr;
5625 TCGv_i64 tmp64;
5626
5627 insn = ldl_code(s->pc);
5628 s->pc += 4;
5629
5630 /* M variants do not implement ARM mode. */
5631 if (IS_M(env))
5632 goto illegal_op;
5633 cond = insn >> 28;
5634 if (cond == 0xf){
5635 /* Unconditional instructions. */
5636 if (((insn >> 25) & 7) == 1) {
5637 /* NEON Data processing. */
5638 if (!arm_feature(env, ARM_FEATURE_NEON))
5639 goto illegal_op;
5640
5641 if (disas_neon_data_insn(env, s, insn))
5642 goto illegal_op;
5643 return;
5644 }
5645 if ((insn & 0x0f100000) == 0x04000000) {
5646 /* NEON load/store. */
5647 if (!arm_feature(env, ARM_FEATURE_NEON))
5648 goto illegal_op;
5649
5650 if (disas_neon_ls_insn(env, s, insn))
5651 goto illegal_op;
5652 return;
5653 }
5654 if ((insn & 0x0d70f000) == 0x0550f000)
5655 return; /* PLD */
5656 else if ((insn & 0x0ffffdff) == 0x01010000) {
5657 ARCH(6);
5658 /* setend */
5659 if (insn & (1 << 9)) {
5660 /* BE8 mode not implemented. */
5661 goto illegal_op;
5662 }
5663 return;
5664 } else if ((insn & 0x0fffff00) == 0x057ff000) {
5665 switch ((insn >> 4) & 0xf) {
5666 case 1: /* clrex */
5667 ARCH(6K);
5668 gen_helper_clrex(cpu_env);
5669 return;
5670 case 4: /* dsb */
5671 case 5: /* dmb */
5672 case 6: /* isb */
5673 ARCH(7);
5674 /* We don't emulate caches so these are a no-op. */
5675 return;
5676 default:
5677 goto illegal_op;
5678 }
5679 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
5680 /* srs */
5681 uint32_t offset;
5682 if (IS_USER(s))
5683 goto illegal_op;
5684 ARCH(6);
5685 op1 = (insn & 0x1f);
5686 if (op1 == (env->uncached_cpsr & CPSR_M)) {
5687 addr = load_reg(s, 13);
5688 } else {
5689 addr = new_tmp();
5690 gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op1));
5691 }
5692 i = (insn >> 23) & 3;
5693 switch (i) {
5694 case 0: offset = -4; break; /* DA */
5695 case 1: offset = -8; break; /* DB */
5696 case 2: offset = 0; break; /* IA */
5697 case 3: offset = 4; break; /* IB */
5698 default: abort();
5699 }
5700 if (offset)
5701 tcg_gen_addi_i32(addr, addr, offset);
5702 tmp = load_reg(s, 14);
5703 gen_st32(tmp, addr, 0);
5704 tmp = new_tmp();
5705 gen_helper_cpsr_read(tmp);
5706 tcg_gen_addi_i32(addr, addr, 4);
5707 gen_st32(tmp, addr, 0);
5708 if (insn & (1 << 21)) {
5709 /* Base writeback. */
5710 switch (i) {
5711 case 0: offset = -8; break;
5712 case 1: offset = -4; break;
5713 case 2: offset = 4; break;
5714 case 3: offset = 0; break;
5715 default: abort();
5716 }
5717 if (offset)
5718 tcg_gen_addi_i32(addr, tmp, offset);
5719 if (op1 == (env->uncached_cpsr & CPSR_M)) {
5720 gen_movl_reg_T1(s, 13);
5721 } else {
5722 gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]);
5723 }
5724 } else {
5725 dead_tmp(addr);
5726 }
5727 } else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
5728 /* rfe */
5729 uint32_t offset;
5730 if (IS_USER(s))
5731 goto illegal_op;
5732 ARCH(6);
5733 rn = (insn >> 16) & 0xf;
5734 addr = load_reg(s, rn);
5735 i = (insn >> 23) & 3;
5736 switch (i) {
5737 case 0: offset = -4; break; /* DA */
5738 case 1: offset = -8; break; /* DB */
5739 case 2: offset = 0; break; /* IA */
5740 case 3: offset = 4; break; /* IB */
5741 default: abort();
5742 }
5743 if (offset)
5744 tcg_gen_addi_i32(addr, addr, offset);
5745 /* Load PC into tmp and CPSR into tmp2. */
5746 tmp = gen_ld32(addr, 0);
5747 tcg_gen_addi_i32(addr, addr, 4);
5748 tmp2 = gen_ld32(addr, 0);
5749 if (insn & (1 << 21)) {
5750 /* Base writeback. */
5751 switch (i) {
5752 case 0: offset = -8; break;
5753 case 1: offset = -4; break;
5754 case 2: offset = 4; break;
5755 case 3: offset = 0; break;
5756 default: abort();
5757 }
5758 if (offset)
5759 tcg_gen_addi_i32(addr, addr, offset);
5760 store_reg(s, rn, addr);
5761 } else {
5762 dead_tmp(addr);
5763 }
5764 gen_rfe(s, tmp, tmp2);
5765 } else if ((insn & 0x0e000000) == 0x0a000000) {
5766 /* branch link and change to thumb (blx <offset>) */
5767 int32_t offset;
5768
5769 val = (uint32_t)s->pc;
5770 tmp = new_tmp();
5771 tcg_gen_movi_i32(tmp, val);
5772 store_reg(s, 14, tmp);
5773 /* Sign-extend the 24-bit offset */
5774 offset = (((int32_t)insn) << 8) >> 8;
5775 /* offset * 4 + bit24 * 2 + (thumb bit) */
5776 val += (offset << 2) | ((insn >> 23) & 2) | 1;
5777 /* pipeline offset */
5778 val += 4;
5779 gen_bx_im(s, val);
5780 return;
5781 } else if ((insn & 0x0e000f00) == 0x0c000100) {
5782 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5783 /* iWMMXt register transfer. */
5784 if (env->cp15.c15_cpar & (1 << 1))
5785 if (!disas_iwmmxt_insn(env, s, insn))
5786 return;
5787 }
5788 } else if ((insn & 0x0fe00000) == 0x0c400000) {
5789 /* Coprocessor double register transfer. */
5790 } else if ((insn & 0x0f000010) == 0x0e000010) {
5791 /* Additional coprocessor register transfer. */
5792 } else if ((insn & 0x0ff10020) == 0x01000000) {
5793 uint32_t mask;
5794 uint32_t val;
5795 /* cps (privileged) */
5796 if (IS_USER(s))
5797 return;
5798 mask = val = 0;
5799 if (insn & (1 << 19)) {
5800 if (insn & (1 << 8))
5801 mask |= CPSR_A;
5802 if (insn & (1 << 7))
5803 mask |= CPSR_I;
5804 if (insn & (1 << 6))
5805 mask |= CPSR_F;
5806 if (insn & (1 << 18))
5807 val |= mask;
5808 }
5809 if (insn & (1 << 17)) {
5810 mask |= CPSR_M;
5811 val |= (insn & 0x1f);
5812 }
5813 if (mask) {
5814 gen_op_movl_T0_im(val);
5815 gen_set_psr_T0(s, mask, 0);
5816 }
5817 return;
5818 }
5819 goto illegal_op;
5820 }
5821 if (cond != 0xe) {
5822 /* if not always execute, we generate a conditional jump to
5823 next instruction */
5824 s->condlabel = gen_new_label();
5825 gen_test_cc(cond ^ 1, s->condlabel);
5826 s->condjmp = 1;
5827 }
5828 if ((insn & 0x0f900000) == 0x03000000) {
5829 if ((insn & (1 << 21)) == 0) {
5830 ARCH(6T2);
5831 rd = (insn >> 12) & 0xf;
5832 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
5833 if ((insn & (1 << 22)) == 0) {
5834 /* MOVW */
5835 tmp = new_tmp();
5836 tcg_gen_movi_i32(tmp, val);
5837 } else {
5838 /* MOVT */
5839 tmp = load_reg(s, rd);
5840 tcg_gen_ext16u_i32(tmp, tmp);
5841 tcg_gen_ori_i32(tmp, tmp, val << 16);
5842 }
5843 store_reg(s, rd, tmp);
5844 } else {
5845 if (((insn >> 12) & 0xf) != 0xf)
5846 goto illegal_op;
5847 if (((insn >> 16) & 0xf) == 0) {
5848 gen_nop_hint(s, insn & 0xff);
5849 } else {
5850 /* CPSR = immediate */
5851 val = insn & 0xff;
5852 shift = ((insn >> 8) & 0xf) * 2;
5853 if (shift)
5854 val = (val >> shift) | (val << (32 - shift));
5855 gen_op_movl_T0_im(val);
5856 i = ((insn & (1 << 22)) != 0);
5857 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
5858 goto illegal_op;
5859 }
5860 }
5861 } else if ((insn & 0x0f900000) == 0x01000000
5862 && (insn & 0x00000090) != 0x00000090) {
5863 /* miscellaneous instructions */
5864 op1 = (insn >> 21) & 3;
5865 sh = (insn >> 4) & 0xf;
5866 rm = insn & 0xf;
5867 switch (sh) {
5868 case 0x0: /* move program status register */
5869 if (op1 & 1) {
5870 /* PSR = reg */
5871 gen_movl_T0_reg(s, rm);
5872 i = ((op1 & 2) != 0);
5873 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
5874 goto illegal_op;
5875 } else {
5876 /* reg = PSR */
5877 rd = (insn >> 12) & 0xf;
5878 if (op1 & 2) {
5879 if (IS_USER(s))
5880 goto illegal_op;
5881 tmp = load_cpu_field(spsr);
5882 } else {
5883 tmp = new_tmp();
5884 gen_helper_cpsr_read(tmp);
5885 }
5886 store_reg(s, rd, tmp);
5887 }
5888 break;
5889 case 0x1:
5890 if (op1 == 1) {
5891 /* branch/exchange thumb (bx). */
5892 tmp = load_reg(s, rm);
5893 gen_bx(s, tmp);
5894 } else if (op1 == 3) {
5895 /* clz */
5896 rd = (insn >> 12) & 0xf;
5897 tmp = load_reg(s, rm);
5898 gen_helper_clz(tmp, tmp);
5899 store_reg(s, rd, tmp);
5900 } else {
5901 goto illegal_op;
5902 }
5903 break;
5904 case 0x2:
5905 if (op1 == 1) {
5906 ARCH(5J); /* bxj */
5907 /* Trivial implementation equivalent to bx. */
5908 tmp = load_reg(s, rm);
5909 gen_bx(s, tmp);
5910 } else {
5911 goto illegal_op;
5912 }
5913 break;
5914 case 0x3:
5915 if (op1 != 1)
5916 goto illegal_op;
5917
5918 /* branch link/exchange thumb (blx) */
5919 tmp = load_reg(s, rm);
5920 tmp2 = new_tmp();
5921 tcg_gen_movi_i32(tmp2, s->pc);
5922 store_reg(s, 14, tmp2);
5923 gen_bx(s, tmp);
5924 break;
5925 case 0x5: /* saturating add/subtract */
5926 rd = (insn >> 12) & 0xf;
5927 rn = (insn >> 16) & 0xf;
5928 tmp = load_reg(s, rm);
5929 tmp2 = load_reg(s, rn);
5930 if (op1 & 2)
5931 gen_helper_double_saturate(tmp2, tmp2);
5932 if (op1 & 1)
5933 gen_helper_sub_saturate(tmp, tmp, tmp2);
5934 else
5935 gen_helper_add_saturate(tmp, tmp, tmp2);
5936 dead_tmp(tmp2);
5937 store_reg(s, rd, tmp);
5938 break;
5939 case 7: /* bkpt */
5940 gen_set_condexec(s);
5941 gen_set_pc_im(s->pc - 4);
5942 gen_exception(EXCP_BKPT);
5943 s->is_jmp = DISAS_JUMP;
5944 break;
5945 case 0x8: /* signed multiply */
5946 case 0xa:
5947 case 0xc:
5948 case 0xe:
5949 rs = (insn >> 8) & 0xf;
5950 rn = (insn >> 12) & 0xf;
5951 rd = (insn >> 16) & 0xf;
5952 if (op1 == 1) {
5953 /* (32 * 16) >> 16 */
5954 tmp = load_reg(s, rm);
5955 tmp2 = load_reg(s, rs);
5956 if (sh & 4)
5957 tcg_gen_sari_i32(tmp2, tmp2, 16);
5958 else
5959 gen_sxth(tmp2);
5960 tmp64 = gen_muls_i64_i32(tmp, tmp2);
5961 tcg_gen_shri_i64(tmp64, tmp64, 16);
5962 tmp = new_tmp();
5963 tcg_gen_trunc_i64_i32(tmp, tmp64);
5964 if ((sh & 2) == 0) {
5965 tmp2 = load_reg(s, rn);
5966 gen_helper_add_setq(tmp, tmp, tmp2);
5967 dead_tmp(tmp2);
5968 }
5969 store_reg(s, rd, tmp);
5970 } else {
5971 /* 16 * 16 */
5972 tmp = load_reg(s, rm);
5973 tmp2 = load_reg(s, rs);
5974 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
5975 dead_tmp(tmp2);
5976 if (op1 == 2) {
5977 tmp64 = tcg_temp_new_i64();
5978 tcg_gen_ext_i32_i64(tmp64, tmp);
5979 dead_tmp(tmp);
5980 gen_addq(s, tmp64, rn, rd);
5981 gen_storeq_reg(s, rn, rd, tmp64);
5982 } else {
5983 if (op1 == 0) {
5984 tmp2 = load_reg(s, rn);
5985 gen_helper_add_setq(tmp, tmp, tmp2);
5986 dead_tmp(tmp2);
5987 }
5988 store_reg(s, rd, tmp);
5989 }
5990 }
5991 break;
5992 default:
5993 goto illegal_op;
5994 }
5995 } else if (((insn & 0x0e000000) == 0 &&
5996 (insn & 0x00000090) != 0x90) ||
5997 ((insn & 0x0e000000) == (1 << 25))) {
5998 int set_cc, logic_cc, shiftop;
5999
6000 op1 = (insn >> 21) & 0xf;
6001 set_cc = (insn >> 20) & 1;
6002 logic_cc = table_logic_cc[op1] & set_cc;
6003
6004 /* data processing instruction */
6005 if (insn & (1 << 25)) {
6006 /* immediate operand */
6007 val = insn & 0xff;
6008 shift = ((insn >> 8) & 0xf) * 2;
6009 if (shift)
6010 val = (val >> shift) | (val << (32 - shift));
6011 gen_op_movl_T1_im(val);
6012 if (logic_cc && shift)
6013 gen_set_CF_bit31(cpu_T[1]);
6014 } else {
6015 /* register */
6016 rm = (insn) & 0xf;
6017 gen_movl_T1_reg(s, rm);
6018 shiftop = (insn >> 5) & 3;
6019 if (!(insn & (1 << 4))) {
6020 shift = (insn >> 7) & 0x1f;
6021 gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
6022 } else {
6023 rs = (insn >> 8) & 0xf;
6024 tmp = load_reg(s, rs);
6025 gen_arm_shift_reg(cpu_T[1], shiftop, tmp, logic_cc);
6026 }
6027 }
6028 if (op1 != 0x0f && op1 != 0x0d) {
6029 rn = (insn >> 16) & 0xf;
6030 gen_movl_T0_reg(s, rn);
6031 }
6032 rd = (insn >> 12) & 0xf;
6033 switch(op1) {
6034 case 0x00:
6035 gen_op_andl_T0_T1();
6036 gen_movl_reg_T0(s, rd);
6037 if (logic_cc)
6038 gen_op_logic_T0_cc();
6039 break;
6040 case 0x01:
6041 gen_op_xorl_T0_T1();
6042 gen_movl_reg_T0(s, rd);
6043 if (logic_cc)
6044 gen_op_logic_T0_cc();
6045 break;
6046 case 0x02:
6047 if (set_cc && rd == 15) {
6048 /* SUBS r15, ... is used for exception return. */
6049 if (IS_USER(s))
6050 goto illegal_op;
6051 gen_op_subl_T0_T1_cc();
6052 gen_exception_return(s);
6053 } else {
6054 if (set_cc)
6055 gen_op_subl_T0_T1_cc();
6056 else
6057 gen_op_subl_T0_T1();
6058 gen_movl_reg_T0(s, rd);
6059 }
6060 break;
6061 case 0x03:
6062 if (set_cc)
6063 gen_op_rsbl_T0_T1_cc();
6064 else
6065 gen_op_rsbl_T0_T1();
6066 gen_movl_reg_T0(s, rd);
6067 break;
6068 case 0x04:
6069 if (set_cc)
6070 gen_op_addl_T0_T1_cc();
6071 else
6072 gen_op_addl_T0_T1();
6073 gen_movl_reg_T0(s, rd);
6074 break;
6075 case 0x05:
6076 if (set_cc)
6077 gen_op_adcl_T0_T1_cc();
6078 else
6079 gen_adc_T0_T1();
6080 gen_movl_reg_T0(s, rd);
6081 break;
6082 case 0x06:
6083 if (set_cc)
6084 gen_op_sbcl_T0_T1_cc();
6085 else
6086 gen_sbc_T0_T1();
6087 gen_movl_reg_T0(s, rd);
6088 break;
6089 case 0x07:
6090 if (set_cc)
6091 gen_op_rscl_T0_T1_cc();
6092 else
6093 gen_rsc_T0_T1();
6094 gen_movl_reg_T0(s, rd);
6095 break;
6096 case 0x08:
6097 if (set_cc) {
6098 gen_op_andl_T0_T1();
6099 gen_op_logic_T0_cc();
6100 }
6101 break;
6102 case 0x09:
6103 if (set_cc) {
6104 gen_op_xorl_T0_T1();
6105 gen_op_logic_T0_cc();
6106 }
6107 break;
6108 case 0x0a:
6109 if (set_cc) {
6110 gen_op_subl_T0_T1_cc();
6111 }
6112 break;
6113 case 0x0b:
6114 if (set_cc) {
6115 gen_op_addl_T0_T1_cc();
6116 }
6117 break;
6118 case 0x0c:
6119 gen_op_orl_T0_T1();
6120 gen_movl_reg_T0(s, rd);
6121 if (logic_cc)
6122 gen_op_logic_T0_cc();
6123 break;
6124 case 0x0d:
6125 if (logic_cc && rd == 15) {
6126 /* MOVS r15, ... is used for exception return. */
6127 if (IS_USER(s))
6128 goto illegal_op;
6129 gen_op_movl_T0_T1();
6130 gen_exception_return(s);
6131 } else {
6132 gen_movl_reg_T1(s, rd);
6133 if (logic_cc)
6134 gen_op_logic_T1_cc();
6135 }
6136 break;
6137 case 0x0e:
6138 gen_op_bicl_T0_T1();
6139 gen_movl_reg_T0(s, rd);
6140 if (logic_cc)
6141 gen_op_logic_T0_cc();
6142 break;
6143 default:
6144 case 0x0f:
6145 gen_op_notl_T1();
6146 gen_movl_reg_T1(s, rd);
6147 if (logic_cc)
6148 gen_op_logic_T1_cc();
6149 break;
6150 }
6151 } else {
6152 /* other instructions */
6153 op1 = (insn >> 24) & 0xf;
6154 switch(op1) {
6155 case 0x0:
6156 case 0x1:
6157 /* multiplies, extra load/stores */
6158 sh = (insn >> 5) & 3;
6159 if (sh == 0) {
6160 if (op1 == 0x0) {
6161 rd = (insn >> 16) & 0xf;
6162 rn = (insn >> 12) & 0xf;
6163 rs = (insn >> 8) & 0xf;
6164 rm = (insn) & 0xf;
6165 op1 = (insn >> 20) & 0xf;
6166 switch (op1) {
6167 case 0: case 1: case 2: case 3: case 6:
6168 /* 32 bit mul */
6169 tmp = load_reg(s, rs);
6170 tmp2 = load_reg(s, rm);
6171 tcg_gen_mul_i32(tmp, tmp, tmp2);
6172 dead_tmp(tmp2);
6173 if (insn & (1 << 22)) {
6174 /* Subtract (mls) */
6175 ARCH(6T2);
6176 tmp2 = load_reg(s, rn);
6177 tcg_gen_sub_i32(tmp, tmp2, tmp);
6178 dead_tmp(tmp2);
6179 } else if (insn & (1 << 21)) {
6180 /* Add */
6181 tmp2 = load_reg(s, rn);
6182 tcg_gen_add_i32(tmp, tmp, tmp2);
6183 dead_tmp(tmp2);
6184 }
6185 if (insn & (1 << 20))
6186 gen_logic_CC(tmp);
6187 store_reg(s, rd, tmp);
6188 break;
6189 default:
6190 /* 64 bit mul */
6191 tmp = load_reg(s, rs);
6192 tmp2 = load_reg(s, rm);
6193 if (insn & (1 << 22))
6194 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6195 else
6196 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6197 if (insn & (1 << 21)) /* mult accumulate */
6198 gen_addq(s, tmp64, rn, rd);
6199 if (!(insn & (1 << 23))) { /* double accumulate */
6200 ARCH(6);
6201 gen_addq_lo(s, tmp64, rn);
6202 gen_addq_lo(s, tmp64, rd);
6203 }
6204 if (insn & (1 << 20))
6205 gen_logicq_cc(tmp64);
6206 gen_storeq_reg(s, rn, rd, tmp64);
6207 break;
6208 }
6209 } else {
6210 rn = (insn >> 16) & 0xf;
6211 rd = (insn >> 12) & 0xf;
6212 if (insn & (1 << 23)) {
6213 /* load/store exclusive */
6214 op1 = (insn >> 21) & 0x3;
6215 if (op1)
6216 ARCH(6K);
6217 else
6218 ARCH(6);
6219 gen_movl_T1_reg(s, rn);
6220 addr = cpu_T[1];
6221 if (insn & (1 << 20)) {
6222 gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
6223 switch (op1) {
6224 case 0: /* ldrex */
6225 tmp = gen_ld32(addr, IS_USER(s));
6226 break;
6227 case 1: /* ldrexd */
6228 tmp = gen_ld32(addr, IS_USER(s));
6229 store_reg(s, rd, tmp);
6230 tcg_gen_addi_i32(addr, addr, 4);
6231 tmp = gen_ld32(addr, IS_USER(s));
6232 rd++;
6233 break;
6234 case 2: /* ldrexb */
6235 tmp = gen_ld8u(addr, IS_USER(s));
6236 break;
6237 case 3: /* ldrexh */
6238 tmp = gen_ld16u(addr, IS_USER(s));
6239 break;
6240 default:
6241 abort();
6242 }
6243 store_reg(s, rd, tmp);
6244 } else {
6245 int label = gen_new_label();
6246 rm = insn & 0xf;
6247 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
6248 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
6249 0, label);
6250 tmp = load_reg(s,rm);
6251 switch (op1) {
6252 case 0: /* strex */
6253 gen_st32(tmp, addr, IS_USER(s));
6254 break;
6255 case 1: /* strexd */
6256 gen_st32(tmp, addr, IS_USER(s));
6257 tcg_gen_addi_i32(addr, addr, 4);
6258 tmp = load_reg(s, rm + 1);
6259 gen_st32(tmp, addr, IS_USER(s));
6260 break;
6261 case 2: /* strexb */
6262 gen_st8(tmp, addr, IS_USER(s));
6263 break;
6264 case 3: /* strexh */
6265 gen_st16(tmp, addr, IS_USER(s));
6266 break;
6267 default:
6268 abort();
6269 }
6270 gen_set_label(label);
6271 gen_movl_reg_T0(s, rd);
6272 }
6273 } else {
6274 /* SWP instruction */
6275 rm = (insn) & 0xf;
6276
6277 /* ??? This is not really atomic. However we know
6278 we never have multiple CPUs running in parallel,
6279 so it is good enough. */
6280 addr = load_reg(s, rn);
6281 tmp = load_reg(s, rm);
6282 if (insn & (1 << 22)) {
6283 tmp2 = gen_ld8u(addr, IS_USER(s));
6284 gen_st8(tmp, addr, IS_USER(s));
6285 } else {
6286 tmp2 = gen_ld32(addr, IS_USER(s));
6287 gen_st32(tmp, addr, IS_USER(s));
6288 }
6289 dead_tmp(addr);
6290 store_reg(s, rd, tmp2);
6291 }
6292 }
6293 } else {
6294 int address_offset;
6295 int load;
6296 /* Misc load/store */
6297 rn = (insn >> 16) & 0xf;
6298 rd = (insn >> 12) & 0xf;
6299 addr = load_reg(s, rn);
6300 if (insn & (1 << 24))
6301 gen_add_datah_offset(s, insn, 0, addr);
6302 address_offset = 0;
6303 if (insn & (1 << 20)) {
6304 /* load */
6305 switch(sh) {
6306 case 1:
6307 tmp = gen_ld16u(addr, IS_USER(s));
6308 break;
6309 case 2:
6310 tmp = gen_ld8s(addr, IS_USER(s));
6311 break;
6312 default:
6313 case 3:
6314 tmp = gen_ld16s(addr, IS_USER(s));
6315 break;
6316 }
6317 load = 1;
6318 } else if (sh & 2) {
6319 /* doubleword */
6320 if (sh & 1) {
6321 /* store */
6322 tmp = load_reg(s, rd);
6323 gen_st32(tmp, addr, IS_USER(s));
6324 tcg_gen_addi_i32(addr, addr, 4);
6325 tmp = load_reg(s, rd + 1);
6326 gen_st32(tmp, addr, IS_USER(s));
6327 load = 0;
6328 } else {
6329 /* load */
6330 tmp = gen_ld32(addr, IS_USER(s));
6331 store_reg(s, rd, tmp);
6332 tcg_gen_addi_i32(addr, addr, 4);
6333 tmp = gen_ld32(addr, IS_USER(s));
6334 rd++;
6335 load = 1;
6336 }
6337 address_offset = -4;
6338 } else {
6339 /* store */
6340 tmp = load_reg(s, rd);
6341 gen_st16(tmp, addr, IS_USER(s));
6342 load = 0;
6343 }
6344 /* Perform base writeback before the loaded value to
6345 ensure correct behavior with overlapping index registers.
6346 ldrd with base writeback is is undefined if the
6347 destination and index registers overlap. */
6348 if (!(insn & (1 << 24))) {
6349 gen_add_datah_offset(s, insn, address_offset, addr);
6350 store_reg(s, rn, addr);
6351 } else if (insn & (1 << 21)) {
6352 if (address_offset)
6353 tcg_gen_addi_i32(addr, addr, address_offset);
6354 store_reg(s, rn, addr);
6355 } else {
6356 dead_tmp(addr);
6357 }
6358 if (load) {
6359 /* Complete the load. */
6360 store_reg(s, rd, tmp);
6361 }
6362 }
6363 break;
6364 case 0x4:
6365 case 0x5:
6366 goto do_ldst;
6367 case 0x6:
6368 case 0x7:
6369 if (insn & (1 << 4)) {
6370 ARCH(6);
6371 /* Armv6 Media instructions. */
6372 rm = insn & 0xf;
6373 rn = (insn >> 16) & 0xf;
6374 rd = (insn >> 12) & 0xf;
6375 rs = (insn >> 8) & 0xf;
6376 switch ((insn >> 23) & 3) {
6377 case 0: /* Parallel add/subtract. */
6378 op1 = (insn >> 20) & 7;
6379 tmp = load_reg(s, rn);
6380 tmp2 = load_reg(s, rm);
6381 sh = (insn >> 5) & 7;
6382 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6383 goto illegal_op;
6384 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6385 dead_tmp(tmp2);
6386 store_reg(s, rd, tmp);
6387 break;
6388 case 1:
6389 if ((insn & 0x00700020) == 0) {
6390 /* Halfword pack. */
6391 tmp = load_reg(s, rn);
6392 tmp2 = load_reg(s, rm);
6393 shift = (insn >> 7) & 0x1f;
6394 if (insn & (1 << 6)) {
6395 /* pkhtb */
6396 if (shift == 0)
6397 shift = 31;
6398 tcg_gen_sari_i32(tmp2, tmp2, shift);
6399 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6400 tcg_gen_ext16u_i32(tmp2, tmp2);
6401 } else {
6402 /* pkhbt */
6403 if (shift)
6404 tcg_gen_shli_i32(tmp2, tmp2, shift);
6405 tcg_gen_ext16u_i32(tmp, tmp);
6406 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6407 }
6408 tcg_gen_or_i32(tmp, tmp, tmp2);
6409 dead_tmp(tmp2);
6410 store_reg(s, rd, tmp);
6411 } else if ((insn & 0x00200020) == 0x00200000) {
6412 /* [us]sat */
6413 tmp = load_reg(s, rm);
6414 shift = (insn >> 7) & 0x1f;
6415 if (insn & (1 << 6)) {
6416 if (shift == 0)
6417 shift = 31;
6418 tcg_gen_sari_i32(tmp, tmp, shift);
6419 } else {
6420 tcg_gen_shli_i32(tmp, tmp, shift);
6421 }
6422 sh = (insn >> 16) & 0x1f;
6423 if (sh != 0) {
6424 if (insn & (1 << 22))
6425 gen_helper_usat(tmp, tmp, tcg_const_i32(sh));
6426 else
6427 gen_helper_ssat(tmp, tmp, tcg_const_i32(sh));
6428 }
6429 store_reg(s, rd, tmp);
6430 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6431 /* [us]sat16 */
6432 tmp = load_reg(s, rm);
6433 sh = (insn >> 16) & 0x1f;
6434 if (sh != 0) {
6435 if (insn & (1 << 22))
6436 gen_helper_usat16(tmp, tmp, tcg_const_i32(sh));
6437 else
6438 gen_helper_ssat16(tmp, tmp, tcg_const_i32(sh));
6439 }
6440 store_reg(s, rd, tmp);
6441 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6442 /* Select bytes. */
6443 tmp = load_reg(s, rn);
6444 tmp2 = load_reg(s, rm);
6445 tmp3 = new_tmp();
6446 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6447 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6448 dead_tmp(tmp3);
6449 dead_tmp(tmp2);
6450 store_reg(s, rd, tmp);
6451 } else if ((insn & 0x000003e0) == 0x00000060) {
6452 tmp = load_reg(s, rm);
6453 shift = (insn >> 10) & 3;
6454 /* ??? In many cases it's not neccessary to do a
6455 rotate, a shift is sufficient. */
6456 if (shift != 0)
6457 tcg_gen_rori_i32(tmp, tmp, shift * 8);
6458 op1 = (insn >> 20) & 7;
6459 switch (op1) {
6460 case 0: gen_sxtb16(tmp); break;
6461 case 2: gen_sxtb(tmp); break;
6462 case 3: gen_sxth(tmp); break;
6463 case 4: gen_uxtb16(tmp); break;
6464 case 6: gen_uxtb(tmp); break;
6465 case 7: gen_uxth(tmp); break;
6466 default: goto illegal_op;
6467 }
6468 if (rn != 15) {
6469 tmp2 = load_reg(s, rn);
6470 if ((op1 & 3) == 0) {
6471 gen_add16(tmp, tmp2);
6472 } else {
6473 tcg_gen_add_i32(tmp, tmp, tmp2);
6474 dead_tmp(tmp2);
6475 }
6476 }
6477 store_reg(s, rd, tmp);
6478 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6479 /* rev */
6480 tmp = load_reg(s, rm);
6481 if (insn & (1 << 22)) {
6482 if (insn & (1 << 7)) {
6483 gen_revsh(tmp);
6484 } else {
6485 ARCH(6T2);
6486 gen_helper_rbit(tmp, tmp);
6487 }
6488 } else {
6489 if (insn & (1 << 7))
6490 gen_rev16(tmp);
6491 else
6492 tcg_gen_bswap_i32(tmp, tmp);
6493 }
6494 store_reg(s, rd, tmp);
6495 } else {
6496 goto illegal_op;
6497 }
6498 break;
6499 case 2: /* Multiplies (Type 3). */
6500 tmp = load_reg(s, rm);
6501 tmp2 = load_reg(s, rs);
6502 if (insn & (1 << 20)) {
6503 /* Signed multiply most significant [accumulate]. */
6504 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6505 if (insn & (1 << 5))
6506 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6507 tcg_gen_shri_i64(tmp64, tmp64, 32);
6508 tmp = new_tmp();
6509 tcg_gen_trunc_i64_i32(tmp, tmp64);
6510 if (rd != 15) {
6511 tmp2 = load_reg(s, rd);
6512 if (insn & (1 << 6)) {
6513 tcg_gen_sub_i32(tmp, tmp, tmp2);
6514 } else {
6515 tcg_gen_add_i32(tmp, tmp, tmp2);
6516 }
6517 dead_tmp(tmp2);
6518 }
6519 store_reg(s, rn, tmp);
6520 } else {
6521 if (insn & (1 << 5))
6522 gen_swap_half(tmp2);
6523 gen_smul_dual(tmp, tmp2);
6524 /* This addition cannot overflow. */
6525 if (insn & (1 << 6)) {
6526 tcg_gen_sub_i32(tmp, tmp, tmp2);
6527 } else {
6528 tcg_gen_add_i32(tmp, tmp, tmp2);
6529 }
6530 dead_tmp(tmp2);
6531 if (insn & (1 << 22)) {
6532 /* smlald, smlsld */
6533 tmp64 = tcg_temp_new_i64();
6534 tcg_gen_ext_i32_i64(tmp64, tmp);
6535 dead_tmp(tmp);
6536 gen_addq(s, tmp64, rd, rn);
6537 gen_storeq_reg(s, rd, rn, tmp64);
6538 } else {
6539 /* smuad, smusd, smlad, smlsd */
6540 if (rd != 15)
6541 {
6542 tmp2 = load_reg(s, rd);
6543 gen_helper_add_setq(tmp, tmp, tmp2);
6544 dead_tmp(tmp2);
6545 }
6546 store_reg(s, rn, tmp);
6547 }
6548 }
6549 break;
6550 case 3:
6551 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6552 switch (op1) {
6553 case 0: /* Unsigned sum of absolute differences. */
6554 ARCH(6);
6555 tmp = load_reg(s, rm);
6556 tmp2 = load_reg(s, rs);
6557 gen_helper_usad8(tmp, tmp, tmp2);
6558 dead_tmp(tmp2);
6559 if (rd != 15) {
6560 tmp2 = load_reg(s, rd);
6561 tcg_gen_add_i32(tmp, tmp, tmp2);
6562 dead_tmp(tmp2);
6563 }
6564 store_reg(s, rn, tmp);
6565 break;
6566 case 0x20: case 0x24: case 0x28: case 0x2c:
6567 /* Bitfield insert/clear. */
6568 ARCH(6T2);
6569 shift = (insn >> 7) & 0x1f;
6570 i = (insn >> 16) & 0x1f;
6571 i = i + 1 - shift;
6572 if (rm == 15) {
6573 tmp = new_tmp();
6574 tcg_gen_movi_i32(tmp, 0);
6575 } else {
6576 tmp = load_reg(s, rm);
6577 }
6578 if (i != 32) {
6579 tmp2 = load_reg(s, rd);
6580 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
6581 dead_tmp(tmp2);
6582 }
6583 store_reg(s, rd, tmp);
6584 break;
6585 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
6586 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
6587 ARCH(6T2);
6588 tmp = load_reg(s, rm);
6589 shift = (insn >> 7) & 0x1f;
6590 i = ((insn >> 16) & 0x1f) + 1;
6591 if (shift + i > 32)
6592 goto illegal_op;
6593 if (i < 32) {
6594 if (op1 & 0x20) {
6595 gen_ubfx(tmp, shift, (1u << i) - 1);
6596 } else {
6597 gen_sbfx(tmp, shift, i);
6598 }
6599 }
6600 store_reg(s, rd, tmp);
6601 break;
6602 default:
6603 goto illegal_op;
6604 }
6605 break;
6606 }
6607 break;
6608 }
6609 do_ldst:
6610 /* Check for undefined extension instructions
6611 * per the ARM Bible IE:
6612 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
6613 */
6614 sh = (0xf << 20) | (0xf << 4);
6615 if (op1 == 0x7 && ((insn & sh) == sh))
6616 {
6617 goto illegal_op;
6618 }
6619 /* load/store byte/word */
6620 rn = (insn >> 16) & 0xf;
6621 rd = (insn >> 12) & 0xf;
6622 tmp2 = load_reg(s, rn);
6623 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
6624 if (insn & (1 << 24))
6625 gen_add_data_offset(s, insn, tmp2);
6626 if (insn & (1 << 20)) {
6627 /* load */
6628 if (insn & (1 << 22)) {
6629 tmp = gen_ld8u(tmp2, i);
6630 } else {
6631 tmp = gen_ld32(tmp2, i);
6632 }
6633 } else {
6634 /* store */
6635 tmp = load_reg(s, rd);
6636 if (insn & (1 << 22))
6637 gen_st8(tmp, tmp2, i);
6638 else
6639 gen_st32(tmp, tmp2, i);
6640 }
6641 if (!(insn & (1 << 24))) {
6642 gen_add_data_offset(s, insn, tmp2);
6643 store_reg(s, rn, tmp2);
6644 } else if (insn & (1 << 21)) {
6645 store_reg(s, rn, tmp2);
6646 } else {
6647 dead_tmp(tmp2);
6648 }
6649 if (insn & (1 << 20)) {
6650 /* Complete the load. */
6651 if (rd == 15)
6652 gen_bx(s, tmp);
6653 else
6654 store_reg(s, rd, tmp);
6655 }
6656 break;
6657 case 0x08:
6658 case 0x09:
6659 {
6660 int j, n, user, loaded_base;
6661 TCGv loaded_var;
6662 /* load/store multiple words */
6663 /* XXX: store correct base if write back */
6664 user = 0;
6665 if (insn & (1 << 22)) {
6666 if (IS_USER(s))
6667 goto illegal_op; /* only usable in supervisor mode */
6668
6669 if ((insn & (1 << 15)) == 0)
6670 user = 1;
6671 }
6672 rn = (insn >> 16) & 0xf;
6673 addr = load_reg(s, rn);
6674
6675 /* compute total size */
6676 loaded_base = 0;
6677 TCGV_UNUSED(loaded_var);
6678 n = 0;
6679 for(i=0;i<16;i++) {
6680 if (insn & (1 << i))
6681 n++;
6682 }
6683 /* XXX: test invalid n == 0 case ? */
6684 if (insn & (1 << 23)) {
6685 if (insn & (1 << 24)) {
6686 /* pre increment */
6687 tcg_gen_addi_i32(addr, addr, 4);
6688 } else {
6689 /* post increment */
6690 }
6691 } else {
6692 if (insn & (1 << 24)) {
6693 /* pre decrement */
6694 tcg_gen_addi_i32(addr, addr, -(n * 4));
6695 } else {
6696 /* post decrement */
6697 if (n != 1)
6698 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
6699 }
6700 }
6701 j = 0;
6702 for(i=0;i<16;i++) {
6703 if (insn & (1 << i)) {
6704 if (insn & (1 << 20)) {
6705 /* load */
6706 tmp = gen_ld32(addr, IS_USER(s));
6707 if (i == 15) {
6708 gen_bx(s, tmp);
6709 } else if (user) {
6710 gen_helper_set_user_reg(tcg_const_i32(i), tmp);
6711 dead_tmp(tmp);
6712 } else if (i == rn) {
6713 loaded_var = tmp;
6714 loaded_base = 1;
6715 } else {
6716 store_reg(s, i, tmp);
6717 }
6718 } else {
6719 /* store */
6720 if (i == 15) {
6721 /* special case: r15 = PC + 8 */
6722 val = (long)s->pc + 4;
6723 tmp = new_tmp();
6724 tcg_gen_movi_i32(tmp, val);
6725 } else if (user) {
6726 tmp = new_tmp();
6727 gen_helper_get_user_reg(tmp, tcg_const_i32(i));
6728 } else {
6729 tmp = load_reg(s, i);
6730 }
6731 gen_st32(tmp, addr, IS_USER(s));
6732 }
6733 j++;
6734 /* no need to add after the last transfer */
6735 if (j != n)
6736 tcg_gen_addi_i32(addr, addr, 4);
6737 }
6738 }
6739 if (insn & (1 << 21)) {
6740 /* write back */
6741 if (insn & (1 << 23)) {
6742 if (insn & (1 << 24)) {
6743 /* pre increment */
6744 } else {
6745 /* post increment */
6746 tcg_gen_addi_i32(addr, addr, 4);
6747 }
6748 } else {
6749 if (insn & (1 << 24)) {
6750 /* pre decrement */
6751 if (n != 1)
6752 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
6753 } else {
6754 /* post decrement */
6755 tcg_gen_addi_i32(addr, addr, -(n * 4));
6756 }
6757 }
6758 store_reg(s, rn, addr);
6759 } else {
6760 dead_tmp(addr);
6761 }
6762 if (loaded_base) {
6763 store_reg(s, rn, loaded_var);
6764 }
6765 if ((insn & (1 << 22)) && !user) {
6766 /* Restore CPSR from SPSR. */
6767 tmp = load_cpu_field(spsr);
6768 gen_set_cpsr(tmp, 0xffffffff);
6769 dead_tmp(tmp);
6770 s->is_jmp = DISAS_UPDATE;
6771 }
6772 }
6773 break;
6774 case 0xa:
6775 case 0xb:
6776 {
6777 int32_t offset;
6778
6779 /* branch (and link) */
6780 val = (int32_t)s->pc;
6781 if (insn & (1 << 24)) {
6782 tmp = new_tmp();
6783 tcg_gen_movi_i32(tmp, val);
6784 store_reg(s, 14, tmp);
6785 }
6786 offset = (((int32_t)insn << 8) >> 8);
6787 val += (offset << 2) + 4;
6788 gen_jmp(s, val);
6789 }
6790 break;
6791 case 0xc:
6792 case 0xd:
6793 case 0xe:
6794 /* Coprocessor. */
6795 if (disas_coproc_insn(env, s, insn))
6796 goto illegal_op;
6797 break;
6798 case 0xf:
6799 /* swi */
6800 gen_set_pc_im(s->pc);
6801 s->is_jmp = DISAS_SWI;
6802 break;
6803 default:
6804 illegal_op:
6805 gen_set_condexec(s);
6806 gen_set_pc_im(s->pc - 4);
6807 gen_exception(EXCP_UDEF);
6808 s->is_jmp = DISAS_JUMP;
6809 break;
6810 }
6811 }
6812 }
6813
6814 /* Return true if this is a Thumb-2 logical op. */
6815 static int
6816 thumb2_logic_op(int op)
6817 {
6818 return (op < 8);
6819 }
6820
6821 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
6822 then set condition code flags based on the result of the operation.
6823 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
6824 to the high bit of T1.
6825 Returns zero if the opcode is valid. */
6826
6827 static int
6828 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out)
6829 {
6830 int logic_cc;
6831
6832 logic_cc = 0;
6833 switch (op) {
6834 case 0: /* and */
6835 gen_op_andl_T0_T1();
6836 logic_cc = conds;
6837 break;
6838 case 1: /* bic */
6839 gen_op_bicl_T0_T1();
6840 logic_cc = conds;
6841 break;
6842 case 2: /* orr */
6843 gen_op_orl_T0_T1();
6844 logic_cc = conds;
6845 break;
6846 case 3: /* orn */
6847 gen_op_notl_T1();
6848 gen_op_orl_T0_T1();
6849 logic_cc = conds;
6850 break;
6851 case 4: /* eor */
6852 gen_op_xorl_T0_T1();
6853 logic_cc = conds;
6854 break;
6855 case 8: /* add */
6856 if (conds)
6857 gen_op_addl_T0_T1_cc();
6858 else
6859 gen_op_addl_T0_T1();
6860 break;
6861 case 10: /* adc */
6862 if (conds)
6863 gen_op_adcl_T0_T1_cc();
6864 else
6865 gen_adc_T0_T1();
6866 break;
6867 case 11: /* sbc */
6868 if (conds)
6869 gen_op_sbcl_T0_T1_cc();
6870 else
6871 gen_sbc_T0_T1();
6872 break;
6873 case 13: /* sub */
6874 if (conds)
6875 gen_op_subl_T0_T1_cc();
6876 else
6877 gen_op_subl_T0_T1();
6878 break;
6879 case 14: /* rsb */
6880 if (conds)
6881 gen_op_rsbl_T0_T1_cc();
6882 else
6883 gen_op_rsbl_T0_T1();
6884 break;
6885 default: /* 5, 6, 7, 9, 12, 15. */
6886 return 1;
6887 }
6888 if (logic_cc) {
6889 gen_op_logic_T0_cc();
6890 if (shifter_out)
6891 gen_set_CF_bit31(cpu_T[1]);
6892 }
6893 return 0;
6894 }
6895
6896 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
6897 is not legal. */
6898 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
6899 {
6900 uint32_t insn, imm, shift, offset;
6901 uint32_t rd, rn, rm, rs;
6902 TCGv tmp;
6903 TCGv tmp2;
6904 TCGv tmp3;
6905 TCGv addr;
6906 TCGv_i64 tmp64;
6907 int op;
6908 int shiftop;
6909 int conds;
6910 int logic_cc;
6911
6912 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
6913 || arm_feature (env, ARM_FEATURE_M))) {
6914 /* Thumb-1 cores may need to treat bl and blx as a pair of
6915 16-bit instructions to get correct prefetch abort behavior. */
6916 insn = insn_hw1;
6917 if ((insn & (1 << 12)) == 0) {
6918 /* Second half of blx. */
6919 offset = ((insn & 0x7ff) << 1);
6920 tmp = load_reg(s, 14);
6921 tcg_gen_addi_i32(tmp, tmp, offset);
6922 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
6923
6924 tmp2 = new_tmp();
6925 tcg_gen_movi_i32(tmp2, s->pc | 1);
6926 store_reg(s, 14, tmp2);
6927 gen_bx(s, tmp);
6928 return 0;
6929 }
6930 if (insn & (1 << 11)) {
6931 /* Second half of bl. */
6932 offset = ((insn & 0x7ff) << 1) | 1;
6933 tmp = load_reg(s, 14);
6934 tcg_gen_addi_i32(tmp, tmp, offset);
6935
6936 tmp2 = new_tmp();
6937 tcg_gen_movi_i32(tmp2, s->pc | 1);
6938 store_reg(s, 14, tmp2);
6939 gen_bx(s, tmp);
6940 return 0;
6941 }
6942 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
6943 /* Instruction spans a page boundary. Implement it as two
6944 16-bit instructions in case the second half causes an
6945 prefetch abort. */
6946 offset = ((int32_t)insn << 21) >> 9;
6947 gen_op_movl_T0_im(s->pc + 2 + offset);
6948 gen_movl_reg_T0(s, 14);
6949 return 0;
6950 }
6951 /* Fall through to 32-bit decode. */
6952 }
6953
6954 insn = lduw_code(s->pc);
6955 s->pc += 2;
6956 insn |= (uint32_t)insn_hw1 << 16;
6957
6958 if ((insn & 0xf800e800) != 0xf000e800) {
6959 ARCH(6T2);
6960 }
6961
6962 rn = (insn >> 16) & 0xf;
6963 rs = (insn >> 12) & 0xf;
6964 rd = (insn >> 8) & 0xf;
6965 rm = insn & 0xf;
6966 switch ((insn >> 25) & 0xf) {
6967 case 0: case 1: case 2: case 3:
6968 /* 16-bit instructions. Should never happen. */
6969 abort();
6970 case 4:
6971 if (insn & (1 << 22)) {
6972 /* Other load/store, table branch. */
6973 if (insn & 0x01200000) {
6974 /* Load/store doubleword. */
6975 if (rn == 15) {
6976 addr = new_tmp();
6977 tcg_gen_movi_i32(addr, s->pc & ~3);
6978 } else {
6979 addr = load_reg(s, rn);
6980 }
6981 offset = (insn & 0xff) * 4;
6982 if ((insn & (1 << 23)) == 0)
6983 offset = -offset;
6984 if (insn & (1 << 24)) {
6985 tcg_gen_addi_i32(addr, addr, offset);
6986 offset = 0;
6987 }
6988 if (insn & (1 << 20)) {
6989 /* ldrd */
6990 tmp = gen_ld32(addr, IS_USER(s));
6991 store_reg(s, rs, tmp);
6992 tcg_gen_addi_i32(addr, addr, 4);
6993 tmp = gen_ld32(addr, IS_USER(s));
6994 store_reg(s, rd, tmp);
6995 } else {
6996 /* strd */
6997 tmp = load_reg(s, rs);
6998 gen_st32(tmp, addr, IS_USER(s));
6999 tcg_gen_addi_i32(addr, addr, 4);
7000 tmp = load_reg(s, rd);
7001 gen_st32(tmp, addr, IS_USER(s));
7002 }
7003 if (insn & (1 << 21)) {
7004 /* Base writeback. */
7005 if (rn == 15)
7006 goto illegal_op;
7007 tcg_gen_addi_i32(addr, addr, offset - 4);
7008 store_reg(s, rn, addr);
7009 } else {
7010 dead_tmp(addr);
7011 }
7012 } else if ((insn & (1 << 23)) == 0) {
7013 /* Load/store exclusive word. */
7014 gen_movl_T1_reg(s, rn);
7015 addr = cpu_T[1];
7016 if (insn & (1 << 20)) {
7017 gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
7018 tmp = gen_ld32(addr, IS_USER(s));
7019 store_reg(s, rd, tmp);
7020 } else {
7021 int label = gen_new_label();
7022 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
7023 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
7024 0, label);
7025 tmp = load_reg(s, rs);
7026 gen_st32(tmp, cpu_T[1], IS_USER(s));
7027 gen_set_label(label);
7028 gen_movl_reg_T0(s, rd);
7029 }
7030 } else if ((insn & (1 << 6)) == 0) {
7031 /* Table Branch. */
7032 if (rn == 15) {
7033 addr = new_tmp();
7034 tcg_gen_movi_i32(addr, s->pc);
7035 } else {
7036 addr = load_reg(s, rn);
7037 }
7038 tmp = load_reg(s, rm);
7039 tcg_gen_add_i32(addr, addr, tmp);
7040 if (insn & (1 << 4)) {
7041 /* tbh */
7042 tcg_gen_add_i32(addr, addr, tmp);
7043 dead_tmp(tmp);
7044 tmp = gen_ld16u(addr, IS_USER(s));
7045 } else { /* tbb */
7046 dead_tmp(tmp);
7047 tmp = gen_ld8u(addr, IS_USER(s));
7048 }
7049 dead_tmp(addr);
7050 tcg_gen_shli_i32(tmp, tmp, 1);
7051 tcg_gen_addi_i32(tmp, tmp, s->pc);
7052 store_reg(s, 15, tmp);
7053 } else {
7054 /* Load/store exclusive byte/halfword/doubleword. */
7055 /* ??? These are not really atomic. However we know
7056 we never have multiple CPUs running in parallel,
7057 so it is good enough. */
7058 op = (insn >> 4) & 0x3;
7059 /* Must use a global reg for the address because we have
7060 a conditional branch in the store instruction. */
7061 gen_movl_T1_reg(s, rn);
7062 addr = cpu_T[1];
7063 if (insn & (1 << 20)) {
7064 gen_helper_mark_exclusive(cpu_env, addr);
7065 switch (op) {
7066 case 0:
7067 tmp = gen_ld8u(addr, IS_USER(s));
7068 break;
7069 case 1:
7070 tmp = gen_ld16u(addr, IS_USER(s));
7071 break;
7072 case 3:
7073 tmp = gen_ld32(addr, IS_USER(s));
7074 tcg_gen_addi_i32(addr, addr, 4);
7075 tmp2 = gen_ld32(addr, IS_USER(s));
7076 store_reg(s, rd, tmp2);
7077 break;
7078 default:
7079 goto illegal_op;
7080 }
7081 store_reg(s, rs, tmp);
7082 } else {
7083 int label = gen_new_label();
7084 /* Must use a global that is not killed by the branch. */
7085 gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
7086 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label);
7087 tmp = load_reg(s, rs);
7088 switch (op) {
7089 case 0:
7090 gen_st8(tmp, addr, IS_USER(s));
7091 break;
7092 case 1:
7093 gen_st16(tmp, addr, IS_USER(s));
7094 break;
7095 case 3:
7096 gen_st32(tmp, addr, IS_USER(s));
7097 tcg_gen_addi_i32(addr, addr, 4);
7098 tmp = load_reg(s, rd);
7099 gen_st32(tmp, addr, IS_USER(s));
7100 break;
7101 default:
7102 goto illegal_op;
7103 }
7104 gen_set_label(label);
7105 gen_movl_reg_T0(s, rm);
7106 }
7107 }
7108 } else {
7109 /* Load/store multiple, RFE, SRS. */
7110 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7111 /* Not available in user mode. */
7112 if (IS_USER(s))
7113 goto illegal_op;
7114 if (insn & (1 << 20)) {
7115 /* rfe */
7116 addr = load_reg(s, rn);
7117 if ((insn & (1 << 24)) == 0)
7118 tcg_gen_addi_i32(addr, addr, -8);
7119 /* Load PC into tmp and CPSR into tmp2. */
7120 tmp = gen_ld32(addr, 0);
7121 tcg_gen_addi_i32(addr, addr, 4);
7122 tmp2 = gen_ld32(addr, 0);
7123 if (insn & (1 << 21)) {
7124 /* Base writeback. */
7125 if (insn & (1 << 24)) {
7126 tcg_gen_addi_i32(addr, addr, 4);
7127 } else {
7128 tcg_gen_addi_i32(addr, addr, -4);
7129 }
7130 store_reg(s, rn, addr);
7131 } else {
7132 dead_tmp(addr);
7133 }
7134 gen_rfe(s, tmp, tmp2);
7135 } else {
7136 /* srs */
7137 op = (insn & 0x1f);
7138 if (op == (env->uncached_cpsr & CPSR_M)) {
7139 addr = load_reg(s, 13);
7140 } else {
7141 addr = new_tmp();
7142 gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op));
7143 }
7144 if ((insn & (1 << 24)) == 0) {
7145 tcg_gen_addi_i32(addr, addr, -8);
7146 }
7147 tmp = load_reg(s, 14);
7148 gen_st32(tmp, addr, 0);
7149 tcg_gen_addi_i32(addr, addr, 4);
7150 tmp = new_tmp();
7151 gen_helper_cpsr_read(tmp);
7152 gen_st32(tmp, addr, 0);
7153 if (insn & (1 << 21)) {
7154 if ((insn & (1 << 24)) == 0) {
7155 tcg_gen_addi_i32(addr, addr, -4);
7156 } else {
7157 tcg_gen_addi_i32(addr, addr, 4);
7158 }
7159 if (op == (env->uncached_cpsr & CPSR_M)) {
7160 store_reg(s, 13, addr);
7161 } else {
7162 gen_helper_set_r13_banked(cpu_env,
7163 tcg_const_i32(op), addr);
7164 }
7165 } else {
7166 dead_tmp(addr);
7167 }
7168 }
7169 } else {
7170 int i;
7171 /* Load/store multiple. */
7172 addr = load_reg(s, rn);
7173 offset = 0;
7174 for (i = 0; i < 16; i++) {
7175 if (insn & (1 << i))
7176 offset += 4;
7177 }
7178 if (insn & (1 << 24)) {
7179 tcg_gen_addi_i32(addr, addr, -offset);
7180 }
7181
7182 for (i = 0; i < 16; i++) {
7183 if ((insn & (1 << i)) == 0)
7184 continue;
7185 if (insn & (1 << 20)) {
7186 /* Load. */
7187 tmp = gen_ld32(addr, IS_USER(s));
7188 if (i == 15) {
7189 gen_bx(s, tmp);
7190 } else {
7191 store_reg(s, i, tmp);
7192 }
7193 } else {
7194 /* Store. */
7195 tmp = load_reg(s, i);
7196 gen_st32(tmp, addr, IS_USER(s));
7197 }
7198 tcg_gen_addi_i32(addr, addr, 4);
7199 }
7200 if (insn & (1 << 21)) {
7201 /* Base register writeback. */
7202 if (insn & (1 << 24)) {
7203 tcg_gen_addi_i32(addr, addr, -offset);
7204 }
7205 /* Fault if writeback register is in register list. */
7206 if (insn & (1 << rn))
7207 goto illegal_op;
7208 store_reg(s, rn, addr);
7209 } else {
7210 dead_tmp(addr);
7211 }
7212 }
7213 }
7214 break;
7215 case 5: /* Data processing register constant shift. */
7216 if (rn == 15)
7217 gen_op_movl_T0_im(0);
7218 else
7219 gen_movl_T0_reg(s, rn);
7220 gen_movl_T1_reg(s, rm);
7221 op = (insn >> 21) & 0xf;
7222 shiftop = (insn >> 4) & 3;
7223 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7224 conds = (insn & (1 << 20)) != 0;
7225 logic_cc = (conds && thumb2_logic_op(op));
7226 gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
7227 if (gen_thumb2_data_op(s, op, conds, 0))
7228 goto illegal_op;
7229 if (rd != 15)
7230 gen_movl_reg_T0(s, rd);
7231 break;
7232 case 13: /* Misc data processing. */
7233 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7234 if (op < 4 && (insn & 0xf000) != 0xf000)
7235 goto illegal_op;
7236 switch (op) {
7237 case 0: /* Register controlled shift. */
7238 tmp = load_reg(s, rn);
7239 tmp2 = load_reg(s, rm);
7240 if ((insn & 0x70) != 0)
7241 goto illegal_op;
7242 op = (insn >> 21) & 3;
7243 logic_cc = (insn & (1 << 20)) != 0;
7244 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7245 if (logic_cc)
7246 gen_logic_CC(tmp);
7247 store_reg(s, rd, tmp);
7248 break;
7249 case 1: /* Sign/zero extend. */
7250 tmp = load_reg(s, rm);
7251 shift = (insn >> 4) & 3;
7252 /* ??? In many cases it's not neccessary to do a
7253 rotate, a shift is sufficient. */
7254 if (shift != 0)
7255 tcg_gen_rori_i32(tmp, tmp, shift * 8);
7256 op = (insn >> 20) & 7;
7257 switch (op) {
7258 case 0: gen_sxth(tmp); break;
7259 case 1: gen_uxth(tmp); break;
7260 case 2: gen_sxtb16(tmp); break;
7261 case 3: gen_uxtb16(tmp); break;
7262 case 4: gen_sxtb(tmp); break;
7263 case 5: gen_uxtb(tmp); break;
7264 default: goto illegal_op;
7265 }
7266 if (rn != 15) {
7267 tmp2 = load_reg(s, rn);
7268 if ((op >> 1) == 1) {
7269 gen_add16(tmp, tmp2);
7270 } else {
7271 tcg_gen_add_i32(tmp, tmp, tmp2);
7272 dead_tmp(tmp2);
7273 }
7274 }
7275 store_reg(s, rd, tmp);
7276 break;
7277 case 2: /* SIMD add/subtract. */
7278 op = (insn >> 20) & 7;
7279 shift = (insn >> 4) & 7;
7280 if ((op & 3) == 3 || (shift & 3) == 3)
7281 goto illegal_op;
7282 tmp = load_reg(s, rn);
7283 tmp2 = load_reg(s, rm);
7284 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7285 dead_tmp(tmp2);
7286 store_reg(s, rd, tmp);
7287 break;
7288 case 3: /* Other data processing. */
7289 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7290 if (op < 4) {
7291 /* Saturating add/subtract. */
7292 tmp = load_reg(s, rn);
7293 tmp2 = load_reg(s, rm);
7294 if (op & 2)
7295 gen_helper_double_saturate(tmp, tmp);
7296 if (op & 1)
7297 gen_helper_sub_saturate(tmp, tmp2, tmp);
7298 else
7299 gen_helper_add_saturate(tmp, tmp, tmp2);
7300 dead_tmp(tmp2);
7301 } else {
7302 tmp = load_reg(s, rn);
7303 switch (op) {
7304 case 0x0a: /* rbit */
7305 gen_helper_rbit(tmp, tmp);
7306 break;
7307 case 0x08: /* rev */
7308 tcg_gen_bswap_i32(tmp, tmp);
7309 break;
7310 case 0x09: /* rev16 */
7311 gen_rev16(tmp);
7312 break;
7313 case 0x0b: /* revsh */
7314 gen_revsh(tmp);
7315 break;
7316 case 0x10: /* sel */
7317 tmp2 = load_reg(s, rm);
7318 tmp3 = new_tmp();
7319 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7320 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7321 dead_tmp(tmp3);
7322 dead_tmp(tmp2);
7323 break;
7324 case 0x18: /* clz */
7325 gen_helper_clz(tmp, tmp);
7326 break;
7327 default:
7328 goto illegal_op;
7329 }
7330 }
7331 store_reg(s, rd, tmp);
7332 break;
7333 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7334 op = (insn >> 4) & 0xf;
7335 tmp = load_reg(s, rn);
7336 tmp2 = load_reg(s, rm);
7337 switch ((insn >> 20) & 7) {
7338 case 0: /* 32 x 32 -> 32 */
7339 tcg_gen_mul_i32(tmp, tmp, tmp2);
7340 dead_tmp(tmp2);
7341 if (rs != 15) {
7342 tmp2 = load_reg(s, rs);
7343 if (op)
7344 tcg_gen_sub_i32(tmp, tmp2, tmp);
7345 else
7346 tcg_gen_add_i32(tmp, tmp, tmp2);
7347 dead_tmp(tmp2);
7348 }
7349 break;
7350 case 1: /* 16 x 16 -> 32 */
7351 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7352 dead_tmp(tmp2);
7353 if (rs != 15) {
7354 tmp2 = load_reg(s, rs);
7355 gen_helper_add_setq(tmp, tmp, tmp2);
7356 dead_tmp(tmp2);
7357 }
7358 break;
7359 case 2: /* Dual multiply add. */
7360 case 4: /* Dual multiply subtract. */
7361 if (op)
7362 gen_swap_half(tmp2);
7363 gen_smul_dual(tmp, tmp2);
7364 /* This addition cannot overflow. */
7365 if (insn & (1 << 22)) {
7366 tcg_gen_sub_i32(tmp, tmp, tmp2);
7367 } else {
7368 tcg_gen_add_i32(tmp, tmp, tmp2);
7369 }
7370 dead_tmp(tmp2);
7371 if (rs != 15)
7372 {
7373 tmp2 = load_reg(s, rs);
7374 gen_helper_add_setq(tmp, tmp, tmp2);
7375 dead_tmp(tmp2);
7376 }
7377 break;
7378 case 3: /* 32 * 16 -> 32msb */
7379 if (op)
7380 tcg_gen_sari_i32(tmp2, tmp2, 16);
7381 else
7382 gen_sxth(tmp2);
7383 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7384 tcg_gen_shri_i64(tmp64, tmp64, 16);
7385 tmp = new_tmp();
7386 tcg_gen_trunc_i64_i32(tmp, tmp64);
7387 if (rs != 15)
7388 {
7389 tmp2 = load_reg(s, rs);
7390 gen_helper_add_setq(tmp, tmp, tmp2);
7391 dead_tmp(tmp2);
7392 }
7393 break;
7394 case 5: case 6: /* 32 * 32 -> 32msb */
7395 gen_imull(tmp, tmp2);
7396 if (insn & (1 << 5)) {
7397 gen_roundqd(tmp, tmp2);
7398 dead_tmp(tmp2);
7399 } else {
7400 dead_tmp(tmp);
7401 tmp = tmp2;
7402 }
7403 if (rs != 15) {
7404 tmp2 = load_reg(s, rs);
7405 if (insn & (1 << 21)) {
7406 tcg_gen_add_i32(tmp, tmp, tmp2);
7407 } else {
7408 tcg_gen_sub_i32(tmp, tmp2, tmp);
7409 }
7410 dead_tmp(tmp2);
7411 }
7412 break;
7413 case 7: /* Unsigned sum of absolute differences. */
7414 gen_helper_usad8(tmp, tmp, tmp2);
7415 dead_tmp(tmp2);
7416 if (rs != 15) {
7417 tmp2 = load_reg(s, rs);
7418 tcg_gen_add_i32(tmp, tmp, tmp2);
7419 dead_tmp(tmp2);
7420 }
7421 break;
7422 }
7423 store_reg(s, rd, tmp);
7424 break;
7425 case 6: case 7: /* 64-bit multiply, Divide. */
7426 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7427 tmp = load_reg(s, rn);
7428 tmp2 = load_reg(s, rm);
7429 if ((op & 0x50) == 0x10) {
7430 /* sdiv, udiv */
7431 if (!arm_feature(env, ARM_FEATURE_DIV))
7432 goto illegal_op;
7433 if (op & 0x20)
7434 gen_helper_udiv(tmp, tmp, tmp2);
7435 else
7436 gen_helper_sdiv(tmp, tmp, tmp2);
7437 dead_tmp(tmp2);
7438 store_reg(s, rd, tmp);
7439 } else if ((op & 0xe) == 0xc) {
7440 /* Dual multiply accumulate long. */
7441 if (op & 1)
7442 gen_swap_half(tmp2);
7443 gen_smul_dual(tmp, tmp2);
7444 if (op & 0x10) {
7445 tcg_gen_sub_i32(tmp, tmp, tmp2);
7446 } else {
7447 tcg_gen_add_i32(tmp, tmp, tmp2);
7448 }
7449 dead_tmp(tmp2);
7450 /* BUGFIX */
7451 tmp64 = tcg_temp_new_i64();
7452 tcg_gen_ext_i32_i64(tmp64, tmp);
7453 dead_tmp(tmp);
7454 gen_addq(s, tmp64, rs, rd);
7455 gen_storeq_reg(s, rs, rd, tmp64);
7456 } else {
7457 if (op & 0x20) {
7458 /* Unsigned 64-bit multiply */
7459 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7460 } else {
7461 if (op & 8) {
7462 /* smlalxy */
7463 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7464 dead_tmp(tmp2);
7465 tmp64 = tcg_temp_new_i64();
7466 tcg_gen_ext_i32_i64(tmp64, tmp);
7467 dead_tmp(tmp);
7468 } else {
7469 /* Signed 64-bit multiply */
7470 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7471 }
7472 }
7473 if (op & 4) {
7474 /* umaal */
7475 gen_addq_lo(s, tmp64, rs);
7476 gen_addq_lo(s, tmp64, rd);
7477 } else if (op & 0x40) {
7478 /* 64-bit accumulate. */
7479 gen_addq(s, tmp64, rs, rd);
7480 }
7481 gen_storeq_reg(s, rs, rd, tmp64);
7482 }
7483 break;
7484 }
7485 break;
7486 case 6: case 7: case 14: case 15:
7487 /* Coprocessor. */
7488 if (((insn >> 24) & 3) == 3) {
7489 /* Translate into the equivalent ARM encoding. */
7490 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7491 if (disas_neon_data_insn(env, s, insn))
7492 goto illegal_op;
7493 } else {
7494 if (insn & (1 << 28))
7495 goto illegal_op;
7496 if (disas_coproc_insn (env, s, insn))
7497 goto illegal_op;
7498 }
7499 break;
7500 case 8: case 9: case 10: case 11:
7501 if (insn & (1 << 15)) {
7502 /* Branches, misc control. */
7503 if (insn & 0x5000) {
7504 /* Unconditional branch. */
7505 /* signextend(hw1[10:0]) -> offset[:12]. */
7506 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7507 /* hw1[10:0] -> offset[11:1]. */
7508 offset |= (insn & 0x7ff) << 1;
7509 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7510 offset[24:22] already have the same value because of the
7511 sign extension above. */
7512 offset ^= ((~insn) & (1 << 13)) << 10;
7513 offset ^= ((~insn) & (1 << 11)) << 11;
7514
7515 if (insn & (1 << 14)) {
7516 /* Branch and link. */
7517 gen_op_movl_T1_im(s->pc | 1);
7518 gen_movl_reg_T1(s, 14);
7519 }
7520
7521 offset += s->pc;
7522 if (insn & (1 << 12)) {
7523 /* b/bl */
7524 gen_jmp(s, offset);
7525 } else {
7526 /* blx */
7527 offset &= ~(uint32_t)2;
7528 gen_bx_im(s, offset);
7529 }
7530 } else if (((insn >> 23) & 7) == 7) {
7531 /* Misc control */
7532 if (insn & (1 << 13))
7533 goto illegal_op;
7534
7535 if (insn & (1 << 26)) {
7536 /* Secure monitor call (v6Z) */
7537 goto illegal_op; /* not implemented. */
7538 } else {
7539 op = (insn >> 20) & 7;
7540 switch (op) {
7541 case 0: /* msr cpsr. */
7542 if (IS_M(env)) {
7543 tmp = load_reg(s, rn);
7544 addr = tcg_const_i32(insn & 0xff);
7545 gen_helper_v7m_msr(cpu_env, addr, tmp);
7546 gen_lookup_tb(s);
7547 break;
7548 }
7549 /* fall through */
7550 case 1: /* msr spsr. */
7551 if (IS_M(env))
7552 goto illegal_op;
7553 gen_movl_T0_reg(s, rn);
7554 if (gen_set_psr_T0(s,
7555 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
7556 op == 1))
7557 goto illegal_op;
7558 break;
7559 case 2: /* cps, nop-hint. */
7560 if (((insn >> 8) & 7) == 0) {
7561 gen_nop_hint(s, insn & 0xff);
7562 }
7563 /* Implemented as NOP in user mode. */
7564 if (IS_USER(s))
7565 break;
7566 offset = 0;
7567 imm = 0;
7568 if (insn & (1 << 10)) {
7569 if (insn & (1 << 7))
7570 offset |= CPSR_A;
7571 if (insn & (1 << 6))
7572 offset |= CPSR_I;
7573 if (insn & (1 << 5))
7574 offset |= CPSR_F;
7575 if (insn & (1 << 9))
7576 imm = CPSR_A | CPSR_I | CPSR_F;
7577 }
7578 if (insn & (1 << 8)) {
7579 offset |= 0x1f;
7580 imm |= (insn & 0x1f);
7581 }
7582 if (offset) {
7583 gen_op_movl_T0_im(imm);
7584 gen_set_psr_T0(s, offset, 0);
7585 }
7586 break;
7587 case 3: /* Special control operations. */
7588 op = (insn >> 4) & 0xf;
7589 switch (op) {
7590 case 2: /* clrex */
7591 gen_helper_clrex(cpu_env);
7592 break;
7593 case 4: /* dsb */
7594 case 5: /* dmb */
7595 case 6: /* isb */
7596 /* These execute as NOPs. */
7597 ARCH(7);
7598 break;
7599 default:
7600 goto illegal_op;
7601 }
7602 break;
7603 case 4: /* bxj */
7604 /* Trivial implementation equivalent to bx. */
7605 tmp = load_reg(s, rn);
7606 gen_bx(s, tmp);
7607 break;
7608 case 5: /* Exception return. */
7609 /* Unpredictable in user mode. */
7610 goto illegal_op;
7611 case 6: /* mrs cpsr. */
7612 tmp = new_tmp();
7613 if (IS_M(env)) {
7614 addr = tcg_const_i32(insn & 0xff);
7615 gen_helper_v7m_mrs(tmp, cpu_env, addr);
7616 } else {
7617 gen_helper_cpsr_read(tmp);
7618 }
7619 store_reg(s, rd, tmp);
7620 break;
7621 case 7: /* mrs spsr. */
7622 /* Not accessible in user mode. */
7623 if (IS_USER(s) || IS_M(env))
7624 goto illegal_op;
7625 tmp = load_cpu_field(spsr);
7626 store_reg(s, rd, tmp);
7627 break;
7628 }
7629 }
7630 } else {
7631 /* Conditional branch. */
7632 op = (insn >> 22) & 0xf;
7633 /* Generate a conditional jump to next instruction. */
7634 s->condlabel = gen_new_label();
7635 gen_test_cc(op ^ 1, s->condlabel);
7636 s->condjmp = 1;
7637
7638 /* offset[11:1] = insn[10:0] */
7639 offset = (insn & 0x7ff) << 1;
7640 /* offset[17:12] = insn[21:16]. */
7641 offset |= (insn & 0x003f0000) >> 4;
7642 /* offset[31:20] = insn[26]. */
7643 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
7644 /* offset[18] = insn[13]. */
7645 offset |= (insn & (1 << 13)) << 5;
7646 /* offset[19] = insn[11]. */
7647 offset |= (insn & (1 << 11)) << 8;
7648
7649 /* jump to the offset */
7650 gen_jmp(s, s->pc + offset);
7651 }
7652 } else {
7653 /* Data processing immediate. */
7654 if (insn & (1 << 25)) {
7655 if (insn & (1 << 24)) {
7656 if (insn & (1 << 20))
7657 goto illegal_op;
7658 /* Bitfield/Saturate. */
7659 op = (insn >> 21) & 7;
7660 imm = insn & 0x1f;
7661 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7662 if (rn == 15) {
7663 tmp = new_tmp();
7664 tcg_gen_movi_i32(tmp, 0);
7665 } else {
7666 tmp = load_reg(s, rn);
7667 }
7668 switch (op) {
7669 case 2: /* Signed bitfield extract. */
7670 imm++;
7671 if (shift + imm > 32)
7672 goto illegal_op;
7673 if (imm < 32)
7674 gen_sbfx(tmp, shift, imm);
7675 break;
7676 case 6: /* Unsigned bitfield extract. */
7677 imm++;
7678 if (shift + imm > 32)
7679 goto illegal_op;
7680 if (imm < 32)
7681 gen_ubfx(tmp, shift, (1u << imm) - 1);
7682 break;
7683 case 3: /* Bitfield insert/clear. */
7684 if (imm < shift)
7685 goto illegal_op;
7686 imm = imm + 1 - shift;
7687 if (imm != 32) {
7688 tmp2 = load_reg(s, rd);
7689 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
7690 dead_tmp(tmp2);
7691 }
7692 break;
7693 case 7:
7694 goto illegal_op;
7695 default: /* Saturate. */
7696 if (shift) {
7697 if (op & 1)
7698 tcg_gen_sari_i32(tmp, tmp, shift);
7699 else
7700 tcg_gen_shli_i32(tmp, tmp, shift);
7701 }
7702 tmp2 = tcg_const_i32(imm);
7703 if (op & 4) {
7704 /* Unsigned. */
7705 if ((op & 1) && shift == 0)
7706 gen_helper_usat16(tmp, tmp, tmp2);
7707 else
7708 gen_helper_usat(tmp, tmp, tmp2);
7709 } else {
7710 /* Signed. */
7711 if ((op & 1) && shift == 0)
7712 gen_helper_ssat16(tmp, tmp, tmp2);
7713 else
7714 gen_helper_ssat(tmp, tmp, tmp2);
7715 }
7716 break;
7717 }
7718 store_reg(s, rd, tmp);
7719 } else {
7720 imm = ((insn & 0x04000000) >> 15)
7721 | ((insn & 0x7000) >> 4) | (insn & 0xff);
7722 if (insn & (1 << 22)) {
7723 /* 16-bit immediate. */
7724 imm |= (insn >> 4) & 0xf000;
7725 if (insn & (1 << 23)) {
7726 /* movt */
7727 tmp = load_reg(s, rd);
7728 tcg_gen_ext16u_i32(tmp, tmp);
7729 tcg_gen_ori_i32(tmp, tmp, imm << 16);
7730 } else {
7731 /* movw */
7732 tmp = new_tmp();
7733 tcg_gen_movi_i32(tmp, imm);
7734 }
7735 } else {
7736 /* Add/sub 12-bit immediate. */
7737 if (rn == 15) {
7738 offset = s->pc & ~(uint32_t)3;
7739 if (insn & (1 << 23))
7740 offset -= imm;
7741 else
7742 offset += imm;
7743 tmp = new_tmp();
7744 tcg_gen_movi_i32(tmp, offset);
7745 } else {
7746 tmp = load_reg(s, rn);
7747 if (insn & (1 << 23))
7748 tcg_gen_subi_i32(tmp, tmp, imm);
7749 else
7750 tcg_gen_addi_i32(tmp, tmp, imm);
7751 }
7752 }
7753 store_reg(s, rd, tmp);
7754 }
7755 } else {
7756 int shifter_out = 0;
7757 /* modified 12-bit immediate. */
7758 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
7759 imm = (insn & 0xff);
7760 switch (shift) {
7761 case 0: /* XY */
7762 /* Nothing to do. */
7763 break;
7764 case 1: /* 00XY00XY */
7765 imm |= imm << 16;
7766 break;
7767 case 2: /* XY00XY00 */
7768 imm |= imm << 16;
7769 imm <<= 8;
7770 break;
7771 case 3: /* XYXYXYXY */
7772 imm |= imm << 16;
7773 imm |= imm << 8;
7774 break;
7775 default: /* Rotated constant. */
7776 shift = (shift << 1) | (imm >> 7);
7777 imm |= 0x80;
7778 imm = imm << (32 - shift);
7779 shifter_out = 1;
7780 break;
7781 }
7782 gen_op_movl_T1_im(imm);
7783 rn = (insn >> 16) & 0xf;
7784 if (rn == 15)
7785 gen_op_movl_T0_im(0);
7786 else
7787 gen_movl_T0_reg(s, rn);
7788 op = (insn >> 21) & 0xf;
7789 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
7790 shifter_out))
7791 goto illegal_op;
7792 rd = (insn >> 8) & 0xf;
7793 if (rd != 15) {
7794 gen_movl_reg_T0(s, rd);
7795 }
7796 }
7797 }
7798 break;
7799 case 12: /* Load/store single data item. */
7800 {
7801 int postinc = 0;
7802 int writeback = 0;
7803 int user;
7804 if ((insn & 0x01100000) == 0x01000000) {
7805 if (disas_neon_ls_insn(env, s, insn))
7806 goto illegal_op;
7807 break;
7808 }
7809 user = IS_USER(s);
7810 if (rn == 15) {
7811 addr = new_tmp();
7812 /* PC relative. */
7813 /* s->pc has already been incremented by 4. */
7814 imm = s->pc & 0xfffffffc;
7815 if (insn & (1 << 23))
7816 imm += insn & 0xfff;
7817 else
7818 imm -= insn & 0xfff;
7819 tcg_gen_movi_i32(addr, imm);
7820 } else {
7821 addr = load_reg(s, rn);
7822 if (insn & (1 << 23)) {
7823 /* Positive offset. */
7824 imm = insn & 0xfff;
7825 tcg_gen_addi_i32(addr, addr, imm);
7826 } else {
7827 op = (insn >> 8) & 7;
7828 imm = insn & 0xff;
7829 switch (op) {
7830 case 0: case 8: /* Shifted Register. */
7831 shift = (insn >> 4) & 0xf;
7832 if (shift > 3)
7833 goto illegal_op;
7834 tmp = load_reg(s, rm);
7835 if (shift)
7836 tcg_gen_shli_i32(tmp, tmp, shift);
7837 tcg_gen_add_i32(addr, addr, tmp);
7838 dead_tmp(tmp);
7839 break;
7840 case 4: /* Negative offset. */
7841 tcg_gen_addi_i32(addr, addr, -imm);
7842 break;
7843 case 6: /* User privilege. */
7844 tcg_gen_addi_i32(addr, addr, imm);
7845 user = 1;
7846 break;
7847 case 1: /* Post-decrement. */
7848 imm = -imm;
7849 /* Fall through. */
7850 case 3: /* Post-increment. */
7851 postinc = 1;
7852 writeback = 1;
7853 break;
7854 case 5: /* Pre-decrement. */
7855 imm = -imm;
7856 /* Fall through. */
7857 case 7: /* Pre-increment. */
7858 tcg_gen_addi_i32(addr, addr, imm);
7859 writeback = 1;
7860 break;
7861 default:
7862 goto illegal_op;
7863 }
7864 }
7865 }
7866 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
7867 if (insn & (1 << 20)) {
7868 /* Load. */
7869 if (rs == 15 && op != 2) {
7870 if (op & 2)
7871 goto illegal_op;
7872 /* Memory hint. Implemented as NOP. */
7873 } else {
7874 switch (op) {
7875 case 0: tmp = gen_ld8u(addr, user); break;
7876 case 4: tmp = gen_ld8s(addr, user); break;
7877 case 1: tmp = gen_ld16u(addr, user); break;
7878 case 5: tmp = gen_ld16s(addr, user); break;
7879 case 2: tmp = gen_ld32(addr, user); break;
7880 default: goto illegal_op;
7881 }
7882 if (rs == 15) {
7883 gen_bx(s, tmp);
7884 } else {
7885 store_reg(s, rs, tmp);
7886 }
7887 }
7888 } else {
7889 /* Store. */
7890 if (rs == 15)
7891 goto illegal_op;
7892 tmp = load_reg(s, rs);
7893 switch (op) {
7894 case 0: gen_st8(tmp, addr, user); break;
7895 case 1: gen_st16(tmp, addr, user); break;
7896 case 2: gen_st32(tmp, addr, user); break;
7897 default: goto illegal_op;
7898 }
7899 }
7900 if (postinc)
7901 tcg_gen_addi_i32(addr, addr, imm);
7902 if (writeback) {
7903 store_reg(s, rn, addr);
7904 } else {
7905 dead_tmp(addr);
7906 }
7907 }
7908 break;
7909 default:
7910 goto illegal_op;
7911 }
7912 return 0;
7913 illegal_op:
7914 return 1;
7915 }
7916
7917 static void disas_thumb_insn(CPUState *env, DisasContext *s)
7918 {
7919 uint32_t val, insn, op, rm, rn, rd, shift, cond;
7920 int32_t offset;
7921 int i;
7922 TCGv tmp;
7923 TCGv tmp2;
7924 TCGv addr;
7925
7926 if (s->condexec_mask) {
7927 cond = s->condexec_cond;
7928 s->condlabel = gen_new_label();
7929 gen_test_cc(cond ^ 1, s->condlabel);
7930 s->condjmp = 1;
7931 }
7932
7933 insn = lduw_code(s->pc);
7934 s->pc += 2;
7935
7936 switch (insn >> 12) {
7937 case 0: case 1:
7938 rd = insn & 7;
7939 op = (insn >> 11) & 3;
7940 if (op == 3) {
7941 /* add/subtract */
7942 rn = (insn >> 3) & 7;
7943 gen_movl_T0_reg(s, rn);
7944 if (insn & (1 << 10)) {
7945 /* immediate */
7946 gen_op_movl_T1_im((insn >> 6) & 7);
7947 } else {
7948 /* reg */
7949 rm = (insn >> 6) & 7;
7950 gen_movl_T1_reg(s, rm);
7951 }
7952 if (insn & (1 << 9)) {
7953 if (s->condexec_mask)
7954 gen_op_subl_T0_T1();
7955 else
7956 gen_op_subl_T0_T1_cc();
7957 } else {
7958 if (s->condexec_mask)
7959 gen_op_addl_T0_T1();
7960 else
7961 gen_op_addl_T0_T1_cc();
7962 }
7963 gen_movl_reg_T0(s, rd);
7964 } else {
7965 /* shift immediate */
7966 rm = (insn >> 3) & 7;
7967 shift = (insn >> 6) & 0x1f;
7968 tmp = load_reg(s, rm);
7969 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
7970 if (!s->condexec_mask)
7971 gen_logic_CC(tmp);
7972 store_reg(s, rd, tmp);
7973 }
7974 break;
7975 case 2: case 3:
7976 /* arithmetic large immediate */
7977 op = (insn >> 11) & 3;
7978 rd = (insn >> 8) & 0x7;
7979 if (op == 0) {
7980 gen_op_movl_T0_im(insn & 0xff);
7981 } else {
7982 gen_movl_T0_reg(s, rd);
7983 gen_op_movl_T1_im(insn & 0xff);
7984 }
7985 switch (op) {
7986 case 0: /* mov */
7987 if (!s->condexec_mask)
7988 gen_op_logic_T0_cc();
7989 break;
7990 case 1: /* cmp */
7991 gen_op_subl_T0_T1_cc();
7992 break;
7993 case 2: /* add */
7994 if (s->condexec_mask)
7995 gen_op_addl_T0_T1();
7996 else
7997 gen_op_addl_T0_T1_cc();
7998 break;
7999 case 3: /* sub */
8000 if (s->condexec_mask)
8001 gen_op_subl_T0_T1();
8002 else
8003 gen_op_subl_T0_T1_cc();
8004 break;
8005 }
8006 if (op != 1)
8007 gen_movl_reg_T0(s, rd);
8008 break;
8009 case 4:
8010 if (insn & (1 << 11)) {
8011 rd = (insn >> 8) & 7;
8012 /* load pc-relative. Bit 1 of PC is ignored. */
8013 val = s->pc + 2 + ((insn & 0xff) * 4);
8014 val &= ~(uint32_t)2;
8015 addr = new_tmp();
8016 tcg_gen_movi_i32(addr, val);
8017 tmp = gen_ld32(addr, IS_USER(s));
8018 dead_tmp(addr);
8019 store_reg(s, rd, tmp);
8020 break;
8021 }
8022 if (insn & (1 << 10)) {
8023 /* data processing extended or blx */
8024 rd = (insn & 7) | ((insn >> 4) & 8);
8025 rm = (insn >> 3) & 0xf;
8026 op = (insn >> 8) & 3;
8027 switch (op) {
8028 case 0: /* add */
8029 gen_movl_T0_reg(s, rd);
8030 gen_movl_T1_reg(s, rm);
8031 gen_op_addl_T0_T1();
8032 gen_movl_reg_T0(s, rd);
8033 break;
8034 case 1: /* cmp */
8035 gen_movl_T0_reg(s, rd);
8036 gen_movl_T1_reg(s, rm);
8037 gen_op_subl_T0_T1_cc();
8038 break;
8039 case 2: /* mov/cpy */
8040 gen_movl_T0_reg(s, rm);
8041 gen_movl_reg_T0(s, rd);
8042 break;
8043 case 3:/* branch [and link] exchange thumb register */
8044 tmp = load_reg(s, rm);
8045 if (insn & (1 << 7)) {
8046 val = (uint32_t)s->pc | 1;
8047 tmp2 = new_tmp();
8048 tcg_gen_movi_i32(tmp2, val);
8049 store_reg(s, 14, tmp2);
8050 }
8051 gen_bx(s, tmp);
8052 break;
8053 }
8054 break;
8055 }
8056
8057 /* data processing register */
8058 rd = insn & 7;
8059 rm = (insn >> 3) & 7;
8060 op = (insn >> 6) & 0xf;
8061 if (op == 2 || op == 3 || op == 4 || op == 7) {
8062 /* the shift/rotate ops want the operands backwards */
8063 val = rm;
8064 rm = rd;
8065 rd = val;
8066 val = 1;
8067 } else {
8068 val = 0;
8069 }
8070
8071 if (op == 9) /* neg */
8072 gen_op_movl_T0_im(0);
8073 else if (op != 0xf) /* mvn doesn't read its first operand */
8074 gen_movl_T0_reg(s, rd);
8075
8076 gen_movl_T1_reg(s, rm);
8077 switch (op) {
8078 case 0x0: /* and */
8079 gen_op_andl_T0_T1();
8080 if (!s->condexec_mask)
8081 gen_op_logic_T0_cc();
8082 break;
8083 case 0x1: /* eor */
8084 gen_op_xorl_T0_T1();
8085 if (!s->condexec_mask)
8086 gen_op_logic_T0_cc();
8087 break;
8088 case 0x2: /* lsl */
8089 if (s->condexec_mask) {
8090 gen_helper_shl(cpu_T[1], cpu_T[1], cpu_T[0]);
8091 } else {
8092 gen_helper_shl_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
8093 gen_op_logic_T1_cc();
8094 }
8095 break;
8096 case 0x3: /* lsr */
8097 if (s->condexec_mask) {
8098 gen_helper_shr(cpu_T[1], cpu_T[1], cpu_T[0]);
8099 } else {
8100 gen_helper_shr_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
8101 gen_op_logic_T1_cc();
8102 }
8103 break;
8104 case 0x4: /* asr */
8105 if (s->condexec_mask) {
8106 gen_helper_sar(cpu_T[1], cpu_T[1], cpu_T[0]);
8107 } else {
8108 gen_helper_sar_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
8109 gen_op_logic_T1_cc();
8110 }
8111 break;
8112 case 0x5: /* adc */
8113 if (s->condexec_mask)
8114 gen_adc_T0_T1();
8115 else
8116 gen_op_adcl_T0_T1_cc();
8117 break;
8118 case 0x6: /* sbc */
8119 if (s->condexec_mask)
8120 gen_sbc_T0_T1();
8121 else
8122 gen_op_sbcl_T0_T1_cc();
8123 break;
8124 case 0x7: /* ror */
8125 if (s->condexec_mask) {
8126 gen_helper_ror(cpu_T[1], cpu_T[1], cpu_T[0]);
8127 } else {
8128 gen_helper_ror_cc(cpu_T[1], cpu_T[1], cpu_T[0]);
8129 gen_op_logic_T1_cc();
8130 }
8131 break;
8132 case 0x8: /* tst */
8133 gen_op_andl_T0_T1();
8134 gen_op_logic_T0_cc();
8135 rd = 16;
8136 break;
8137 case 0x9: /* neg */
8138 if (s->condexec_mask)
8139 tcg_gen_neg_i32(cpu_T[0], cpu_T[1]);
8140 else
8141 gen_op_subl_T0_T1_cc();
8142 break;
8143 case 0xa: /* cmp */
8144 gen_op_subl_T0_T1_cc();
8145 rd = 16;
8146 break;
8147 case 0xb: /* cmn */
8148 gen_op_addl_T0_T1_cc();
8149 rd = 16;
8150 break;
8151 case 0xc: /* orr */
8152 gen_op_orl_T0_T1();
8153 if (!s->condexec_mask)
8154 gen_op_logic_T0_cc();
8155 break;
8156 case 0xd: /* mul */
8157 gen_op_mull_T0_T1();
8158 if (!s->condexec_mask)
8159 gen_op_logic_T0_cc();
8160 break;
8161 case 0xe: /* bic */
8162 gen_op_bicl_T0_T1();
8163 if (!s->condexec_mask)
8164 gen_op_logic_T0_cc();
8165 break;
8166 case 0xf: /* mvn */
8167 gen_op_notl_T1();
8168 if (!s->condexec_mask)
8169 gen_op_logic_T1_cc();
8170 val = 1;
8171 rm = rd;
8172 break;
8173 }
8174 if (rd != 16) {
8175 if (val)
8176 gen_movl_reg_T1(s, rm);
8177 else
8178 gen_movl_reg_T0(s, rd);
8179 }
8180 break;
8181
8182 case 5:
8183 /* load/store register offset. */
8184 rd = insn & 7;
8185 rn = (insn >> 3) & 7;
8186 rm = (insn >> 6) & 7;
8187 op = (insn >> 9) & 7;
8188 addr = load_reg(s, rn);
8189 tmp = load_reg(s, rm);
8190 tcg_gen_add_i32(addr, addr, tmp);
8191 dead_tmp(tmp);
8192
8193 if (op < 3) /* store */
8194 tmp = load_reg(s, rd);
8195
8196 switch (op) {
8197 case 0: /* str */
8198 gen_st32(tmp, addr, IS_USER(s));
8199 break;
8200 case 1: /* strh */
8201 gen_st16(tmp, addr, IS_USER(s));
8202 break;
8203 case 2: /* strb */
8204 gen_st8(tmp, addr, IS_USER(s));
8205 break;
8206 case 3: /* ldrsb */
8207 tmp = gen_ld8s(addr, IS_USER(s));
8208 break;
8209 case 4: /* ldr */
8210 tmp = gen_ld32(addr, IS_USER(s));
8211 break;
8212 case 5: /* ldrh */
8213 tmp = gen_ld16u(addr, IS_USER(s));
8214 break;
8215 case 6: /* ldrb */
8216 tmp = gen_ld8u(addr, IS_USER(s));
8217 break;
8218 case 7: /* ldrsh */
8219 tmp = gen_ld16s(addr, IS_USER(s));
8220 break;
8221 }
8222 if (op >= 3) /* load */
8223 store_reg(s, rd, tmp);
8224 dead_tmp(addr);
8225 break;
8226
8227 case 6:
8228 /* load/store word immediate offset */
8229 rd = insn & 7;
8230 rn = (insn >> 3) & 7;
8231 addr = load_reg(s, rn);
8232 val = (insn >> 4) & 0x7c;
8233 tcg_gen_addi_i32(addr, addr, val);
8234
8235 if (insn & (1 << 11)) {
8236 /* load */
8237 tmp = gen_ld32(addr, IS_USER(s));
8238 store_reg(s, rd, tmp);
8239 } else {
8240 /* store */
8241 tmp = load_reg(s, rd);
8242 gen_st32(tmp, addr, IS_USER(s));
8243 }
8244 dead_tmp(addr);
8245 break;
8246
8247 case 7:
8248 /* load/store byte immediate offset */
8249 rd = insn & 7;
8250 rn = (insn >> 3) & 7;
8251 addr = load_reg(s, rn);
8252 val = (insn >> 6) & 0x1f;
8253 tcg_gen_addi_i32(addr, addr, val);
8254
8255 if (insn & (1 << 11)) {
8256 /* load */
8257 tmp = gen_ld8u(addr, IS_USER(s));
8258 store_reg(s, rd, tmp);
8259 } else {
8260 /* store */
8261 tmp = load_reg(s, rd);
8262 gen_st8(tmp, addr, IS_USER(s));
8263 }
8264 dead_tmp(addr);
8265 break;
8266
8267 case 8:
8268 /* load/store halfword immediate offset */
8269 rd = insn & 7;
8270 rn = (insn >> 3) & 7;
8271 addr = load_reg(s, rn);
8272 val = (insn >> 5) & 0x3e;
8273 tcg_gen_addi_i32(addr, addr, val);
8274
8275 if (insn & (1 << 11)) {
8276 /* load */
8277 tmp = gen_ld16u(addr, IS_USER(s));
8278 store_reg(s, rd, tmp);
8279 } else {
8280 /* store */
8281 tmp = load_reg(s, rd);
8282 gen_st16(tmp, addr, IS_USER(s));
8283 }
8284 dead_tmp(addr);
8285 break;
8286
8287 case 9:
8288 /* load/store from stack */
8289 rd = (insn >> 8) & 7;
8290 addr = load_reg(s, 13);
8291 val = (insn & 0xff) * 4;
8292 tcg_gen_addi_i32(addr, addr, val);
8293
8294 if (insn & (1 << 11)) {
8295 /* load */
8296 tmp = gen_ld32(addr, IS_USER(s));
8297 store_reg(s, rd, tmp);
8298 } else {
8299 /* store */
8300 tmp = load_reg(s, rd);
8301 gen_st32(tmp, addr, IS_USER(s));
8302 }
8303 dead_tmp(addr);
8304 break;
8305
8306 case 10:
8307 /* add to high reg */
8308 rd = (insn >> 8) & 7;
8309 if (insn & (1 << 11)) {
8310 /* SP */
8311 tmp = load_reg(s, 13);
8312 } else {
8313 /* PC. bit 1 is ignored. */
8314 tmp = new_tmp();
8315 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
8316 }
8317 val = (insn & 0xff) * 4;
8318 tcg_gen_addi_i32(tmp, tmp, val);
8319 store_reg(s, rd, tmp);
8320 break;
8321
8322 case 11:
8323 /* misc */
8324 op = (insn >> 8) & 0xf;
8325 switch (op) {
8326 case 0:
8327 /* adjust stack pointer */
8328 tmp = load_reg(s, 13);
8329 val = (insn & 0x7f) * 4;
8330 if (insn & (1 << 7))
8331 val = -(int32_t)val;
8332 tcg_gen_addi_i32(tmp, tmp, val);
8333 store_reg(s, 13, tmp);
8334 break;
8335
8336 case 2: /* sign/zero extend. */
8337 ARCH(6);
8338 rd = insn & 7;
8339 rm = (insn >> 3) & 7;
8340 tmp = load_reg(s, rm);
8341 switch ((insn >> 6) & 3) {
8342 case 0: gen_sxth(tmp); break;
8343 case 1: gen_sxtb(tmp); break;
8344 case 2: gen_uxth(tmp); break;
8345 case 3: gen_uxtb(tmp); break;
8346 }
8347 store_reg(s, rd, tmp);
8348 break;
8349 case 4: case 5: case 0xc: case 0xd:
8350 /* push/pop */
8351 addr = load_reg(s, 13);
8352 if (insn & (1 << 8))
8353 offset = 4;
8354 else
8355 offset = 0;
8356 for (i = 0; i < 8; i++) {
8357 if (insn & (1 << i))
8358 offset += 4;
8359 }
8360 if ((insn & (1 << 11)) == 0) {
8361 tcg_gen_addi_i32(addr, addr, -offset);
8362 }
8363 for (i = 0; i < 8; i++) {
8364 if (insn & (1 << i)) {
8365 if (insn & (1 << 11)) {
8366 /* pop */
8367 tmp = gen_ld32(addr, IS_USER(s));
8368 store_reg(s, i, tmp);
8369 } else {
8370 /* push */
8371 tmp = load_reg(s, i);
8372 gen_st32(tmp, addr, IS_USER(s));
8373 }
8374 /* advance to the next address. */
8375 tcg_gen_addi_i32(addr, addr, 4);
8376 }
8377 }
8378 TCGV_UNUSED(tmp);
8379 if (insn & (1 << 8)) {
8380 if (insn & (1 << 11)) {
8381 /* pop pc */
8382 tmp = gen_ld32(addr, IS_USER(s));
8383 /* don't set the pc until the rest of the instruction
8384 has completed */
8385 } else {
8386 /* push lr */
8387 tmp = load_reg(s, 14);
8388 gen_st32(tmp, addr, IS_USER(s));
8389 }
8390 tcg_gen_addi_i32(addr, addr, 4);
8391 }
8392 if ((insn & (1 << 11)) == 0) {
8393 tcg_gen_addi_i32(addr, addr, -offset);
8394 }
8395 /* write back the new stack pointer */
8396 store_reg(s, 13, addr);
8397 /* set the new PC value */
8398 if ((insn & 0x0900) == 0x0900)
8399 gen_bx(s, tmp);
8400 break;
8401
8402 case 1: case 3: case 9: case 11: /* czb */
8403 rm = insn & 7;
8404 tmp = load_reg(s, rm);
8405 s->condlabel = gen_new_label();
8406 s->condjmp = 1;
8407 if (insn & (1 << 11))
8408 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
8409 else
8410 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
8411 dead_tmp(tmp);
8412 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8413 val = (uint32_t)s->pc + 2;
8414 val += offset;
8415 gen_jmp(s, val);
8416 break;
8417
8418 case 15: /* IT, nop-hint. */
8419 if ((insn & 0xf) == 0) {
8420 gen_nop_hint(s, (insn >> 4) & 0xf);
8421 break;
8422 }
8423 /* If Then. */
8424 s->condexec_cond = (insn >> 4) & 0xe;
8425 s->condexec_mask = insn & 0x1f;
8426 /* No actual code generated for this insn, just setup state. */
8427 break;
8428
8429 case 0xe: /* bkpt */
8430 gen_set_condexec(s);
8431 gen_set_pc_im(s->pc - 2);
8432 gen_exception(EXCP_BKPT);
8433 s->is_jmp = DISAS_JUMP;
8434 break;
8435
8436 case 0xa: /* rev */
8437 ARCH(6);
8438 rn = (insn >> 3) & 0x7;
8439 rd = insn & 0x7;
8440 tmp = load_reg(s, rn);
8441 switch ((insn >> 6) & 3) {
8442 case 0: tcg_gen_bswap_i32(tmp, tmp); break;
8443 case 1: gen_rev16(tmp); break;
8444 case 3: gen_revsh(tmp); break;
8445 default: goto illegal_op;
8446 }
8447 store_reg(s, rd, tmp);
8448 break;
8449
8450 case 6: /* cps */
8451 ARCH(6);
8452 if (IS_USER(s))
8453 break;
8454 if (IS_M(env)) {
8455 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
8456 /* PRIMASK */
8457 if (insn & 1) {
8458 addr = tcg_const_i32(16);
8459 gen_helper_v7m_msr(cpu_env, addr, tmp);
8460 }
8461 /* FAULTMASK */
8462 if (insn & 2) {
8463 addr = tcg_const_i32(17);
8464 gen_helper_v7m_msr(cpu_env, addr, tmp);
8465 }
8466 gen_lookup_tb(s);
8467 } else {
8468 if (insn & (1 << 4))
8469 shift = CPSR_A | CPSR_I | CPSR_F;
8470 else
8471 shift = 0;
8472
8473 val = ((insn & 7) << 6) & shift;
8474 gen_op_movl_T0_im(val);
8475 gen_set_psr_T0(s, shift, 0);
8476 }
8477 break;
8478
8479 default:
8480 goto undef;
8481 }
8482 break;
8483
8484 case 12:
8485 /* load/store multiple */
8486 rn = (insn >> 8) & 0x7;
8487 addr = load_reg(s, rn);
8488 for (i = 0; i < 8; i++) {
8489 if (insn & (1 << i)) {
8490 if (insn & (1 << 11)) {
8491 /* load */
8492 tmp = gen_ld32(addr, IS_USER(s));
8493 store_reg(s, i, tmp);
8494 } else {
8495 /* store */
8496 tmp = load_reg(s, i);
8497 gen_st32(tmp, addr, IS_USER(s));
8498 }
8499 /* advance to the next address */
8500 tcg_gen_addi_i32(addr, addr, 4);
8501 }
8502 }
8503 /* Base register writeback. */
8504 if ((insn & (1 << rn)) == 0) {
8505 store_reg(s, rn, addr);
8506 } else {
8507 dead_tmp(addr);
8508 }
8509 break;
8510
8511 case 13:
8512 /* conditional branch or swi */
8513 cond = (insn >> 8) & 0xf;
8514 if (cond == 0xe)
8515 goto undef;
8516
8517 if (cond == 0xf) {
8518 /* swi */
8519 gen_set_condexec(s);
8520 gen_set_pc_im(s->pc);
8521 s->is_jmp = DISAS_SWI;
8522 break;
8523 }
8524 /* generate a conditional jump to next instruction */
8525 s->condlabel = gen_new_label();
8526 gen_test_cc(cond ^ 1, s->condlabel);
8527 s->condjmp = 1;
8528 gen_movl_T1_reg(s, 15);
8529
8530 /* jump to the offset */
8531 val = (uint32_t)s->pc + 2;
8532 offset = ((int32_t)insn << 24) >> 24;
8533 val += offset << 1;
8534 gen_jmp(s, val);
8535 break;
8536
8537 case 14:
8538 if (insn & (1 << 11)) {
8539 if (disas_thumb2_insn(env, s, insn))
8540 goto undef32;
8541 break;
8542 }
8543 /* unconditional branch */
8544 val = (uint32_t)s->pc;
8545 offset = ((int32_t)insn << 21) >> 21;
8546 val += (offset << 1) + 2;
8547 gen_jmp(s, val);
8548 break;
8549
8550 case 15:
8551 if (disas_thumb2_insn(env, s, insn))
8552 goto undef32;
8553 break;
8554 }
8555 return;
8556 undef32:
8557 gen_set_condexec(s);
8558 gen_set_pc_im(s->pc - 4);
8559 gen_exception(EXCP_UDEF);
8560 s->is_jmp = DISAS_JUMP;
8561 return;
8562 illegal_op:
8563 undef:
8564 gen_set_condexec(s);
8565 gen_set_pc_im(s->pc - 2);
8566 gen_exception(EXCP_UDEF);
8567 s->is_jmp = DISAS_JUMP;
8568 }
8569
8570 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
8571 basic block 'tb'. If search_pc is TRUE, also generate PC
8572 information for each intermediate instruction. */
8573 static inline void gen_intermediate_code_internal(CPUState *env,
8574 TranslationBlock *tb,
8575 int search_pc)
8576 {
8577 DisasContext dc1, *dc = &dc1;
8578 CPUBreakpoint *bp;
8579 uint16_t *gen_opc_end;
8580 int j, lj;
8581 target_ulong pc_start;
8582 uint32_t next_page_start;
8583 int num_insns;
8584 int max_insns;
8585
8586 /* generate intermediate code */
8587 num_temps = 0;
8588 memset(temps, 0, sizeof(temps));
8589
8590 pc_start = tb->pc;
8591
8592 dc->tb = tb;
8593
8594 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8595
8596 dc->is_jmp = DISAS_NEXT;
8597 dc->pc = pc_start;
8598 dc->singlestep_enabled = env->singlestep_enabled;
8599 dc->condjmp = 0;
8600 dc->thumb = env->thumb;
8601 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
8602 dc->condexec_cond = env->condexec_bits >> 4;
8603 #if !defined(CONFIG_USER_ONLY)
8604 if (IS_M(env)) {
8605 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
8606 } else {
8607 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
8608 }
8609 #endif
8610 cpu_F0s = tcg_temp_new_i32();
8611 cpu_F1s = tcg_temp_new_i32();
8612 cpu_F0d = tcg_temp_new_i64();
8613 cpu_F1d = tcg_temp_new_i64();
8614 cpu_V0 = cpu_F0d;
8615 cpu_V1 = cpu_F1d;
8616 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
8617 cpu_M0 = tcg_temp_new_i64();
8618 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
8619 lj = -1;
8620 num_insns = 0;
8621 max_insns = tb->cflags & CF_COUNT_MASK;
8622 if (max_insns == 0)
8623 max_insns = CF_COUNT_MASK;
8624
8625 gen_icount_start();
8626 /* Reset the conditional execution bits immediately. This avoids
8627 complications trying to do it at the end of the block. */
8628 if (env->condexec_bits)
8629 {
8630 TCGv tmp = new_tmp();
8631 tcg_gen_movi_i32(tmp, 0);
8632 store_cpu_field(tmp, condexec_bits);
8633 }
8634 do {
8635 #ifdef CONFIG_USER_ONLY
8636 /* Intercept jump to the magic kernel page. */
8637 if (dc->pc >= 0xffff0000) {
8638 /* We always get here via a jump, so know we are not in a
8639 conditional execution block. */
8640 gen_exception(EXCP_KERNEL_TRAP);
8641 dc->is_jmp = DISAS_UPDATE;
8642 break;
8643 }
8644 #else
8645 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
8646 /* We always get here via a jump, so know we are not in a
8647 conditional execution block. */
8648 gen_exception(EXCP_EXCEPTION_EXIT);
8649 dc->is_jmp = DISAS_UPDATE;
8650 break;
8651 }
8652 #endif
8653
8654 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8655 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8656 if (bp->pc == dc->pc) {
8657 gen_set_condexec(dc);
8658 gen_set_pc_im(dc->pc);
8659 gen_exception(EXCP_DEBUG);
8660 dc->is_jmp = DISAS_JUMP;
8661 /* Advance PC so that clearing the breakpoint will
8662 invalidate this TB. */
8663 dc->pc += 2;
8664 goto done_generating;
8665 break;
8666 }
8667 }
8668 }
8669 if (search_pc) {
8670 j = gen_opc_ptr - gen_opc_buf;
8671 if (lj < j) {
8672 lj++;
8673 while (lj < j)
8674 gen_opc_instr_start[lj++] = 0;
8675 }
8676 gen_opc_pc[lj] = dc->pc;
8677 gen_opc_instr_start[lj] = 1;
8678 gen_opc_icount[lj] = num_insns;
8679 }
8680
8681 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8682 gen_io_start();
8683
8684 if (env->thumb) {
8685 disas_thumb_insn(env, dc);
8686 if (dc->condexec_mask) {
8687 dc->condexec_cond = (dc->condexec_cond & 0xe)
8688 | ((dc->condexec_mask >> 4) & 1);
8689 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
8690 if (dc->condexec_mask == 0) {
8691 dc->condexec_cond = 0;
8692 }
8693 }
8694 } else {
8695 disas_arm_insn(env, dc);
8696 }
8697 if (num_temps) {
8698 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
8699 num_temps = 0;
8700 }
8701
8702 if (dc->condjmp && !dc->is_jmp) {
8703 gen_set_label(dc->condlabel);
8704 dc->condjmp = 0;
8705 }
8706 /* Translation stops when a conditional branch is encountered.
8707 * Otherwise the subsequent code could get translated several times.
8708 * Also stop translation when a page boundary is reached. This
8709 * ensures prefetch aborts occur at the right place. */
8710 num_insns ++;
8711 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
8712 !env->singlestep_enabled &&
8713 dc->pc < next_page_start &&
8714 num_insns < max_insns);
8715
8716 if (tb->cflags & CF_LAST_IO) {
8717 if (dc->condjmp) {
8718 /* FIXME: This can theoretically happen with self-modifying
8719 code. */
8720 cpu_abort(env, "IO on conditional branch instruction");
8721 }
8722 gen_io_end();
8723 }
8724
8725 /* At this stage dc->condjmp will only be set when the skipped
8726 instruction was a conditional branch or trap, and the PC has
8727 already been written. */
8728 if (unlikely(env->singlestep_enabled)) {
8729 /* Make sure the pc is updated, and raise a debug exception. */
8730 if (dc->condjmp) {
8731 gen_set_condexec(dc);
8732 if (dc->is_jmp == DISAS_SWI) {
8733 gen_exception(EXCP_SWI);
8734 } else {
8735 gen_exception(EXCP_DEBUG);
8736 }
8737 gen_set_label(dc->condlabel);
8738 }
8739 if (dc->condjmp || !dc->is_jmp) {
8740 gen_set_pc_im(dc->pc);
8741 dc->condjmp = 0;
8742 }
8743 gen_set_condexec(dc);
8744 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
8745 gen_exception(EXCP_SWI);
8746 } else {
8747 /* FIXME: Single stepping a WFI insn will not halt
8748 the CPU. */
8749 gen_exception(EXCP_DEBUG);
8750 }
8751 } else {
8752 /* While branches must always occur at the end of an IT block,
8753 there are a few other things that can cause us to terminate
8754 the TB in the middel of an IT block:
8755 - Exception generating instructions (bkpt, swi, undefined).
8756 - Page boundaries.
8757 - Hardware watchpoints.
8758 Hardware breakpoints have already been handled and skip this code.
8759 */
8760 gen_set_condexec(dc);
8761 switch(dc->is_jmp) {
8762 case DISAS_NEXT:
8763 gen_goto_tb(dc, 1, dc->pc);
8764 break;
8765 default:
8766 case DISAS_JUMP:
8767 case DISAS_UPDATE:
8768 /* indicate that the hash table must be used to find the next TB */
8769 tcg_gen_exit_tb(0);
8770 break;
8771 case DISAS_TB_JUMP:
8772 /* nothing more to generate */
8773 break;
8774 case DISAS_WFI:
8775 gen_helper_wfi();
8776 break;
8777 case DISAS_SWI:
8778 gen_exception(EXCP_SWI);
8779 break;
8780 }
8781 if (dc->condjmp) {
8782 gen_set_label(dc->condlabel);
8783 gen_set_condexec(dc);
8784 gen_goto_tb(dc, 1, dc->pc);
8785 dc->condjmp = 0;
8786 }
8787 }
8788
8789 done_generating:
8790 gen_icount_end(tb, num_insns);
8791 *gen_opc_ptr = INDEX_op_end;
8792
8793 #ifdef DEBUG_DISAS
8794 if (loglevel & CPU_LOG_TB_IN_ASM) {
8795 fprintf(logfile, "----------------\n");
8796 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
8797 target_disas(logfile, pc_start, dc->pc - pc_start, env->thumb);
8798 fprintf(logfile, "\n");
8799 }
8800 #endif
8801 if (search_pc) {
8802 j = gen_opc_ptr - gen_opc_buf;
8803 lj++;
8804 while (lj <= j)
8805 gen_opc_instr_start[lj++] = 0;
8806 } else {
8807 tb->size = dc->pc - pc_start;
8808 tb->icount = num_insns;
8809 }
8810 }
8811
8812 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
8813 {
8814 gen_intermediate_code_internal(env, tb, 0);
8815 }
8816
8817 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
8818 {
8819 gen_intermediate_code_internal(env, tb, 1);
8820 }
8821
8822 static const char *cpu_mode_names[16] = {
8823 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
8824 "???", "???", "???", "und", "???", "???", "???", "sys"
8825 };
8826
8827 void cpu_dump_state(CPUState *env, FILE *f,
8828 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8829 int flags)
8830 {
8831 int i;
8832 #if 0
8833 union {
8834 uint32_t i;
8835 float s;
8836 } s0, s1;
8837 CPU_DoubleU d;
8838 /* ??? This assumes float64 and double have the same layout.
8839 Oh well, it's only debug dumps. */
8840 union {
8841 float64 f64;
8842 double d;
8843 } d0;
8844 #endif
8845 uint32_t psr;
8846
8847 for(i=0;i<16;i++) {
8848 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
8849 if ((i % 4) == 3)
8850 cpu_fprintf(f, "\n");
8851 else
8852 cpu_fprintf(f, " ");
8853 }
8854 psr = cpsr_read(env);
8855 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
8856 psr,
8857 psr & (1 << 31) ? 'N' : '-',
8858 psr & (1 << 30) ? 'Z' : '-',
8859 psr & (1 << 29) ? 'C' : '-',
8860 psr & (1 << 28) ? 'V' : '-',
8861 psr & CPSR_T ? 'T' : 'A',
8862 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
8863
8864 #if 0
8865 for (i = 0; i < 16; i++) {
8866 d.d = env->vfp.regs[i];
8867 s0.i = d.l.lower;
8868 s1.i = d.l.upper;
8869 d0.f64 = d.d;
8870 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
8871 i * 2, (int)s0.i, s0.s,
8872 i * 2 + 1, (int)s1.i, s1.s,
8873 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
8874 d0.d);
8875 }
8876 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
8877 #endif
8878 }
8879
8880 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8881 unsigned long searched_pc, int pc_pos, void *puc)
8882 {
8883 env->regs[15] = gen_opc_pc[pc_pos];
8884 }
Samsung s3c2440 and arm920t support for the mini2440 dev board