2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
41 //#define MIPS_SINGLE_STEP
43 /* MIPS major opcodes */
44 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
47 /* indirect opcode tables */
48 OPC_SPECIAL
= (0x00 << 26),
49 OPC_REGIMM
= (0x01 << 26),
50 OPC_CP0
= (0x10 << 26),
51 OPC_CP1
= (0x11 << 26),
52 OPC_CP2
= (0x12 << 26),
53 OPC_CP3
= (0x13 << 26),
54 OPC_SPECIAL2
= (0x1C << 26),
55 OPC_SPECIAL3
= (0x1F << 26),
56 /* arithmetic with immediate */
57 OPC_ADDI
= (0x08 << 26),
58 OPC_ADDIU
= (0x09 << 26),
59 OPC_SLTI
= (0x0A << 26),
60 OPC_SLTIU
= (0x0B << 26),
61 OPC_ANDI
= (0x0C << 26),
62 OPC_ORI
= (0x0D << 26),
63 OPC_XORI
= (0x0E << 26),
64 OPC_LUI
= (0x0F << 26),
65 OPC_DADDI
= (0x18 << 26),
66 OPC_DADDIU
= (0x19 << 26),
67 /* Jump and branches */
69 OPC_JAL
= (0x03 << 26),
70 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
71 OPC_BEQL
= (0x14 << 26),
72 OPC_BNE
= (0x05 << 26),
73 OPC_BNEL
= (0x15 << 26),
74 OPC_BLEZ
= (0x06 << 26),
75 OPC_BLEZL
= (0x16 << 26),
76 OPC_BGTZ
= (0x07 << 26),
77 OPC_BGTZL
= (0x17 << 26),
78 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
80 OPC_LDL
= (0x1A << 26),
81 OPC_LDR
= (0x1B << 26),
82 OPC_LB
= (0x20 << 26),
83 OPC_LH
= (0x21 << 26),
84 OPC_LWL
= (0x22 << 26),
85 OPC_LW
= (0x23 << 26),
86 OPC_LBU
= (0x24 << 26),
87 OPC_LHU
= (0x25 << 26),
88 OPC_LWR
= (0x26 << 26),
89 OPC_LWU
= (0x27 << 26),
90 OPC_SB
= (0x28 << 26),
91 OPC_SH
= (0x29 << 26),
92 OPC_SWL
= (0x2A << 26),
93 OPC_SW
= (0x2B << 26),
94 OPC_SDL
= (0x2C << 26),
95 OPC_SDR
= (0x2D << 26),
96 OPC_SWR
= (0x2E << 26),
97 OPC_LL
= (0x30 << 26),
98 OPC_LLD
= (0x34 << 26),
99 OPC_LD
= (0x37 << 26),
100 OPC_SC
= (0x38 << 26),
101 OPC_SCD
= (0x3C << 26),
102 OPC_SD
= (0x3F << 26),
103 /* Floating point load/store */
104 OPC_LWC1
= (0x31 << 26),
105 OPC_LWC2
= (0x32 << 26),
106 OPC_LDC1
= (0x35 << 26),
107 OPC_LDC2
= (0x36 << 26),
108 OPC_SWC1
= (0x39 << 26),
109 OPC_SWC2
= (0x3A << 26),
110 OPC_SDC1
= (0x3D << 26),
111 OPC_SDC2
= (0x3E << 26),
112 /* MDMX ASE specific */
113 OPC_MDMX
= (0x1E << 26),
114 /* Cache and prefetch */
115 OPC_CACHE
= (0x2F << 26),
116 OPC_PREF
= (0x33 << 26),
117 /* Reserved major opcode */
118 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
121 /* MIPS special opcodes */
122 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
126 OPC_SLL
= 0x00 | OPC_SPECIAL
,
127 /* NOP is SLL r0, r0, 0 */
128 /* SSNOP is SLL r0, r0, 1 */
129 /* EHB is SLL r0, r0, 3 */
130 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
131 OPC_SRA
= 0x03 | OPC_SPECIAL
,
132 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
133 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
134 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
135 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
136 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
137 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
138 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
139 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
140 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
141 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
142 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
143 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
144 /* Multiplication / division */
145 OPC_MULT
= 0x18 | OPC_SPECIAL
,
146 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
147 OPC_DIV
= 0x1A | OPC_SPECIAL
,
148 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
149 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
150 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
151 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
152 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
153 /* 2 registers arithmetic / logic */
154 OPC_ADD
= 0x20 | OPC_SPECIAL
,
155 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
156 OPC_SUB
= 0x22 | OPC_SPECIAL
,
157 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
158 OPC_AND
= 0x24 | OPC_SPECIAL
,
159 OPC_OR
= 0x25 | OPC_SPECIAL
,
160 OPC_XOR
= 0x26 | OPC_SPECIAL
,
161 OPC_NOR
= 0x27 | OPC_SPECIAL
,
162 OPC_SLT
= 0x2A | OPC_SPECIAL
,
163 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
164 OPC_DADD
= 0x2C | OPC_SPECIAL
,
165 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
166 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
167 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
169 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
170 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
172 OPC_TGE
= 0x30 | OPC_SPECIAL
,
173 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
174 OPC_TLT
= 0x32 | OPC_SPECIAL
,
175 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
176 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
177 OPC_TNE
= 0x36 | OPC_SPECIAL
,
178 /* HI / LO registers load & stores */
179 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
180 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
181 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
182 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
183 /* Conditional moves */
184 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
185 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
187 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
190 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
191 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
192 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
193 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
194 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
196 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
197 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
198 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
199 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
200 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
201 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
202 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
205 /* Multiplication variants of the vr54xx. */
206 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
209 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
210 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
211 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
212 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
213 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
214 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
215 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
216 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
217 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
218 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
219 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
220 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
221 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
222 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
225 /* REGIMM (rt field) opcodes */
226 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
229 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
230 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
231 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
232 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
233 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
234 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
235 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
236 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
237 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
238 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
239 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
240 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
241 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
242 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
243 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
246 /* Special2 opcodes */
247 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
250 /* Multiply & xxx operations */
251 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
252 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
253 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
254 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
255 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
257 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
258 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
259 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
260 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
262 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
265 /* Special3 opcodes */
266 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
269 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
270 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
271 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
272 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
273 OPC_INS
= 0x04 | OPC_SPECIAL3
,
274 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
275 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
276 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
277 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
278 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
279 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
280 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
281 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
285 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
288 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
289 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
290 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
294 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
297 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
298 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
301 /* Coprocessor 0 (rs field) */
302 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
305 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
306 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
307 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
308 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
309 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
310 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
311 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
312 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
313 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
314 OPC_C0
= (0x10 << 21) | OPC_CP0
,
315 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
316 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
320 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
323 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
324 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
325 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
326 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
327 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
331 /* Coprocessor 0 (with rs == C0) */
332 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
335 OPC_TLBR
= 0x01 | OPC_C0
,
336 OPC_TLBWI
= 0x02 | OPC_C0
,
337 OPC_TLBWR
= 0x06 | OPC_C0
,
338 OPC_TLBP
= 0x08 | OPC_C0
,
339 OPC_RFE
= 0x10 | OPC_C0
,
340 OPC_ERET
= 0x18 | OPC_C0
,
341 OPC_DERET
= 0x1F | OPC_C0
,
342 OPC_WAIT
= 0x20 | OPC_C0
,
345 /* Coprocessor 1 (rs field) */
346 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
349 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
350 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
351 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
352 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
353 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
354 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
355 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
356 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
357 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
358 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
359 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
360 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
361 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
362 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
363 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
364 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
365 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
366 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
369 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
370 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
373 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
374 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
375 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
376 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
380 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
381 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
385 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
386 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
389 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
392 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
393 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
394 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
395 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
396 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
397 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
398 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
399 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
400 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
403 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
406 OPC_LWXC1
= 0x00 | OPC_CP3
,
407 OPC_LDXC1
= 0x01 | OPC_CP3
,
408 OPC_LUXC1
= 0x05 | OPC_CP3
,
409 OPC_SWXC1
= 0x08 | OPC_CP3
,
410 OPC_SDXC1
= 0x09 | OPC_CP3
,
411 OPC_SUXC1
= 0x0D | OPC_CP3
,
412 OPC_PREFX
= 0x0F | OPC_CP3
,
413 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
414 OPC_MADD_S
= 0x20 | OPC_CP3
,
415 OPC_MADD_D
= 0x21 | OPC_CP3
,
416 OPC_MADD_PS
= 0x26 | OPC_CP3
,
417 OPC_MSUB_S
= 0x28 | OPC_CP3
,
418 OPC_MSUB_D
= 0x29 | OPC_CP3
,
419 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
420 OPC_NMADD_S
= 0x30 | OPC_CP3
,
421 OPC_NMADD_D
= 0x31 | OPC_CP3
,
422 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
423 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
424 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
425 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
428 /* global register indices */
429 static TCGv_ptr cpu_env
;
430 static TCGv cpu_gpr
[32], cpu_PC
;
431 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
432 static TCGv cpu_dspctrl
, btarget
;
433 static TCGv_i32 bcond
;
434 static TCGv_i32 fpu_fpr32
[32], fpu_fpr32h
[32];
435 static TCGv_i64 fpu_fpr64
[32];
436 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
438 #include "gen-icount.h"
440 #define gen_helper_0i(name, arg) do { \
441 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
442 gen_helper_##name(helper_tmp); \
443 tcg_temp_free_i32(helper_tmp); \
446 #define gen_helper_1i(name, arg1, arg2) do { \
447 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
448 gen_helper_##name(arg1, helper_tmp); \
449 tcg_temp_free_i32(helper_tmp); \
452 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
453 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
454 gen_helper_##name(arg1, arg2, helper_tmp); \
455 tcg_temp_free_i32(helper_tmp); \
458 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
459 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
460 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
461 tcg_temp_free_i32(helper_tmp); \
464 typedef struct DisasContext
{
465 struct TranslationBlock
*tb
;
466 target_ulong pc
, saved_pc
;
468 /* Routine used to access memory */
470 uint32_t hflags
, saved_hflags
;
472 target_ulong btarget
;
476 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
477 * exception condition */
478 BS_STOP
= 1, /* We want to stop translation for any reason */
479 BS_BRANCH
= 2, /* We reached a branch condition */
480 BS_EXCP
= 3, /* We reached an exception condition */
483 static const char *regnames
[] =
484 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
485 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
486 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
487 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
489 static const char *regnames_HI
[] =
490 { "HI0", "HI1", "HI2", "HI3", };
492 static const char *regnames_LO
[] =
493 { "LO0", "LO1", "LO2", "LO3", };
495 static const char *regnames_ACX
[] =
496 { "ACX0", "ACX1", "ACX2", "ACX3", };
498 static const char *fregnames
[] =
499 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
500 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
501 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
502 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
504 static const char *fregnames_64
[] =
505 { "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
506 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
507 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
508 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", };
510 static const char *fregnames_h
[] =
511 { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
512 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
513 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
514 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
516 #ifdef MIPS_DEBUG_DISAS
517 #define MIPS_DEBUG(fmt, args...) \
519 if (loglevel & CPU_LOG_TB_IN_ASM) { \
520 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
521 ctx->pc, ctx->opcode , ##args); \
525 #define MIPS_DEBUG(fmt, args...) do { } while(0)
528 #define MIPS_INVAL(op) \
530 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
531 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
534 /* General purpose registers moves. */
535 static inline void gen_load_gpr (TCGv t
, int reg
)
538 tcg_gen_movi_tl(t
, 0);
540 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
543 static inline void gen_store_gpr (TCGv t
, int reg
)
546 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
549 /* Moves to/from ACX register. */
550 static inline void gen_load_ACX (TCGv t
, int reg
)
552 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
555 static inline void gen_store_ACX (TCGv t
, int reg
)
557 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
560 /* Moves to/from shadow registers. */
561 static inline void gen_load_srsgpr (int from
, int to
)
563 TCGv r_tmp1
= tcg_temp_new();
566 tcg_gen_movi_tl(r_tmp1
, 0);
568 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
569 TCGv_ptr addr
= tcg_temp_new_ptr();
571 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
572 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
573 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
574 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
575 tcg_gen_ext_i32_ptr(addr
, r_tmp2
);
576 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
578 tcg_gen_ld_tl(r_tmp1
, addr
, sizeof(target_ulong
) * from
);
579 tcg_temp_free_ptr(addr
);
580 tcg_temp_free_i32(r_tmp2
);
582 gen_store_gpr(r_tmp1
, to
);
583 tcg_temp_free(r_tmp1
);
586 static inline void gen_store_srsgpr (int from
, int to
)
589 TCGv r_tmp1
= tcg_temp_new();
590 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
591 TCGv_ptr addr
= tcg_temp_new_ptr();
593 gen_load_gpr(r_tmp1
, from
);
594 tcg_gen_ld_i32(r_tmp2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
595 tcg_gen_shri_i32(r_tmp2
, r_tmp2
, CP0SRSCtl_PSS
);
596 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xf);
597 tcg_gen_muli_i32(r_tmp2
, r_tmp2
, sizeof(target_ulong
) * 32);
598 tcg_gen_ext_i32_ptr(addr
, r_tmp2
);
599 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
601 tcg_gen_st_tl(r_tmp1
, addr
, sizeof(target_ulong
) * to
);
602 tcg_temp_free_ptr(addr
);
603 tcg_temp_free_i32(r_tmp2
);
604 tcg_temp_free(r_tmp1
);
608 /* Floating point register moves. */
609 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
611 tcg_gen_mov_i32(t
, fpu_fpr32
[reg
]);
614 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
616 tcg_gen_mov_i32(fpu_fpr32
[reg
], t
);
619 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
621 if (ctx
->hflags
& MIPS_HFLAG_F64
)
622 tcg_gen_mov_i64(t
, fpu_fpr64
[reg
]);
624 tcg_gen_concat_i32_i64(t
, fpu_fpr32
[reg
& ~1], fpu_fpr32
[reg
| 1]);
628 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
630 if (ctx
->hflags
& MIPS_HFLAG_F64
)
631 tcg_gen_mov_i64(fpu_fpr64
[reg
], t
);
633 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
& ~1], t
);
634 tcg_gen_shri_i64(t
, t
, 32);
635 tcg_gen_trunc_i64_i32(fpu_fpr32
[reg
| 1], t
);
639 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
641 tcg_gen_mov_i32(t
, fpu_fpr32h
[reg
]);
644 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
646 tcg_gen_mov_i32(fpu_fpr32h
[reg
], t
);
649 static inline void get_fp_cond (TCGv_i32 t
)
651 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
652 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
654 tcg_gen_shri_i32(r_tmp2
, fpu_fcr31
, 24);
655 tcg_gen_andi_i32(r_tmp2
, r_tmp2
, 0xfe);
656 tcg_gen_shri_i32(r_tmp1
, fpu_fcr31
, 23);
657 tcg_gen_andi_i32(r_tmp1
, r_tmp1
, 0x1);
658 tcg_gen_or_i32(t
, r_tmp1
, r_tmp2
);
659 tcg_temp_free_i32(r_tmp1
);
660 tcg_temp_free_i32(r_tmp2
);
663 #define FOP_CONDS(type, fmt, bits) \
664 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
665 TCGv_i##bits b, int cc) \
668 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
669 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
670 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
671 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
672 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
673 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
674 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
675 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
676 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
677 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
678 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
679 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
680 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
681 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
682 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
683 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
689 FOP_CONDS(abs
, d
, 64)
691 FOP_CONDS(abs
, s
, 32)
693 FOP_CONDS(abs
, ps
, 64)
697 #define OP_COND(name, cond) \
698 static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
700 int l1 = gen_new_label(); \
701 int l2 = gen_new_label(); \
703 tcg_gen_brcond_tl(cond, t0, t1, l1); \
704 tcg_gen_movi_tl(t0, 0); \
707 tcg_gen_movi_tl(t0, 1); \
710 OP_COND(eq
, TCG_COND_EQ
);
711 OP_COND(ne
, TCG_COND_NE
);
712 OP_COND(ge
, TCG_COND_GE
);
713 OP_COND(geu
, TCG_COND_GEU
);
714 OP_COND(lt
, TCG_COND_LT
);
715 OP_COND(ltu
, TCG_COND_LTU
);
718 #define OP_CONDI(name, cond) \
719 static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
721 int l1 = gen_new_label(); \
722 int l2 = gen_new_label(); \
724 tcg_gen_brcondi_tl(cond, t, val, l1); \
725 tcg_gen_movi_tl(t, 0); \
728 tcg_gen_movi_tl(t, 1); \
731 OP_CONDI(lti
, TCG_COND_LT
);
732 OP_CONDI(ltiu
, TCG_COND_LTU
);
735 #define OP_CONDZ(name, cond) \
736 static inline void glue(gen_op_, name) (TCGv t) \
738 int l1 = gen_new_label(); \
739 int l2 = gen_new_label(); \
741 tcg_gen_brcondi_tl(cond, t, 0, l1); \
742 tcg_gen_movi_tl(t, 0); \
745 tcg_gen_movi_tl(t, 1); \
748 OP_CONDZ(gez
, TCG_COND_GE
);
749 OP_CONDZ(gtz
, TCG_COND_GT
);
750 OP_CONDZ(lez
, TCG_COND_LE
);
751 OP_CONDZ(ltz
, TCG_COND_LT
);
754 static inline void gen_save_pc(target_ulong pc
)
756 tcg_gen_movi_tl(cpu_PC
, pc
);
759 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
761 #if defined MIPS_DEBUG_DISAS
762 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
763 fprintf(logfile
, "hflags %08x saved %08x\n",
764 ctx
->hflags
, ctx
->saved_hflags
);
767 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
768 gen_save_pc(ctx
->pc
);
769 ctx
->saved_pc
= ctx
->pc
;
771 if (ctx
->hflags
!= ctx
->saved_hflags
) {
772 TCGv_i32 r_tmp
= tcg_temp_new_i32();
774 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
);
775 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
776 tcg_temp_free_i32(r_tmp
);
777 ctx
->saved_hflags
= ctx
->hflags
;
778 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
784 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
790 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
792 ctx
->saved_hflags
= ctx
->hflags
;
793 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
799 ctx
->btarget
= env
->btarget
;
805 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
807 TCGv_i32 texcp
= tcg_const_i32(excp
);
808 TCGv_i32 terr
= tcg_const_i32(err
);
809 save_cpu_state(ctx
, 1);
810 gen_helper_raise_exception_err(texcp
, terr
);
811 tcg_temp_free_i32(terr
);
812 tcg_temp_free_i32(texcp
);
813 gen_helper_interrupt_restart();
818 generate_exception (DisasContext
*ctx
, int excp
)
820 save_cpu_state(ctx
, 1);
821 gen_helper_0i(raise_exception
, excp
);
822 gen_helper_interrupt_restart();
826 /* Addresses computation */
827 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv t0
, TCGv t1
)
829 tcg_gen_add_tl(t0
, t0
, t1
);
831 #if defined(TARGET_MIPS64)
832 /* For compatibility with 32-bit code, data reference in user mode
833 with Status_UX = 0 should be casted to 32-bit and sign extended.
834 See the MIPS64 PRA manual, section 4.10. */
835 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
836 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
837 tcg_gen_ext32s_i64(t0
, t0
);
842 static inline void check_cp0_enabled(DisasContext
*ctx
)
844 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
845 generate_exception_err(ctx
, EXCP_CpU
, 1);
848 static inline void check_cp1_enabled(DisasContext
*ctx
)
850 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
851 generate_exception_err(ctx
, EXCP_CpU
, 1);
854 /* Verify that the processor is running with COP1X instructions enabled.
855 This is associated with the nabla symbol in the MIPS32 and MIPS64
858 static inline void check_cop1x(DisasContext
*ctx
)
860 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
861 generate_exception(ctx
, EXCP_RI
);
864 /* Verify that the processor is running with 64-bit floating-point
865 operations enabled. */
867 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
869 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
870 generate_exception(ctx
, EXCP_RI
);
874 * Verify if floating point register is valid; an operation is not defined
875 * if bit 0 of any register specification is set and the FR bit in the
876 * Status register equals zero, since the register numbers specify an
877 * even-odd pair of adjacent coprocessor general registers. When the FR bit
878 * in the Status register equals one, both even and odd register numbers
879 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
881 * Multiple 64 bit wide registers can be checked by calling
882 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
884 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
886 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
887 generate_exception(ctx
, EXCP_RI
);
890 /* This code generates a "reserved instruction" exception if the
891 CPU does not support the instruction set corresponding to flags. */
892 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
894 if (unlikely(!(env
->insn_flags
& flags
)))
895 generate_exception(ctx
, EXCP_RI
);
898 /* This code generates a "reserved instruction" exception if 64-bit
899 instructions are not enabled. */
900 static inline void check_mips_64(DisasContext
*ctx
)
902 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
903 generate_exception(ctx
, EXCP_RI
);
906 /* load/store instructions. */
907 #define OP_LD(insn,fname) \
908 static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
910 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
917 #if defined(TARGET_MIPS64)
923 #define OP_ST(insn,fname) \
924 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
926 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
931 #if defined(TARGET_MIPS64)
936 #define OP_LD_ATOMIC(insn,fname) \
937 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
939 tcg_gen_mov_tl(t1, t0); \
940 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
941 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
943 OP_LD_ATOMIC(ll
,ld32s
);
944 #if defined(TARGET_MIPS64)
945 OP_LD_ATOMIC(lld
,ld64
);
949 #define OP_ST_ATOMIC(insn,fname,almask) \
950 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
952 TCGv r_tmp = tcg_temp_local_new(); \
953 int l1 = gen_new_label(); \
954 int l2 = gen_new_label(); \
955 int l3 = gen_new_label(); \
957 tcg_gen_andi_tl(r_tmp, t0, almask); \
958 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
959 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
960 generate_exception(ctx, EXCP_AdES); \
962 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
963 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
964 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
965 tcg_gen_movi_tl(t0, 1); \
968 tcg_gen_movi_tl(t0, 0); \
970 tcg_temp_free(r_tmp); \
972 OP_ST_ATOMIC(sc
,st32
,0x3);
973 #if defined(TARGET_MIPS64)
974 OP_ST_ATOMIC(scd
,st64
,0x7);
979 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
980 int base
, int16_t offset
)
982 const char *opn
= "ldst";
983 TCGv t0
= tcg_temp_local_new();
984 TCGv t1
= tcg_temp_local_new();
987 tcg_gen_movi_tl(t0
, offset
);
988 } else if (offset
== 0) {
989 gen_load_gpr(t0
, base
);
991 tcg_gen_movi_tl(t0
, offset
);
992 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
994 /* Don't do NOP if destination is zero: we must perform the actual
997 #if defined(TARGET_MIPS64)
999 op_ldst_lwu(t0
, ctx
);
1000 gen_store_gpr(t0
, rt
);
1004 op_ldst_ld(t0
, ctx
);
1005 gen_store_gpr(t0
, rt
);
1009 op_ldst_lld(t0
, t1
, ctx
);
1010 gen_store_gpr(t0
, rt
);
1014 gen_load_gpr(t1
, rt
);
1015 op_ldst_sd(t0
, t1
, ctx
);
1019 save_cpu_state(ctx
, 1);
1020 gen_load_gpr(t1
, rt
);
1021 op_ldst_scd(t0
, t1
, ctx
);
1022 gen_store_gpr(t0
, rt
);
1026 save_cpu_state(ctx
, 1);
1027 gen_load_gpr(t1
, rt
);
1028 gen_helper_3i(ldl
, t1
, t0
, t1
, ctx
->mem_idx
);
1029 gen_store_gpr(t1
, rt
);
1033 save_cpu_state(ctx
, 1);
1034 gen_load_gpr(t1
, rt
);
1035 gen_helper_2i(sdl
, t0
, t1
, ctx
->mem_idx
);
1039 save_cpu_state(ctx
, 1);
1040 gen_load_gpr(t1
, rt
);
1041 gen_helper_3i(ldr
, t1
, t0
, t1
, ctx
->mem_idx
);
1042 gen_store_gpr(t1
, rt
);
1046 save_cpu_state(ctx
, 1);
1047 gen_load_gpr(t1
, rt
);
1048 gen_helper_2i(sdr
, t0
, t1
, ctx
->mem_idx
);
1053 op_ldst_lw(t0
, ctx
);
1054 gen_store_gpr(t0
, rt
);
1058 gen_load_gpr(t1
, rt
);
1059 op_ldst_sw(t0
, t1
, ctx
);
1063 op_ldst_lh(t0
, ctx
);
1064 gen_store_gpr(t0
, rt
);
1068 gen_load_gpr(t1
, rt
);
1069 op_ldst_sh(t0
, t1
, ctx
);
1073 op_ldst_lhu(t0
, ctx
);
1074 gen_store_gpr(t0
, rt
);
1078 op_ldst_lb(t0
, ctx
);
1079 gen_store_gpr(t0
, rt
);
1083 gen_load_gpr(t1
, rt
);
1084 op_ldst_sb(t0
, t1
, ctx
);
1088 op_ldst_lbu(t0
, ctx
);
1089 gen_store_gpr(t0
, rt
);
1093 save_cpu_state(ctx
, 1);
1094 gen_load_gpr(t1
, rt
);
1095 gen_helper_3i(lwl
, t1
, t0
, t1
, ctx
->mem_idx
);
1096 gen_store_gpr(t1
, rt
);
1100 save_cpu_state(ctx
, 1);
1101 gen_load_gpr(t1
, rt
);
1102 gen_helper_2i(swl
, t0
, t1
, ctx
->mem_idx
);
1106 save_cpu_state(ctx
, 1);
1107 gen_load_gpr(t1
, rt
);
1108 gen_helper_3i(lwr
, t1
, t0
, t1
, ctx
->mem_idx
);
1109 gen_store_gpr(t1
, rt
);
1113 save_cpu_state(ctx
, 1);
1114 gen_load_gpr(t1
, rt
);
1115 gen_helper_2i(swr
, t0
, t1
, ctx
->mem_idx
);
1119 op_ldst_ll(t0
, t1
, ctx
);
1120 gen_store_gpr(t0
, rt
);
1124 save_cpu_state(ctx
, 1);
1125 gen_load_gpr(t1
, rt
);
1126 op_ldst_sc(t0
, t1
, ctx
);
1127 gen_store_gpr(t0
, rt
);
1132 generate_exception(ctx
, EXCP_RI
);
1135 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1141 /* Load and store */
1142 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1143 int base
, int16_t offset
)
1145 const char *opn
= "flt_ldst";
1146 TCGv t0
= tcg_temp_local_new();
1149 tcg_gen_movi_tl(t0
, offset
);
1150 } else if (offset
== 0) {
1151 gen_load_gpr(t0
, base
);
1153 tcg_gen_movi_tl(t0
, offset
);
1154 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
1156 /* Don't do NOP if destination is zero: we must perform the actual
1161 TCGv_i32 fp0
= tcg_temp_new_i32();
1162 TCGv t1
= tcg_temp_new();
1164 tcg_gen_qemu_ld32s(t1
, t0
, ctx
->mem_idx
);
1165 tcg_gen_trunc_tl_i32(fp0
, t1
);
1166 gen_store_fpr32(fp0
, ft
);
1168 tcg_temp_free_i32(fp0
);
1174 TCGv_i32 fp0
= tcg_temp_new_i32();
1175 TCGv t1
= tcg_temp_new();
1177 gen_load_fpr32(fp0
, ft
);
1178 tcg_gen_extu_i32_tl(t1
, fp0
);
1179 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1181 tcg_temp_free_i32(fp0
);
1187 TCGv_i64 fp0
= tcg_temp_new_i64();
1189 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1190 gen_store_fpr64(ctx
, fp0
, ft
);
1191 tcg_temp_free_i64(fp0
);
1197 TCGv_i64 fp0
= tcg_temp_new_i64();
1199 gen_load_fpr64(ctx
, fp0
, ft
);
1200 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1201 tcg_temp_free_i64(fp0
);
1207 generate_exception(ctx
, EXCP_RI
);
1210 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1215 /* Arithmetic with immediate operand */
1216 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1217 int rt
, int rs
, int16_t imm
)
1220 const char *opn
= "imm arith";
1221 TCGv t0
= tcg_temp_local_new();
1223 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1224 /* If no destination, treat it as a NOP.
1225 For addi, we must generate the overflow exception when needed. */
1229 uimm
= (uint16_t)imm
;
1233 #if defined(TARGET_MIPS64)
1239 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1244 gen_load_gpr(t0
, rs
);
1247 tcg_gen_movi_tl(t0
, imm
<< 16);
1252 #if defined(TARGET_MIPS64)
1261 gen_load_gpr(t0
, rs
);
1267 TCGv r_tmp1
= tcg_temp_new();
1268 TCGv r_tmp2
= tcg_temp_new();
1269 int l1
= gen_new_label();
1271 save_cpu_state(ctx
, 1);
1272 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1273 tcg_gen_addi_tl(t0
, r_tmp1
, uimm
);
1275 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1276 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1277 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1278 tcg_temp_free(r_tmp2
);
1279 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1280 /* operands of same sign, result different sign */
1281 generate_exception(ctx
, EXCP_OVERFLOW
);
1283 tcg_temp_free(r_tmp1
);
1285 tcg_gen_ext32s_tl(t0
, t0
);
1290 tcg_gen_addi_tl(t0
, t0
, uimm
);
1291 tcg_gen_ext32s_tl(t0
, t0
);
1294 #if defined(TARGET_MIPS64)
1297 TCGv r_tmp1
= tcg_temp_new();
1298 TCGv r_tmp2
= tcg_temp_new();
1299 int l1
= gen_new_label();
1301 save_cpu_state(ctx
, 1);
1302 tcg_gen_mov_tl(r_tmp1
, t0
);
1303 tcg_gen_addi_tl(t0
, t0
, uimm
);
1305 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, ~uimm
);
1306 tcg_gen_xori_tl(r_tmp2
, t0
, uimm
);
1307 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1308 tcg_temp_free(r_tmp2
);
1309 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1310 /* operands of same sign, result different sign */
1311 generate_exception(ctx
, EXCP_OVERFLOW
);
1313 tcg_temp_free(r_tmp1
);
1318 tcg_gen_addi_tl(t0
, t0
, uimm
);
1323 gen_op_lti(t0
, uimm
);
1327 gen_op_ltiu(t0
, uimm
);
1331 tcg_gen_andi_tl(t0
, t0
, uimm
);
1335 tcg_gen_ori_tl(t0
, t0
, uimm
);
1339 tcg_gen_xori_tl(t0
, t0
, uimm
);
1346 tcg_gen_shli_tl(t0
, t0
, uimm
);
1347 tcg_gen_ext32s_tl(t0
, t0
);
1351 tcg_gen_ext32s_tl(t0
, t0
);
1352 tcg_gen_sari_tl(t0
, t0
, uimm
);
1356 switch ((ctx
->opcode
>> 21) & 0x1f) {
1359 tcg_gen_ext32u_tl(t0
, t0
);
1360 tcg_gen_shri_tl(t0
, t0
, uimm
);
1362 tcg_gen_ext32s_tl(t0
, t0
);
1367 /* rotr is decoded as srl on non-R2 CPUs */
1368 if (env
->insn_flags
& ISA_MIPS32R2
) {
1370 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
1372 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1373 tcg_gen_rotri_i32(r_tmp1
, r_tmp1
, uimm
);
1374 tcg_gen_ext_i32_tl(t0
, r_tmp1
);
1375 tcg_temp_free_i32(r_tmp1
);
1380 tcg_gen_ext32u_tl(t0
, t0
);
1381 tcg_gen_shri_tl(t0
, t0
, uimm
);
1383 tcg_gen_ext32s_tl(t0
, t0
);
1389 MIPS_INVAL("invalid srl flag");
1390 generate_exception(ctx
, EXCP_RI
);
1394 #if defined(TARGET_MIPS64)
1396 tcg_gen_shli_tl(t0
, t0
, uimm
);
1400 tcg_gen_sari_tl(t0
, t0
, uimm
);
1404 switch ((ctx
->opcode
>> 21) & 0x1f) {
1406 tcg_gen_shri_tl(t0
, t0
, uimm
);
1410 /* drotr is decoded as dsrl on non-R2 CPUs */
1411 if (env
->insn_flags
& ISA_MIPS32R2
) {
1413 tcg_gen_rotri_tl(t0
, t0
, uimm
);
1417 tcg_gen_shri_tl(t0
, t0
, uimm
);
1422 MIPS_INVAL("invalid dsrl flag");
1423 generate_exception(ctx
, EXCP_RI
);
1428 tcg_gen_shli_tl(t0
, t0
, uimm
+ 32);
1432 tcg_gen_sari_tl(t0
, t0
, uimm
+ 32);
1436 switch ((ctx
->opcode
>> 21) & 0x1f) {
1438 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1442 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1443 if (env
->insn_flags
& ISA_MIPS32R2
) {
1444 tcg_gen_rotri_tl(t0
, t0
, uimm
+ 32);
1447 tcg_gen_shri_tl(t0
, t0
, uimm
+ 32);
1452 MIPS_INVAL("invalid dsrl32 flag");
1453 generate_exception(ctx
, EXCP_RI
);
1460 generate_exception(ctx
, EXCP_RI
);
1463 gen_store_gpr(t0
, rt
);
1464 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1470 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1471 int rd
, int rs
, int rt
)
1473 const char *opn
= "arith";
1474 TCGv t0
= tcg_temp_local_new();
1475 TCGv t1
= tcg_temp_local_new();
1477 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1478 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1479 /* If no destination, treat it as a NOP.
1480 For add & sub, we must generate the overflow exception when needed. */
1484 gen_load_gpr(t0
, rs
);
1485 /* Specialcase the conventional move operation. */
1486 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1487 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1488 gen_store_gpr(t0
, rd
);
1491 gen_load_gpr(t1
, rt
);
1495 TCGv r_tmp1
= tcg_temp_new();
1496 TCGv r_tmp2
= tcg_temp_new();
1497 int l1
= gen_new_label();
1499 save_cpu_state(ctx
, 1);
1500 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1501 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1502 tcg_gen_add_tl(t0
, r_tmp1
, r_tmp2
);
1504 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1505 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1506 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1507 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1508 tcg_temp_free(r_tmp2
);
1509 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1510 /* operands of same sign, result different sign */
1511 generate_exception(ctx
, EXCP_OVERFLOW
);
1513 tcg_temp_free(r_tmp1
);
1515 tcg_gen_ext32s_tl(t0
, t0
);
1520 tcg_gen_add_tl(t0
, t0
, t1
);
1521 tcg_gen_ext32s_tl(t0
, t0
);
1526 TCGv r_tmp1
= tcg_temp_new();
1527 TCGv r_tmp2
= tcg_temp_new();
1528 int l1
= gen_new_label();
1530 save_cpu_state(ctx
, 1);
1531 tcg_gen_ext32s_tl(r_tmp1
, t0
);
1532 tcg_gen_ext32s_tl(r_tmp2
, t1
);
1533 tcg_gen_sub_tl(t0
, r_tmp1
, r_tmp2
);
1535 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1536 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1537 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1538 tcg_temp_free(r_tmp2
);
1539 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1540 /* operands of different sign, first operand and result different sign */
1541 generate_exception(ctx
, EXCP_OVERFLOW
);
1543 tcg_temp_free(r_tmp1
);
1545 tcg_gen_ext32s_tl(t0
, t0
);
1550 tcg_gen_sub_tl(t0
, t0
, t1
);
1551 tcg_gen_ext32s_tl(t0
, t0
);
1554 #if defined(TARGET_MIPS64)
1557 TCGv r_tmp1
= tcg_temp_new();
1558 TCGv r_tmp2
= tcg_temp_new();
1559 int l1
= gen_new_label();
1561 save_cpu_state(ctx
, 1);
1562 tcg_gen_mov_tl(r_tmp1
, t0
);
1563 tcg_gen_add_tl(t0
, t0
, t1
);
1565 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t1
);
1566 tcg_gen_xori_tl(r_tmp1
, r_tmp1
, -1);
1567 tcg_gen_xor_tl(r_tmp2
, t0
, t1
);
1568 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1569 tcg_temp_free(r_tmp2
);
1570 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1571 /* operands of same sign, result different sign */
1572 generate_exception(ctx
, EXCP_OVERFLOW
);
1574 tcg_temp_free(r_tmp1
);
1579 tcg_gen_add_tl(t0
, t0
, t1
);
1584 TCGv r_tmp1
= tcg_temp_new();
1585 TCGv r_tmp2
= tcg_temp_new();
1586 int l1
= gen_new_label();
1588 save_cpu_state(ctx
, 1);
1589 tcg_gen_mov_tl(r_tmp1
, t0
);
1590 tcg_gen_sub_tl(t0
, t0
, t1
);
1592 tcg_gen_xor_tl(r_tmp2
, r_tmp1
, t1
);
1593 tcg_gen_xor_tl(r_tmp1
, r_tmp1
, t0
);
1594 tcg_gen_and_tl(r_tmp1
, r_tmp1
, r_tmp2
);
1595 tcg_temp_free(r_tmp2
);
1596 tcg_gen_brcondi_tl(TCG_COND_GE
, r_tmp1
, 0, l1
);
1597 /* operands of different sign, first operand and result different sign */
1598 generate_exception(ctx
, EXCP_OVERFLOW
);
1600 tcg_temp_free(r_tmp1
);
1605 tcg_gen_sub_tl(t0
, t0
, t1
);
1618 tcg_gen_and_tl(t0
, t0
, t1
);
1622 tcg_gen_or_tl(t0
, t0
, t1
);
1623 tcg_gen_not_tl(t0
, t0
);
1627 tcg_gen_or_tl(t0
, t0
, t1
);
1631 tcg_gen_xor_tl(t0
, t0
, t1
);
1635 tcg_gen_mul_tl(t0
, t0
, t1
);
1636 tcg_gen_ext32s_tl(t0
, t0
);
1641 int l1
= gen_new_label();
1643 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1644 gen_store_gpr(t0
, rd
);
1651 int l1
= gen_new_label();
1653 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
1654 gen_store_gpr(t0
, rd
);
1660 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1661 tcg_gen_shl_tl(t0
, t1
, t0
);
1662 tcg_gen_ext32s_tl(t0
, t0
);
1666 tcg_gen_ext32s_tl(t1
, t1
);
1667 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1668 tcg_gen_sar_tl(t0
, t1
, t0
);
1672 switch ((ctx
->opcode
>> 6) & 0x1f) {
1674 tcg_gen_ext32u_tl(t1
, t1
);
1675 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1676 tcg_gen_shr_tl(t0
, t1
, t0
);
1677 tcg_gen_ext32s_tl(t0
, t0
);
1681 /* rotrv is decoded as srlv on non-R2 CPUs */
1682 if (env
->insn_flags
& ISA_MIPS32R2
) {
1683 int l1
= gen_new_label();
1684 int l2
= gen_new_label();
1686 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1687 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1689 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
1690 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
1692 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1693 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1694 tcg_gen_rotr_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1695 tcg_temp_free_i32(r_tmp1
);
1696 tcg_temp_free_i32(r_tmp2
);
1700 tcg_gen_mov_tl(t0
, t1
);
1704 tcg_gen_ext32u_tl(t1
, t1
);
1705 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1706 tcg_gen_shr_tl(t0
, t1
, t0
);
1707 tcg_gen_ext32s_tl(t0
, t0
);
1712 MIPS_INVAL("invalid srlv flag");
1713 generate_exception(ctx
, EXCP_RI
);
1717 #if defined(TARGET_MIPS64)
1719 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1720 tcg_gen_shl_tl(t0
, t1
, t0
);
1724 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1725 tcg_gen_sar_tl(t0
, t1
, t0
);
1729 switch ((ctx
->opcode
>> 6) & 0x1f) {
1731 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1732 tcg_gen_shr_tl(t0
, t1
, t0
);
1736 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1737 if (env
->insn_flags
& ISA_MIPS32R2
) {
1738 int l1
= gen_new_label();
1739 int l2
= gen_new_label();
1741 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1742 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1744 tcg_gen_rotr_tl(t0
, t1
, t0
);
1748 tcg_gen_mov_tl(t0
, t1
);
1752 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1753 tcg_gen_shr_tl(t0
, t1
, t0
);
1758 MIPS_INVAL("invalid dsrlv flag");
1759 generate_exception(ctx
, EXCP_RI
);
1766 generate_exception(ctx
, EXCP_RI
);
1769 gen_store_gpr(t0
, rd
);
1771 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1777 /* Arithmetic on HI/LO registers */
1778 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1780 const char *opn
= "hilo";
1781 TCGv t0
= tcg_temp_local_new();
1783 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1790 tcg_gen_mov_tl(t0
, cpu_HI
[0]);
1791 gen_store_gpr(t0
, reg
);
1795 tcg_gen_mov_tl(t0
, cpu_LO
[0]);
1796 gen_store_gpr(t0
, reg
);
1800 gen_load_gpr(t0
, reg
);
1801 tcg_gen_mov_tl(cpu_HI
[0], t0
);
1805 gen_load_gpr(t0
, reg
);
1806 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1811 generate_exception(ctx
, EXCP_RI
);
1814 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1819 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1822 const char *opn
= "mul/div";
1823 TCGv t0
= tcg_temp_local_new();
1824 TCGv t1
= tcg_temp_local_new();
1826 gen_load_gpr(t0
, rs
);
1827 gen_load_gpr(t1
, rt
);
1831 int l1
= gen_new_label();
1833 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1835 int l2
= gen_new_label();
1836 TCGv_i32 r_tmp1
= tcg_temp_local_new_i32();
1837 TCGv_i32 r_tmp2
= tcg_temp_local_new_i32();
1838 TCGv_i32 r_tmp3
= tcg_temp_local_new_i32();
1840 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1841 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1842 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp1
, -1 << 31, l2
);
1843 tcg_gen_brcondi_i32(TCG_COND_NE
, r_tmp2
, -1, l2
);
1844 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1845 tcg_gen_movi_tl(cpu_HI
[0], 0);
1848 tcg_gen_div_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1849 tcg_gen_rem_i32(r_tmp2
, r_tmp1
, r_tmp2
);
1850 tcg_gen_ext_i32_tl(cpu_LO
[0], r_tmp3
);
1851 tcg_gen_ext_i32_tl(cpu_HI
[0], r_tmp2
);
1852 tcg_temp_free_i32(r_tmp1
);
1853 tcg_temp_free_i32(r_tmp2
);
1854 tcg_temp_free_i32(r_tmp3
);
1862 int l1
= gen_new_label();
1864 tcg_gen_ext32s_tl(t1
, t1
);
1865 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1867 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
1868 TCGv_i32 r_tmp2
= tcg_temp_new_i32();
1869 TCGv_i32 r_tmp3
= tcg_temp_new_i32();
1871 tcg_gen_trunc_tl_i32(r_tmp1
, t0
);
1872 tcg_gen_trunc_tl_i32(r_tmp2
, t1
);
1873 tcg_gen_divu_i32(r_tmp3
, r_tmp1
, r_tmp2
);
1874 tcg_gen_remu_i32(r_tmp1
, r_tmp1
, r_tmp2
);
1875 tcg_gen_ext_i32_tl(cpu_LO
[0], r_tmp3
);
1876 tcg_gen_ext_i32_tl(cpu_HI
[0], r_tmp1
);
1877 tcg_temp_free_i32(r_tmp1
);
1878 tcg_temp_free_i32(r_tmp2
);
1879 tcg_temp_free_i32(r_tmp3
);
1887 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
1888 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
1890 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1891 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1892 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1893 tcg_temp_free_i64(r_tmp2
);
1894 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1895 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1896 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1897 tcg_temp_free_i64(r_tmp1
);
1898 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1899 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1905 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
1906 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
1908 tcg_gen_ext32u_tl(t0
, t0
);
1909 tcg_gen_ext32u_tl(t1
, t1
);
1910 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
1911 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
1912 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1913 tcg_temp_free_i64(r_tmp2
);
1914 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1915 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1916 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1917 tcg_temp_free_i64(r_tmp1
);
1918 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1919 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1923 #if defined(TARGET_MIPS64)
1926 int l1
= gen_new_label();
1928 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1930 int l2
= gen_new_label();
1932 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
1933 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
1934 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1935 tcg_gen_movi_tl(cpu_HI
[0], 0);
1938 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
1939 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
1947 int l1
= gen_new_label();
1949 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1950 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
1951 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
1957 gen_helper_dmult(t0
, t1
);
1961 gen_helper_dmultu(t0
, t1
);
1967 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
1968 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
1970 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
1971 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
1972 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1973 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
1974 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1975 tcg_temp_free_i64(r_tmp2
);
1976 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1977 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
1978 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
1979 tcg_temp_free_i64(r_tmp1
);
1980 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1981 tcg_gen_ext32s_tl(cpu_LO
[1], t1
);
1987 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
1988 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
1990 tcg_gen_ext32u_tl(t0
, t0
);
1991 tcg_gen_ext32u_tl(t1
, t1
);
1992 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
1993 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
1994 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1995 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
1996 tcg_gen_add_i64(r_tmp1
, r_tmp1
, r_tmp2
);
1997 tcg_temp_free_i64(r_tmp2
);
1998 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
1999 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2000 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2001 tcg_temp_free_i64(r_tmp1
);
2002 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2003 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2009 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
2010 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
2012 tcg_gen_ext_tl_i64(r_tmp1
, t0
);
2013 tcg_gen_ext_tl_i64(r_tmp2
, t1
);
2014 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2015 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2016 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2017 tcg_temp_free_i64(r_tmp2
);
2018 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2019 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2020 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2021 tcg_temp_free_i64(r_tmp1
);
2022 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2023 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2029 TCGv_i64 r_tmp1
= tcg_temp_new_i64();
2030 TCGv_i64 r_tmp2
= tcg_temp_new_i64();
2032 tcg_gen_ext32u_tl(t0
, t0
);
2033 tcg_gen_ext32u_tl(t1
, t1
);
2034 tcg_gen_extu_tl_i64(r_tmp1
, t0
);
2035 tcg_gen_extu_tl_i64(r_tmp2
, t1
);
2036 tcg_gen_mul_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2037 tcg_gen_concat_tl_i64(r_tmp2
, cpu_LO
[0], cpu_HI
[0]);
2038 tcg_gen_sub_i64(r_tmp1
, r_tmp1
, r_tmp2
);
2039 tcg_temp_free_i64(r_tmp2
);
2040 tcg_gen_trunc_i64_tl(t0
, r_tmp1
);
2041 tcg_gen_shri_i64(r_tmp1
, r_tmp1
, 32);
2042 tcg_gen_trunc_i64_tl(t1
, r_tmp1
);
2043 tcg_temp_free_i64(r_tmp1
);
2044 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2045 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2051 generate_exception(ctx
, EXCP_RI
);
2054 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2060 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2061 int rd
, int rs
, int rt
)
2063 const char *opn
= "mul vr54xx";
2064 TCGv t0
= tcg_temp_local_new();
2065 TCGv t1
= tcg_temp_local_new();
2067 gen_load_gpr(t0
, rs
);
2068 gen_load_gpr(t1
, rt
);
2071 case OPC_VR54XX_MULS
:
2072 gen_helper_muls(t0
, t0
, t1
);
2075 case OPC_VR54XX_MULSU
:
2076 gen_helper_mulsu(t0
, t0
, t1
);
2079 case OPC_VR54XX_MACC
:
2080 gen_helper_macc(t0
, t0
, t1
);
2083 case OPC_VR54XX_MACCU
:
2084 gen_helper_maccu(t0
, t0
, t1
);
2087 case OPC_VR54XX_MSAC
:
2088 gen_helper_msac(t0
, t0
, t1
);
2091 case OPC_VR54XX_MSACU
:
2092 gen_helper_msacu(t0
, t0
, t1
);
2095 case OPC_VR54XX_MULHI
:
2096 gen_helper_mulhi(t0
, t0
, t1
);
2099 case OPC_VR54XX_MULHIU
:
2100 gen_helper_mulhiu(t0
, t0
, t1
);
2103 case OPC_VR54XX_MULSHI
:
2104 gen_helper_mulshi(t0
, t0
, t1
);
2107 case OPC_VR54XX_MULSHIU
:
2108 gen_helper_mulshiu(t0
, t0
, t1
);
2111 case OPC_VR54XX_MACCHI
:
2112 gen_helper_macchi(t0
, t0
, t1
);
2115 case OPC_VR54XX_MACCHIU
:
2116 gen_helper_macchiu(t0
, t0
, t1
);
2119 case OPC_VR54XX_MSACHI
:
2120 gen_helper_msachi(t0
, t0
, t1
);
2123 case OPC_VR54XX_MSACHIU
:
2124 gen_helper_msachiu(t0
, t0
, t1
);
2128 MIPS_INVAL("mul vr54xx");
2129 generate_exception(ctx
, EXCP_RI
);
2132 gen_store_gpr(t0
, rd
);
2133 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2140 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2143 const char *opn
= "CLx";
2144 TCGv t0
= tcg_temp_local_new();
2151 gen_load_gpr(t0
, rs
);
2154 gen_helper_clo(t0
, t0
);
2158 gen_helper_clz(t0
, t0
);
2161 #if defined(TARGET_MIPS64)
2163 gen_helper_dclo(t0
, t0
);
2167 gen_helper_dclz(t0
, t0
);
2173 generate_exception(ctx
, EXCP_RI
);
2176 gen_store_gpr(t0
, rd
);
2177 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2184 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2185 int rs
, int rt
, int16_t imm
)
2188 TCGv t0
= tcg_temp_local_new();
2189 TCGv t1
= tcg_temp_local_new();
2192 /* Load needed operands */
2200 /* Compare two registers */
2202 gen_load_gpr(t0
, rs
);
2203 gen_load_gpr(t1
, rt
);
2213 /* Compare register to immediate */
2214 if (rs
!= 0 || imm
!= 0) {
2215 gen_load_gpr(t0
, rs
);
2216 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2223 case OPC_TEQ
: /* rs == rs */
2224 case OPC_TEQI
: /* r0 == 0 */
2225 case OPC_TGE
: /* rs >= rs */
2226 case OPC_TGEI
: /* r0 >= 0 */
2227 case OPC_TGEU
: /* rs >= rs unsigned */
2228 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2230 tcg_gen_movi_tl(t0
, 1);
2232 case OPC_TLT
: /* rs < rs */
2233 case OPC_TLTI
: /* r0 < 0 */
2234 case OPC_TLTU
: /* rs < rs unsigned */
2235 case OPC_TLTIU
: /* r0 < 0 unsigned */
2236 case OPC_TNE
: /* rs != rs */
2237 case OPC_TNEI
: /* r0 != 0 */
2238 /* Never trap: treat as NOP. */
2242 generate_exception(ctx
, EXCP_RI
);
2273 generate_exception(ctx
, EXCP_RI
);
2277 save_cpu_state(ctx
, 1);
2279 int l1
= gen_new_label();
2281 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2282 gen_helper_0i(raise_exception
, EXCP_TRAP
);
2285 ctx
->bstate
= BS_STOP
;
2291 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2293 TranslationBlock
*tb
;
2295 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2298 tcg_gen_exit_tb((long)tb
+ n
);
2305 /* Branches (before delay slot) */
2306 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2307 int rs
, int rt
, int32_t offset
)
2309 target_ulong btgt
= -1;
2311 int bcond_compute
= 0;
2312 TCGv t0
= tcg_temp_local_new();
2313 TCGv t1
= tcg_temp_local_new();
2315 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2316 #ifdef MIPS_DEBUG_DISAS
2317 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2319 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
2323 generate_exception(ctx
, EXCP_RI
);
2327 /* Load needed operands */
2333 /* Compare two registers */
2335 gen_load_gpr(t0
, rs
);
2336 gen_load_gpr(t1
, rt
);
2339 btgt
= ctx
->pc
+ 4 + offset
;
2353 /* Compare to zero */
2355 gen_load_gpr(t0
, rs
);
2358 btgt
= ctx
->pc
+ 4 + offset
;
2362 /* Jump to immediate */
2363 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2367 /* Jump to register */
2368 if (offset
!= 0 && offset
!= 16) {
2369 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2370 others are reserved. */
2371 MIPS_INVAL("jump hint");
2372 generate_exception(ctx
, EXCP_RI
);
2375 gen_load_gpr(btarget
, rs
);
2378 MIPS_INVAL("branch/jump");
2379 generate_exception(ctx
, EXCP_RI
);
2382 if (bcond_compute
== 0) {
2383 /* No condition to be computed */
2385 case OPC_BEQ
: /* rx == rx */
2386 case OPC_BEQL
: /* rx == rx likely */
2387 case OPC_BGEZ
: /* 0 >= 0 */
2388 case OPC_BGEZL
: /* 0 >= 0 likely */
2389 case OPC_BLEZ
: /* 0 <= 0 */
2390 case OPC_BLEZL
: /* 0 <= 0 likely */
2392 ctx
->hflags
|= MIPS_HFLAG_B
;
2393 MIPS_DEBUG("balways");
2395 case OPC_BGEZAL
: /* 0 >= 0 */
2396 case OPC_BGEZALL
: /* 0 >= 0 likely */
2397 /* Always take and link */
2399 ctx
->hflags
|= MIPS_HFLAG_B
;
2400 MIPS_DEBUG("balways and link");
2402 case OPC_BNE
: /* rx != rx */
2403 case OPC_BGTZ
: /* 0 > 0 */
2404 case OPC_BLTZ
: /* 0 < 0 */
2406 MIPS_DEBUG("bnever (NOP)");
2408 case OPC_BLTZAL
: /* 0 < 0 */
2409 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2410 gen_store_gpr(t0
, 31);
2411 MIPS_DEBUG("bnever and link");
2413 case OPC_BLTZALL
: /* 0 < 0 likely */
2414 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2415 gen_store_gpr(t0
, 31);
2416 /* Skip the instruction in the delay slot */
2417 MIPS_DEBUG("bnever, link and skip");
2420 case OPC_BNEL
: /* rx != rx likely */
2421 case OPC_BGTZL
: /* 0 > 0 likely */
2422 case OPC_BLTZL
: /* 0 < 0 likely */
2423 /* Skip the instruction in the delay slot */
2424 MIPS_DEBUG("bnever and skip");
2428 ctx
->hflags
|= MIPS_HFLAG_B
;
2429 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2433 ctx
->hflags
|= MIPS_HFLAG_B
;
2434 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2437 ctx
->hflags
|= MIPS_HFLAG_BR
;
2438 MIPS_DEBUG("jr %s", regnames
[rs
]);
2442 ctx
->hflags
|= MIPS_HFLAG_BR
;
2443 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2446 MIPS_INVAL("branch/jump");
2447 generate_exception(ctx
, EXCP_RI
);
2454 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2455 regnames
[rs
], regnames
[rt
], btgt
);
2459 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2460 regnames
[rs
], regnames
[rt
], btgt
);
2464 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2465 regnames
[rs
], regnames
[rt
], btgt
);
2469 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2470 regnames
[rs
], regnames
[rt
], btgt
);
2474 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2478 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2482 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2488 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2492 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2496 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2500 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2504 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2508 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2512 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2517 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2519 ctx
->hflags
|= MIPS_HFLAG_BC
;
2520 tcg_gen_trunc_tl_i32(bcond
, t0
);
2525 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2527 ctx
->hflags
|= MIPS_HFLAG_BL
;
2528 tcg_gen_trunc_tl_i32(bcond
, t0
);
2531 MIPS_INVAL("conditional branch/jump");
2532 generate_exception(ctx
, EXCP_RI
);
2536 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2537 blink
, ctx
->hflags
, btgt
);
2539 ctx
->btarget
= btgt
;
2541 tcg_gen_movi_tl(t0
, ctx
->pc
+ 8);
2542 gen_store_gpr(t0
, blink
);
2550 /* special3 bitfield operations */
2551 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2552 int rs
, int lsb
, int msb
)
2554 TCGv t0
= tcg_temp_new();
2555 TCGv t1
= tcg_temp_new();
2558 gen_load_gpr(t1
, rs
);
2563 tcg_gen_shri_tl(t0
, t1
, lsb
);
2565 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2567 tcg_gen_ext32s_tl(t0
, t0
);
2570 #if defined(TARGET_MIPS64)
2572 tcg_gen_shri_tl(t0
, t1
, lsb
);
2574 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2578 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2579 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2582 tcg_gen_shri_tl(t0
, t1
, lsb
);
2583 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2589 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2590 gen_load_gpr(t0
, rt
);
2591 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2592 tcg_gen_shli_tl(t1
, t1
, lsb
);
2593 tcg_gen_andi_tl(t1
, t1
, mask
);
2594 tcg_gen_or_tl(t0
, t0
, t1
);
2595 tcg_gen_ext32s_tl(t0
, t0
);
2597 #if defined(TARGET_MIPS64)
2601 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2602 gen_load_gpr(t0
, rt
);
2603 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2604 tcg_gen_shli_tl(t1
, t1
, lsb
);
2605 tcg_gen_andi_tl(t1
, t1
, mask
);
2606 tcg_gen_or_tl(t0
, t0
, t1
);
2611 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2612 gen_load_gpr(t0
, rt
);
2613 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2614 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2615 tcg_gen_andi_tl(t1
, t1
, mask
);
2616 tcg_gen_or_tl(t0
, t0
, t1
);
2621 gen_load_gpr(t0
, rt
);
2622 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2623 gen_load_gpr(t0
, rt
);
2624 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2625 tcg_gen_shli_tl(t1
, t1
, lsb
);
2626 tcg_gen_andi_tl(t1
, t1
, mask
);
2627 tcg_gen_or_tl(t0
, t0
, t1
);
2632 MIPS_INVAL("bitops");
2633 generate_exception(ctx
, EXCP_RI
);
2638 gen_store_gpr(t0
, rt
);
2643 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2645 TCGv t0
= tcg_temp_new();
2646 TCGv t1
= tcg_temp_new();
2648 gen_load_gpr(t1
, rt
);
2651 tcg_gen_shri_tl(t0
, t1
, 8);
2652 tcg_gen_andi_tl(t0
, t0
, 0x00FF00FF);
2653 tcg_gen_shli_tl(t1
, t1
, 8);
2654 tcg_gen_andi_tl(t1
, t1
, ~0x00FF00FF);
2655 tcg_gen_or_tl(t0
, t0
, t1
);
2656 tcg_gen_ext32s_tl(t0
, t0
);
2659 tcg_gen_ext8s_tl(t0
, t1
);
2662 tcg_gen_ext16s_tl(t0
, t1
);
2664 #if defined(TARGET_MIPS64)
2666 gen_load_gpr(t1
, rt
);
2667 tcg_gen_shri_tl(t0
, t1
, 8);
2668 tcg_gen_andi_tl(t0
, t0
, 0x00FF00FF00FF00FFULL
);
2669 tcg_gen_shli_tl(t1
, t1
, 8);
2670 tcg_gen_andi_tl(t1
, t1
, ~0x00FF00FF00FF00FFULL
);
2671 tcg_gen_or_tl(t0
, t0
, t1
);
2674 gen_load_gpr(t1
, rt
);
2675 tcg_gen_shri_tl(t0
, t1
, 16);
2676 tcg_gen_andi_tl(t0
, t0
, 0x0000FFFF0000FFFFULL
);
2677 tcg_gen_shli_tl(t1
, t1
, 16);
2678 tcg_gen_andi_tl(t1
, t1
, ~0x0000FFFF0000FFFFULL
);
2679 tcg_gen_or_tl(t1
, t0
, t1
);
2680 tcg_gen_shri_tl(t0
, t1
, 32);
2681 tcg_gen_shli_tl(t1
, t1
, 32);
2682 tcg_gen_or_tl(t0
, t0
, t1
);
2686 MIPS_INVAL("bsfhl");
2687 generate_exception(ctx
, EXCP_RI
);
2692 gen_store_gpr(t0
, rd
);
2697 #ifndef CONFIG_USER_ONLY
2698 /* CP0 (MMU and control) */
2699 static inline void gen_mfc0_load32 (TCGv t
, target_ulong off
)
2701 TCGv_i32 r_tmp
= tcg_temp_new_i32();
2703 tcg_gen_ld_i32(r_tmp
, cpu_env
, off
);
2704 tcg_gen_ext_i32_tl(t
, r_tmp
);
2705 tcg_temp_free_i32(r_tmp
);
2708 static inline void gen_mfc0_load64 (TCGv t
, target_ulong off
)
2710 tcg_gen_ld_tl(t
, cpu_env
, off
);
2711 tcg_gen_ext32s_tl(t
, t
);
2714 static inline void gen_mtc0_store32 (TCGv t
, target_ulong off
)
2716 TCGv_i32 r_tmp
= tcg_temp_new_i32();
2718 tcg_gen_trunc_tl_i32(r_tmp
, t
);
2719 tcg_gen_st_i32(r_tmp
, cpu_env
, off
);
2720 tcg_temp_free_i32(r_tmp
);
2723 static inline void gen_mtc0_store64 (TCGv t
, target_ulong off
)
2725 tcg_gen_ext32s_tl(t
, t
);
2726 tcg_gen_st_tl(t
, cpu_env
, off
);
2729 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
2731 const char *rn
= "invalid";
2734 check_insn(env
, ctx
, ISA_MIPS32
);
2740 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
2744 check_insn(env
, ctx
, ASE_MT
);
2745 gen_helper_mfc0_mvpcontrol(t0
);
2749 check_insn(env
, ctx
, ASE_MT
);
2750 gen_helper_mfc0_mvpconf0(t0
);
2754 check_insn(env
, ctx
, ASE_MT
);
2755 gen_helper_mfc0_mvpconf1(t0
);
2765 gen_helper_mfc0_random(t0
);
2769 check_insn(env
, ctx
, ASE_MT
);
2770 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
2774 check_insn(env
, ctx
, ASE_MT
);
2775 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
2779 check_insn(env
, ctx
, ASE_MT
);
2780 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
2784 check_insn(env
, ctx
, ASE_MT
);
2785 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_YQMask
));
2789 check_insn(env
, ctx
, ASE_MT
);
2790 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
2794 check_insn(env
, ctx
, ASE_MT
);
2795 gen_mfc0_load64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
2796 rn
= "VPEScheFBack";
2799 check_insn(env
, ctx
, ASE_MT
);
2800 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
2810 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2811 tcg_gen_ext32s_tl(t0
, t0
);
2815 check_insn(env
, ctx
, ASE_MT
);
2816 gen_helper_mfc0_tcstatus(t0
);
2820 check_insn(env
, ctx
, ASE_MT
);
2821 gen_helper_mfc0_tcbind(t0
);
2825 check_insn(env
, ctx
, ASE_MT
);
2826 gen_helper_mfc0_tcrestart(t0
);
2830 check_insn(env
, ctx
, ASE_MT
);
2831 gen_helper_mfc0_tchalt(t0
);
2835 check_insn(env
, ctx
, ASE_MT
);
2836 gen_helper_mfc0_tccontext(t0
);
2840 check_insn(env
, ctx
, ASE_MT
);
2841 gen_helper_mfc0_tcschedule(t0
);
2845 check_insn(env
, ctx
, ASE_MT
);
2846 gen_helper_mfc0_tcschefback(t0
);
2856 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2857 tcg_gen_ext32s_tl(t0
, t0
);
2867 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2868 tcg_gen_ext32s_tl(t0
, t0
);
2872 // gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
2873 rn
= "ContextConfig";
2882 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
2886 check_insn(env
, ctx
, ISA_MIPS32R2
);
2887 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
2897 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
2901 check_insn(env
, ctx
, ISA_MIPS32R2
);
2902 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
2906 check_insn(env
, ctx
, ISA_MIPS32R2
);
2907 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
2911 check_insn(env
, ctx
, ISA_MIPS32R2
);
2912 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
2916 check_insn(env
, ctx
, ISA_MIPS32R2
);
2917 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
2921 check_insn(env
, ctx
, ISA_MIPS32R2
);
2922 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
2932 check_insn(env
, ctx
, ISA_MIPS32R2
);
2933 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
2943 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
2944 tcg_gen_ext32s_tl(t0
, t0
);
2954 /* Mark as an IO operation because we read the time. */
2957 gen_helper_mfc0_count(t0
);
2960 ctx
->bstate
= BS_STOP
;
2964 /* 6,7 are implementation dependent */
2972 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
2973 tcg_gen_ext32s_tl(t0
, t0
);
2983 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
2986 /* 6,7 are implementation dependent */
2994 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
2998 check_insn(env
, ctx
, ISA_MIPS32R2
);
2999 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
3003 check_insn(env
, ctx
, ISA_MIPS32R2
);
3004 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
3008 check_insn(env
, ctx
, ISA_MIPS32R2
);
3009 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3019 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
3029 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3030 tcg_gen_ext32s_tl(t0
, t0
);
3040 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
3044 check_insn(env
, ctx
, ISA_MIPS32R2
);
3045 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
3055 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
3059 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
3063 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
3067 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
3070 /* 4,5 are reserved */
3071 /* 6,7 are implementation dependent */
3073 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
3077 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
3087 gen_helper_mfc0_lladdr(t0
);
3097 gen_helper_1i(mfc0_watchlo
, t0
, sel
);
3107 gen_helper_1i(mfc0_watchhi
, t0
, sel
);
3117 #if defined(TARGET_MIPS64)
3118 check_insn(env
, ctx
, ISA_MIPS3
);
3119 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3120 tcg_gen_ext32s_tl(t0
, t0
);
3129 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3132 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
3140 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3141 rn
= "'Diagnostic"; /* implementation dependent */
3146 gen_helper_mfc0_debug(t0
); /* EJTAG support */
3150 // gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
3151 rn
= "TraceControl";
3154 // gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
3155 rn
= "TraceControl2";
3158 // gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
3159 rn
= "UserTraceData";
3162 // gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
3173 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3174 tcg_gen_ext32s_tl(t0
, t0
);
3184 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
3185 rn
= "Performance0";
3188 // gen_helper_mfc0_performance1(t0);
3189 rn
= "Performance1";
3192 // gen_helper_mfc0_performance2(t0);
3193 rn
= "Performance2";
3196 // gen_helper_mfc0_performance3(t0);
3197 rn
= "Performance3";
3200 // gen_helper_mfc0_performance4(t0);
3201 rn
= "Performance4";
3204 // gen_helper_mfc0_performance5(t0);
3205 rn
= "Performance5";
3208 // gen_helper_mfc0_performance6(t0);
3209 rn
= "Performance6";
3212 // gen_helper_mfc0_performance7(t0);
3213 rn
= "Performance7";
3220 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3226 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
3239 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
3246 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
3259 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
3266 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
3276 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3277 tcg_gen_ext32s_tl(t0
, t0
);
3288 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3298 #if defined MIPS_DEBUG_DISAS
3299 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3300 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3307 #if defined MIPS_DEBUG_DISAS
3308 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3309 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
3313 generate_exception(ctx
, EXCP_RI
);
3316 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3318 const char *rn
= "invalid";
3321 check_insn(env
, ctx
, ISA_MIPS32
);
3330 gen_helper_mtc0_index(t0
);
3334 check_insn(env
, ctx
, ASE_MT
);
3335 gen_helper_mtc0_mvpcontrol(t0
);
3339 check_insn(env
, ctx
, ASE_MT
);
3344 check_insn(env
, ctx
, ASE_MT
);
3359 check_insn(env
, ctx
, ASE_MT
);
3360 gen_helper_mtc0_vpecontrol(t0
);
3364 check_insn(env
, ctx
, ASE_MT
);
3365 gen_helper_mtc0_vpeconf0(t0
);
3369 check_insn(env
, ctx
, ASE_MT
);
3370 gen_helper_mtc0_vpeconf1(t0
);
3374 check_insn(env
, ctx
, ASE_MT
);
3375 gen_helper_mtc0_yqmask(t0
);
3379 check_insn(env
, ctx
, ASE_MT
);
3380 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPESchedule
));
3384 check_insn(env
, ctx
, ASE_MT
);
3385 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_VPEScheFBack
));
3386 rn
= "VPEScheFBack";
3389 check_insn(env
, ctx
, ASE_MT
);
3390 gen_helper_mtc0_vpeopt(t0
);
3400 gen_helper_mtc0_entrylo0(t0
);
3404 check_insn(env
, ctx
, ASE_MT
);
3405 gen_helper_mtc0_tcstatus(t0
);
3409 check_insn(env
, ctx
, ASE_MT
);
3410 gen_helper_mtc0_tcbind(t0
);
3414 check_insn(env
, ctx
, ASE_MT
);
3415 gen_helper_mtc0_tcrestart(t0
);
3419 check_insn(env
, ctx
, ASE_MT
);
3420 gen_helper_mtc0_tchalt(t0
);
3424 check_insn(env
, ctx
, ASE_MT
);
3425 gen_helper_mtc0_tccontext(t0
);
3429 check_insn(env
, ctx
, ASE_MT
);
3430 gen_helper_mtc0_tcschedule(t0
);
3434 check_insn(env
, ctx
, ASE_MT
);
3435 gen_helper_mtc0_tcschefback(t0
);
3445 gen_helper_mtc0_entrylo1(t0
);
3455 gen_helper_mtc0_context(t0
);
3459 // gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
3460 rn
= "ContextConfig";
3469 gen_helper_mtc0_pagemask(t0
);
3473 check_insn(env
, ctx
, ISA_MIPS32R2
);
3474 gen_helper_mtc0_pagegrain(t0
);
3484 gen_helper_mtc0_wired(t0
);
3488 check_insn(env
, ctx
, ISA_MIPS32R2
);
3489 gen_helper_mtc0_srsconf0(t0
);
3493 check_insn(env
, ctx
, ISA_MIPS32R2
);
3494 gen_helper_mtc0_srsconf1(t0
);
3498 check_insn(env
, ctx
, ISA_MIPS32R2
);
3499 gen_helper_mtc0_srsconf2(t0
);
3503 check_insn(env
, ctx
, ISA_MIPS32R2
);
3504 gen_helper_mtc0_srsconf3(t0
);
3508 check_insn(env
, ctx
, ISA_MIPS32R2
);
3509 gen_helper_mtc0_srsconf4(t0
);
3519 check_insn(env
, ctx
, ISA_MIPS32R2
);
3520 gen_helper_mtc0_hwrena(t0
);
3534 gen_helper_mtc0_count(t0
);
3537 /* 6,7 are implementation dependent */
3541 /* Stop translation as we may have switched the execution mode */
3542 ctx
->bstate
= BS_STOP
;
3547 gen_helper_mtc0_entryhi(t0
);
3557 gen_helper_mtc0_compare(t0
);
3560 /* 6,7 are implementation dependent */
3564 /* Stop translation as we may have switched the execution mode */
3565 ctx
->bstate
= BS_STOP
;
3570 gen_helper_mtc0_status(t0
);
3571 /* BS_STOP isn't good enough here, hflags may have changed. */
3572 gen_save_pc(ctx
->pc
+ 4);
3573 ctx
->bstate
= BS_EXCP
;
3577 check_insn(env
, ctx
, ISA_MIPS32R2
);
3578 gen_helper_mtc0_intctl(t0
);
3579 /* Stop translation as we may have switched the execution mode */
3580 ctx
->bstate
= BS_STOP
;
3584 check_insn(env
, ctx
, ISA_MIPS32R2
);
3585 gen_helper_mtc0_srsctl(t0
);
3586 /* Stop translation as we may have switched the execution mode */
3587 ctx
->bstate
= BS_STOP
;
3591 check_insn(env
, ctx
, ISA_MIPS32R2
);
3592 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
3593 /* Stop translation as we may have switched the execution mode */
3594 ctx
->bstate
= BS_STOP
;
3604 gen_helper_mtc0_cause(t0
);
3610 /* Stop translation as we may have switched the execution mode */
3611 ctx
->bstate
= BS_STOP
;
3616 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_EPC
));
3630 check_insn(env
, ctx
, ISA_MIPS32R2
);
3631 gen_helper_mtc0_ebase(t0
);
3641 gen_helper_mtc0_config0(t0
);
3643 /* Stop translation as we may have switched the execution mode */
3644 ctx
->bstate
= BS_STOP
;
3647 /* ignored, read only */
3651 gen_helper_mtc0_config2(t0
);
3653 /* Stop translation as we may have switched the execution mode */
3654 ctx
->bstate
= BS_STOP
;
3657 /* ignored, read only */
3660 /* 4,5 are reserved */
3661 /* 6,7 are implementation dependent */
3671 rn
= "Invalid config selector";
3688 gen_helper_1i(mtc0_watchlo
, t0
, sel
);
3698 gen_helper_1i(mtc0_watchhi
, t0
, sel
);
3708 #if defined(TARGET_MIPS64)
3709 check_insn(env
, ctx
, ISA_MIPS3
);
3710 gen_helper_mtc0_xcontext(t0
);
3719 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3722 gen_helper_mtc0_framemask(t0
);
3731 rn
= "Diagnostic"; /* implementation dependent */
3736 gen_helper_mtc0_debug(t0
); /* EJTAG support */
3737 /* BS_STOP isn't good enough here, hflags may have changed. */
3738 gen_save_pc(ctx
->pc
+ 4);
3739 ctx
->bstate
= BS_EXCP
;
3743 // gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
3744 rn
= "TraceControl";
3745 /* Stop translation as we may have switched the execution mode */
3746 ctx
->bstate
= BS_STOP
;
3749 // gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
3750 rn
= "TraceControl2";
3751 /* Stop translation as we may have switched the execution mode */
3752 ctx
->bstate
= BS_STOP
;
3755 /* Stop translation as we may have switched the execution mode */
3756 ctx
->bstate
= BS_STOP
;
3757 // gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
3758 rn
= "UserTraceData";
3759 /* Stop translation as we may have switched the execution mode */
3760 ctx
->bstate
= BS_STOP
;
3763 // gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
3764 /* Stop translation as we may have switched the execution mode */
3765 ctx
->bstate
= BS_STOP
;
3776 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_DEPC
));
3786 gen_helper_mtc0_performance0(t0
);
3787 rn
= "Performance0";
3790 // gen_helper_mtc0_performance1(t0);
3791 rn
= "Performance1";
3794 // gen_helper_mtc0_performance2(t0);
3795 rn
= "Performance2";
3798 // gen_helper_mtc0_performance3(t0);
3799 rn
= "Performance3";
3802 // gen_helper_mtc0_performance4(t0);
3803 rn
= "Performance4";
3806 // gen_helper_mtc0_performance5(t0);
3807 rn
= "Performance5";
3810 // gen_helper_mtc0_performance6(t0);
3811 rn
= "Performance6";
3814 // gen_helper_mtc0_performance7(t0);
3815 rn
= "Performance7";
3841 gen_helper_mtc0_taglo(t0
);
3848 gen_helper_mtc0_datalo(t0
);
3861 gen_helper_mtc0_taghi(t0
);
3868 gen_helper_mtc0_datahi(t0
);
3879 gen_mtc0_store64(t0
, offsetof(CPUState
, CP0_ErrorEPC
));
3890 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
3896 /* Stop translation as we may have switched the execution mode */
3897 ctx
->bstate
= BS_STOP
;
3902 #if defined MIPS_DEBUG_DISAS
3903 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3904 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3908 /* For simplicity assume that all writes can cause interrupts. */
3911 ctx
->bstate
= BS_STOP
;
3916 #if defined MIPS_DEBUG_DISAS
3917 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3918 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3922 generate_exception(ctx
, EXCP_RI
);
3925 #if defined(TARGET_MIPS64)
3926 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
3928 const char *rn
= "invalid";
3931 check_insn(env
, ctx
, ISA_MIPS64
);
3937 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Index
));
3941 check_insn(env
, ctx
, ASE_MT
);
3942 gen_helper_mfc0_mvpcontrol(t0
);
3946 check_insn(env
, ctx
, ASE_MT
);
3947 gen_helper_mfc0_mvpconf0(t0
);
3951 check_insn(env
, ctx
, ASE_MT
);
3952 gen_helper_mfc0_mvpconf1(t0
);
3962 gen_helper_mfc0_random(t0
);
3966 check_insn(env
, ctx
, ASE_MT
);
3967 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEControl
));
3971 check_insn(env
, ctx
, ASE_MT
);
3972 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf0
));
3976 check_insn(env
, ctx
, ASE_MT
);
3977 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEConf1
));
3981 check_insn(env
, ctx
, ASE_MT
);
3982 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
3986 check_insn(env
, ctx
, ASE_MT
);
3987 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
3991 check_insn(env
, ctx
, ASE_MT
);
3992 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
3993 rn
= "VPEScheFBack";
3996 check_insn(env
, ctx
, ASE_MT
);
3997 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_VPEOpt
));
4007 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4011 check_insn(env
, ctx
, ASE_MT
);
4012 gen_helper_mfc0_tcstatus(t0
);
4016 check_insn(env
, ctx
, ASE_MT
);
4017 gen_helper_mfc0_tcbind(t0
);
4021 check_insn(env
, ctx
, ASE_MT
);
4022 gen_helper_dmfc0_tcrestart(t0
);
4026 check_insn(env
, ctx
, ASE_MT
);
4027 gen_helper_dmfc0_tchalt(t0
);
4031 check_insn(env
, ctx
, ASE_MT
);
4032 gen_helper_dmfc0_tccontext(t0
);
4036 check_insn(env
, ctx
, ASE_MT
);
4037 gen_helper_dmfc0_tcschedule(t0
);
4041 check_insn(env
, ctx
, ASE_MT
);
4042 gen_helper_dmfc0_tcschefback(t0
);
4052 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4062 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4066 // gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
4067 rn
= "ContextConfig";
4076 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageMask
));
4080 check_insn(env
, ctx
, ISA_MIPS32R2
);
4081 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PageGrain
));
4091 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Wired
));
4095 check_insn(env
, ctx
, ISA_MIPS32R2
);
4096 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf0
));
4100 check_insn(env
, ctx
, ISA_MIPS32R2
);
4101 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf1
));
4105 check_insn(env
, ctx
, ISA_MIPS32R2
);
4106 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf2
));
4110 check_insn(env
, ctx
, ISA_MIPS32R2
);
4111 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf3
));
4115 check_insn(env
, ctx
, ISA_MIPS32R2
);
4116 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSConf4
));
4126 check_insn(env
, ctx
, ISA_MIPS32R2
);
4127 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_HWREna
));
4137 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4147 /* Mark as an IO operation because we read the time. */
4150 gen_helper_mfc0_count(t0
);
4153 ctx
->bstate
= BS_STOP
;
4157 /* 6,7 are implementation dependent */
4165 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4175 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Compare
));
4178 /* 6,7 are implementation dependent */
4186 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Status
));
4190 check_insn(env
, ctx
, ISA_MIPS32R2
);
4191 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_IntCtl
));
4195 check_insn(env
, ctx
, ISA_MIPS32R2
);
4196 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSCtl
));
4200 check_insn(env
, ctx
, ISA_MIPS32R2
);
4201 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4211 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Cause
));
4221 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4231 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_PRid
));
4235 check_insn(env
, ctx
, ISA_MIPS32R2
);
4236 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_EBase
));
4246 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config0
));
4250 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config1
));
4254 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config2
));
4258 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config3
));
4261 /* 6,7 are implementation dependent */
4263 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config6
));
4267 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Config7
));
4277 gen_helper_dmfc0_lladdr(t0
);
4287 gen_helper_1i(dmfc0_watchlo
, t0
, sel
);
4297 gen_helper_1i(mfc0_watchhi
, t0
, sel
);
4307 check_insn(env
, ctx
, ISA_MIPS3
);
4308 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4316 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4319 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Framemask
));
4327 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4328 rn
= "'Diagnostic"; /* implementation dependent */
4333 gen_helper_mfc0_debug(t0
); /* EJTAG support */
4337 // gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
4338 rn
= "TraceControl";
4341 // gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
4342 rn
= "TraceControl2";
4345 // gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
4346 rn
= "UserTraceData";
4349 // gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
4360 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4370 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_Performance0
));
4371 rn
= "Performance0";
4374 // gen_helper_dmfc0_performance1(t0);
4375 rn
= "Performance1";
4378 // gen_helper_dmfc0_performance2(t0);
4379 rn
= "Performance2";
4382 // gen_helper_dmfc0_performance3(t0);
4383 rn
= "Performance3";
4386 // gen_helper_dmfc0_performance4(t0);
4387 rn
= "Performance4";
4390 // gen_helper_dmfc0_performance5(t0);
4391 rn
= "Performance5";
4394 // gen_helper_dmfc0_performance6(t0);
4395 rn
= "Performance6";
4398 // gen_helper_dmfc0_performance7(t0);
4399 rn
= "Performance7";
4406 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4413 tcg_gen_movi_tl(t0
, 0); /* unimplemented */
4426 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagLo
));
4433 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataLo
));
4446 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_TagHi
));
4453 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DataHi
));
4463 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4474 gen_mfc0_load32(t0
, offsetof(CPUState
, CP0_DESAVE
));
4484 #if defined MIPS_DEBUG_DISAS
4485 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4486 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4493 #if defined MIPS_DEBUG_DISAS
4494 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4495 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
4499 generate_exception(ctx
, EXCP_RI
);
4502 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv t0
, int reg
, int sel
)
4504 const char *rn
= "invalid";
4507 check_insn(env
, ctx
, ISA_MIPS64
);
4516 gen_helper_mtc0_index(t0
);
4520 check_insn(env
, ctx
, ASE_MT
);
4521 gen_helper_mtc0_mvpcontrol(t0
);
4525 check_insn(env
, ctx
, ASE_MT
);
4530 check_insn(env
, ctx
, ASE_MT
);
4545 check_insn(env
, ctx
, ASE_MT
);
4546 gen_helper_mtc0_vpecontrol(t0
);
4550 check_insn(env
, ctx
, ASE_MT
);
4551 gen_helper_mtc0_vpeconf0(t0
);
4555 check_insn(env
, ctx
, ASE_MT
);
4556 gen_helper_mtc0_vpeconf1(t0
);
4560 check_insn(env
, ctx
, ASE_MT
);
4561 gen_helper_mtc0_yqmask(t0
);
4565 check_insn(env
, ctx
, ASE_MT
);
4566 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4570 check_insn(env
, ctx
, ASE_MT
);
4571 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4572 rn
= "VPEScheFBack";
4575 check_insn(env
, ctx
, ASE_MT
);
4576 gen_helper_mtc0_vpeopt(t0
);
4586 gen_helper_mtc0_entrylo0(t0
);
4590 check_insn(env
, ctx
, ASE_MT
);
4591 gen_helper_mtc0_tcstatus(t0
);
4595 check_insn(env
, ctx
, ASE_MT
);
4596 gen_helper_mtc0_tcbind(t0
);
4600 check_insn(env
, ctx
, ASE_MT
);
4601 gen_helper_mtc0_tcrestart(t0
);
4605 check_insn(env
, ctx
, ASE_MT
);
4606 gen_helper_mtc0_tchalt(t0
);
4610 check_insn(env
, ctx
, ASE_MT
);
4611 gen_helper_mtc0_tccontext(t0
);
4615 check_insn(env
, ctx
, ASE_MT
);
4616 gen_helper_mtc0_tcschedule(t0
);
4620 check_insn(env
, ctx
, ASE_MT
);
4621 gen_helper_mtc0_tcschefback(t0
);
4631 gen_helper_mtc0_entrylo1(t0
);
4641 gen_helper_mtc0_context(t0
);
4645 // gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
4646 rn
= "ContextConfig";
4655 gen_helper_mtc0_pagemask(t0
);
4659 check_insn(env
, ctx
, ISA_MIPS32R2
);
4660 gen_helper_mtc0_pagegrain(t0
);
4670 gen_helper_mtc0_wired(t0
);
4674 check_insn(env
, ctx
, ISA_MIPS32R2
);
4675 gen_helper_mtc0_srsconf0(t0
);
4679 check_insn(env
, ctx
, ISA_MIPS32R2
);
4680 gen_helper_mtc0_srsconf1(t0
);
4684 check_insn(env
, ctx
, ISA_MIPS32R2
);
4685 gen_helper_mtc0_srsconf2(t0
);
4689 check_insn(env
, ctx
, ISA_MIPS32R2
);
4690 gen_helper_mtc0_srsconf3(t0
);
4694 check_insn(env
, ctx
, ISA_MIPS32R2
);
4695 gen_helper_mtc0_srsconf4(t0
);
4705 check_insn(env
, ctx
, ISA_MIPS32R2
);
4706 gen_helper_mtc0_hwrena(t0
);
4720 gen_helper_mtc0_count(t0
);
4723 /* 6,7 are implementation dependent */
4727 /* Stop translation as we may have switched the execution mode */
4728 ctx
->bstate
= BS_STOP
;
4733 gen_helper_mtc0_entryhi(t0
);
4743 gen_helper_mtc0_compare(t0
);
4746 /* 6,7 are implementation dependent */
4750 /* Stop translation as we may have switched the execution mode */
4751 ctx
->bstate
= BS_STOP
;
4756 gen_helper_mtc0_status(t0
);
4757 /* BS_STOP isn't good enough here, hflags may have changed. */
4758 gen_save_pc(ctx
->pc
+ 4);
4759 ctx
->bstate
= BS_EXCP
;
4763 check_insn(env
, ctx
, ISA_MIPS32R2
);
4764 gen_helper_mtc0_intctl(t0
);
4765 /* Stop translation as we may have switched the execution mode */
4766 ctx
->bstate
= BS_STOP
;
4770 check_insn(env
, ctx
, ISA_MIPS32R2
);
4771 gen_helper_mtc0_srsctl(t0
);
4772 /* Stop translation as we may have switched the execution mode */
4773 ctx
->bstate
= BS_STOP
;
4777 check_insn(env
, ctx
, ISA_MIPS32R2
);
4778 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_SRSMap
));
4779 /* Stop translation as we may have switched the execution mode */
4780 ctx
->bstate
= BS_STOP
;
4790 gen_helper_mtc0_cause(t0
);
4796 /* Stop translation as we may have switched the execution mode */
4797 ctx
->bstate
= BS_STOP
;
4802 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4816 check_insn(env
, ctx
, ISA_MIPS32R2
);
4817 gen_helper_mtc0_ebase(t0
);
4827 gen_helper_mtc0_config0(t0
);
4829 /* Stop translation as we may have switched the execution mode */
4830 ctx
->bstate
= BS_STOP
;
4837 gen_helper_mtc0_config2(t0
);
4839 /* Stop translation as we may have switched the execution mode */
4840 ctx
->bstate
= BS_STOP
;
4846 /* 6,7 are implementation dependent */
4848 rn
= "Invalid config selector";
4865 gen_helper_1i(mtc0_watchlo
, t0
, sel
);
4875 gen_helper_1i(mtc0_watchhi
, t0
, sel
);
4885 check_insn(env
, ctx
, ISA_MIPS3
);
4886 gen_helper_mtc0_xcontext(t0
);
4894 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4897 gen_helper_mtc0_framemask(t0
);
4906 rn
= "Diagnostic"; /* implementation dependent */
4911 gen_helper_mtc0_debug(t0
); /* EJTAG support */
4912 /* BS_STOP isn't good enough here, hflags may have changed. */
4913 gen_save_pc(ctx
->pc
+ 4);
4914 ctx
->bstate
= BS_EXCP
;
4918 // gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
4919 /* Stop translation as we may have switched the execution mode */
4920 ctx
->bstate
= BS_STOP
;
4921 rn
= "TraceControl";
4924 // gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
4925 /* Stop translation as we may have switched the execution mode */
4926 ctx
->bstate
= BS_STOP
;
4927 rn
= "TraceControl2";
4930 // gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
4931 /* Stop translation as we may have switched the execution mode */
4932 ctx
->bstate
= BS_STOP
;
4933 rn
= "UserTraceData";
4936 // gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
4937 /* Stop translation as we may have switched the execution mode */
4938 ctx
->bstate
= BS_STOP
;
4949 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4959 gen_helper_mtc0_performance0(t0
);
4960 rn
= "Performance0";
4963 // gen_helper_mtc0_performance1(t0);
4964 rn
= "Performance1";
4967 // gen_helper_mtc0_performance2(t0);
4968 rn
= "Performance2";
4971 // gen_helper_mtc0_performance3(t0);
4972 rn
= "Performance3";
4975 // gen_helper_mtc0_performance4(t0);
4976 rn
= "Performance4";
4979 // gen_helper_mtc0_performance5(t0);
4980 rn
= "Performance5";
4983 // gen_helper_mtc0_performance6(t0);
4984 rn
= "Performance6";
4987 // gen_helper_mtc0_performance7(t0);
4988 rn
= "Performance7";
5014 gen_helper_mtc0_taglo(t0
);
5021 gen_helper_mtc0_datalo(t0
);
5034 gen_helper_mtc0_taghi(t0
);
5041 gen_helper_mtc0_datahi(t0
);
5052 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5063 gen_mtc0_store32(t0
, offsetof(CPUState
, CP0_DESAVE
));
5069 /* Stop translation as we may have switched the execution mode */
5070 ctx
->bstate
= BS_STOP
;
5075 #if defined MIPS_DEBUG_DISAS
5076 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5077 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5081 /* For simplicity assume that all writes can cause interrupts. */
5084 ctx
->bstate
= BS_STOP
;
5089 #if defined MIPS_DEBUG_DISAS
5090 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5091 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
5095 generate_exception(ctx
, EXCP_RI
);
5097 #endif /* TARGET_MIPS64 */
5099 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5100 int u
, int sel
, int h
)
5102 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5103 TCGv t0
= tcg_temp_local_new();
5105 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5106 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5107 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5108 tcg_gen_movi_tl(t0
, -1);
5109 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5110 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5111 tcg_gen_movi_tl(t0
, -1);
5117 gen_helper_mftc0_tcstatus(t0
);
5120 gen_helper_mftc0_tcbind(t0
);
5123 gen_helper_mftc0_tcrestart(t0
);
5126 gen_helper_mftc0_tchalt(t0
);
5129 gen_helper_mftc0_tccontext(t0
);
5132 gen_helper_mftc0_tcschedule(t0
);
5135 gen_helper_mftc0_tcschefback(t0
);
5138 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5145 gen_helper_mftc0_entryhi(t0
);
5148 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5154 gen_helper_mftc0_status(t0
);
5157 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5163 gen_helper_mftc0_debug(t0
);
5166 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5171 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5173 } else switch (sel
) {
5174 /* GPR registers. */
5176 gen_helper_1i(mftgpr
, t0
, rt
);
5178 /* Auxiliary CPU registers */
5182 gen_helper_1i(mftlo
, t0
, 0);
5185 gen_helper_1i(mfthi
, t0
, 0);
5188 gen_helper_1i(mftacx
, t0
, 0);
5191 gen_helper_1i(mftlo
, t0
, 1);
5194 gen_helper_1i(mfthi
, t0
, 1);
5197 gen_helper_1i(mftacx
, t0
, 1);
5200 gen_helper_1i(mftlo
, t0
, 2);
5203 gen_helper_1i(mfthi
, t0
, 2);
5206 gen_helper_1i(mftacx
, t0
, 2);
5209 gen_helper_1i(mftlo
, t0
, 3);
5212 gen_helper_1i(mfthi
, t0
, 3);
5215 gen_helper_1i(mftacx
, t0
, 3);
5218 gen_helper_mftdsp(t0
);
5224 /* Floating point (COP1). */
5226 /* XXX: For now we support only a single FPU context. */
5228 TCGv_i32 fp0
= tcg_temp_new_i32();
5230 gen_load_fpr32(fp0
, rt
);
5231 tcg_gen_ext_i32_tl(t0
, fp0
);
5232 tcg_temp_free_i32(fp0
);
5234 TCGv_i32 fp0
= tcg_temp_new_i32();
5236 gen_load_fpr32h(fp0
, rt
);
5237 tcg_gen_ext_i32_tl(t0
, fp0
);
5238 tcg_temp_free_i32(fp0
);
5242 /* XXX: For now we support only a single FPU context. */
5243 gen_helper_1i(cfc1
, t0
, rt
);
5245 /* COP2: Not implemented. */
5252 #if defined MIPS_DEBUG_DISAS
5253 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5254 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5258 gen_store_gpr(t0
, rd
);
5264 #if defined MIPS_DEBUG_DISAS
5265 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5266 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
5270 generate_exception(ctx
, EXCP_RI
);
5273 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5274 int u
, int sel
, int h
)
5276 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5277 TCGv t0
= tcg_temp_local_new();
5279 gen_load_gpr(t0
, rt
);
5280 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5281 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5282 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5284 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5285 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5292 gen_helper_mttc0_tcstatus(t0
);
5295 gen_helper_mttc0_tcbind(t0
);
5298 gen_helper_mttc0_tcrestart(t0
);
5301 gen_helper_mttc0_tchalt(t0
);
5304 gen_helper_mttc0_tccontext(t0
);
5307 gen_helper_mttc0_tcschedule(t0
);
5310 gen_helper_mttc0_tcschefback(t0
);
5313 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5320 gen_helper_mttc0_entryhi(t0
);
5323 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5329 gen_helper_mttc0_status(t0
);
5332 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5338 gen_helper_mttc0_debug(t0
);
5341 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5346 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5348 } else switch (sel
) {
5349 /* GPR registers. */
5351 gen_helper_1i(mttgpr
, t0
, rd
);
5353 /* Auxiliary CPU registers */
5357 gen_helper_1i(mttlo
, t0
, 0);
5360 gen_helper_1i(mtthi
, t0
, 0);
5363 gen_helper_1i(mttacx
, t0
, 0);
5366 gen_helper_1i(mttlo
, t0
, 1);
5369 gen_helper_1i(mtthi
, t0
, 1);
5372 gen_helper_1i(mttacx
, t0
, 1);
5375 gen_helper_1i(mttlo
, t0
, 2);
5378 gen_helper_1i(mtthi
, t0
, 2);
5381 gen_helper_1i(mttacx
, t0
, 2);
5384 gen_helper_1i(mttlo
, t0
, 3);
5387 gen_helper_1i(mtthi
, t0
, 3);
5390 gen_helper_1i(mttacx
, t0
, 3);
5393 gen_helper_mttdsp(t0
);
5399 /* Floating point (COP1). */
5401 /* XXX: For now we support only a single FPU context. */
5403 TCGv_i32 fp0
= tcg_temp_new_i32();
5405 tcg_gen_trunc_tl_i32(fp0
, t0
);
5406 gen_store_fpr32(fp0
, rd
);
5407 tcg_temp_free_i32(fp0
);
5409 TCGv_i32 fp0
= tcg_temp_new_i32();
5411 tcg_gen_trunc_tl_i32(fp0
, t0
);
5412 gen_store_fpr32h(fp0
, rd
);
5413 tcg_temp_free_i32(fp0
);
5417 /* XXX: For now we support only a single FPU context. */
5418 gen_helper_1i(ctc1
, t0
, rd
);
5420 /* COP2: Not implemented. */
5427 #if defined MIPS_DEBUG_DISAS
5428 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5429 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5438 #if defined MIPS_DEBUG_DISAS
5439 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5440 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
5444 generate_exception(ctx
, EXCP_RI
);
5447 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5449 const char *opn
= "ldst";
5458 TCGv t0
= tcg_temp_local_new();
5460 gen_mfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5461 gen_store_gpr(t0
, rt
);
5468 TCGv t0
= tcg_temp_local_new();
5470 gen_load_gpr(t0
, rt
);
5471 save_cpu_state(ctx
, 1);
5472 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5477 #if defined(TARGET_MIPS64)
5479 check_insn(env
, ctx
, ISA_MIPS3
);
5485 TCGv t0
= tcg_temp_local_new();
5487 gen_dmfc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5488 gen_store_gpr(t0
, rt
);
5494 check_insn(env
, ctx
, ISA_MIPS3
);
5496 TCGv t0
= tcg_temp_local_new();
5498 gen_load_gpr(t0
, rt
);
5499 save_cpu_state(ctx
, 1);
5500 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5507 check_insn(env
, ctx
, ASE_MT
);
5512 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5513 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5517 check_insn(env
, ctx
, ASE_MT
);
5518 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5519 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5524 if (!env
->tlb
->do_tlbwi
)
5530 if (!env
->tlb
->do_tlbwr
)
5536 if (!env
->tlb
->do_tlbp
)
5542 if (!env
->tlb
->do_tlbr
)
5548 check_insn(env
, ctx
, ISA_MIPS2
);
5549 save_cpu_state(ctx
, 1);
5551 ctx
->bstate
= BS_EXCP
;
5555 check_insn(env
, ctx
, ISA_MIPS32
);
5556 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5558 generate_exception(ctx
, EXCP_RI
);
5560 save_cpu_state(ctx
, 1);
5562 ctx
->bstate
= BS_EXCP
;
5567 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5568 /* If we get an exception, we want to restart at next instruction */
5570 save_cpu_state(ctx
, 1);
5573 ctx
->bstate
= BS_EXCP
;
5578 generate_exception(ctx
, EXCP_RI
);
5581 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5583 #endif /* !CONFIG_USER_ONLY */
5585 /* CP1 Branches (before delay slot) */
5586 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5587 int32_t cc
, int32_t offset
)
5589 target_ulong btarget
;
5590 const char *opn
= "cp1 cond branch";
5591 TCGv_i32 t0
= tcg_temp_new_i32();
5594 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5596 btarget
= ctx
->pc
+ 4 + offset
;
5601 int l1
= gen_new_label();
5602 int l2
= gen_new_label();
5605 tcg_gen_andi_i32(t0
, t0
, 0x1 << cc
);
5606 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
5607 tcg_gen_movi_i32(bcond
, 0);
5610 tcg_gen_movi_i32(bcond
, 1);
5617 int l1
= gen_new_label();
5618 int l2
= gen_new_label();
5621 tcg_gen_andi_i32(t0
, t0
, 0x1 << cc
);
5622 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
5623 tcg_gen_movi_i32(bcond
, 0);
5626 tcg_gen_movi_i32(bcond
, 1);
5633 int l1
= gen_new_label();
5634 int l2
= gen_new_label();
5637 tcg_gen_andi_i32(t0
, t0
, 0x1 << cc
);
5638 tcg_gen_brcondi_i32(TCG_COND_NE
, t0
, 0, l1
);
5639 tcg_gen_movi_i32(bcond
, 0);
5642 tcg_gen_movi_i32(bcond
, 1);
5649 int l1
= gen_new_label();
5650 int l2
= gen_new_label();
5653 tcg_gen_andi_i32(t0
, t0
, 0x1 << cc
);
5654 tcg_gen_brcondi_i32(TCG_COND_NE
, t0
, 0, l1
);
5655 tcg_gen_movi_i32(bcond
, 0);
5658 tcg_gen_movi_i32(bcond
, 1);
5663 ctx
->hflags
|= MIPS_HFLAG_BL
;
5667 int l1
= gen_new_label();
5668 int l2
= gen_new_label();
5671 tcg_gen_andi_i32(t0
, t0
, 0x3 << cc
);
5672 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
5673 tcg_gen_movi_i32(bcond
, 0);
5676 tcg_gen_movi_i32(bcond
, 1);
5683 int l1
= gen_new_label();
5684 int l2
= gen_new_label();
5687 tcg_gen_andi_i32(t0
, t0
, 0x3 << cc
);
5688 tcg_gen_brcondi_i32(TCG_COND_NE
, t0
, 0, l1
);
5689 tcg_gen_movi_i32(bcond
, 0);
5692 tcg_gen_movi_i32(bcond
, 1);
5699 int l1
= gen_new_label();
5700 int l2
= gen_new_label();
5703 tcg_gen_andi_i32(t0
, t0
, 0xf << cc
);
5704 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
5705 tcg_gen_movi_i32(bcond
, 0);
5708 tcg_gen_movi_i32(bcond
, 1);
5715 int l1
= gen_new_label();
5716 int l2
= gen_new_label();
5719 tcg_gen_andi_i32(t0
, t0
, 0xf << cc
);
5720 tcg_gen_brcondi_i32(TCG_COND_NE
, t0
, 0, l1
);
5721 tcg_gen_movi_i32(bcond
, 0);
5724 tcg_gen_movi_i32(bcond
, 1);
5729 ctx
->hflags
|= MIPS_HFLAG_BC
;
5733 generate_exception (ctx
, EXCP_RI
);
5736 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5737 ctx
->hflags
, btarget
);
5738 ctx
->btarget
= btarget
;
5741 tcg_temp_free_i32(t0
);
5744 /* Coprocessor 1 (FPU) */
5746 #define FOP(func, fmt) (((fmt) << 21) | (func))
5748 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5750 const char *opn
= "cp1 move";
5751 TCGv t0
= tcg_temp_local_new();
5756 TCGv_i32 fp0
= tcg_temp_new_i32();
5758 gen_load_fpr32(fp0
, fs
);
5759 tcg_gen_ext_i32_tl(t0
, fp0
);
5760 tcg_temp_free_i32(fp0
);
5762 gen_store_gpr(t0
, rt
);
5766 gen_load_gpr(t0
, rt
);
5768 TCGv_i32 fp0
= tcg_temp_new_i32();
5770 tcg_gen_trunc_tl_i32(fp0
, t0
);
5771 gen_store_fpr32(fp0
, fs
);
5772 tcg_temp_free_i32(fp0
);
5777 gen_helper_1i(cfc1
, t0
, fs
);
5778 gen_store_gpr(t0
, rt
);
5782 gen_load_gpr(t0
, rt
);
5783 gen_helper_1i(ctc1
, t0
, fs
);
5788 TCGv_i64 fp0
= tcg_temp_new_i64();
5790 gen_load_fpr64(ctx
, fp0
, fs
);
5791 tcg_gen_trunc_i64_tl(t0
, fp0
);
5792 tcg_temp_free_i64(fp0
);
5794 gen_store_gpr(t0
, rt
);
5798 gen_load_gpr(t0
, rt
);
5800 TCGv_i64 fp0
= tcg_temp_new_i64();
5802 tcg_gen_extu_tl_i64(fp0
, t0
);
5803 gen_store_fpr64(ctx
, fp0
, fs
);
5804 tcg_temp_free_i64(fp0
);
5810 TCGv_i32 fp0
= tcg_temp_new_i32();
5812 gen_load_fpr32h(fp0
, fs
);
5813 tcg_gen_ext_i32_tl(t0
, fp0
);
5814 tcg_temp_free_i32(fp0
);
5816 gen_store_gpr(t0
, rt
);
5820 gen_load_gpr(t0
, rt
);
5822 TCGv_i32 fp0
= tcg_temp_new_i32();
5824 tcg_gen_trunc_tl_i32(fp0
, t0
);
5825 gen_store_fpr32h(fp0
, fs
);
5826 tcg_temp_free_i32(fp0
);
5832 generate_exception (ctx
, EXCP_RI
);
5835 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5841 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5843 int l1
= gen_new_label();
5846 TCGv t0
= tcg_temp_local_new();
5847 TCGv_i32 r_tmp
= tcg_temp_new_i32();
5850 ccbit
= 1 << (24 + cc
);
5858 gen_load_gpr(t0
, rd
);
5859 tcg_gen_andi_i32(r_tmp
, fpu_fcr31
, ccbit
);
5860 tcg_gen_brcondi_i32(cond
, r_tmp
, 0, l1
);
5861 tcg_temp_free_i32(r_tmp
);
5862 gen_load_gpr(t0
, rs
);
5864 gen_store_gpr(t0
, rd
);
5868 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5872 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
5873 TCGv_i32 fp0
= tcg_temp_local_new_i32();
5874 int l1
= gen_new_label();
5877 ccbit
= 1 << (24 + cc
);
5886 gen_load_fpr32(fp0
, fd
);
5887 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
5888 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
5889 tcg_temp_free_i32(r_tmp1
);
5890 gen_load_fpr32(fp0
, fs
);
5892 gen_store_fpr32(fp0
, fd
);
5893 tcg_temp_free_i32(fp0
);
5896 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5900 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
5901 TCGv_i64 fp0
= tcg_temp_local_new_i64();
5902 int l1
= gen_new_label();
5905 ccbit
= 1 << (24 + cc
);
5914 gen_load_fpr64(ctx
, fp0
, fd
);
5915 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit
);
5916 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
5917 tcg_temp_free_i32(r_tmp1
);
5918 gen_load_fpr64(ctx
, fp0
, fs
);
5920 gen_store_fpr64(ctx
, fp0
, fd
);
5921 tcg_temp_free_i64(fp0
);
5924 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5926 uint32_t ccbit1
, ccbit2
;
5928 TCGv_i32 r_tmp1
= tcg_temp_new_i32();
5929 TCGv_i32 fp0
= tcg_temp_local_new_i32();
5930 int l1
= gen_new_label();
5931 int l2
= gen_new_label();
5934 ccbit1
= 1 << (24 + cc
);
5935 ccbit2
= 1 << (25 + cc
);
5946 gen_load_fpr32(fp0
, fd
);
5947 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit1
);
5948 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l1
);
5949 gen_load_fpr32(fp0
, fs
);
5951 gen_store_fpr32(fp0
, fd
);
5953 gen_load_fpr32h(fp0
, fd
);
5954 tcg_gen_andi_i32(r_tmp1
, fpu_fcr31
, ccbit2
);
5955 tcg_gen_brcondi_i32(cond
, r_tmp1
, 0, l2
);
5956 gen_load_fpr32h(fp0
, fs
);
5958 gen_store_fpr32h(fp0
, fd
);
5960 tcg_temp_free_i32(r_tmp1
);
5961 tcg_temp_free_i32(fp0
);
5965 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5966 int ft
, int fs
, int fd
, int cc
)
5968 const char *opn
= "farith";
5969 const char *condnames
[] = {
5987 const char *condnames_abs
[] = {
6005 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6006 uint32_t func
= ctx
->opcode
& 0x3f;
6008 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6011 TCGv_i32 fp0
= tcg_temp_new_i32();
6012 TCGv_i32 fp1
= tcg_temp_new_i32();
6014 gen_load_fpr32(fp0
, fs
);
6015 gen_load_fpr32(fp1
, ft
);
6016 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6017 tcg_temp_free_i32(fp1
);
6018 gen_store_fpr32(fp0
, fd
);
6019 tcg_temp_free_i32(fp0
);
6026 TCGv_i32 fp0
= tcg_temp_new_i32();
6027 TCGv_i32 fp1
= tcg_temp_new_i32();
6029 gen_load_fpr32(fp0
, fs
);
6030 gen_load_fpr32(fp1
, ft
);
6031 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6032 tcg_temp_free_i32(fp1
);
6033 gen_store_fpr32(fp0
, fd
);
6034 tcg_temp_free_i32(fp0
);
6041 TCGv_i32 fp0
= tcg_temp_new_i32();
6042 TCGv_i32 fp1
= tcg_temp_new_i32();
6044 gen_load_fpr32(fp0
, fs
);
6045 gen_load_fpr32(fp1
, ft
);
6046 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6047 tcg_temp_free_i32(fp1
);
6048 gen_store_fpr32(fp0
, fd
);
6049 tcg_temp_free_i32(fp0
);
6056 TCGv_i32 fp0
= tcg_temp_new_i32();
6057 TCGv_i32 fp1
= tcg_temp_new_i32();
6059 gen_load_fpr32(fp0
, fs
);
6060 gen_load_fpr32(fp1
, ft
);
6061 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6062 tcg_temp_free_i32(fp1
);
6063 gen_store_fpr32(fp0
, fd
);
6064 tcg_temp_free_i32(fp0
);
6071 TCGv_i32 fp0
= tcg_temp_new_i32();
6073 gen_load_fpr32(fp0
, fs
);
6074 gen_helper_float_sqrt_s(fp0
, fp0
);
6075 gen_store_fpr32(fp0
, fd
);
6076 tcg_temp_free_i32(fp0
);
6082 TCGv_i32 fp0
= tcg_temp_new_i32();
6084 gen_load_fpr32(fp0
, fs
);
6085 gen_helper_float_abs_s(fp0
, fp0
);
6086 gen_store_fpr32(fp0
, fd
);
6087 tcg_temp_free_i32(fp0
);
6093 TCGv_i32 fp0
= tcg_temp_new_i32();
6095 gen_load_fpr32(fp0
, fs
);
6096 gen_store_fpr32(fp0
, fd
);
6097 tcg_temp_free_i32(fp0
);
6103 TCGv_i32 fp0
= tcg_temp_new_i32();
6105 gen_load_fpr32(fp0
, fs
);
6106 gen_helper_float_chs_s(fp0
, fp0
);
6107 gen_store_fpr32(fp0
, fd
);
6108 tcg_temp_free_i32(fp0
);
6113 check_cp1_64bitmode(ctx
);
6115 TCGv_i32 fp32
= tcg_temp_new_i32();
6116 TCGv_i64 fp64
= tcg_temp_new_i64();
6118 gen_load_fpr32(fp32
, fs
);
6119 gen_helper_float_roundl_s(fp64
, fp32
);
6120 tcg_temp_free_i32(fp32
);
6121 gen_store_fpr64(ctx
, fp64
, fd
);
6122 tcg_temp_free_i64(fp64
);
6127 check_cp1_64bitmode(ctx
);
6129 TCGv_i32 fp32
= tcg_temp_new_i32();
6130 TCGv_i64 fp64
= tcg_temp_new_i64();
6132 gen_load_fpr32(fp32
, fs
);
6133 gen_helper_float_truncl_s(fp64
, fp32
);
6134 tcg_temp_free_i32(fp32
);
6135 gen_store_fpr64(ctx
, fp64
, fd
);
6136 tcg_temp_free_i64(fp64
);
6141 check_cp1_64bitmode(ctx
);
6143 TCGv_i32 fp32
= tcg_temp_new_i32();
6144 TCGv_i64 fp64
= tcg_temp_new_i64();
6146 gen_load_fpr32(fp32
, fs
);
6147 gen_helper_float_ceill_s(fp64
, fp32
);
6148 tcg_temp_free_i32(fp32
);
6149 gen_store_fpr64(ctx
, fp64
, fd
);
6150 tcg_temp_free_i64(fp64
);
6155 check_cp1_64bitmode(ctx
);
6157 TCGv_i32 fp32
= tcg_temp_new_i32();
6158 TCGv_i64 fp64
= tcg_temp_new_i64();
6160 gen_load_fpr32(fp32
, fs
);
6161 gen_helper_float_floorl_s(fp64
, fp32
);
6162 tcg_temp_free_i32(fp32
);
6163 gen_store_fpr64(ctx
, fp64
, fd
);
6164 tcg_temp_free_i64(fp64
);
6170 TCGv_i32 fp0
= tcg_temp_new_i32();
6172 gen_load_fpr32(fp0
, fs
);
6173 gen_helper_float_roundw_s(fp0
, fp0
);
6174 gen_store_fpr32(fp0
, fd
);
6175 tcg_temp_free_i32(fp0
);
6181 TCGv_i32 fp0
= tcg_temp_new_i32();
6183 gen_load_fpr32(fp0
, fs
);
6184 gen_helper_float_truncw_s(fp0
, fp0
);
6185 gen_store_fpr32(fp0
, fd
);
6186 tcg_temp_free_i32(fp0
);
6192 TCGv_i32 fp0
= tcg_temp_new_i32();
6194 gen_load_fpr32(fp0
, fs
);
6195 gen_helper_float_ceilw_s(fp0
, fp0
);
6196 gen_store_fpr32(fp0
, fd
);
6197 tcg_temp_free_i32(fp0
);
6203 TCGv_i32 fp0
= tcg_temp_new_i32();
6205 gen_load_fpr32(fp0
, fs
);
6206 gen_helper_float_floorw_s(fp0
, fp0
);
6207 gen_store_fpr32(fp0
, fd
);
6208 tcg_temp_free_i32(fp0
);
6213 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6218 int l1
= gen_new_label();
6219 TCGv t0
= tcg_temp_new();
6220 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6222 gen_load_gpr(t0
, ft
);
6223 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6224 gen_load_fpr32(fp0
, fs
);
6225 gen_store_fpr32(fp0
, fd
);
6226 tcg_temp_free_i32(fp0
);
6234 int l1
= gen_new_label();
6235 TCGv t0
= tcg_temp_new();
6236 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6238 gen_load_gpr(t0
, ft
);
6239 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6240 gen_load_fpr32(fp0
, fs
);
6241 gen_store_fpr32(fp0
, fd
);
6242 tcg_temp_free_i32(fp0
);
6251 TCGv_i32 fp0
= tcg_temp_new_i32();
6253 gen_load_fpr32(fp0
, fs
);
6254 gen_helper_float_recip_s(fp0
, fp0
);
6255 gen_store_fpr32(fp0
, fd
);
6256 tcg_temp_free_i32(fp0
);
6263 TCGv_i32 fp0
= tcg_temp_new_i32();
6265 gen_load_fpr32(fp0
, fs
);
6266 gen_helper_float_rsqrt_s(fp0
, fp0
);
6267 gen_store_fpr32(fp0
, fd
);
6268 tcg_temp_free_i32(fp0
);
6273 check_cp1_64bitmode(ctx
);
6275 TCGv_i32 fp0
= tcg_temp_new_i32();
6276 TCGv_i32 fp1
= tcg_temp_new_i32();
6278 gen_load_fpr32(fp0
, fs
);
6279 gen_load_fpr32(fp1
, fd
);
6280 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6281 tcg_temp_free_i32(fp1
);
6282 gen_store_fpr32(fp0
, fd
);
6283 tcg_temp_free_i32(fp0
);
6288 check_cp1_64bitmode(ctx
);
6290 TCGv_i32 fp0
= tcg_temp_new_i32();
6292 gen_load_fpr32(fp0
, fs
);
6293 gen_helper_float_recip1_s(fp0
, fp0
);
6294 gen_store_fpr32(fp0
, fd
);
6295 tcg_temp_free_i32(fp0
);
6300 check_cp1_64bitmode(ctx
);
6302 TCGv_i32 fp0
= tcg_temp_new_i32();
6304 gen_load_fpr32(fp0
, fs
);
6305 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6306 gen_store_fpr32(fp0
, fd
);
6307 tcg_temp_free_i32(fp0
);
6312 check_cp1_64bitmode(ctx
);
6314 TCGv_i32 fp0
= tcg_temp_new_i32();
6315 TCGv_i32 fp1
= tcg_temp_new_i32();
6317 gen_load_fpr32(fp0
, fs
);
6318 gen_load_fpr32(fp1
, ft
);
6319 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6320 tcg_temp_free_i32(fp1
);
6321 gen_store_fpr32(fp0
, fd
);
6322 tcg_temp_free_i32(fp0
);
6327 check_cp1_registers(ctx
, fd
);
6329 TCGv_i32 fp32
= tcg_temp_new_i32();
6330 TCGv_i64 fp64
= tcg_temp_new_i64();
6332 gen_load_fpr32(fp32
, fs
);
6333 gen_helper_float_cvtd_s(fp64
, fp32
);
6334 tcg_temp_free_i32(fp32
);
6335 gen_store_fpr64(ctx
, fp64
, fd
);
6336 tcg_temp_free_i64(fp64
);
6342 TCGv_i32 fp0
= tcg_temp_new_i32();
6344 gen_load_fpr32(fp0
, fs
);
6345 gen_helper_float_cvtw_s(fp0
, fp0
);
6346 gen_store_fpr32(fp0
, fd
);
6347 tcg_temp_free_i32(fp0
);
6352 check_cp1_64bitmode(ctx
);
6354 TCGv_i32 fp32
= tcg_temp_new_i32();
6355 TCGv_i64 fp64
= tcg_temp_new_i64();
6357 gen_load_fpr32(fp32
, fs
);
6358 gen_helper_float_cvtl_s(fp64
, fp32
);
6359 tcg_temp_free_i32(fp32
);
6360 gen_store_fpr64(ctx
, fp64
, fd
);
6361 tcg_temp_free_i64(fp64
);
6366 check_cp1_64bitmode(ctx
);
6368 TCGv_i64 fp64
= tcg_temp_new_i64();
6369 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6370 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6372 gen_load_fpr32(fp32_0
, fs
);
6373 gen_load_fpr32(fp32_1
, ft
);
6374 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6375 tcg_temp_free_i32(fp32_1
);
6376 tcg_temp_free_i32(fp32_0
);
6377 gen_store_fpr64(ctx
, fp64
, fd
);
6378 tcg_temp_free_i64(fp64
);
6399 TCGv_i32 fp0
= tcg_temp_new_i32();
6400 TCGv_i32 fp1
= tcg_temp_new_i32();
6402 gen_load_fpr32(fp0
, fs
);
6403 gen_load_fpr32(fp1
, ft
);
6404 if (ctx
->opcode
& (1 << 6)) {
6406 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6407 opn
= condnames_abs
[func
-48];
6409 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6410 opn
= condnames
[func
-48];
6412 tcg_temp_free_i32(fp0
);
6413 tcg_temp_free_i32(fp1
);
6417 check_cp1_registers(ctx
, fs
| ft
| fd
);
6419 TCGv_i64 fp0
= tcg_temp_new_i64();
6420 TCGv_i64 fp1
= tcg_temp_new_i64();
6422 gen_load_fpr64(ctx
, fp0
, fs
);
6423 gen_load_fpr64(ctx
, fp1
, ft
);
6424 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6425 tcg_temp_free_i64(fp1
);
6426 gen_store_fpr64(ctx
, fp0
, fd
);
6427 tcg_temp_free_i64(fp0
);
6433 check_cp1_registers(ctx
, fs
| ft
| fd
);
6435 TCGv_i64 fp0
= tcg_temp_new_i64();
6436 TCGv_i64 fp1
= tcg_temp_new_i64();
6438 gen_load_fpr64(ctx
, fp0
, fs
);
6439 gen_load_fpr64(ctx
, fp1
, ft
);
6440 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6441 tcg_temp_free_i64(fp1
);
6442 gen_store_fpr64(ctx
, fp0
, fd
);
6443 tcg_temp_free_i64(fp0
);
6449 check_cp1_registers(ctx
, fs
| ft
| fd
);
6451 TCGv_i64 fp0
= tcg_temp_new_i64();
6452 TCGv_i64 fp1
= tcg_temp_new_i64();
6454 gen_load_fpr64(ctx
, fp0
, fs
);
6455 gen_load_fpr64(ctx
, fp1
, ft
);
6456 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6457 tcg_temp_free_i64(fp1
);
6458 gen_store_fpr64(ctx
, fp0
, fd
);
6459 tcg_temp_free_i64(fp0
);
6465 check_cp1_registers(ctx
, fs
| ft
| fd
);
6467 TCGv_i64 fp0
= tcg_temp_new_i64();
6468 TCGv_i64 fp1
= tcg_temp_new_i64();
6470 gen_load_fpr64(ctx
, fp0
, fs
);
6471 gen_load_fpr64(ctx
, fp1
, ft
);
6472 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6473 tcg_temp_free_i64(fp1
);
6474 gen_store_fpr64(ctx
, fp0
, fd
);
6475 tcg_temp_free_i64(fp0
);
6481 check_cp1_registers(ctx
, fs
| fd
);
6483 TCGv_i64 fp0
= tcg_temp_new_i64();
6485 gen_load_fpr64(ctx
, fp0
, fs
);
6486 gen_helper_float_sqrt_d(fp0
, fp0
);
6487 gen_store_fpr64(ctx
, fp0
, fd
);
6488 tcg_temp_free_i64(fp0
);
6493 check_cp1_registers(ctx
, fs
| fd
);
6495 TCGv_i64 fp0
= tcg_temp_new_i64();
6497 gen_load_fpr64(ctx
, fp0
, fs
);
6498 gen_helper_float_abs_d(fp0
, fp0
);
6499 gen_store_fpr64(ctx
, fp0
, fd
);
6500 tcg_temp_free_i64(fp0
);
6505 check_cp1_registers(ctx
, fs
| fd
);
6507 TCGv_i64 fp0
= tcg_temp_new_i64();
6509 gen_load_fpr64(ctx
, fp0
, fs
);
6510 gen_store_fpr64(ctx
, fp0
, fd
);
6511 tcg_temp_free_i64(fp0
);
6516 check_cp1_registers(ctx
, fs
| fd
);
6518 TCGv_i64 fp0
= tcg_temp_new_i64();
6520 gen_load_fpr64(ctx
, fp0
, fs
);
6521 gen_helper_float_chs_d(fp0
, fp0
);
6522 gen_store_fpr64(ctx
, fp0
, fd
);
6523 tcg_temp_free_i64(fp0
);
6528 check_cp1_64bitmode(ctx
);
6530 TCGv_i64 fp0
= tcg_temp_new_i64();
6532 gen_load_fpr64(ctx
, fp0
, fs
);
6533 gen_helper_float_roundl_d(fp0
, fp0
);
6534 gen_store_fpr64(ctx
, fp0
, fd
);
6535 tcg_temp_free_i64(fp0
);
6540 check_cp1_64bitmode(ctx
);
6542 TCGv_i64 fp0
= tcg_temp_new_i64();
6544 gen_load_fpr64(ctx
, fp0
, fs
);
6545 gen_helper_float_truncl_d(fp0
, fp0
);
6546 gen_store_fpr64(ctx
, fp0
, fd
);
6547 tcg_temp_free_i64(fp0
);
6552 check_cp1_64bitmode(ctx
);
6554 TCGv_i64 fp0
= tcg_temp_new_i64();
6556 gen_load_fpr64(ctx
, fp0
, fs
);
6557 gen_helper_float_ceill_d(fp0
, fp0
);
6558 gen_store_fpr64(ctx
, fp0
, fd
);
6559 tcg_temp_free_i64(fp0
);
6564 check_cp1_64bitmode(ctx
);
6566 TCGv_i64 fp0
= tcg_temp_new_i64();
6568 gen_load_fpr64(ctx
, fp0
, fs
);
6569 gen_helper_float_floorl_d(fp0
, fp0
);
6570 gen_store_fpr64(ctx
, fp0
, fd
);
6571 tcg_temp_free_i64(fp0
);
6576 check_cp1_registers(ctx
, fs
);
6578 TCGv_i32 fp32
= tcg_temp_new_i32();
6579 TCGv_i64 fp64
= tcg_temp_new_i64();
6581 gen_load_fpr64(ctx
, fp64
, fs
);
6582 gen_helper_float_roundw_d(fp32
, fp64
);
6583 tcg_temp_free_i64(fp64
);
6584 gen_store_fpr32(fp32
, fd
);
6585 tcg_temp_free_i32(fp32
);
6590 check_cp1_registers(ctx
, fs
);
6592 TCGv_i32 fp32
= tcg_temp_new_i32();
6593 TCGv_i64 fp64
= tcg_temp_new_i64();
6595 gen_load_fpr64(ctx
, fp64
, fs
);
6596 gen_helper_float_truncw_d(fp32
, fp64
);
6597 tcg_temp_free_i64(fp64
);
6598 gen_store_fpr32(fp32
, fd
);
6599 tcg_temp_free_i32(fp32
);
6604 check_cp1_registers(ctx
, fs
);
6606 TCGv_i32 fp32
= tcg_temp_new_i32();
6607 TCGv_i64 fp64
= tcg_temp_new_i64();
6609 gen_load_fpr64(ctx
, fp64
, fs
);
6610 gen_helper_float_ceilw_d(fp32
, fp64
);
6611 tcg_temp_free_i64(fp64
);
6612 gen_store_fpr32(fp32
, fd
);
6613 tcg_temp_free_i32(fp32
);
6618 check_cp1_registers(ctx
, fs
);
6620 TCGv_i32 fp32
= tcg_temp_new_i32();
6621 TCGv_i64 fp64
= tcg_temp_new_i64();
6623 gen_load_fpr64(ctx
, fp64
, fs
);
6624 gen_helper_float_floorw_d(fp32
, fp64
);
6625 tcg_temp_free_i64(fp64
);
6626 gen_store_fpr32(fp32
, fd
);
6627 tcg_temp_free_i32(fp32
);
6632 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6637 int l1
= gen_new_label();
6638 TCGv t0
= tcg_temp_new();
6639 TCGv_i64 fp0
= tcg_temp_local_new_i64();
6641 gen_load_gpr(t0
, ft
);
6642 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6643 gen_load_fpr64(ctx
, fp0
, fs
);
6644 gen_store_fpr64(ctx
, fp0
, fd
);
6645 tcg_temp_free_i64(fp0
);
6653 int l1
= gen_new_label();
6654 TCGv t0
= tcg_temp_new();
6655 TCGv_i64 fp0
= tcg_temp_local_new_i64();
6657 gen_load_gpr(t0
, ft
);
6658 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6659 gen_load_fpr64(ctx
, fp0
, fs
);
6660 gen_store_fpr64(ctx
, fp0
, fd
);
6661 tcg_temp_free_i64(fp0
);
6668 check_cp1_64bitmode(ctx
);
6670 TCGv_i64 fp0
= tcg_temp_new_i64();
6672 gen_load_fpr64(ctx
, fp0
, fs
);
6673 gen_helper_float_recip_d(fp0
, fp0
);
6674 gen_store_fpr64(ctx
, fp0
, fd
);
6675 tcg_temp_free_i64(fp0
);
6680 check_cp1_64bitmode(ctx
);
6682 TCGv_i64 fp0
= tcg_temp_new_i64();
6684 gen_load_fpr64(ctx
, fp0
, fs
);
6685 gen_helper_float_rsqrt_d(fp0
, fp0
);
6686 gen_store_fpr64(ctx
, fp0
, fd
);
6687 tcg_temp_free_i64(fp0
);
6692 check_cp1_64bitmode(ctx
);
6694 TCGv_i64 fp0
= tcg_temp_new_i64();
6695 TCGv_i64 fp1
= tcg_temp_new_i64();
6697 gen_load_fpr64(ctx
, fp0
, fs
);
6698 gen_load_fpr64(ctx
, fp1
, ft
);
6699 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6700 tcg_temp_free_i64(fp1
);
6701 gen_store_fpr64(ctx
, fp0
, fd
);
6702 tcg_temp_free_i64(fp0
);
6707 check_cp1_64bitmode(ctx
);
6709 TCGv_i64 fp0
= tcg_temp_new_i64();
6711 gen_load_fpr64(ctx
, fp0
, fs
);
6712 gen_helper_float_recip1_d(fp0
, fp0
);
6713 gen_store_fpr64(ctx
, fp0
, fd
);
6714 tcg_temp_free_i64(fp0
);
6719 check_cp1_64bitmode(ctx
);
6721 TCGv_i64 fp0
= tcg_temp_new_i64();
6723 gen_load_fpr64(ctx
, fp0
, fs
);
6724 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6725 gen_store_fpr64(ctx
, fp0
, fd
);
6726 tcg_temp_free_i64(fp0
);
6731 check_cp1_64bitmode(ctx
);
6733 TCGv_i64 fp0
= tcg_temp_new_i64();
6734 TCGv_i64 fp1
= tcg_temp_new_i64();
6736 gen_load_fpr64(ctx
, fp0
, fs
);
6737 gen_load_fpr64(ctx
, fp1
, ft
);
6738 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6739 tcg_temp_free_i64(fp1
);
6740 gen_store_fpr64(ctx
, fp0
, fd
);
6741 tcg_temp_free_i64(fp0
);
6762 TCGv_i64 fp0
= tcg_temp_new_i64();
6763 TCGv_i64 fp1
= tcg_temp_new_i64();
6765 gen_load_fpr64(ctx
, fp0
, fs
);
6766 gen_load_fpr64(ctx
, fp1
, ft
);
6767 if (ctx
->opcode
& (1 << 6)) {
6769 check_cp1_registers(ctx
, fs
| ft
);
6770 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6771 opn
= condnames_abs
[func
-48];
6773 check_cp1_registers(ctx
, fs
| ft
);
6774 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6775 opn
= condnames
[func
-48];
6777 tcg_temp_free_i64(fp0
);
6778 tcg_temp_free_i64(fp1
);
6782 check_cp1_registers(ctx
, fs
);
6784 TCGv_i32 fp32
= tcg_temp_new_i32();
6785 TCGv_i64 fp64
= tcg_temp_new_i64();
6787 gen_load_fpr64(ctx
, fp64
, fs
);
6788 gen_helper_float_cvts_d(fp32
, fp64
);
6789 tcg_temp_free_i64(fp64
);
6790 gen_store_fpr32(fp32
, fd
);
6791 tcg_temp_free_i32(fp32
);
6796 check_cp1_registers(ctx
, fs
);
6798 TCGv_i32 fp32
= tcg_temp_new_i32();
6799 TCGv_i64 fp64
= tcg_temp_new_i64();
6801 gen_load_fpr64(ctx
, fp64
, fs
);
6802 gen_helper_float_cvtw_d(fp32
, fp64
);
6803 tcg_temp_free_i64(fp64
);
6804 gen_store_fpr32(fp32
, fd
);
6805 tcg_temp_free_i32(fp32
);
6810 check_cp1_64bitmode(ctx
);
6812 TCGv_i64 fp0
= tcg_temp_new_i64();
6814 gen_load_fpr64(ctx
, fp0
, fs
);
6815 gen_helper_float_cvtl_d(fp0
, fp0
);
6816 gen_store_fpr64(ctx
, fp0
, fd
);
6817 tcg_temp_free_i64(fp0
);
6823 TCGv_i32 fp0
= tcg_temp_new_i32();
6825 gen_load_fpr32(fp0
, fs
);
6826 gen_helper_float_cvts_w(fp0
, fp0
);
6827 gen_store_fpr32(fp0
, fd
);
6828 tcg_temp_free_i32(fp0
);
6833 check_cp1_registers(ctx
, fd
);
6835 TCGv_i32 fp32
= tcg_temp_new_i32();
6836 TCGv_i64 fp64
= tcg_temp_new_i64();
6838 gen_load_fpr32(fp32
, fs
);
6839 gen_helper_float_cvtd_w(fp64
, fp32
);
6840 tcg_temp_free_i32(fp32
);
6841 gen_store_fpr64(ctx
, fp64
, fd
);
6842 tcg_temp_free_i64(fp64
);
6847 check_cp1_64bitmode(ctx
);
6849 TCGv_i32 fp32
= tcg_temp_new_i32();
6850 TCGv_i64 fp64
= tcg_temp_new_i64();
6852 gen_load_fpr64(ctx
, fp64
, fs
);
6853 gen_helper_float_cvts_l(fp32
, fp64
);
6854 tcg_temp_free_i64(fp64
);
6855 gen_store_fpr32(fp32
, fd
);
6856 tcg_temp_free_i32(fp32
);
6861 check_cp1_64bitmode(ctx
);
6863 TCGv_i64 fp0
= tcg_temp_new_i64();
6865 gen_load_fpr64(ctx
, fp0
, fs
);
6866 gen_helper_float_cvtd_l(fp0
, fp0
);
6867 gen_store_fpr64(ctx
, fp0
, fd
);
6868 tcg_temp_free_i64(fp0
);
6873 check_cp1_64bitmode(ctx
);
6875 TCGv_i64 fp0
= tcg_temp_new_i64();
6877 gen_load_fpr64(ctx
, fp0
, fs
);
6878 gen_helper_float_cvtps_pw(fp0
, fp0
);
6879 gen_store_fpr64(ctx
, fp0
, fd
);
6880 tcg_temp_free_i64(fp0
);
6885 check_cp1_64bitmode(ctx
);
6887 TCGv_i64 fp0
= tcg_temp_new_i64();
6888 TCGv_i64 fp1
= tcg_temp_new_i64();
6890 gen_load_fpr64(ctx
, fp0
, fs
);
6891 gen_load_fpr64(ctx
, fp1
, ft
);
6892 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6893 tcg_temp_free_i64(fp1
);
6894 gen_store_fpr64(ctx
, fp0
, fd
);
6895 tcg_temp_free_i64(fp0
);
6900 check_cp1_64bitmode(ctx
);
6902 TCGv_i64 fp0
= tcg_temp_new_i64();
6903 TCGv_i64 fp1
= tcg_temp_new_i64();
6905 gen_load_fpr64(ctx
, fp0
, fs
);
6906 gen_load_fpr64(ctx
, fp1
, ft
);
6907 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6908 tcg_temp_free_i64(fp1
);
6909 gen_store_fpr64(ctx
, fp0
, fd
);
6910 tcg_temp_free_i64(fp0
);
6915 check_cp1_64bitmode(ctx
);
6917 TCGv_i64 fp0
= tcg_temp_new_i64();
6918 TCGv_i64 fp1
= tcg_temp_new_i64();
6920 gen_load_fpr64(ctx
, fp0
, fs
);
6921 gen_load_fpr64(ctx
, fp1
, ft
);
6922 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6923 tcg_temp_free_i64(fp1
);
6924 gen_store_fpr64(ctx
, fp0
, fd
);
6925 tcg_temp_free_i64(fp0
);
6930 check_cp1_64bitmode(ctx
);
6932 TCGv_i64 fp0
= tcg_temp_new_i64();
6934 gen_load_fpr64(ctx
, fp0
, fs
);
6935 gen_helper_float_abs_ps(fp0
, fp0
);
6936 gen_store_fpr64(ctx
, fp0
, fd
);
6937 tcg_temp_free_i64(fp0
);
6942 check_cp1_64bitmode(ctx
);
6944 TCGv_i64 fp0
= tcg_temp_new_i64();
6946 gen_load_fpr64(ctx
, fp0
, fs
);
6947 gen_store_fpr64(ctx
, fp0
, fd
);
6948 tcg_temp_free_i64(fp0
);
6953 check_cp1_64bitmode(ctx
);
6955 TCGv_i64 fp0
= tcg_temp_new_i64();
6957 gen_load_fpr64(ctx
, fp0
, fs
);
6958 gen_helper_float_chs_ps(fp0
, fp0
);
6959 gen_store_fpr64(ctx
, fp0
, fd
);
6960 tcg_temp_free_i64(fp0
);
6965 check_cp1_64bitmode(ctx
);
6966 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6970 check_cp1_64bitmode(ctx
);
6972 int l1
= gen_new_label();
6973 TCGv t0
= tcg_temp_new();
6974 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6975 TCGv_i32 fph0
= tcg_temp_local_new_i32();
6977 gen_load_gpr(t0
, ft
);
6978 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
6979 gen_load_fpr32(fp0
, fs
);
6980 gen_load_fpr32h(fph0
, fs
);
6981 gen_store_fpr32(fp0
, fd
);
6982 gen_store_fpr32h(fph0
, fd
);
6983 tcg_temp_free_i32(fp0
);
6984 tcg_temp_free_i32(fph0
);
6991 check_cp1_64bitmode(ctx
);
6993 int l1
= gen_new_label();
6994 TCGv t0
= tcg_temp_new();
6995 TCGv_i32 fp0
= tcg_temp_local_new_i32();
6996 TCGv_i32 fph0
= tcg_temp_local_new_i32();
6998 gen_load_gpr(t0
, ft
);
6999 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
7000 gen_load_fpr32(fp0
, fs
);
7001 gen_load_fpr32h(fph0
, fs
);
7002 gen_store_fpr32(fp0
, fd
);
7003 gen_store_fpr32h(fph0
, fd
);
7004 tcg_temp_free_i32(fp0
);
7005 tcg_temp_free_i32(fph0
);
7012 check_cp1_64bitmode(ctx
);
7014 TCGv_i64 fp0
= tcg_temp_new_i64();
7015 TCGv_i64 fp1
= tcg_temp_new_i64();
7017 gen_load_fpr64(ctx
, fp0
, ft
);
7018 gen_load_fpr64(ctx
, fp1
, fs
);
7019 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7020 tcg_temp_free_i64(fp1
);
7021 gen_store_fpr64(ctx
, fp0
, fd
);
7022 tcg_temp_free_i64(fp0
);
7027 check_cp1_64bitmode(ctx
);
7029 TCGv_i64 fp0
= tcg_temp_new_i64();
7030 TCGv_i64 fp1
= tcg_temp_new_i64();
7032 gen_load_fpr64(ctx
, fp0
, ft
);
7033 gen_load_fpr64(ctx
, fp1
, fs
);
7034 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7035 tcg_temp_free_i64(fp1
);
7036 gen_store_fpr64(ctx
, fp0
, fd
);
7037 tcg_temp_free_i64(fp0
);
7042 check_cp1_64bitmode(ctx
);
7044 TCGv_i64 fp0
= tcg_temp_new_i64();
7045 TCGv_i64 fp1
= tcg_temp_new_i64();
7047 gen_load_fpr64(ctx
, fp0
, fs
);
7048 gen_load_fpr64(ctx
, fp1
, fd
);
7049 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7050 tcg_temp_free_i64(fp1
);
7051 gen_store_fpr64(ctx
, fp0
, fd
);
7052 tcg_temp_free_i64(fp0
);
7057 check_cp1_64bitmode(ctx
);
7059 TCGv_i64 fp0
= tcg_temp_new_i64();
7061 gen_load_fpr64(ctx
, fp0
, fs
);
7062 gen_helper_float_recip1_ps(fp0
, fp0
);
7063 gen_store_fpr64(ctx
, fp0
, fd
);
7064 tcg_temp_free_i64(fp0
);
7069 check_cp1_64bitmode(ctx
);
7071 TCGv_i64 fp0
= tcg_temp_new_i64();
7073 gen_load_fpr64(ctx
, fp0
, fs
);
7074 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7075 gen_store_fpr64(ctx
, fp0
, fd
);
7076 tcg_temp_free_i64(fp0
);
7081 check_cp1_64bitmode(ctx
);
7083 TCGv_i64 fp0
= tcg_temp_new_i64();
7084 TCGv_i64 fp1
= tcg_temp_new_i64();
7086 gen_load_fpr64(ctx
, fp0
, fs
);
7087 gen_load_fpr64(ctx
, fp1
, ft
);
7088 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7089 tcg_temp_free_i64(fp1
);
7090 gen_store_fpr64(ctx
, fp0
, fd
);
7091 tcg_temp_free_i64(fp0
);
7096 check_cp1_64bitmode(ctx
);
7098 TCGv_i32 fp0
= tcg_temp_new_i32();
7100 gen_load_fpr32h(fp0
, fs
);
7101 gen_helper_float_cvts_pu(fp0
, fp0
);
7102 gen_store_fpr32(fp0
, fd
);
7103 tcg_temp_free_i32(fp0
);
7108 check_cp1_64bitmode(ctx
);
7110 TCGv_i64 fp0
= tcg_temp_new_i64();
7112 gen_load_fpr64(ctx
, fp0
, fs
);
7113 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7114 gen_store_fpr64(ctx
, fp0
, fd
);
7115 tcg_temp_free_i64(fp0
);
7120 check_cp1_64bitmode(ctx
);
7122 TCGv_i32 fp0
= tcg_temp_new_i32();
7124 gen_load_fpr32(fp0
, fs
);
7125 gen_helper_float_cvts_pl(fp0
, fp0
);
7126 gen_store_fpr32(fp0
, fd
);
7127 tcg_temp_free_i32(fp0
);
7132 check_cp1_64bitmode(ctx
);
7134 TCGv_i32 fp0
= tcg_temp_new_i32();
7135 TCGv_i32 fp1
= tcg_temp_new_i32();
7137 gen_load_fpr32(fp0
, fs
);
7138 gen_load_fpr32(fp1
, ft
);
7139 gen_store_fpr32h(fp0
, fd
);
7140 gen_store_fpr32(fp1
, fd
);
7141 tcg_temp_free_i32(fp0
);
7142 tcg_temp_free_i32(fp1
);
7147 check_cp1_64bitmode(ctx
);
7149 TCGv_i32 fp0
= tcg_temp_new_i32();
7150 TCGv_i32 fp1
= tcg_temp_new_i32();
7152 gen_load_fpr32(fp0
, fs
);
7153 gen_load_fpr32h(fp1
, ft
);
7154 gen_store_fpr32(fp1
, fd
);
7155 gen_store_fpr32h(fp0
, fd
);
7156 tcg_temp_free_i32(fp0
);
7157 tcg_temp_free_i32(fp1
);
7162 check_cp1_64bitmode(ctx
);
7164 TCGv_i32 fp0
= tcg_temp_new_i32();
7165 TCGv_i32 fp1
= tcg_temp_new_i32();
7167 gen_load_fpr32h(fp0
, fs
);
7168 gen_load_fpr32(fp1
, ft
);
7169 gen_store_fpr32(fp1
, fd
);
7170 gen_store_fpr32h(fp0
, fd
);
7171 tcg_temp_free_i32(fp0
);
7172 tcg_temp_free_i32(fp1
);
7177 check_cp1_64bitmode(ctx
);
7179 TCGv_i32 fp0
= tcg_temp_new_i32();
7180 TCGv_i32 fp1
= tcg_temp_new_i32();
7182 gen_load_fpr32h(fp0
, fs
);
7183 gen_load_fpr32h(fp1
, ft
);
7184 gen_store_fpr32(fp1
, fd
);
7185 gen_store_fpr32h(fp0
, fd
);
7186 tcg_temp_free_i32(fp0
);
7187 tcg_temp_free_i32(fp1
);
7207 check_cp1_64bitmode(ctx
);
7209 TCGv_i64 fp0
= tcg_temp_new_i64();
7210 TCGv_i64 fp1
= tcg_temp_new_i64();
7212 gen_load_fpr64(ctx
, fp0
, fs
);
7213 gen_load_fpr64(ctx
, fp1
, ft
);
7214 if (ctx
->opcode
& (1 << 6)) {
7215 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7216 opn
= condnames_abs
[func
-48];
7218 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7219 opn
= condnames
[func
-48];
7221 tcg_temp_free_i64(fp0
);
7222 tcg_temp_free_i64(fp1
);
7227 generate_exception (ctx
, EXCP_RI
);
7232 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7235 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7238 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7243 /* Coprocessor 3 (FPU) */
7244 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7245 int fd
, int fs
, int base
, int index
)
7247 const char *opn
= "extended float load/store";
7249 TCGv t0
= tcg_temp_local_new();
7250 TCGv t1
= tcg_temp_local_new();
7253 gen_load_gpr(t0
, index
);
7254 } else if (index
== 0) {
7255 gen_load_gpr(t0
, base
);
7257 gen_load_gpr(t0
, index
);
7258 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
]);
7260 /* Don't do NOP if destination is zero: we must perform the actual
7266 TCGv_i32 fp0
= tcg_temp_new_i32();
7268 tcg_gen_qemu_ld32s(t1
, t0
, ctx
->mem_idx
);
7269 tcg_gen_trunc_tl_i32(fp0
, t1
);
7270 gen_store_fpr32(fp0
, fd
);
7271 tcg_temp_free_i32(fp0
);
7277 check_cp1_registers(ctx
, fd
);
7279 TCGv_i64 fp0
= tcg_temp_new_i64();
7281 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7282 gen_store_fpr64(ctx
, fp0
, fd
);
7283 tcg_temp_free_i64(fp0
);
7288 check_cp1_64bitmode(ctx
);
7289 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7291 TCGv_i64 fp0
= tcg_temp_new_i64();
7293 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7294 gen_store_fpr64(ctx
, fp0
, fd
);
7295 tcg_temp_free_i64(fp0
);
7302 TCGv_i32 fp0
= tcg_temp_new_i32();
7304 gen_load_fpr32(fp0
, fs
);
7305 tcg_gen_extu_i32_tl(t1
, fp0
);
7306 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7307 tcg_temp_free_i32(fp0
);
7314 check_cp1_registers(ctx
, fs
);
7316 TCGv_i64 fp0
= tcg_temp_new_i64();
7318 gen_load_fpr64(ctx
, fp0
, fs
);
7319 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7320 tcg_temp_free_i64(fp0
);
7326 check_cp1_64bitmode(ctx
);
7327 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7329 TCGv_i64 fp0
= tcg_temp_new_i64();
7331 gen_load_fpr64(ctx
, fp0
, fs
);
7332 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7333 tcg_temp_free_i64(fp0
);
7340 generate_exception(ctx
, EXCP_RI
);
7347 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7348 regnames
[index
], regnames
[base
]);
7351 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7352 int fd
, int fr
, int fs
, int ft
)
7354 const char *opn
= "flt3_arith";
7358 check_cp1_64bitmode(ctx
);
7360 TCGv t0
= tcg_temp_local_new();
7361 TCGv_i32 fp0
= tcg_temp_local_new_i32();
7362 TCGv_i32 fph0
= tcg_temp_local_new_i32();
7363 TCGv_i32 fp1
= tcg_temp_local_new_i32();
7364 TCGv_i32 fph1
= tcg_temp_local_new_i32();
7365 int l1
= gen_new_label();
7366 int l2
= gen_new_label();
7368 gen_load_gpr(t0
, fr
);
7369 tcg_gen_andi_tl(t0
, t0
, 0x7);
7370 gen_load_fpr32(fp0
, fs
);
7371 gen_load_fpr32h(fph0
, fs
);
7372 gen_load_fpr32(fp1
, ft
);
7373 gen_load_fpr32h(fph1
, ft
);
7375 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7376 gen_store_fpr32(fp0
, fd
);
7377 gen_store_fpr32h(fph0
, fd
);
7380 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7382 #ifdef TARGET_WORDS_BIGENDIAN
7383 gen_store_fpr32(fph1
, fd
);
7384 gen_store_fpr32h(fp0
, fd
);
7386 gen_store_fpr32(fph0
, fd
);
7387 gen_store_fpr32h(fp1
, fd
);
7390 tcg_temp_free_i32(fp0
);
7391 tcg_temp_free_i32(fph0
);
7392 tcg_temp_free_i32(fp1
);
7393 tcg_temp_free_i32(fph1
);
7400 TCGv_i32 fp0
= tcg_temp_new_i32();
7401 TCGv_i32 fp1
= tcg_temp_new_i32();
7402 TCGv_i32 fp2
= tcg_temp_new_i32();
7404 gen_load_fpr32(fp0
, fs
);
7405 gen_load_fpr32(fp1
, ft
);
7406 gen_load_fpr32(fp2
, fr
);
7407 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7408 tcg_temp_free_i32(fp0
);
7409 tcg_temp_free_i32(fp1
);
7410 gen_store_fpr32(fp2
, fd
);
7411 tcg_temp_free_i32(fp2
);
7417 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7419 TCGv_i64 fp0
= tcg_temp_new_i64();
7420 TCGv_i64 fp1
= tcg_temp_new_i64();
7421 TCGv_i64 fp2
= tcg_temp_new_i64();
7423 gen_load_fpr64(ctx
, fp0
, fs
);
7424 gen_load_fpr64(ctx
, fp1
, ft
);
7425 gen_load_fpr64(ctx
, fp2
, fr
);
7426 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7427 tcg_temp_free_i64(fp0
);
7428 tcg_temp_free_i64(fp1
);
7429 gen_store_fpr64(ctx
, fp2
, fd
);
7430 tcg_temp_free_i64(fp2
);
7435 check_cp1_64bitmode(ctx
);
7437 TCGv_i64 fp0
= tcg_temp_new_i64();
7438 TCGv_i64 fp1
= tcg_temp_new_i64();
7439 TCGv_i64 fp2
= tcg_temp_new_i64();
7441 gen_load_fpr64(ctx
, fp0
, fs
);
7442 gen_load_fpr64(ctx
, fp1
, ft
);
7443 gen_load_fpr64(ctx
, fp2
, fr
);
7444 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7445 tcg_temp_free_i64(fp0
);
7446 tcg_temp_free_i64(fp1
);
7447 gen_store_fpr64(ctx
, fp2
, fd
);
7448 tcg_temp_free_i64(fp2
);
7455 TCGv_i32 fp0
= tcg_temp_new_i32();
7456 TCGv_i32 fp1
= tcg_temp_new_i32();
7457 TCGv_i32 fp2
= tcg_temp_new_i32();
7459 gen_load_fpr32(fp0
, fs
);
7460 gen_load_fpr32(fp1
, ft
);
7461 gen_load_fpr32(fp2
, fr
);
7462 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7463 tcg_temp_free_i32(fp0
);
7464 tcg_temp_free_i32(fp1
);
7465 gen_store_fpr32(fp2
, fd
);
7466 tcg_temp_free_i32(fp2
);
7472 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7474 TCGv_i64 fp0
= tcg_temp_new_i64();
7475 TCGv_i64 fp1
= tcg_temp_new_i64();
7476 TCGv_i64 fp2
= tcg_temp_new_i64();
7478 gen_load_fpr64(ctx
, fp0
, fs
);
7479 gen_load_fpr64(ctx
, fp1
, ft
);
7480 gen_load_fpr64(ctx
, fp2
, fr
);
7481 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7482 tcg_temp_free_i64(fp0
);
7483 tcg_temp_free_i64(fp1
);
7484 gen_store_fpr64(ctx
, fp2
, fd
);
7485 tcg_temp_free_i64(fp2
);
7490 check_cp1_64bitmode(ctx
);
7492 TCGv_i64 fp0
= tcg_temp_new_i64();
7493 TCGv_i64 fp1
= tcg_temp_new_i64();
7494 TCGv_i64 fp2
= tcg_temp_new_i64();
7496 gen_load_fpr64(ctx
, fp0
, fs
);
7497 gen_load_fpr64(ctx
, fp1
, ft
);
7498 gen_load_fpr64(ctx
, fp2
, fr
);
7499 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7500 tcg_temp_free_i64(fp0
);
7501 tcg_temp_free_i64(fp1
);
7502 gen_store_fpr64(ctx
, fp2
, fd
);
7503 tcg_temp_free_i64(fp2
);
7510 TCGv_i32 fp0
= tcg_temp_new_i32();
7511 TCGv_i32 fp1
= tcg_temp_new_i32();
7512 TCGv_i32 fp2
= tcg_temp_new_i32();
7514 gen_load_fpr32(fp0
, fs
);
7515 gen_load_fpr32(fp1
, ft
);
7516 gen_load_fpr32(fp2
, fr
);
7517 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7518 tcg_temp_free_i32(fp0
);
7519 tcg_temp_free_i32(fp1
);
7520 gen_store_fpr32(fp2
, fd
);
7521 tcg_temp_free_i32(fp2
);
7527 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7529 TCGv_i64 fp0
= tcg_temp_new_i64();
7530 TCGv_i64 fp1
= tcg_temp_new_i64();
7531 TCGv_i64 fp2
= tcg_temp_new_i64();
7533 gen_load_fpr64(ctx
, fp0
, fs
);
7534 gen_load_fpr64(ctx
, fp1
, ft
);
7535 gen_load_fpr64(ctx
, fp2
, fr
);
7536 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7537 tcg_temp_free_i64(fp0
);
7538 tcg_temp_free_i64(fp1
);
7539 gen_store_fpr64(ctx
, fp2
, fd
);
7540 tcg_temp_free_i64(fp2
);
7545 check_cp1_64bitmode(ctx
);
7547 TCGv_i64 fp0
= tcg_temp_new_i64();
7548 TCGv_i64 fp1
= tcg_temp_new_i64();
7549 TCGv_i64 fp2
= tcg_temp_new_i64();
7551 gen_load_fpr64(ctx
, fp0
, fs
);
7552 gen_load_fpr64(ctx
, fp1
, ft
);
7553 gen_load_fpr64(ctx
, fp2
, fr
);
7554 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7555 tcg_temp_free_i64(fp0
);
7556 tcg_temp_free_i64(fp1
);
7557 gen_store_fpr64(ctx
, fp2
, fd
);
7558 tcg_temp_free_i64(fp2
);
7565 TCGv_i32 fp0
= tcg_temp_new_i32();
7566 TCGv_i32 fp1
= tcg_temp_new_i32();
7567 TCGv_i32 fp2
= tcg_temp_new_i32();
7569 gen_load_fpr32(fp0
, fs
);
7570 gen_load_fpr32(fp1
, ft
);
7571 gen_load_fpr32(fp2
, fr
);
7572 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7573 tcg_temp_free_i32(fp0
);
7574 tcg_temp_free_i32(fp1
);
7575 gen_store_fpr32(fp2
, fd
);
7576 tcg_temp_free_i32(fp2
);
7582 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7584 TCGv_i64 fp0
= tcg_temp_new_i64();
7585 TCGv_i64 fp1
= tcg_temp_new_i64();
7586 TCGv_i64 fp2
= tcg_temp_new_i64();
7588 gen_load_fpr64(ctx
, fp0
, fs
);
7589 gen_load_fpr64(ctx
, fp1
, ft
);
7590 gen_load_fpr64(ctx
, fp2
, fr
);
7591 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7592 tcg_temp_free_i64(fp0
);
7593 tcg_temp_free_i64(fp1
);
7594 gen_store_fpr64(ctx
, fp2
, fd
);
7595 tcg_temp_free_i64(fp2
);
7600 check_cp1_64bitmode(ctx
);
7602 TCGv_i64 fp0
= tcg_temp_new_i64();
7603 TCGv_i64 fp1
= tcg_temp_new_i64();
7604 TCGv_i64 fp2
= tcg_temp_new_i64();
7606 gen_load_fpr64(ctx
, fp0
, fs
);
7607 gen_load_fpr64(ctx
, fp1
, ft
);
7608 gen_load_fpr64(ctx
, fp2
, fr
);
7609 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7610 tcg_temp_free_i64(fp0
);
7611 tcg_temp_free_i64(fp1
);
7612 gen_store_fpr64(ctx
, fp2
, fd
);
7613 tcg_temp_free_i64(fp2
);
7619 generate_exception (ctx
, EXCP_RI
);
7622 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7623 fregnames
[fs
], fregnames
[ft
]);
7626 /* ISA extensions (ASEs) */
7627 /* MIPS16 extension to MIPS32 */
7628 /* SmartMIPS extension to MIPS32 */
7630 #if defined(TARGET_MIPS64)
7632 /* MDMX extension to MIPS64 */
7636 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7640 uint32_t op
, op1
, op2
;
7643 /* make sure instructions are on a word boundary */
7644 if (ctx
->pc
& 0x3) {
7645 env
->CP0_BadVAddr
= ctx
->pc
;
7646 generate_exception(ctx
, EXCP_AdEL
);
7650 /* Handle blikely not taken case */
7651 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7652 int l1
= gen_new_label();
7654 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7655 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
7657 TCGv_i32 r_tmp
= tcg_temp_new_i32();
7659 tcg_gen_movi_i32(r_tmp
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7660 tcg_gen_st_i32(r_tmp
, cpu_env
, offsetof(CPUState
, hflags
));
7661 tcg_temp_free_i32(r_tmp
);
7663 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7666 op
= MASK_OP_MAJOR(ctx
->opcode
);
7667 rs
= (ctx
->opcode
>> 21) & 0x1f;
7668 rt
= (ctx
->opcode
>> 16) & 0x1f;
7669 rd
= (ctx
->opcode
>> 11) & 0x1f;
7670 sa
= (ctx
->opcode
>> 6) & 0x1f;
7671 imm
= (int16_t)ctx
->opcode
;
7674 op1
= MASK_SPECIAL(ctx
->opcode
);
7676 case OPC_SLL
: /* Arithmetic with immediate */
7677 case OPC_SRL
... OPC_SRA
:
7678 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7680 case OPC_MOVZ
... OPC_MOVN
:
7681 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7682 case OPC_SLLV
: /* Arithmetic */
7683 case OPC_SRLV
... OPC_SRAV
:
7684 case OPC_ADD
... OPC_NOR
:
7685 case OPC_SLT
... OPC_SLTU
:
7686 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7688 case OPC_MULT
... OPC_DIVU
:
7690 check_insn(env
, ctx
, INSN_VR54XX
);
7691 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7692 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7694 gen_muldiv(ctx
, op1
, rs
, rt
);
7696 case OPC_JR
... OPC_JALR
:
7697 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7699 case OPC_TGE
... OPC_TEQ
: /* Traps */
7701 gen_trap(ctx
, op1
, rs
, rt
, -1);
7703 case OPC_MFHI
: /* Move from HI/LO */
7705 gen_HILO(ctx
, op1
, rd
);
7708 case OPC_MTLO
: /* Move to HI/LO */
7709 gen_HILO(ctx
, op1
, rs
);
7711 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7712 #ifdef MIPS_STRICT_STANDARD
7713 MIPS_INVAL("PMON / selsl");
7714 generate_exception(ctx
, EXCP_RI
);
7716 gen_helper_0i(pmon
, sa
);
7720 generate_exception(ctx
, EXCP_SYSCALL
);
7723 generate_exception(ctx
, EXCP_BREAK
);
7726 #ifdef MIPS_STRICT_STANDARD
7728 generate_exception(ctx
, EXCP_RI
);
7730 /* Implemented as RI exception for now. */
7731 MIPS_INVAL("spim (unofficial)");
7732 generate_exception(ctx
, EXCP_RI
);
7740 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7741 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7742 save_cpu_state(ctx
, 1);
7743 check_cp1_enabled(ctx
);
7744 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7745 (ctx
->opcode
>> 16) & 1);
7747 generate_exception_err(ctx
, EXCP_CpU
, 1);
7751 #if defined(TARGET_MIPS64)
7752 /* MIPS64 specific opcodes */
7754 case OPC_DSRL
... OPC_DSRA
:
7756 case OPC_DSRL32
... OPC_DSRA32
:
7757 check_insn(env
, ctx
, ISA_MIPS3
);
7759 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7762 case OPC_DSRLV
... OPC_DSRAV
:
7763 case OPC_DADD
... OPC_DSUBU
:
7764 check_insn(env
, ctx
, ISA_MIPS3
);
7766 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7768 case OPC_DMULT
... OPC_DDIVU
:
7769 check_insn(env
, ctx
, ISA_MIPS3
);
7771 gen_muldiv(ctx
, op1
, rs
, rt
);
7774 default: /* Invalid */
7775 MIPS_INVAL("special");
7776 generate_exception(ctx
, EXCP_RI
);
7781 op1
= MASK_SPECIAL2(ctx
->opcode
);
7783 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7784 case OPC_MSUB
... OPC_MSUBU
:
7785 check_insn(env
, ctx
, ISA_MIPS32
);
7786 gen_muldiv(ctx
, op1
, rs
, rt
);
7789 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7791 case OPC_CLZ
... OPC_CLO
:
7792 check_insn(env
, ctx
, ISA_MIPS32
);
7793 gen_cl(ctx
, op1
, rd
, rs
);
7796 /* XXX: not clear which exception should be raised
7797 * when in debug mode...
7799 check_insn(env
, ctx
, ISA_MIPS32
);
7800 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7801 generate_exception(ctx
, EXCP_DBp
);
7803 generate_exception(ctx
, EXCP_DBp
);
7807 #if defined(TARGET_MIPS64)
7808 case OPC_DCLZ
... OPC_DCLO
:
7809 check_insn(env
, ctx
, ISA_MIPS64
);
7811 gen_cl(ctx
, op1
, rd
, rs
);
7814 default: /* Invalid */
7815 MIPS_INVAL("special2");
7816 generate_exception(ctx
, EXCP_RI
);
7821 op1
= MASK_SPECIAL3(ctx
->opcode
);
7825 check_insn(env
, ctx
, ISA_MIPS32R2
);
7826 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7829 check_insn(env
, ctx
, ISA_MIPS32R2
);
7830 op2
= MASK_BSHFL(ctx
->opcode
);
7831 gen_bshfl(ctx
, op2
, rt
, rd
);
7834 check_insn(env
, ctx
, ISA_MIPS32R2
);
7836 TCGv t0
= tcg_temp_local_new();
7840 save_cpu_state(ctx
, 1);
7841 gen_helper_rdhwr_cpunum(t0
);
7844 save_cpu_state(ctx
, 1);
7845 gen_helper_rdhwr_synci_step(t0
);
7848 save_cpu_state(ctx
, 1);
7849 gen_helper_rdhwr_cc(t0
);
7852 save_cpu_state(ctx
, 1);
7853 gen_helper_rdhwr_ccres(t0
);
7856 #if defined(CONFIG_USER_ONLY)
7857 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7860 /* XXX: Some CPUs implement this in hardware.
7861 Not supported yet. */
7863 default: /* Invalid */
7864 MIPS_INVAL("rdhwr");
7865 generate_exception(ctx
, EXCP_RI
);
7868 gen_store_gpr(t0
, rt
);
7873 check_insn(env
, ctx
, ASE_MT
);
7875 TCGv t0
= tcg_temp_local_new();
7876 TCGv t1
= tcg_temp_local_new();
7878 gen_load_gpr(t0
, rt
);
7879 gen_load_gpr(t1
, rs
);
7880 gen_helper_fork(t0
, t1
);
7886 check_insn(env
, ctx
, ASE_MT
);
7888 TCGv t0
= tcg_temp_local_new();
7890 gen_load_gpr(t0
, rs
);
7891 gen_helper_yield(t0
, t0
);
7892 gen_store_gpr(t0
, rd
);
7896 #if defined(TARGET_MIPS64)
7897 case OPC_DEXTM
... OPC_DEXT
:
7898 case OPC_DINSM
... OPC_DINS
:
7899 check_insn(env
, ctx
, ISA_MIPS64R2
);
7901 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7904 check_insn(env
, ctx
, ISA_MIPS64R2
);
7906 op2
= MASK_DBSHFL(ctx
->opcode
);
7907 gen_bshfl(ctx
, op2
, rt
, rd
);
7910 default: /* Invalid */
7911 MIPS_INVAL("special3");
7912 generate_exception(ctx
, EXCP_RI
);
7917 op1
= MASK_REGIMM(ctx
->opcode
);
7919 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7920 case OPC_BLTZAL
... OPC_BGEZALL
:
7921 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7923 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7925 gen_trap(ctx
, op1
, rs
, -1, imm
);
7928 check_insn(env
, ctx
, ISA_MIPS32R2
);
7931 default: /* Invalid */
7932 MIPS_INVAL("regimm");
7933 generate_exception(ctx
, EXCP_RI
);
7938 check_cp0_enabled(ctx
);
7939 op1
= MASK_CP0(ctx
->opcode
);
7945 #if defined(TARGET_MIPS64)
7949 #ifndef CONFIG_USER_ONLY
7950 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7951 #endif /* !CONFIG_USER_ONLY */
7953 case OPC_C0_FIRST
... OPC_C0_LAST
:
7954 #ifndef CONFIG_USER_ONLY
7955 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7956 #endif /* !CONFIG_USER_ONLY */
7959 #ifndef CONFIG_USER_ONLY
7961 TCGv t0
= tcg_temp_local_new();
7963 op2
= MASK_MFMC0(ctx
->opcode
);
7966 check_insn(env
, ctx
, ASE_MT
);
7967 gen_helper_dmt(t0
, t0
);
7970 check_insn(env
, ctx
, ASE_MT
);
7971 gen_helper_emt(t0
, t0
);
7974 check_insn(env
, ctx
, ASE_MT
);
7975 gen_helper_dvpe(t0
, t0
);
7978 check_insn(env
, ctx
, ASE_MT
);
7979 gen_helper_evpe(t0
, t0
);
7982 check_insn(env
, ctx
, ISA_MIPS32R2
);
7983 save_cpu_state(ctx
, 1);
7985 /* Stop translation as we may have switched the execution mode */
7986 ctx
->bstate
= BS_STOP
;
7989 check_insn(env
, ctx
, ISA_MIPS32R2
);
7990 save_cpu_state(ctx
, 1);
7992 /* Stop translation as we may have switched the execution mode */
7993 ctx
->bstate
= BS_STOP
;
7995 default: /* Invalid */
7996 MIPS_INVAL("mfmc0");
7997 generate_exception(ctx
, EXCP_RI
);
8000 gen_store_gpr(t0
, rt
);
8003 #endif /* !CONFIG_USER_ONLY */
8006 check_insn(env
, ctx
, ISA_MIPS32R2
);
8007 gen_load_srsgpr(rt
, rd
);
8010 check_insn(env
, ctx
, ISA_MIPS32R2
);
8011 gen_store_srsgpr(rt
, rd
);
8015 generate_exception(ctx
, EXCP_RI
);
8019 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
8020 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8022 case OPC_J
... OPC_JAL
: /* Jump */
8023 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8024 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8026 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8027 case OPC_BEQL
... OPC_BGTZL
:
8028 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8030 case OPC_LB
... OPC_LWR
: /* Load and stores */
8031 case OPC_SB
... OPC_SW
:
8035 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8038 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8042 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8046 /* Floating point (COP1). */
8051 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8052 save_cpu_state(ctx
, 1);
8053 check_cp1_enabled(ctx
);
8054 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8056 generate_exception_err(ctx
, EXCP_CpU
, 1);
8061 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8062 save_cpu_state(ctx
, 1);
8063 check_cp1_enabled(ctx
);
8064 op1
= MASK_CP1(ctx
->opcode
);
8068 check_insn(env
, ctx
, ISA_MIPS32R2
);
8073 gen_cp1(ctx
, op1
, rt
, rd
);
8075 #if defined(TARGET_MIPS64)
8078 check_insn(env
, ctx
, ISA_MIPS3
);
8079 gen_cp1(ctx
, op1
, rt
, rd
);
8085 check_insn(env
, ctx
, ASE_MIPS3D
);
8088 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8089 (rt
>> 2) & 0x7, imm
<< 2);
8096 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8101 generate_exception (ctx
, EXCP_RI
);
8105 generate_exception_err(ctx
, EXCP_CpU
, 1);
8115 /* COP2: Not implemented. */
8116 generate_exception_err(ctx
, EXCP_CpU
, 2);
8120 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8121 save_cpu_state(ctx
, 1);
8122 check_cp1_enabled(ctx
);
8123 op1
= MASK_CP3(ctx
->opcode
);
8131 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8149 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8153 generate_exception (ctx
, EXCP_RI
);
8157 generate_exception_err(ctx
, EXCP_CpU
, 1);
8161 #if defined(TARGET_MIPS64)
8162 /* MIPS64 opcodes */
8164 case OPC_LDL
... OPC_LDR
:
8165 case OPC_SDL
... OPC_SDR
:
8170 check_insn(env
, ctx
, ISA_MIPS3
);
8172 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8174 case OPC_DADDI
... OPC_DADDIU
:
8175 check_insn(env
, ctx
, ISA_MIPS3
);
8177 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8181 check_insn(env
, ctx
, ASE_MIPS16
);
8182 /* MIPS16: Not implemented. */
8184 check_insn(env
, ctx
, ASE_MDMX
);
8185 /* MDMX: Not implemented. */
8186 default: /* Invalid */
8187 MIPS_INVAL("major opcode");
8188 generate_exception(ctx
, EXCP_RI
);
8191 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8192 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8193 /* Branches completion */
8194 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8195 ctx
->bstate
= BS_BRANCH
;
8196 save_cpu_state(ctx
, 0);
8197 /* FIXME: Need to clear can_do_io. */
8200 /* unconditional branch */
8201 MIPS_DEBUG("unconditional branch");
8202 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8205 /* blikely taken case */
8206 MIPS_DEBUG("blikely branch taken");
8207 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8210 /* Conditional branch */
8211 MIPS_DEBUG("conditional branch");
8213 int l1
= gen_new_label();
8215 tcg_gen_brcondi_i32(TCG_COND_NE
, bcond
, 0, l1
);
8216 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8218 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8222 /* unconditional branch to register */
8223 MIPS_DEBUG("branch to register");
8224 tcg_gen_mov_tl(cpu_PC
, btarget
);
8228 MIPS_DEBUG("unknown branch");
8235 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8239 target_ulong pc_start
;
8240 uint16_t *gen_opc_end
;
8246 if (search_pc
&& loglevel
)
8247 fprintf (logfile
, "search pc %d\n", search_pc
);
8250 /* Leave some spare opc slots for branch handling. */
8251 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
- 16;
8255 ctx
.bstate
= BS_NONE
;
8256 /* Restore delay slot state from the tb context. */
8257 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8258 restore_cpu_state(env
, &ctx
);
8259 #ifdef CONFIG_USER_ONLY
8260 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8262 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8265 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8267 max_insns
= CF_COUNT_MASK
;
8269 if (loglevel
& CPU_LOG_TB_CPU
) {
8270 fprintf(logfile
, "------------------------------------------------\n");
8271 /* FIXME: This may print out stale hflags from env... */
8272 cpu_dump_state(env
, logfile
, fprintf
, 0);
8275 #ifdef MIPS_DEBUG_DISAS
8276 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8277 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
8278 tb
, ctx
.mem_idx
, ctx
.hflags
);
8281 while (ctx
.bstate
== BS_NONE
) {
8282 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
8283 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8284 if (bp
->pc
== ctx
.pc
) {
8285 save_cpu_state(&ctx
, 1);
8286 ctx
.bstate
= BS_BRANCH
;
8287 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8288 /* Include the breakpoint location or the tb won't
8289 * be flushed when it must be. */
8291 goto done_generating
;
8297 j
= gen_opc_ptr
- gen_opc_buf
;
8301 gen_opc_instr_start
[lj
++] = 0;
8303 gen_opc_pc
[lj
] = ctx
.pc
;
8304 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8305 gen_opc_instr_start
[lj
] = 1;
8306 gen_opc_icount
[lj
] = num_insns
;
8308 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8310 ctx
.opcode
= ldl_code(ctx
.pc
);
8311 decode_opc(env
, &ctx
);
8315 if (env
->singlestep_enabled
)
8318 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8321 if (gen_opc_ptr
>= gen_opc_end
)
8324 if (num_insns
>= max_insns
)
8326 #if defined (MIPS_SINGLE_STEP)
8330 if (tb
->cflags
& CF_LAST_IO
)
8332 if (env
->singlestep_enabled
) {
8333 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8334 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8336 switch (ctx
.bstate
) {
8338 gen_helper_interrupt_restart();
8339 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8342 save_cpu_state(&ctx
, 0);
8343 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8346 gen_helper_interrupt_restart();
8355 gen_icount_end(tb
, num_insns
);
8356 *gen_opc_ptr
= INDEX_op_end
;
8358 j
= gen_opc_ptr
- gen_opc_buf
;
8361 gen_opc_instr_start
[lj
++] = 0;
8363 tb
->size
= ctx
.pc
- pc_start
;
8364 tb
->icount
= num_insns
;
8367 #if defined MIPS_DEBUG_DISAS
8368 if (loglevel
& CPU_LOG_TB_IN_ASM
)
8369 fprintf(logfile
, "\n");
8371 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
8372 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
8373 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
8374 fprintf(logfile
, "\n");
8376 if (loglevel
& CPU_LOG_TB_CPU
) {
8377 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8382 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8384 gen_intermediate_code_internal(env
, tb
, 0);
8387 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8389 gen_intermediate_code_internal(env
, tb
, 1);
8392 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8393 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8397 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8399 #define printfpr(fp) \
8402 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8403 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8404 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8407 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8408 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8409 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8410 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8411 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8416 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8417 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8418 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8419 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8420 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8421 printfpr(&env
->active_fpu
.fpr
[i
]);
8427 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8428 /* Debug help: The architecture requires 32bit code to maintain proper
8429 sign-extended values on 64bit machines. */
8431 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8434 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8435 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8440 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8441 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8442 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8443 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8444 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8445 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8446 if (!SIGN_EXT_P(env
->btarget
))
8447 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8449 for (i
= 0; i
< 32; i
++) {
8450 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8451 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8454 if (!SIGN_EXT_P(env
->CP0_EPC
))
8455 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8456 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
8457 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
8461 void cpu_dump_state (CPUState
*env
, FILE *f
,
8462 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8467 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8468 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8469 env
->hflags
, env
->btarget
, env
->bcond
);
8470 for (i
= 0; i
< 32; i
++) {
8472 cpu_fprintf(f
, "GPR%02d:", i
);
8473 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8475 cpu_fprintf(f
, "\n");
8478 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8479 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8480 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8481 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
8482 if (env
->hflags
& MIPS_HFLAG_FPU
)
8483 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8484 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8485 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8489 static void mips_tcg_init(void)
8494 /* Initialize various static tables. */
8498 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8499 for (i
= 0; i
< 32; i
++)
8500 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
8501 offsetof(CPUState
, active_tc
.gpr
[i
]),
8503 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
8504 offsetof(CPUState
, active_tc
.PC
), "PC");
8505 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8506 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
8507 offsetof(CPUState
, active_tc
.HI
[i
]),
8509 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
8510 offsetof(CPUState
, active_tc
.LO
[i
]),
8512 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
8513 offsetof(CPUState
, active_tc
.ACX
[i
]),
8516 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
8517 offsetof(CPUState
, active_tc
.DSPControl
),
8519 bcond
= tcg_global_mem_new_i32(TCG_AREG0
,
8520 offsetof(CPUState
, bcond
), "bcond");
8521 btarget
= tcg_global_mem_new(TCG_AREG0
,
8522 offsetof(CPUState
, btarget
), "btarget");
8523 for (i
= 0; i
< 32; i
++)
8524 fpu_fpr32
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
8525 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]),
8527 for (i
= 0; i
< 32; i
++)
8528 fpu_fpr64
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
8529 offsetof(CPUState
, active_fpu
.fpr
[i
]),
8531 for (i
= 0; i
< 32; i
++)
8532 fpu_fpr32h
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
8533 offsetof(CPUState
, active_fpu
.fpr
[i
].w
[!FP_ENDIAN_IDX
]),
8535 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
8536 offsetof(CPUState
, active_fpu
.fcr0
),
8538 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
8539 offsetof(CPUState
, active_fpu
.fcr31
),
8542 /* register helpers */
8543 #define GEN_HELPER 2
8549 #include "translate_init.c"
8551 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8554 const mips_def_t
*def
;
8556 def
= cpu_mips_find_by_name(cpu_model
);
8559 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8562 env
->cpu_model
= def
;
8565 env
->cpu_model_str
= cpu_model
;
8571 void cpu_reset (CPUMIPSState
*env
)
8573 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8578 #if defined(CONFIG_USER_ONLY)
8579 env
->hflags
= MIPS_HFLAG_UM
;
8581 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8582 /* If the exception was raised from a delay slot,
8583 come back to the jump. */
8584 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8586 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8588 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8590 /* SMP not implemented */
8591 env
->CP0_EBase
= 0x80000000;
8592 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8593 /* vectored interrupts not implemented, timer on int 7,
8594 no performance counters. */
8595 env
->CP0_IntCtl
= 0xe0000000;
8599 for (i
= 0; i
< 7; i
++) {
8600 env
->CP0_WatchLo
[i
] = 0;
8601 env
->CP0_WatchHi
[i
] = 0x80000000;
8603 env
->CP0_WatchLo
[7] = 0;
8604 env
->CP0_WatchHi
[7] = 0;
8606 /* Count register increments in debug mode, EJTAG version 1 */
8607 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8608 env
->hflags
= MIPS_HFLAG_CP0
;
8610 env
->exception_index
= EXCP_NONE
;
8611 cpu_mips_register(env
, env
->cpu_model
);
8614 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8615 unsigned long searched_pc
, int pc_pos
, void *puc
)
8617 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8618 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8619 env
->hflags
|= gen_opc_hflags
[pc_pos
];