2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 //#define MIPS_DEBUG_DISAS
32 //#define MIPS_SINGLE_STEP
34 #ifdef USE_DIRECT_JUMP
37 #define TBPARAM(x) (long)(x)
41 #define DEF(s, n, copy_size) INDEX_op_ ## s,
47 static uint16_t *gen_opc_ptr
;
48 static uint32_t *gen_opparam_ptr
;
53 #define EXT_SPECIAL 0x100
54 #define EXT_SPECIAL2 0x200
55 #define EXT_REGIMM 0x300
62 /* indirect opcode tables */
70 /* arithmetic with immediate */
79 /* Jump and branches */
82 OPC_BEQ
= 0x04, /* Unconditional if rs = rt = 0 (B) */
90 OPC_JALX
= 0x1D, /* MIPS 16 only */
106 /* Floating point load/store */
115 /* Cache and prefetch */
120 /* MIPS special opcodes */
123 OPC_SLL
= 0x00 | EXT_SPECIAL
,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 OPC_SRL
= 0x02 | EXT_SPECIAL
,
127 OPC_SRA
= 0x03 | EXT_SPECIAL
,
128 OPC_SLLV
= 0x04 | EXT_SPECIAL
,
129 OPC_SRLV
= 0x06 | EXT_SPECIAL
,
130 OPC_SRAV
= 0x07 | EXT_SPECIAL
,
131 /* Multiplication / division */
132 OPC_MULT
= 0x18 | EXT_SPECIAL
,
133 OPC_MULTU
= 0x19 | EXT_SPECIAL
,
134 OPC_DIV
= 0x1A | EXT_SPECIAL
,
135 OPC_DIVU
= 0x1B | EXT_SPECIAL
,
136 /* 2 registers arithmetic / logic */
137 OPC_ADD
= 0x20 | EXT_SPECIAL
,
138 OPC_ADDU
= 0x21 | EXT_SPECIAL
,
139 OPC_SUB
= 0x22 | EXT_SPECIAL
,
140 OPC_SUBU
= 0x23 | EXT_SPECIAL
,
141 OPC_AND
= 0x24 | EXT_SPECIAL
,
142 OPC_OR
= 0x25 | EXT_SPECIAL
,
143 OPC_XOR
= 0x26 | EXT_SPECIAL
,
144 OPC_NOR
= 0x27 | EXT_SPECIAL
,
145 OPC_SLT
= 0x2A | EXT_SPECIAL
,
146 OPC_SLTU
= 0x2B | EXT_SPECIAL
,
148 OPC_JR
= 0x08 | EXT_SPECIAL
,
149 OPC_JALR
= 0x09 | EXT_SPECIAL
,
151 OPC_TGE
= 0x30 | EXT_SPECIAL
,
152 OPC_TGEU
= 0x31 | EXT_SPECIAL
,
153 OPC_TLT
= 0x32 | EXT_SPECIAL
,
154 OPC_TLTU
= 0x33 | EXT_SPECIAL
,
155 OPC_TEQ
= 0x34 | EXT_SPECIAL
,
156 OPC_TNE
= 0x36 | EXT_SPECIAL
,
157 /* HI / LO registers load & stores */
158 OPC_MFHI
= 0x10 | EXT_SPECIAL
,
159 OPC_MTHI
= 0x11 | EXT_SPECIAL
,
160 OPC_MFLO
= 0x12 | EXT_SPECIAL
,
161 OPC_MTLO
= 0x13 | EXT_SPECIAL
,
162 /* Conditional moves */
163 OPC_MOVZ
= 0x0A | EXT_SPECIAL
,
164 OPC_MOVN
= 0x0B | EXT_SPECIAL
,
166 OPC_MOVCI
= 0x01 | EXT_SPECIAL
,
169 OPC_PMON
= 0x05 | EXT_SPECIAL
,
170 OPC_SYSCALL
= 0x0C | EXT_SPECIAL
,
171 OPC_BREAK
= 0x0D | EXT_SPECIAL
,
172 OPC_SYNC
= 0x0F | EXT_SPECIAL
,
176 /* Mutiply & xxx operations */
177 OPC_MADD
= 0x00 | EXT_SPECIAL2
,
178 OPC_MADDU
= 0x01 | EXT_SPECIAL2
,
179 OPC_MUL
= 0x02 | EXT_SPECIAL2
,
180 OPC_MSUB
= 0x04 | EXT_SPECIAL2
,
181 OPC_MSUBU
= 0x05 | EXT_SPECIAL2
,
183 OPC_CLZ
= 0x20 | EXT_SPECIAL2
,
184 OPC_CLO
= 0x21 | EXT_SPECIAL2
,
186 OPC_SDBBP
= 0x3F | EXT_SPECIAL2
,
191 OPC_BLTZ
= 0x00 | EXT_REGIMM
,
192 OPC_BLTZL
= 0x02 | EXT_REGIMM
,
193 OPC_BGEZ
= 0x01 | EXT_REGIMM
,
194 OPC_BGEZL
= 0x03 | EXT_REGIMM
,
195 OPC_BLTZAL
= 0x10 | EXT_REGIMM
,
196 OPC_BLTZALL
= 0x12 | EXT_REGIMM
,
197 OPC_BGEZAL
= 0x11 | EXT_REGIMM
,
198 OPC_BGEZALL
= 0x13 | EXT_REGIMM
,
199 OPC_TGEI
= 0x08 | EXT_REGIMM
,
200 OPC_TGEIU
= 0x09 | EXT_REGIMM
,
201 OPC_TLTI
= 0x0A | EXT_REGIMM
,
202 OPC_TLTIU
= 0x0B | EXT_REGIMM
,
203 OPC_TEQI
= 0x0C | EXT_REGIMM
,
204 OPC_TNEI
= 0x0E | EXT_REGIMM
,
208 /* Coprocessor 0 (MMU) */
209 OPC_MFC0
= 0x00 | EXT_CP0
,
210 OPC_MTC0
= 0x04 | EXT_CP0
,
211 OPC_TLBR
= 0x01 | EXT_CP0
,
212 OPC_TLBWI
= 0x02 | EXT_CP0
,
213 OPC_TLBWR
= 0x06 | EXT_CP0
,
214 OPC_TLBP
= 0x08 | EXT_CP0
,
215 OPC_ERET
= 0x18 | EXT_CP0
,
216 OPC_DERET
= 0x1F | EXT_CP0
,
217 OPC_WAIT
= 0x20 | EXT_CP0
,
220 const unsigned char *regnames
[] =
221 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
222 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
223 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
224 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
226 /* Warning: no function for r0 register (hard wired to zero) */
227 #define GEN32(func, NAME) \
228 static GenOpFunc *NAME ## _table [32] = { \
229 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
230 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
231 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
232 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
233 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
234 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
235 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
236 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
238 static inline void func(int n) \
240 NAME ## _table[n](); \
243 /* General purpose registers moves */
244 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
245 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
246 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
248 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
249 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
251 typedef struct DisasContext
{
252 struct TranslationBlock
*tb
;
253 target_ulong pc
, saved_pc
;
255 /* Routine used to access memory */
257 uint32_t hflags
, saved_hflags
;
260 target_ulong btarget
;
264 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
265 * exception condition
267 BS_STOP
= 1, /* We want to stop translation for any reason */
268 BS_BRANCH
= 2, /* We reached a branch condition */
269 BS_EXCP
= 3, /* We reached an exception condition */
272 #if defined MIPS_DEBUG_DISAS
273 #define MIPS_DEBUG(fmt, args...) \
275 if (loglevel & CPU_LOG_TB_IN_ASM) { \
276 fprintf(logfile, "%08x: %08x " fmt "\n", \
277 ctx->pc, ctx->opcode , ##args); \
281 #define MIPS_DEBUG(fmt, args...) do { } while(0)
284 #define MIPS_INVAL(op) \
286 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
287 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
290 #define GEN_LOAD_REG_TN(Tn, Rn) \
293 glue(gen_op_reset_, Tn)(); \
295 glue(gen_op_load_gpr_, Tn)(Rn); \
299 #define GEN_LOAD_IMM_TN(Tn, Imm) \
302 glue(gen_op_reset_, Tn)(); \
304 glue(gen_op_set_, Tn)(Imm); \
308 #define GEN_STORE_TN_REG(Rn, Tn) \
311 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
315 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
317 #if defined MIPS_DEBUG_DISAS
318 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
319 fprintf(logfile
, "hflags %08x saved %08x\n",
320 ctx
->hflags
, ctx
->saved_hflags
);
323 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
324 gen_op_save_pc(ctx
->pc
);
325 ctx
->saved_pc
= ctx
->pc
;
327 if (ctx
->hflags
!= ctx
->saved_hflags
) {
328 gen_op_save_state(ctx
->hflags
);
329 ctx
->saved_hflags
= ctx
->hflags
;
330 if (ctx
->hflags
& MIPS_HFLAG_BR
) {
331 gen_op_save_breg_target();
332 } else if (ctx
->hflags
& MIPS_HFLAG_B
) {
333 gen_op_save_btarget(ctx
->btarget
);
334 } else if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
336 gen_op_save_btarget(ctx
->btarget
);
341 static inline void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
343 #if defined MIPS_DEBUG_DISAS
344 if (loglevel
& CPU_LOG_TB_IN_ASM
)
345 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
347 save_cpu_state(ctx
, 1);
349 gen_op_raise_exception(excp
);
351 gen_op_raise_exception_err(excp
, err
);
352 ctx
->bstate
= BS_EXCP
;
355 static inline void generate_exception (DisasContext
*ctx
, int excp
)
357 generate_exception_err (ctx
, excp
, 0);
360 #if defined(CONFIG_USER_ONLY)
361 #define op_ldst(name) gen_op_##name##_raw()
362 #define OP_LD_TABLE(width)
363 #define OP_ST_TABLE(width)
365 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
366 #define OP_LD_TABLE(width) \
367 static GenOpFunc *gen_op_l##width[] = { \
368 &gen_op_l##width##_user, \
369 &gen_op_l##width##_kernel, \
371 #define OP_ST_TABLE(width) \
372 static GenOpFunc *gen_op_s##width[] = { \
373 &gen_op_s##width##_user, \
374 &gen_op_s##width##_kernel, \
402 static void gen_ldst (DisasContext
*ctx
, uint16_t opc
, int rt
,
403 int base
, int16_t offset
)
405 const unsigned char *opn
= "unk";
408 GEN_LOAD_IMM_TN(T0
, offset
);
409 } else if (offset
== 0) {
410 gen_op_load_gpr_T0(base
);
412 gen_op_load_gpr_T0(base
);
413 gen_op_set_T1(offset
);
416 /* Don't do NOP if destination is zero: we must perform the actual
420 #if defined(TARGET_MIPS64)
422 #if defined (MIPS_HAS_UNALIGNED_LS)
426 GEN_STORE_TN_REG(rt
, T0
);
430 #if defined (MIPS_HAS_UNALIGNED_LS)
433 GEN_LOAD_REG_TN(T1
, rt
);
439 GEN_STORE_TN_REG(rt
, T0
);
443 GEN_LOAD_REG_TN(T1
, rt
);
449 GEN_STORE_TN_REG(rt
, T0
);
453 GEN_LOAD_REG_TN(T1
, rt
);
459 #if defined (MIPS_HAS_UNALIGNED_LS)
463 GEN_STORE_TN_REG(rt
, T0
);
467 #if defined (MIPS_HAS_UNALIGNED_LS)
470 GEN_LOAD_REG_TN(T1
, rt
);
475 #if defined (MIPS_HAS_UNALIGNED_LS)
479 GEN_STORE_TN_REG(rt
, T0
);
483 #if defined (MIPS_HAS_UNALIGNED_LS)
486 GEN_LOAD_REG_TN(T1
, rt
);
491 #if defined (MIPS_HAS_UNALIGNED_LS)
495 GEN_STORE_TN_REG(rt
, T0
);
500 GEN_STORE_TN_REG(rt
, T0
);
504 GEN_LOAD_REG_TN(T1
, rt
);
510 GEN_STORE_TN_REG(rt
, T0
);
514 GEN_LOAD_REG_TN(T1
, rt
);
516 GEN_STORE_TN_REG(rt
, T0
);
520 GEN_LOAD_REG_TN(T1
, rt
);
525 GEN_LOAD_REG_TN(T1
, rt
);
527 GEN_STORE_TN_REG(rt
, T0
);
531 GEN_LOAD_REG_TN(T1
, rt
);
537 GEN_STORE_TN_REG(rt
, T0
);
541 GEN_LOAD_REG_TN(T1
, rt
);
543 GEN_STORE_TN_REG(rt
, T0
);
547 MIPS_INVAL("load/store");
548 generate_exception(ctx
, EXCP_RI
);
551 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
554 /* Arithmetic with immediate operand */
555 static void gen_arith_imm (DisasContext
*ctx
, uint16_t opc
, int rt
,
559 const unsigned char *opn
= "unk";
561 if (rt
== 0 && opc
!= OPC_ADDI
) {
562 /* if no destination, treat it as a NOP
563 * For addi, we must generate the overflow exception when needed.
568 if (opc
== OPC_ADDI
|| opc
== OPC_ADDIU
||
569 opc
== OPC_SLTI
|| opc
== OPC_SLTIU
)
570 uimm
= (int32_t)imm
; /* Sign extent to 32 bits */
572 uimm
= (uint16_t)imm
;
573 if (opc
!= OPC_LUI
) {
574 GEN_LOAD_REG_TN(T0
, rs
);
575 GEN_LOAD_IMM_TN(T1
, uimm
);
578 GEN_LOAD_IMM_TN(T0
, uimm
);
582 save_cpu_state(ctx
, 1);
626 MIPS_INVAL("imm arith");
627 generate_exception(ctx
, EXCP_RI
);
630 GEN_STORE_TN_REG(rt
, T0
);
631 MIPS_DEBUG("%s %s, %s, %x", opn
, regnames
[rt
], regnames
[rs
], uimm
);
635 static void gen_arith (DisasContext
*ctx
, uint16_t opc
,
636 int rd
, int rs
, int rt
)
638 const unsigned char *opn
= "unk";
640 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
) {
641 /* if no destination, treat it as a NOP
642 * For add & sub, we must generate the overflow exception when needed.
647 GEN_LOAD_REG_TN(T0
, rs
);
648 GEN_LOAD_REG_TN(T1
, rt
);
651 save_cpu_state(ctx
, 1);
660 save_cpu_state(ctx
, 1);
718 generate_exception(ctx
, EXCP_RI
);
721 GEN_STORE_TN_REG(rd
, T0
);
723 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
726 /* Arithmetic on HI/LO registers */
727 static void gen_HILO (DisasContext
*ctx
, uint16_t opc
, int reg
)
729 const unsigned char *opn
= "unk";
731 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
739 GEN_STORE_TN_REG(reg
, T0
);
744 GEN_STORE_TN_REG(reg
, T0
);
748 GEN_LOAD_REG_TN(T0
, reg
);
753 GEN_LOAD_REG_TN(T0
, reg
);
759 generate_exception(ctx
, EXCP_RI
);
762 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
765 static void gen_muldiv (DisasContext
*ctx
, uint16_t opc
,
768 const unsigned char *opn
= "unk";
770 GEN_LOAD_REG_TN(T0
, rs
);
771 GEN_LOAD_REG_TN(T1
, rt
);
806 MIPS_INVAL("mul/div");
807 generate_exception(ctx
, EXCP_RI
);
810 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
813 static void gen_cl (DisasContext
*ctx
, uint16_t opc
,
816 const unsigned char *opn
= "unk";
822 GEN_LOAD_REG_TN(T0
, rs
);
836 generate_exception(ctx
, EXCP_RI
);
839 gen_op_store_T0_gpr(rd
);
840 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
844 static void gen_trap (DisasContext
*ctx
, uint16_t opc
,
845 int rs
, int rt
, int16_t imm
)
850 /* Load needed operands */
858 /* Compare two registers */
860 GEN_LOAD_REG_TN(T0
, rs
);
861 GEN_LOAD_REG_TN(T1
, rt
);
870 /* Compare register to immediate */
871 if (rs
!= 0 || imm
!= 0) {
872 GEN_LOAD_REG_TN(T0
, rs
);
873 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
880 case OPC_TEQ
: /* rs == rs */
881 case OPC_TEQI
: /* r0 == 0 */
882 case OPC_TGE
: /* rs >= rs */
883 case OPC_TGEI
: /* r0 >= 0 */
884 case OPC_TGEU
: /* rs >= rs unsigned */
885 case OPC_TGEIU
: /* r0 >= 0 unsigned */
889 case OPC_TLT
: /* rs < rs */
890 case OPC_TLTI
: /* r0 < 0 */
891 case OPC_TLTU
: /* rs < rs unsigned */
892 case OPC_TLTIU
: /* r0 < 0 unsigned */
893 case OPC_TNE
: /* rs != rs */
894 case OPC_TNEI
: /* r0 != 0 */
895 /* Never trap: treat as NOP */
899 generate_exception(ctx
, EXCP_RI
);
930 generate_exception(ctx
, EXCP_RI
);
934 save_cpu_state(ctx
, 1);
936 ctx
->bstate
= BS_STOP
;
939 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
941 TranslationBlock
*tb
;
943 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
945 gen_op_goto_tb0(TBPARAM(tb
));
947 gen_op_goto_tb1(TBPARAM(tb
));
948 gen_op_save_pc(dest
);
949 gen_op_set_T0((long)tb
+ n
);
952 gen_op_save_pc(dest
);
958 /* Branches (before delay slot) */
959 static void gen_compute_branch (DisasContext
*ctx
, uint16_t opc
,
960 int rs
, int rt
, int32_t offset
)
962 target_ulong btarget
;
968 /* Load needed operands */
974 /* Compare two registers */
976 GEN_LOAD_REG_TN(T0
, rs
);
977 GEN_LOAD_REG_TN(T1
, rt
);
980 btarget
= ctx
->pc
+ 4 + offset
;
994 /* Compare to zero */
996 gen_op_load_gpr_T0(rs
);
999 btarget
= ctx
->pc
+ 4 + offset
;
1003 /* Jump to immediate */
1004 btarget
= ((ctx
->pc
+ 4) & 0xF0000000) | offset
;
1008 /* Jump to register */
1010 /* Only hint = 0 is valid */
1011 generate_exception(ctx
, EXCP_RI
);
1014 GEN_LOAD_REG_TN(T2
, rs
);
1017 MIPS_INVAL("branch/jump");
1018 generate_exception(ctx
, EXCP_RI
);
1022 /* No condition to be computed */
1024 case OPC_BEQ
: /* rx == rx */
1025 case OPC_BEQL
: /* rx == rx likely */
1026 case OPC_BGEZ
: /* 0 >= 0 */
1027 case OPC_BGEZL
: /* 0 >= 0 likely */
1028 case OPC_BLEZ
: /* 0 <= 0 */
1029 case OPC_BLEZL
: /* 0 <= 0 likely */
1031 ctx
->hflags
|= MIPS_HFLAG_B
;
1032 MIPS_DEBUG("balways");
1034 case OPC_BGEZAL
: /* 0 >= 0 */
1035 case OPC_BGEZALL
: /* 0 >= 0 likely */
1036 /* Always take and link */
1038 ctx
->hflags
|= MIPS_HFLAG_B
;
1039 MIPS_DEBUG("balways and link");
1041 case OPC_BNE
: /* rx != rx */
1042 case OPC_BGTZ
: /* 0 > 0 */
1043 case OPC_BLTZ
: /* 0 < 0 */
1044 /* Treated as NOP */
1045 MIPS_DEBUG("bnever (NOP)");
1047 case OPC_BLTZAL
: /* 0 < 0 */
1048 gen_op_set_T0(ctx
->pc
+ 8);
1049 gen_op_store_T0_gpr(31);
1051 case OPC_BLTZALL
: /* 0 < 0 likely */
1052 gen_op_set_T0(ctx
->pc
+ 8);
1053 gen_op_store_T0_gpr(31);
1054 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1056 case OPC_BNEL
: /* rx != rx likely */
1057 case OPC_BGTZL
: /* 0 > 0 likely */
1058 case OPC_BLTZL
: /* 0 < 0 likely */
1059 /* Skip the instruction in the delay slot */
1060 MIPS_DEBUG("bnever and skip");
1061 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1064 ctx
->hflags
|= MIPS_HFLAG_B
;
1065 MIPS_DEBUG("j %08x", btarget
);
1069 ctx
->hflags
|= MIPS_HFLAG_B
;
1070 MIPS_DEBUG("jal %08x", btarget
);
1073 ctx
->hflags
|= MIPS_HFLAG_BR
;
1074 MIPS_DEBUG("jr %s", regnames
[rs
]);
1078 ctx
->hflags
|= MIPS_HFLAG_BR
;
1079 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1082 MIPS_INVAL("branch/jump");
1083 generate_exception(ctx
, EXCP_RI
);
1090 MIPS_DEBUG("beq %s, %s, %08x",
1091 regnames
[rs
], regnames
[rt
], btarget
);
1095 MIPS_DEBUG("beql %s, %s, %08x",
1096 regnames
[rs
], regnames
[rt
], btarget
);
1100 MIPS_DEBUG("bne %s, %s, %08x",
1101 regnames
[rs
], regnames
[rt
], btarget
);
1105 MIPS_DEBUG("bnel %s, %s, %08x",
1106 regnames
[rs
], regnames
[rt
], btarget
);
1110 MIPS_DEBUG("bgez %s, %08x", regnames
[rs
], btarget
);
1114 MIPS_DEBUG("bgezl %s, %08x", regnames
[rs
], btarget
);
1118 MIPS_DEBUG("bgezal %s, %08x", regnames
[rs
], btarget
);
1124 MIPS_DEBUG("bgezall %s, %08x", regnames
[rs
], btarget
);
1128 MIPS_DEBUG("bgtz %s, %08x", regnames
[rs
], btarget
);
1132 MIPS_DEBUG("bgtzl %s, %08x", regnames
[rs
], btarget
);
1136 MIPS_DEBUG("blez %s, %08x", regnames
[rs
], btarget
);
1140 MIPS_DEBUG("blezl %s, %08x", regnames
[rs
], btarget
);
1144 MIPS_DEBUG("bltz %s, %08x", regnames
[rs
], btarget
);
1148 MIPS_DEBUG("bltzl %s, %08x", regnames
[rs
], btarget
);
1153 MIPS_DEBUG("bltzal %s, %08x", regnames
[rs
], btarget
);
1155 ctx
->hflags
|= MIPS_HFLAG_BC
;
1160 MIPS_DEBUG("bltzall %s, %08x", regnames
[rs
], btarget
);
1162 ctx
->hflags
|= MIPS_HFLAG_BL
;
1167 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1168 blink
, ctx
->hflags
, btarget
);
1169 ctx
->btarget
= btarget
;
1171 gen_op_set_T0(ctx
->pc
+ 8);
1172 gen_op_store_T0_gpr(blink
);
1177 /* CP0 (MMU and control) */
1178 static void gen_cp0 (DisasContext
*ctx
, uint16_t opc
, int rt
, int rd
)
1180 const unsigned char *opn
= "unk";
1182 if (!(ctx
->CP0_Status
& (1 << CP0St_CU0
)) &&
1183 (ctx
->hflags
& MIPS_HFLAG_UM
) &&
1184 !(ctx
->hflags
& MIPS_HFLAG_ERL
) &&
1185 !(ctx
->hflags
& MIPS_HFLAG_EXL
)) {
1186 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1187 fprintf(logfile
, "CP0 is not usable\n");
1189 generate_exception_err (ctx
, EXCP_CpU
, 0);
1198 gen_op_mfc0(rd
, ctx
->opcode
& 0x7);
1199 gen_op_store_T0_gpr(rt
);
1203 /* If we get an exception, we want to restart at next instruction */
1205 save_cpu_state(ctx
, 1);
1207 GEN_LOAD_REG_TN(T0
, rt
);
1208 gen_op_mtc0(rd
, ctx
->opcode
& 0x7);
1209 /* Stop translation as we may have switched the execution mode */
1210 ctx
->bstate
= BS_STOP
;
1213 #if defined(MIPS_USES_R4K_TLB)
1233 save_cpu_state(ctx
, 0);
1235 ctx
->bstate
= BS_EXCP
;
1239 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
1240 generate_exception(ctx
, EXCP_RI
);
1242 save_cpu_state(ctx
, 0);
1244 ctx
->bstate
= BS_EXCP
;
1249 /* If we get an exception, we want to restart at next instruction */
1251 save_cpu_state(ctx
, 1);
1254 ctx
->bstate
= BS_EXCP
;
1257 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1258 fprintf(logfile
, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
1259 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
1260 ((ctx
->opcode
>> 16) & 0x1F));
1262 generate_exception(ctx
, EXCP_RI
);
1265 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
1268 /* Coprocessor 1 (FPU) */
1270 /* ISA extensions */
1271 /* MIPS16 extension to MIPS32 */
1272 /* SmartMIPS extension to MIPS32 */
1274 #ifdef TARGET_MIPS64
1275 static void gen_arith64 (DisasContext
*ctx
, uint16_t opc
)
1277 if (func
== 0x02 && rd
== 0) {
1281 if (rs
== 0 || rt
== 0) {
1285 gen_op_load_gpr_T0(rs
);
1286 gen_op_load_gpr_T1(rt
);
1299 /* Coprocessor 3 (FPU) */
1301 /* MDMX extension to MIPS64 */
1302 /* MIPS-3D extension to MIPS64 */
1306 static void gen_blikely(DisasContext
*ctx
)
1309 l1
= gen_new_label();
1311 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
1312 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
1316 static void decode_opc (DisasContext
*ctx
)
1323 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
1324 /* Handle blikely not taken case */
1325 MIPS_DEBUG("blikely condition (%08x)", ctx
->pc
+ 4);
1328 op
= ctx
->opcode
>> 26;
1329 rs
= ((ctx
->opcode
>> 21) & 0x1F);
1330 rt
= ((ctx
->opcode
>> 16) & 0x1F);
1331 rd
= ((ctx
->opcode
>> 11) & 0x1F);
1332 sa
= ((ctx
->opcode
>> 6) & 0x1F);
1333 imm
= (int16_t)ctx
->opcode
;
1335 case 0x00: /* Special opcode */
1336 op1
= ctx
->opcode
& 0x3F;
1338 case 0x00: /* Arithmetic with immediate */
1340 gen_arith_imm(ctx
, op1
| EXT_SPECIAL
, rd
, rt
, sa
);
1342 case 0x04: /* Arithmetic */
1347 gen_arith(ctx
, op1
| EXT_SPECIAL
, rd
, rs
, rt
);
1349 case 0x18 ... 0x1B: /* MULT / DIV */
1350 gen_muldiv(ctx
, op1
| EXT_SPECIAL
, rs
, rt
);
1352 case 0x08 ... 0x09: /* Jumps */
1353 gen_compute_branch(ctx
, op1
| EXT_SPECIAL
, rs
, rd
, sa
);
1355 case 0x30 ... 0x34: /* Traps */
1357 gen_trap(ctx
, op1
| EXT_SPECIAL
, rs
, rt
, -1);
1359 case 0x10: /* Move from HI/LO */
1361 gen_HILO(ctx
, op1
| EXT_SPECIAL
, rd
);
1364 case 0x13: /* Move to HI/LO */
1365 gen_HILO(ctx
, op1
| EXT_SPECIAL
, rs
);
1367 case 0x0C: /* SYSCALL */
1368 generate_exception(ctx
, EXCP_SYSCALL
);
1370 case 0x0D: /* BREAK */
1371 generate_exception(ctx
, EXCP_BREAK
);
1373 case 0x0F: /* SYNC */
1374 /* Treat as a noop */
1376 case 0x05: /* Pmon entry point */
1377 gen_op_pmon((ctx
->opcode
>> 6) & 0x1F);
1380 case 0x01: /* MOVCI */
1381 #if defined (MIPS_HAS_MOVCI)
1384 /* Not implemented */
1385 generate_exception_err (ctx
, EXCP_CpU
, 1);
1389 #if defined (TARGET_MIPS64)
1390 case 0x14: /* MIPS64 specific opcodes */
1399 default: /* Invalid */
1400 MIPS_INVAL("special");
1401 generate_exception(ctx
, EXCP_RI
);
1405 case 0x1C: /* Special2 opcode */
1406 op1
= ctx
->opcode
& 0x3F;
1408 #if defined (MIPS_USES_R4K_EXT)
1409 /* Those instructions are not part of MIPS32 core */
1410 case 0x00 ... 0x01: /* Multiply and add/sub */
1412 gen_muldiv(ctx
, op1
| EXT_SPECIAL2
, rs
, rt
);
1414 case 0x02: /* MUL */
1415 gen_arith(ctx
, op1
| EXT_SPECIAL2
, rd
, rs
, rt
);
1417 case 0x20 ... 0x21: /* CLO / CLZ */
1418 gen_cl(ctx
, op1
| EXT_SPECIAL2
, rd
, rs
);
1421 case 0x3F: /* SDBBP */
1422 /* XXX: not clear which exception should be raised
1423 * when in debug mode...
1425 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
1426 generate_exception(ctx
, EXCP_DBp
);
1428 generate_exception(ctx
, EXCP_DBp
);
1430 /* Treat as a noop */
1432 default: /* Invalid */
1433 MIPS_INVAL("special2");
1434 generate_exception(ctx
, EXCP_RI
);
1438 case 0x01: /* B REGIMM opcode */
1439 op1
= ((ctx
->opcode
>> 16) & 0x1F);
1441 case 0x00 ... 0x03: /* REGIMM branches */
1443 gen_compute_branch(ctx
, op1
| EXT_REGIMM
, rs
, -1, imm
<< 2);
1445 case 0x08 ... 0x0C: /* Traps */
1447 gen_trap(ctx
, op1
| EXT_REGIMM
, rs
, -1, imm
);
1449 default: /* Invalid */
1450 MIPS_INVAL("REGIMM");
1451 generate_exception(ctx
, EXCP_RI
);
1455 case 0x10: /* CP0 opcode */
1456 op1
= ((ctx
->opcode
>> 21) & 0x1F);
1460 gen_cp0(ctx
, op1
| EXT_CP0
, rt
, rd
);
1463 gen_cp0(ctx
, (ctx
->opcode
& 0x3F) | EXT_CP0
, rt
, rd
);
1467 case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
1468 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
1470 case 0x02 ... 0x03: /* Jump */
1471 offset
= (int32_t)(ctx
->opcode
& 0x03FFFFFF) << 2;
1472 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
1474 case 0x04 ... 0x07: /* Branch */
1476 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
1478 case 0x20 ... 0x26: /* Load and stores */
1482 gen_ldst(ctx
, op
, rt
, rs
, imm
);
1484 case 0x2F: /* Cache operation */
1485 /* Treat as a noop */
1487 case 0x33: /* Prefetch */
1488 /* Treat as a noop */
1490 case 0x3F: /* HACK */
1493 /* Floating point. */
1494 case 0x31: /* LWC1 */
1495 case 0x35: /* LDC1 */
1496 case 0x39: /* SWC1 */
1497 case 0x3D: /* SDC1 */
1498 case 0x11: /* CP1 opcode */
1499 #if defined(MIPS_USES_FPU)
1500 /* XXX: not correct */
1502 generate_exception_err(ctx
, EXCP_CpU
, 1);
1507 case 0x32: /* LWC2 */
1508 case 0x36: /* LDC2 */
1509 case 0x3A: /* SWC2 */
1510 case 0x3E: /* SDC2 */
1511 case 0x12: /* CP2 opcode */
1512 /* Not implemented */
1513 generate_exception_err(ctx
, EXCP_CpU
, 2);
1516 case 0x13: /* CP3 opcode */
1517 /* Not implemented */
1518 generate_exception_err(ctx
, EXCP_CpU
, 3);
1521 #if defined (TARGET_MIPS64)
1526 /* MIPS64 opcodes */
1528 #if defined (MIPS_HAS_JALX)
1530 /* JALX: not implemented */
1534 default: /* Invalid */
1536 generate_exception(ctx
, EXCP_RI
);
1539 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1540 int hflags
= ctx
->hflags
;
1541 /* Branches completion */
1542 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
1543 ctx
->bstate
= BS_BRANCH
;
1544 save_cpu_state(ctx
, 0);
1545 switch (hflags
& MIPS_HFLAG_BMASK
) {
1547 /* unconditional branch */
1548 MIPS_DEBUG("unconditional branch");
1549 gen_goto_tb(ctx
, 0, ctx
->btarget
);
1552 /* blikely taken case */
1553 MIPS_DEBUG("blikely branch taken");
1554 gen_goto_tb(ctx
, 0, ctx
->btarget
);
1557 /* Conditional branch */
1558 MIPS_DEBUG("conditional branch");
1561 l1
= gen_new_label();
1563 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
1565 gen_goto_tb(ctx
, 0, ctx
->btarget
);
1569 /* unconditional branch to register */
1570 MIPS_DEBUG("branch to register");
1574 MIPS_DEBUG("unknown branch");
1580 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
1583 DisasContext ctx
, *ctxp
= &ctx
;
1584 target_ulong pc_start
;
1585 uint16_t *gen_opc_end
;
1588 if (search_pc
&& loglevel
)
1589 fprintf (logfile
, "search pc %d\n", search_pc
);
1592 gen_opc_ptr
= gen_opc_buf
;
1593 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1594 gen_opparam_ptr
= gen_opparam_buf
;
1599 ctx
.bstate
= BS_NONE
;
1600 /* Restore delay slot state from the tb context. */
1601 ctx
.hflags
= tb
->flags
;
1602 ctx
.saved_hflags
= ctx
.hflags
;
1603 if (ctx
.hflags
& MIPS_HFLAG_BR
) {
1604 gen_op_restore_breg_target();
1605 } else if (ctx
.hflags
& MIPS_HFLAG_B
) {
1606 ctx
.btarget
= env
->btarget
;
1607 } else if (ctx
.hflags
& MIPS_HFLAG_BMASK
) {
1608 /* If we are in the delay slot of a conditional branch,
1609 * restore the branch condition from env->bcond to T2
1611 ctx
.btarget
= env
->btarget
;
1612 gen_op_restore_bcond();
1614 #if defined(CONFIG_USER_ONLY)
1617 ctx
.mem_idx
= (ctx
.hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
? 0 : 1;
1619 ctx
.CP0_Status
= env
->CP0_Status
;
1621 if (loglevel
& CPU_LOG_TB_CPU
) {
1622 fprintf(logfile
, "------------------------------------------------\n");
1623 /* FIXME: This may print out stale hflags from env... */
1624 cpu_dump_state(env
, logfile
, fprintf
, 0);
1627 #if defined MIPS_DEBUG_DISAS
1628 if (loglevel
& CPU_LOG_TB_IN_ASM
)
1629 fprintf(logfile
, "\ntb %p super %d cond %04x\n",
1630 tb
, ctx
.mem_idx
, ctx
.hflags
);
1632 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
1633 if (env
->nb_breakpoints
> 0) {
1634 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
1635 if (env
->breakpoints
[j
] == ctx
.pc
) {
1636 save_cpu_state(ctxp
, 1);
1637 ctx
.bstate
= BS_BRANCH
;
1639 goto done_generating
;
1645 j
= gen_opc_ptr
- gen_opc_buf
;
1649 gen_opc_instr_start
[lj
++] = 0;
1651 gen_opc_pc
[lj
] = ctx
.pc
;
1652 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
1653 gen_opc_instr_start
[lj
] = 1;
1655 ctx
.opcode
= ldl_code(ctx
.pc
);
1659 if (env
->singlestep_enabled
)
1662 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
1665 #if defined (MIPS_SINGLE_STEP)
1669 if (env
->singlestep_enabled
) {
1670 save_cpu_state(ctxp
, ctx
.bstate
== BS_NONE
);
1672 goto done_generating
;
1674 else if (ctx
.bstate
!= BS_BRANCH
&& ctx
.bstate
!= BS_EXCP
) {
1675 save_cpu_state(ctxp
, 0);
1676 gen_goto_tb(&ctx
, 0, ctx
.pc
);
1679 /* Generate the return instruction */
1682 *gen_opc_ptr
= INDEX_op_end
;
1684 j
= gen_opc_ptr
- gen_opc_buf
;
1687 gen_opc_instr_start
[lj
++] = 0;
1690 tb
->size
= ctx
.pc
- pc_start
;
1693 #if defined MIPS_DEBUG_DISAS
1694 if (loglevel
& CPU_LOG_TB_IN_ASM
)
1695 fprintf(logfile
, "\n");
1697 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1698 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
1699 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
1700 fprintf(logfile
, "\n");
1702 if (loglevel
& CPU_LOG_TB_OP
) {
1703 fprintf(logfile
, "OP:\n");
1704 dump_ops(gen_opc_buf
, gen_opparam_buf
);
1705 fprintf(logfile
, "\n");
1707 if (loglevel
& CPU_LOG_TB_CPU
) {
1708 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
1715 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
1717 return gen_intermediate_code_internal(env
, tb
, 0);
1720 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
1722 return gen_intermediate_code_internal(env
, tb
, 1);
1725 void cpu_dump_state (CPUState
*env
, FILE *f
,
1726 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1732 cpu_fprintf(f
, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
1733 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
1734 for (i
= 0; i
< 32; i
++) {
1736 cpu_fprintf(f
, "GPR%02d:", i
);
1737 cpu_fprintf(f
, " %s %08x", regnames
[i
], env
->gpr
[i
]);
1739 cpu_fprintf(f
, "\n");
1742 c0_status
= env
->CP0_Status
;
1743 if (env
->hflags
& MIPS_HFLAG_UM
)
1744 c0_status
|= (1 << CP0St_UM
);
1745 if (env
->hflags
& MIPS_HFLAG_ERL
)
1746 c0_status
|= (1 << CP0St_ERL
);
1747 if (env
->hflags
& MIPS_HFLAG_EXL
)
1748 c0_status
|= (1 << CP0St_EXL
);
1750 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
1751 c0_status
, env
->CP0_Cause
, env
->CP0_EPC
);
1752 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
1753 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
1756 CPUMIPSState
*cpu_mips_init (void)
1760 env
= qemu_mallocz(sizeof(CPUMIPSState
));
1766 env
->PC
= 0xBFC00000;
1767 #if defined (MIPS_USES_R4K_TLB)
1768 env
->CP0_random
= MIPS_TLB_NB
- 1;
1771 env
->CP0_Config0
= MIPS_CONFIG0
;
1772 #if defined (MIPS_CONFIG1)
1773 env
->CP0_Config1
= MIPS_CONFIG1
;
1775 #if defined (MIPS_CONFIG2)
1776 env
->CP0_Config2
= MIPS_CONFIG2
;
1778 #if defined (MIPS_CONFIG3)
1779 env
->CP0_Config3
= MIPS_CONFIG3
;
1781 env
->CP0_Status
= (1 << CP0St_CU0
) | (1 << CP0St_BEV
);
1782 env
->CP0_WatchLo
= 0;
1783 env
->hflags
= MIPS_HFLAG_ERL
;
1784 /* Count register increments in debug mode, EJTAG version 1 */
1785 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
1786 env
->CP0_PRid
= MIPS_CPU
;
1787 env
->exception_index
= EXCP_NONE
;
1788 #if defined(CONFIG_USER_ONLY)
1789 env
->hflags
|= MIPS_HFLAG_UM
;