2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #define MIPS_DEBUG_DISAS
24 #define GETPC() (__builtin_return_address(0))
26 /*****************************************************************************/
27 /* Exceptions processing helpers */
28 void cpu_loop_exit(void)
30 longjmp(env
->jmp_env
, 1);
33 void do_raise_exception_err (uint32_t exception
, int error_code
)
36 if (logfile
&& exception
< 0x100)
37 fprintf(logfile
, "%s: %d %d\n", __func__
, exception
, error_code
);
39 env
->exception_index
= exception
;
40 env
->error_code
= error_code
;
45 void do_raise_exception (uint32_t exception
)
47 do_raise_exception_err(exception
, 0);
50 void do_restore_state (void *pc_ptr
)
53 unsigned long pc
= (unsigned long) pc_ptr
;
56 cpu_restore_state (tb
, env
, pc
, NULL
);
59 void do_raise_exception_direct (uint32_t exception
)
61 do_restore_state (GETPC ());
62 do_raise_exception_err (exception
, 0);
65 #define MEMSUFFIX _raw
66 #include "op_helper_mem.c"
68 #if !defined(CONFIG_USER_ONLY)
69 #define MEMSUFFIX _user
70 #include "op_helper_mem.c"
72 #define MEMSUFFIX _kernel
73 #include "op_helper_mem.c"
77 /* 64 bits arithmetic for 32 bits hosts */
78 #if (HOST_LONG_BITS == 32)
79 static inline uint64_t get_HILO (void)
81 return ((uint64_t)env
->HI
<< 32) | (uint64_t)env
->LO
;
84 static inline void set_HILO (uint64_t HILO
)
86 env
->LO
= HILO
& 0xFFFFFFFF;
92 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
97 set_HILO((uint64_t)T0
* (uint64_t)T1
);
104 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
105 set_HILO((int64_t)get_HILO() + tmp
);
112 tmp
= ((uint64_t)T0
* (uint64_t)T1
);
113 set_HILO(get_HILO() + tmp
);
120 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
121 set_HILO((int64_t)get_HILO() - tmp
);
128 tmp
= ((uint64_t)T0
* (uint64_t)T1
);
129 set_HILO(get_HILO() - tmp
);
133 #if defined(CONFIG_USER_ONLY)
134 void do_mfc0 (int reg
, int sel
)
136 cpu_abort(env
, "mfc0 reg=%d sel=%d\n", reg
, sel
);
138 void do_mtc0 (int reg
, int sel
)
140 cpu_abort(env
, "mtc0 reg=%d sel=%d\n", reg
, sel
);
145 cpu_abort(env
, "tlbwi\n");
150 cpu_abort(env
, "tlbwr\n");
155 cpu_abort(env
, "tlbp\n");
160 cpu_abort(env
, "tlbr\n");
165 void do_mfc0 (int reg
, int sel
)
167 const unsigned char *rn
;
169 if (sel
!= 0 && reg
!= 16 && reg
!= 28) {
179 T0
= cpu_mips_get_random(env
);
183 T0
= env
->CP0_EntryLo0
;
187 T0
= env
->CP0_EntryLo1
;
191 T0
= env
->CP0_Context
;
195 T0
= env
->CP0_PageMask
;
203 T0
= env
->CP0_BadVAddr
;
207 T0
= cpu_mips_get_count(env
);
211 T0
= env
->CP0_EntryHi
;
215 T0
= env
->CP0_Compare
;
219 T0
= env
->CP0_Status
;
220 if (env
->hflags
& MIPS_HFLAG_UM
)
221 T0
|= (1 << CP0St_UM
);
222 if (env
->hflags
& MIPS_HFLAG_ERL
)
223 T0
|= (1 << CP0St_ERL
);
224 if (env
->hflags
& MIPS_HFLAG_EXL
)
225 T0
|= (1 << CP0St_EXL
);
243 T0
= env
->CP0_Config0
;
247 T0
= env
->CP0_Config1
;
251 rn
= "Unknown config register";
256 T0
= env
->CP0_LLAddr
>> 4;
260 T0
= env
->CP0_WatchLo
;
264 T0
= env
->CP0_WatchHi
;
269 if (env
->hflags
& MIPS_HFLAG_DM
)
284 T0
= env
->CP0_DataLo
;
293 T0
= env
->CP0_ErrorEPC
;
297 T0
= env
->CP0_DESAVE
;
305 #if defined MIPS_DEBUG_DISAS
306 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
307 fprintf(logfile
, "%08x mfc0 %s => %08x (%d %d)\n",
308 env
->PC
, rn
, T0
, reg
, sel
);
314 void do_mtc0 (int reg
, int sel
)
316 const unsigned char *rn
;
317 uint32_t val
, old
, mask
;
319 if (sel
!= 0 && reg
!= 16 && reg
!= 28) {
327 val
= (env
->CP0_index
& 0x80000000) | (T0
& 0x0000000F);
328 old
= env
->CP0_index
;
329 env
->CP0_index
= val
;
333 val
= T0
& 0x03FFFFFFF;
334 old
= env
->CP0_EntryLo0
;
335 env
->CP0_EntryLo0
= val
;
339 val
= T0
& 0x03FFFFFFF;
340 old
= env
->CP0_EntryLo1
;
341 env
->CP0_EntryLo1
= val
;
345 val
= (env
->CP0_Context
& 0xFF000000) | (T0
& 0x00FFFFF0);
346 old
= env
->CP0_Context
;
347 env
->CP0_Context
= val
;
351 val
= T0
& 0x01FFE000;
352 old
= env
->CP0_PageMask
;
353 env
->CP0_PageMask
= val
;
357 val
= T0
& 0x0000000F;
358 old
= env
->CP0_Wired
;
359 env
->CP0_Wired
= val
;
364 old
= cpu_mips_get_count(env
);
365 cpu_mips_store_count(env
, val
);
369 val
= T0
& 0xFFFFF0FF;
370 old
= env
->CP0_EntryHi
;
371 env
->CP0_EntryHi
= val
;
372 /* If the ASID changes, flush qemu's TLB. */
373 if ((old
& 0xFF) != (val
& 0xFF))
379 old
= env
->CP0_Compare
;
380 cpu_mips_store_compare(env
, val
);
384 val
= T0
& 0xFA78FF01;
385 if (T0
& (1 << CP0St_UM
))
386 env
->hflags
|= MIPS_HFLAG_UM
;
388 env
->hflags
&= ~MIPS_HFLAG_UM
;
389 if (T0
& (1 << CP0St_ERL
))
390 env
->hflags
|= MIPS_HFLAG_ERL
;
392 env
->hflags
&= ~MIPS_HFLAG_ERL
;
393 if (T0
& (1 << CP0St_EXL
))
394 env
->hflags
|= MIPS_HFLAG_EXL
;
396 env
->hflags
&= ~MIPS_HFLAG_EXL
;
397 old
= env
->CP0_Status
;
398 env
->CP0_Status
= val
;
399 /* If we unmasked an asserted IRQ, raise it */
401 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
402 fprintf(logfile
, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
403 old
, val
, env
->CP0_Cause
, old
& mask
, val
& mask
,
404 env
->CP0_Cause
& mask
);
407 if ((val
& (1 << CP0St_IE
)) && !(old
& (1 << CP0St_IE
)) &&
408 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
409 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
410 !(env
->hflags
& MIPS_HFLAG_DM
) &&
411 (env
->CP0_Status
& env
->CP0_Cause
& mask
)) {
413 fprintf(logfile
, "Raise pending IRQs\n");
414 env
->interrupt_request
|= CPU_INTERRUPT_HARD
;
415 do_raise_exception(EXCP_EXT_INTERRUPT
);
416 } else if (!(val
& 0x00000001) && (old
& 0x00000001)) {
417 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
423 val
= (env
->CP0_Cause
& 0xB000F87C) | (T0
& 0x000C00300);
424 old
= env
->CP0_Cause
;
425 env
->CP0_Cause
= val
;
429 /* Check if we ever asserted a software IRQ */
430 for (i
= 0; i
< 2; i
++) {
432 if ((val
& mask
) & !(old
& mask
))
448 #if defined(MIPS_USES_R4K_TLB)
449 val
= (env
->CP0_Config0
& 0x8017FF80) | (T0
& 0x7E000001);
451 val
= (env
->CP0_Config0
& 0xFE17FF80) | (T0
& 0x00000001);
453 old
= env
->CP0_Config0
;
454 env
->CP0_Config0
= val
;
460 rn
= "bad config selector";
466 old
= env
->CP0_WatchLo
;
467 env
->CP0_WatchLo
= val
;
471 val
= T0
& 0x40FF0FF8;
472 old
= env
->CP0_WatchHi
;
473 env
->CP0_WatchHi
= val
;
477 val
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
478 if (T0
& (1 << CP0DB_DM
))
479 env
->hflags
|= MIPS_HFLAG_DM
;
481 env
->hflags
&= ~MIPS_HFLAG_DM
;
482 old
= env
->CP0_Debug
;
483 env
->CP0_Debug
= val
;
495 val
= T0
& 0xFFFFFCF6;
496 old
= env
->CP0_TagLo
;
497 env
->CP0_TagLo
= val
;
509 old
= env
->CP0_ErrorEPC
;
510 env
->CP0_ErrorEPC
= val
;
515 old
= env
->CP0_DESAVE
;
516 env
->CP0_DESAVE
= val
;
526 #if defined MIPS_DEBUG_DISAS
527 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
528 fprintf(logfile
, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
529 env
->PC
, rn
, T0
, val
, reg
, sel
, old
);
536 #if defined(MIPS_USES_R4K_TLB)
537 static void invalidate_tlb (int idx
)
542 tlb
= &env
->tlb
[idx
];
544 tb_invalidate_page_range(tlb
->PFN
[0], tlb
->end
- tlb
->VPN
);
546 while (addr
< tlb
->end
) {
547 tlb_flush_page (env
, addr
);
548 addr
+= TARGET_PAGE_SIZE
;
552 tb_invalidate_page_range(tlb
->PFN
[1], tlb
->end2
- tlb
->end
);
554 while (addr
< tlb
->end2
) {
555 tlb_flush_page (env
, addr
);
556 addr
+= TARGET_PAGE_SIZE
;
561 static void fill_tlb (int idx
)
566 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
567 tlb
= &env
->tlb
[idx
];
568 tlb
->VPN
= env
->CP0_EntryHi
& 0xFFFFE000;
569 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
570 size
= env
->CP0_PageMask
>> 13;
571 size
= 4 * (size
+ 1);
572 tlb
->end
= tlb
->VPN
+ (1 << (8 + size
));
573 tlb
->end2
= tlb
->end
+ (1 << (8 + size
));
574 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
575 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
576 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
577 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
578 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
579 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
580 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
581 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
582 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
587 /* Wildly undefined effects for CP0_index containing a too high value and
588 MIPS_TLB_NB not being a power of two. But so does real silicon. */
589 invalidate_tlb(env
->CP0_index
& (MIPS_TLB_NB
- 1));
590 fill_tlb(env
->CP0_index
& (MIPS_TLB_NB
- 1));
595 int r
= cpu_mips_get_random(env
);
608 tag
= (env
->CP0_EntryHi
& 0xFFFFE000);
609 ASID
= env
->CP0_EntryHi
& 0x000000FF;
610 for (i
= 0; i
< MIPS_TLB_NB
; i
++) {
612 /* Check ASID, virtual page number & size */
613 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && tlb
->VPN
== tag
) {
619 if (i
== MIPS_TLB_NB
) {
620 env
->CP0_index
|= 0x80000000;
630 ASID
= env
->CP0_EntryHi
& 0xFF;
631 tlb
= &env
->tlb
[env
->CP0_index
& (MIPS_TLB_NB
- 1)];
633 /* If this will change the current ASID, flush qemu's TLB. */
634 if (ASID
!= tlb
->ASID
&& tlb
->G
!= 1)
637 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
638 size
= (tlb
->end
- tlb
->VPN
) >> 12;
639 env
->CP0_PageMask
= (size
- 1) << 13;
640 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2)
641 | (tlb
->C0
<< 3) | (tlb
->PFN
[0] >> 6);
642 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2)
643 | (tlb
->C1
<< 3) | (tlb
->PFN
[1] >> 6);
647 #endif /* !CONFIG_USER_ONLY */
649 void op_dump_ldst (const unsigned char *func
)
652 fprintf(logfile
, "%s => %08x %08x\n", __func__
, T0
, T1
);
658 fprintf(logfile
, "%s %08x at %08x (%08x)\n", __func__
,
659 T1
, T0
, env
->CP0_LLAddr
);
663 void debug_eret (void)
666 fprintf(logfile
, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
667 env
->PC
, env
->CP0_EPC
, env
->CP0_ErrorEPC
,
668 env
->hflags
& MIPS_HFLAG_ERL
? 1 : 0);
672 void do_pmon (int function
)
676 case 2: /* TODO: char inbyte(int waitflag); */
677 if (env
->gpr
[4] == 0)
680 case 11: /* TODO: char inbyte (void); */
685 printf("%c", env
->gpr
[4] & 0xFF);
691 unsigned char *fmt
= (void *)env
->gpr
[4];
698 #if !defined(CONFIG_USER_ONLY)
700 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
);
702 #define MMUSUFFIX _mmu
706 #include "softmmu_template.h"
709 #include "softmmu_template.h"
712 #include "softmmu_template.h"
715 #include "softmmu_template.h"
717 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
719 env
->CP0_BadVAddr
= addr
;
720 do_restore_state (retaddr
);
721 do_raise_exception ((is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
);
724 void tlb_fill (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
726 TranslationBlock
*tb
;
731 /* XXX: hack to restore env in all cases, even if not called from
734 env
= cpu_single_env
;
735 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
738 /* now we have a real cpu fault */
739 pc
= (unsigned long)retaddr
;
742 /* the PC is inside the translated code. It means that we have
743 a virtual CPU fault */
744 cpu_restore_state(tb
, env
, pc
, NULL
);
747 do_raise_exception_err(env
->exception_index
, env
->error_code
);