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rtl8139 fixes (Igor Kovalenko)
[qemu/mini2440.git] / hw / rtl8139.c
blobc41b9d6495d5e3563108a16c2f35b1dc59ed610b
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 */
37
38 #include "vl.h"
39
40 /* XXX: such dependency must be suppressed */
41 #include <slirp/slirp.h>
42
43 /* debug RTL8139 card */
44 //#define DEBUG_RTL8139 1
45
46 #define PCI_FREQUENCY 33000000L
47
48 /* debug RTL8139 card C+ mode only */
49 //#define DEBUG_RTL8139CP 1
50
51 /* RTL8139 provides frame CRC with received packet, this feature seems to be
52 ignored by most drivers, disabled by default */
53 //#define RTL8139_CALCULATE_RXCRC 1
54
55 /* Uncomment to enable on-board timer interrupts */
56 //#define RTL8139_ONBOARD_TIMER 1
57
58 #if defined(RTL8139_CALCULATE_RXCRC)
59 /* For crc32 */
60 #include <zlib.h>
61 #endif
62
63 #define SET_MASKED(input, mask, curr) \
64 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
65
66 /* arg % size for size which is a power of 2 */
67 #define MOD2(input, size) \
68 ( ( input ) & ( size - 1 ) )
69
70 #if defined (DEBUG_RTL8139)
71 # define DEBUG_PRINT(x) do { printf x ; } while (0)
72 #else
73 # define DEBUG_PRINT(x)
74 #endif
75
76 /* Symbolic offsets to registers. */
77 enum RTL8139_registers {
78 MAC0 = 0, /* Ethernet hardware address. */
79 MAR0 = 8, /* Multicast filter. */
80 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
81 /* Dump Tally Conter control register(64bit). C+ mode only */
82 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
83 RxBuf = 0x30,
84 ChipCmd = 0x37,
85 RxBufPtr = 0x38,
86 RxBufAddr = 0x3A,
87 IntrMask = 0x3C,
88 IntrStatus = 0x3E,
89 TxConfig = 0x40,
90 RxConfig = 0x44,
91 Timer = 0x48, /* A general-purpose counter. */
92 RxMissed = 0x4C, /* 24 bits valid, write clears. */
93 Cfg9346 = 0x50,
94 Config0 = 0x51,
95 Config1 = 0x52,
96 FlashReg = 0x54,
97 MediaStatus = 0x58,
98 Config3 = 0x59,
99 Config4 = 0x5A, /* absent on RTL-8139A */
100 HltClk = 0x5B,
101 MultiIntr = 0x5C,
102 PCIRevisionID = 0x5E,
103 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
104 BasicModeCtrl = 0x62,
105 BasicModeStatus = 0x64,
106 NWayAdvert = 0x66,
107 NWayLPAR = 0x68,
108 NWayExpansion = 0x6A,
109 /* Undocumented registers, but required for proper operation. */
110 FIFOTMS = 0x70, /* FIFO Control and test. */
111 CSCR = 0x74, /* Chip Status and Configuration Register. */
112 PARA78 = 0x78,
113 PARA7c = 0x7c, /* Magic transceiver parameter register. */
114 Config5 = 0xD8, /* absent on RTL-8139A */
115 /* C+ mode */
116 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
117 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
118 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
119 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
120 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
121 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
122 TxThresh = 0xEC, /* Early Tx threshold */
123 };
124
125 enum ClearBitMasks {
126 MultiIntrClear = 0xF000,
127 ChipCmdClear = 0xE2,
128 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
129 };
130
131 enum ChipCmdBits {
132 CmdReset = 0x10,
133 CmdRxEnb = 0x08,
134 CmdTxEnb = 0x04,
135 RxBufEmpty = 0x01,
136 };
137
138 /* C+ mode */
139 enum CplusCmdBits {
140 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
141 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
142 CPlusRxEnb = 0x0002,
143 CPlusTxEnb = 0x0001,
144 };
145
146 /* Interrupt register bits, using my own meaningful names. */
147 enum IntrStatusBits {
148 PCIErr = 0x8000,
149 PCSTimeout = 0x4000,
150 RxFIFOOver = 0x40,
151 RxUnderrun = 0x20,
152 RxOverflow = 0x10,
153 TxErr = 0x08,
154 TxOK = 0x04,
155 RxErr = 0x02,
156 RxOK = 0x01,
157
158 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
159 };
160
161 enum TxStatusBits {
162 TxHostOwns = 0x2000,
163 TxUnderrun = 0x4000,
164 TxStatOK = 0x8000,
165 TxOutOfWindow = 0x20000000,
166 TxAborted = 0x40000000,
167 TxCarrierLost = 0x80000000,
168 };
169 enum RxStatusBits {
170 RxMulticast = 0x8000,
171 RxPhysical = 0x4000,
172 RxBroadcast = 0x2000,
173 RxBadSymbol = 0x0020,
174 RxRunt = 0x0010,
175 RxTooLong = 0x0008,
176 RxCRCErr = 0x0004,
177 RxBadAlign = 0x0002,
178 RxStatusOK = 0x0001,
179 };
180
181 /* Bits in RxConfig. */
182 enum rx_mode_bits {
183 AcceptErr = 0x20,
184 AcceptRunt = 0x10,
185 AcceptBroadcast = 0x08,
186 AcceptMulticast = 0x04,
187 AcceptMyPhys = 0x02,
188 AcceptAllPhys = 0x01,
189 };
190
191 /* Bits in TxConfig. */
192 enum tx_config_bits {
193
194 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
195 TxIFGShift = 24,
196 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
197 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
198 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
199 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
200
201 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
202 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
203 TxClearAbt = (1 << 0), /* Clear abort (WO) */
204 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
205 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
206
207 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
208 };
209
210
211 /* Transmit Status of All Descriptors (TSAD) Register */
212 enum TSAD_bits {
213 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
214 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
215 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
216 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
217 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
218 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
219 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
220 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
221 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
222 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
223 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
224 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
225 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
226 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
227 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
228 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
229 };
230
231
232 /* Bits in Config1 */
233 enum Config1Bits {
234 Cfg1_PM_Enable = 0x01,
235 Cfg1_VPD_Enable = 0x02,
236 Cfg1_PIO = 0x04,
237 Cfg1_MMIO = 0x08,
238 LWAKE = 0x10, /* not on 8139, 8139A */
239 Cfg1_Driver_Load = 0x20,
240 Cfg1_LED0 = 0x40,
241 Cfg1_LED1 = 0x80,
242 SLEEP = (1 << 1), /* only on 8139, 8139A */
243 PWRDN = (1 << 0), /* only on 8139, 8139A */
244 };
245
246 /* Bits in Config3 */
247 enum Config3Bits {
248 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
249 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
250 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
251 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
252 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
253 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
254 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
255 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
256 };
257
258 /* Bits in Config4 */
259 enum Config4Bits {
260 LWPTN = (1 << 2), /* not on 8139, 8139A */
261 };
262
263 /* Bits in Config5 */
264 enum Config5Bits {
265 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
266 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
267 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
268 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
269 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
270 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
271 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
272 };
273
274 enum RxConfigBits {
275 /* rx fifo threshold */
276 RxCfgFIFOShift = 13,
277 RxCfgFIFONone = (7 << RxCfgFIFOShift),
278
279 /* Max DMA burst */
280 RxCfgDMAShift = 8,
281 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
282
283 /* rx ring buffer length */
284 RxCfgRcv8K = 0,
285 RxCfgRcv16K = (1 << 11),
286 RxCfgRcv32K = (1 << 12),
287 RxCfgRcv64K = (1 << 11) | (1 << 12),
288
289 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
290 RxNoWrap = (1 << 7),
291 };
292
293 /* Twister tuning parameters from RealTek.
294 Completely undocumented, but required to tune bad links on some boards. */
295 /*
296 enum CSCRBits {
297 CSCR_LinkOKBit = 0x0400,
298 CSCR_LinkChangeBit = 0x0800,
299 CSCR_LinkStatusBits = 0x0f000,
300 CSCR_LinkDownOffCmd = 0x003c0,
301 CSCR_LinkDownCmd = 0x0f3c0,
302 */
303 enum CSCRBits {
304 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
305 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
306 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
307 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
308 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
309 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
310 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
311 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
312 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
313 };
314
315 enum Cfg9346Bits {
316 Cfg9346_Lock = 0x00,
317 Cfg9346_Unlock = 0xC0,
318 };
319
320 typedef enum {
321 CH_8139 = 0,
322 CH_8139_K,
323 CH_8139A,
324 CH_8139A_G,
325 CH_8139B,
326 CH_8130,
327 CH_8139C,
328 CH_8100,
329 CH_8100B_8139D,
330 CH_8101,
331 } chip_t;
332
333 enum chip_flags {
334 HasHltClk = (1 << 0),
335 HasLWake = (1 << 1),
336 };
337
338 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
339 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
340 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
341
342 #define RTL8139_PCI_REVID_8139 0x10
343 #define RTL8139_PCI_REVID_8139CPLUS 0x20
344
345 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
346
347 /* Size is 64 * 16bit words */
348 #define EEPROM_9346_ADDR_BITS 6
349 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
350 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
351
352 enum Chip9346Operation
353 {
354 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
355 Chip9346_op_read = 0x80, /* 10 AAAAAA */
356 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
357 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
358 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
359 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
360 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
361 };
362
363 enum Chip9346Mode
364 {
365 Chip9346_none = 0,
366 Chip9346_enter_command_mode,
367 Chip9346_read_command,
368 Chip9346_data_read, /* from output register */
369 Chip9346_data_write, /* to input register, then to contents at specified address */
370 Chip9346_data_write_all, /* to input register, then filling contents */
371 };
372
373 typedef struct EEprom9346
374 {
375 uint16_t contents[EEPROM_9346_SIZE];
376 int mode;
377 uint32_t tick;
378 uint8_t address;
379 uint16_t input;
380 uint16_t output;
381
382 uint8_t eecs;
383 uint8_t eesk;
384 uint8_t eedi;
385 uint8_t eedo;
386 } EEprom9346;
387
388 typedef struct RTL8139TallyCounters
389 {
390 /* Tally counters */
391 uint64_t TxOk;
392 uint64_t RxOk;
393 uint64_t TxERR;
394 uint32_t RxERR;
395 uint16_t MissPkt;
396 uint16_t FAE;
397 uint32_t Tx1Col;
398 uint32_t TxMCol;
399 uint64_t RxOkPhy;
400 uint64_t RxOkBrd;
401 uint32_t RxOkMul;
402 uint16_t TxAbt;
403 uint16_t TxUndrn;
404 } RTL8139TallyCounters;
405
406 /* Clears all tally counters */
407 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
408
409 /* Writes tally counters to specified physical memory address */
410 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
411
412 /* Loads values of tally counters from VM state file */
413 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
414
415 /* Saves values of tally counters to VM state file */
416 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
417
418 typedef struct RTL8139State {
419 uint8_t phys[8]; /* mac address */
420 uint8_t mult[8]; /* multicast mask array */
421
422 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
423 uint32_t TxAddr[4]; /* TxAddr0 */
424 uint32_t RxBuf; /* Receive buffer */
425 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
426 uint32_t RxBufPtr;
427 uint32_t RxBufAddr;
428
429 uint16_t IntrStatus;
430 uint16_t IntrMask;
431
432 uint32_t TxConfig;
433 uint32_t RxConfig;
434 uint32_t RxMissed;
435
436 uint16_t CSCR;
437
438 uint8_t Cfg9346;
439 uint8_t Config0;
440 uint8_t Config1;
441 uint8_t Config3;
442 uint8_t Config4;
443 uint8_t Config5;
444
445 uint8_t clock_enabled;
446 uint8_t bChipCmdState;
447
448 uint16_t MultiIntr;
449
450 uint16_t BasicModeCtrl;
451 uint16_t BasicModeStatus;
452 uint16_t NWayAdvert;
453 uint16_t NWayLPAR;
454 uint16_t NWayExpansion;
455
456 uint16_t CpCmd;
457 uint8_t TxThresh;
458
459 int irq;
460 PCIDevice *pci_dev;
461 VLANClientState *vc;
462 uint8_t macaddr[6];
463 int rtl8139_mmio_io_addr;
464
465 /* C ring mode */
466 uint32_t currTxDesc;
467
468 /* C+ mode */
469 uint32_t currCPlusRxDesc;
470 uint32_t currCPlusTxDesc;
471
472 uint32_t RxRingAddrLO;
473 uint32_t RxRingAddrHI;
474
475 EEprom9346 eeprom;
476
477 uint32_t TCTR;
478 uint32_t TimerInt;
479 int64_t TCTR_base;
480
481 /* Tally counters */
482 RTL8139TallyCounters tally_counters;
483
484 /* Non-persistent data */
485 uint8_t *cplus_txbuffer;
486 int cplus_txbuffer_len;
487 int cplus_txbuffer_offset;
488
489 /* PCI interrupt timer */
490 QEMUTimer *timer;
491
492 } RTL8139State;
493
494 void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
495 {
496 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
497
498 switch (command & Chip9346_op_mask)
499 {
500 case Chip9346_op_read:
501 {
502 eeprom->address = command & EEPROM_9346_ADDR_MASK;
503 eeprom->output = eeprom->contents[eeprom->address];
504 eeprom->eedo = 0;
505 eeprom->tick = 0;
506 eeprom->mode = Chip9346_data_read;
507 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
508 eeprom->address, eeprom->output));
509 }
510 break;
511
512 case Chip9346_op_write:
513 {
514 eeprom->address = command & EEPROM_9346_ADDR_MASK;
515 eeprom->input = 0;
516 eeprom->tick = 0;
517 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
518 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
519 eeprom->address));
520 }
521 break;
522 default:
523 eeprom->mode = Chip9346_none;
524 switch (command & Chip9346_op_ext_mask)
525 {
526 case Chip9346_op_write_enable:
527 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
528 break;
529 case Chip9346_op_write_all:
530 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
531 break;
532 case Chip9346_op_write_disable:
533 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
534 break;
535 }
536 break;
537 }
538 }
539
540 void prom9346_shift_clock(EEprom9346 *eeprom)
541 {
542 int bit = eeprom->eedi?1:0;
543
544 ++ eeprom->tick;
545
546 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
547
548 switch (eeprom->mode)
549 {
550 case Chip9346_enter_command_mode:
551 if (bit)
552 {
553 eeprom->mode = Chip9346_read_command;
554 eeprom->tick = 0;
555 eeprom->input = 0;
556 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
557 }
558 break;
559
560 case Chip9346_read_command:
561 eeprom->input = (eeprom->input << 1) | (bit & 1);
562 if (eeprom->tick == 8)
563 {
564 prom9346_decode_command(eeprom, eeprom->input & 0xff);
565 }
566 break;
567
568 case Chip9346_data_read:
569 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
570 eeprom->output <<= 1;
571 if (eeprom->tick == 16)
572 {
573 #if 1
574 // the FreeBSD drivers (rl and re) don't explicitly toggle
575 // CS between reads (or does setting Cfg9346 to 0 count too?),
576 // so we need to enter wait-for-command state here
577 eeprom->mode = Chip9346_enter_command_mode;
578 eeprom->input = 0;
579 eeprom->tick = 0;
580
581 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
582 #else
583 // original behaviour
584 ++eeprom->address;
585 eeprom->address &= EEPROM_9346_ADDR_MASK;
586 eeprom->output = eeprom->contents[eeprom->address];
587 eeprom->tick = 0;
588
589 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
590 eeprom->address, eeprom->output));
591 #endif
592 }
593 break;
594
595 case Chip9346_data_write:
596 eeprom->input = (eeprom->input << 1) | (bit & 1);
597 if (eeprom->tick == 16)
598 {
599 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
600 eeprom->address, eeprom->input));
601
602 eeprom->contents[eeprom->address] = eeprom->input;
603 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
604 eeprom->tick = 0;
605 eeprom->input = 0;
606 }
607 break;
608
609 case Chip9346_data_write_all:
610 eeprom->input = (eeprom->input << 1) | (bit & 1);
611 if (eeprom->tick == 16)
612 {
613 int i;
614 for (i = 0; i < EEPROM_9346_SIZE; i++)
615 {
616 eeprom->contents[i] = eeprom->input;
617 }
618 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
619 eeprom->input));
620
621 eeprom->mode = Chip9346_enter_command_mode;
622 eeprom->tick = 0;
623 eeprom->input = 0;
624 }
625 break;
626
627 default:
628 break;
629 }
630 }
631
632 int prom9346_get_wire(RTL8139State *s)
633 {
634 EEprom9346 *eeprom = &s->eeprom;
635 if (!eeprom->eecs)
636 return 0;
637
638 return eeprom->eedo;
639 }
640
641 void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
642 {
643 EEprom9346 *eeprom = &s->eeprom;
644 uint8_t old_eecs = eeprom->eecs;
645 uint8_t old_eesk = eeprom->eesk;
646
647 eeprom->eecs = eecs;
648 eeprom->eesk = eesk;
649 eeprom->eedi = eedi;
650
651 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
652 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
653
654 if (!old_eecs && eecs)
655 {
656 /* Synchronize start */
657 eeprom->tick = 0;
658 eeprom->input = 0;
659 eeprom->output = 0;
660 eeprom->mode = Chip9346_enter_command_mode;
661
662 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
663 }
664
665 if (!eecs)
666 {
667 DEBUG_PRINT(("=== eeprom: end access\n"));
668 return;
669 }
670
671 if (!old_eesk && eesk)
672 {
673 /* SK front rules */
674 prom9346_shift_clock(eeprom);
675 }
676 }
677
678 static void rtl8139_update_irq(RTL8139State *s)
679 {
680 int isr;
681 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
682
683 DEBUG_PRINT(("RTL8139: Set IRQ line %d to %d (%04x %04x)\n",
684 s->irq, isr ? 1 : 0, s->IntrStatus, s->IntrMask));
685
686 if (s->irq == 16) {
687 /* PCI irq */
688 pci_set_irq(s->pci_dev, 0, (isr != 0));
689 } else {
690 /* ISA irq */
691 pic_set_irq(s->irq, (isr != 0));
692 }
693 }
694
695 #define POLYNOMIAL 0x04c11db6
696
697 /* From FreeBSD */
698 /* XXX: optimize */
699 static int compute_mcast_idx(const uint8_t *ep)
700 {
701 uint32_t crc;
702 int carry, i, j;
703 uint8_t b;
704
705 crc = 0xffffffff;
706 for (i = 0; i < 6; i++) {
707 b = *ep++;
708 for (j = 0; j < 8; j++) {
709 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
710 crc <<= 1;
711 b >>= 1;
712 if (carry)
713 crc = ((crc ^ POLYNOMIAL) | carry);
714 }
715 }
716 return (crc >> 26);
717 }
718
719 static int rtl8139_RxWrap(RTL8139State *s)
720 {
721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
722 return (s->RxConfig & (1 << 7));
723 }
724
725 static int rtl8139_receiver_enabled(RTL8139State *s)
726 {
727 return s->bChipCmdState & CmdRxEnb;
728 }
729
730 static int rtl8139_transmitter_enabled(RTL8139State *s)
731 {
732 return s->bChipCmdState & CmdTxEnb;
733 }
734
735 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
736 {
737 return s->CpCmd & CPlusRxEnb;
738 }
739
740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
741 {
742 return s->CpCmd & CPlusTxEnb;
743 }
744
745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
746 {
747 if (s->RxBufAddr + size > s->RxBufferSize)
748 {
749 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
750
751 /* write packet data */
752 if (wrapped && s->RxBufferSize < 65536 && !rtl8139_RxWrap(s))
753 {
754 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
755
756 if (size > wrapped)
757 {
758 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
759 buf, size-wrapped );
760 }
761
762 /* reset buffer pointer */
763 s->RxBufAddr = 0;
764
765 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
766 buf + (size-wrapped), wrapped );
767
768 s->RxBufAddr = wrapped;
769
770 return;
771 }
772 }
773
774 /* non-wrapping path or overwrapping enabled */
775 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
776
777 s->RxBufAddr += size;
778 }
779
780 #define MIN_BUF_SIZE 60
781 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
782 {
783 #if TARGET_PHYS_ADDR_BITS > 32
784 return low | ((target_phys_addr_t)high << 32);
785 #else
786 return low;
787 #endif
788 }
789
790 static int rtl8139_can_receive(void *opaque)
791 {
792 RTL8139State *s = opaque;
793 int avail;
794
795 /* Recieve (drop) packets if card is disabled. */
796 if (!s->clock_enabled)
797 return 1;
798 if (!rtl8139_receiver_enabled(s))
799 return 1;
800
801 if (rtl8139_cp_receiver_enabled(s)) {
802 /* ??? Flow control not implemented in c+ mode.
803 This is a hack to work around slirp deficiencies anyway. */
804 return 1;
805 } else {
806 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
807 s->RxBufferSize);
808 return (avail == 0 || avail >= 1514);
809 }
810 }
811
812 static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
813 {
814 RTL8139State *s = opaque;
815
816 uint32_t packet_header = 0;
817
818 uint8_t buf1[60];
819 static const uint8_t broadcast_macaddr[6] =
820 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
821
822 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
823
824 /* test if board clock is stopped */
825 if (!s->clock_enabled)
826 {
827 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
828 return;
829 }
830
831 /* first check if receiver is enabled */
832
833 if (!rtl8139_receiver_enabled(s))
834 {
835 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
836 return;
837 }
838
839 /* XXX: check this */
840 if (s->RxConfig & AcceptAllPhys) {
841 /* promiscuous: receive all */
842 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
843
844 } else {
845 if (!memcmp(buf, broadcast_macaddr, 6)) {
846 /* broadcast address */
847 if (!(s->RxConfig & AcceptBroadcast))
848 {
849 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
850
851 /* update tally counter */
852 ++s->tally_counters.RxERR;
853
854 return;
855 }
856
857 packet_header |= RxBroadcast;
858
859 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
860
861 /* update tally counter */
862 ++s->tally_counters.RxOkBrd;
863
864 } else if (buf[0] & 0x01) {
865 /* multicast */
866 if (!(s->RxConfig & AcceptMulticast))
867 {
868 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
873 return;
874 }
875
876 int mcast_idx = compute_mcast_idx(buf);
877
878 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
879 {
880 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
881
882 /* update tally counter */
883 ++s->tally_counters.RxERR;
884
885 return;
886 }
887
888 packet_header |= RxMulticast;
889
890 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
891
892 /* update tally counter */
893 ++s->tally_counters.RxOkMul;
894
895 } else if (s->phys[0] == buf[0] &&
896 s->phys[1] == buf[1] &&
897 s->phys[2] == buf[2] &&
898 s->phys[3] == buf[3] &&
899 s->phys[4] == buf[4] &&
900 s->phys[5] == buf[5]) {
901 /* match */
902 if (!(s->RxConfig & AcceptMyPhys))
903 {
904 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
905
906 /* update tally counter */
907 ++s->tally_counters.RxERR;
908
909 return;
910 }
911
912 packet_header |= RxPhysical;
913
914 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
915
916 /* update tally counter */
917 ++s->tally_counters.RxOkPhy;
918
919 } else {
920
921 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
922
923 /* update tally counter */
924 ++s->tally_counters.RxERR;
925
926 return;
927 }
928 }
929
930 /* if too small buffer, then expand it */
931 if (size < MIN_BUF_SIZE) {
932 memcpy(buf1, buf, size);
933 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
934 buf = buf1;
935 size = MIN_BUF_SIZE;
936 }
937
938 if (rtl8139_cp_receiver_enabled(s))
939 {
940 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
941
942 /* begin C+ receiver mode */
943
944 /* w0 ownership flag */
945 #define CP_RX_OWN (1<<31)
946 /* w0 end of ring flag */
947 #define CP_RX_EOR (1<<30)
948 /* w0 bits 0...12 : buffer size */
949 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
950 /* w1 tag available flag */
951 #define CP_RX_TAVA (1<<16)
952 /* w1 bits 0...15 : VLAN tag */
953 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
954 /* w2 low 32bit of Rx buffer ptr */
955 /* w3 high 32bit of Rx buffer ptr */
956
957 int descriptor = s->currCPlusRxDesc;
958 target_phys_addr_t cplus_rx_ring_desc;
959
960 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
961 cplus_rx_ring_desc += 16 * descriptor;
962
963 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
964 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
965
966 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
967
968 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
969 rxdw0 = le32_to_cpu(val);
970 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
971 rxdw1 = le32_to_cpu(val);
972 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
973 rxbufLO = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
975 rxbufHI = le32_to_cpu(val);
976
977 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
978 descriptor,
979 rxdw0, rxdw1, rxbufLO, rxbufHI));
980
981 if (!(rxdw0 & CP_RX_OWN))
982 {
983 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
984
985 s->IntrStatus |= RxOverflow;
986 ++s->RxMissed;
987
988 /* update tally counter */
989 ++s->tally_counters.RxERR;
990 ++s->tally_counters.MissPkt;
991
992 rtl8139_update_irq(s);
993 return;
994 }
995
996 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
997
998 /* TODO: scatter the packet over available receive ring descriptors space */
999
1000 if (size+4 > rx_space)
1001 {
1002 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1003 descriptor, rx_space, size));
1004
1005 s->IntrStatus |= RxOverflow;
1006 ++s->RxMissed;
1007
1008 /* update tally counter */
1009 ++s->tally_counters.RxERR;
1010 ++s->tally_counters.MissPkt;
1011
1012 rtl8139_update_irq(s);
1013 return;
1014 }
1015
1016 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1017
1018 /* receive/copy to target memory */
1019 cpu_physical_memory_write( rx_addr, buf, size );
1020
1021 if (s->CpCmd & CPlusRxChkSum)
1022 {
1023 /* do some packet checksumming */
1024 }
1025
1026 /* write checksum */
1027 #if defined (RTL8139_CALCULATE_RXCRC)
1028 val = cpu_to_le32(crc32(~0, buf, size));
1029 #else
1030 val = 0;
1031 #endif
1032 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1033
1034 /* first segment of received packet flag */
1035 #define CP_RX_STATUS_FS (1<<29)
1036 /* last segment of received packet flag */
1037 #define CP_RX_STATUS_LS (1<<28)
1038 /* multicast packet flag */
1039 #define CP_RX_STATUS_MAR (1<<26)
1040 /* physical-matching packet flag */
1041 #define CP_RX_STATUS_PAM (1<<25)
1042 /* broadcast packet flag */
1043 #define CP_RX_STATUS_BAR (1<<24)
1044 /* runt packet flag */
1045 #define CP_RX_STATUS_RUNT (1<<19)
1046 /* crc error flag */
1047 #define CP_RX_STATUS_CRC (1<<18)
1048 /* IP checksum error flag */
1049 #define CP_RX_STATUS_IPF (1<<15)
1050 /* UDP checksum error flag */
1051 #define CP_RX_STATUS_UDPF (1<<14)
1052 /* TCP checksum error flag */
1053 #define CP_RX_STATUS_TCPF (1<<13)
1054
1055 /* transfer ownership to target */
1056 rxdw0 &= ~CP_RX_OWN;
1057
1058 /* set first segment bit */
1059 rxdw0 |= CP_RX_STATUS_FS;
1060
1061 /* set last segment bit */
1062 rxdw0 |= CP_RX_STATUS_LS;
1063
1064 /* set received packet type flags */
1065 if (packet_header & RxBroadcast)
1066 rxdw0 |= CP_RX_STATUS_BAR;
1067 if (packet_header & RxMulticast)
1068 rxdw0 |= CP_RX_STATUS_MAR;
1069 if (packet_header & RxPhysical)
1070 rxdw0 |= CP_RX_STATUS_PAM;
1071
1072 /* set received size */
1073 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1074 rxdw0 |= (size+4);
1075
1076 /* reset VLAN tag flag */
1077 rxdw1 &= ~CP_RX_TAVA;
1078
1079 /* update ring data */
1080 val = cpu_to_le32(rxdw0);
1081 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1082 val = cpu_to_le32(rxdw1);
1083 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1084
1085 /* update tally counter */
1086 ++s->tally_counters.RxOk;
1087
1088 /* seek to next Rx descriptor */
1089 if (rxdw0 & CP_RX_EOR)
1090 {
1091 s->currCPlusRxDesc = 0;
1092 }
1093 else
1094 {
1095 ++s->currCPlusRxDesc;
1096 }
1097
1098 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1099
1100 }
1101 else
1102 {
1103 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1104
1105 /* begin ring receiver mode */
1106 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1107
1108 /* if receiver buffer is empty then avail == 0 */
1109
1110 if (avail != 0 && size + 8 >= avail)
1111 {
1112 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1113 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1114
1115 s->IntrStatus |= RxOverflow;
1116 ++s->RxMissed;
1117 rtl8139_update_irq(s);
1118 return;
1119 }
1120
1121 packet_header |= RxStatusOK;
1122
1123 packet_header |= (((size+4) << 16) & 0xffff0000);
1124
1125 /* write header */
1126 uint32_t val = cpu_to_le32(packet_header);
1127
1128 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1129
1130 rtl8139_write_buffer(s, buf, size);
1131
1132 /* write checksum */
1133 #if defined (RTL8139_CALCULATE_RXCRC)
1134 val = cpu_to_le32(crc32(~0, buf, size));
1135 #else
1136 val = 0;
1137 #endif
1138
1139 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1140
1141 /* correct buffer write pointer */
1142 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1143
1144 /* now we can signal we have received something */
1145
1146 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1147 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1148 }
1149
1150 s->IntrStatus |= RxOK;
1151
1152 if (do_interrupt)
1153 {
1154 rtl8139_update_irq(s);
1155 }
1156 }
1157
1158 static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1159 {
1160 rtl8139_do_receive(opaque, buf, size, 1);
1161 }
1162
1163 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1164 {
1165 s->RxBufferSize = bufferSize;
1166 s->RxBufPtr = 0;
1167 s->RxBufAddr = 0;
1168 }
1169
1170 static void rtl8139_reset(RTL8139State *s)
1171 {
1172 int i;
1173
1174 /* restore MAC address */
1175 memcpy(s->phys, s->macaddr, 6);
1176
1177 /* reset interrupt mask */
1178 s->IntrStatus = 0;
1179 s->IntrMask = 0;
1180
1181 rtl8139_update_irq(s);
1182
1183 /* prepare eeprom */
1184 s->eeprom.contents[0] = 0x8129;
1185 #if 1
1186 // PCI vendor and device ID should be mirrored here
1187 s->eeprom.contents[1] = 0x10ec;
1188 s->eeprom.contents[2] = 0x8139;
1189 #endif
1190 memcpy(&s->eeprom.contents[7], s->macaddr, 6);
1191
1192 /* mark all status registers as owned by host */
1193 for (i = 0; i < 4; ++i)
1194 {
1195 s->TxStatus[i] = TxHostOwns;
1196 }
1197
1198 s->currTxDesc = 0;
1199 s->currCPlusRxDesc = 0;
1200 s->currCPlusTxDesc = 0;
1201
1202 s->RxRingAddrLO = 0;
1203 s->RxRingAddrHI = 0;
1204
1205 s->RxBuf = 0;
1206
1207 rtl8139_reset_rxring(s, 8192);
1208
1209 /* ACK the reset */
1210 s->TxConfig = 0;
1211
1212 #if 0
1213 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1214 s->clock_enabled = 0;
1215 #else
1216 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1217 s->clock_enabled = 1;
1218 #endif
1219
1220 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1221
1222 /* set initial state data */
1223 s->Config0 = 0x0; /* No boot ROM */
1224 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1225 s->Config3 = 0x1; /* fast back-to-back compatible */
1226 s->Config5 = 0x0;
1227
1228 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1229
1230 s->CpCmd = 0x0; /* reset C+ mode */
1231
1232 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1233 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1234 s->BasicModeCtrl = 0x1000; // autonegotiation
1235
1236 s->BasicModeStatus = 0x7809;
1237 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1238 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1239 s->BasicModeStatus |= 0x0004; /* link is up */
1240
1241 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1242 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1243 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1244
1245 /* also reset timer and disable timer interrupt */
1246 s->TCTR = 0;
1247 s->TimerInt = 0;
1248 s->TCTR_base = 0;
1249
1250 /* reset tally counters */
1251 RTL8139TallyCounters_clear(&s->tally_counters);
1252 }
1253
1254 void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1255 {
1256 counters->TxOk = 0;
1257 counters->RxOk = 0;
1258 counters->TxERR = 0;
1259 counters->RxERR = 0;
1260 counters->MissPkt = 0;
1261 counters->FAE = 0;
1262 counters->Tx1Col = 0;
1263 counters->TxMCol = 0;
1264 counters->RxOkPhy = 0;
1265 counters->RxOkBrd = 0;
1266 counters->RxOkMul = 0;
1267 counters->TxAbt = 0;
1268 counters->TxUndrn = 0;
1269 }
1270
1271 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1272 {
1273 uint16_t val16;
1274 uint32_t val32;
1275 uint64_t val64;
1276
1277 val64 = cpu_to_le64(tally_counters->TxOk);
1278 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1279
1280 val64 = cpu_to_le64(tally_counters->RxOk);
1281 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1282
1283 val64 = cpu_to_le64(tally_counters->TxERR);
1284 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1285
1286 val32 = cpu_to_le32(tally_counters->RxERR);
1287 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1288
1289 val16 = cpu_to_le16(tally_counters->MissPkt);
1290 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1291
1292 val16 = cpu_to_le16(tally_counters->FAE);
1293 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1294
1295 val32 = cpu_to_le32(tally_counters->Tx1Col);
1296 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1297
1298 val32 = cpu_to_le32(tally_counters->TxMCol);
1299 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1300
1301 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1302 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1303
1304 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1305 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1306
1307 val32 = cpu_to_le32(tally_counters->RxOkMul);
1308 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1309
1310 val16 = cpu_to_le16(tally_counters->TxAbt);
1311 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1312
1313 val16 = cpu_to_le16(tally_counters->TxUndrn);
1314 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1315 }
1316
1317 /* Loads values of tally counters from VM state file */
1318 static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1319 {
1320 qemu_get_be64s(f, &tally_counters->TxOk);
1321 qemu_get_be64s(f, &tally_counters->RxOk);
1322 qemu_get_be64s(f, &tally_counters->TxERR);
1323 qemu_get_be32s(f, &tally_counters->RxERR);
1324 qemu_get_be16s(f, &tally_counters->MissPkt);
1325 qemu_get_be16s(f, &tally_counters->FAE);
1326 qemu_get_be32s(f, &tally_counters->Tx1Col);
1327 qemu_get_be32s(f, &tally_counters->TxMCol);
1328 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1329 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1330 qemu_get_be32s(f, &tally_counters->RxOkMul);
1331 qemu_get_be16s(f, &tally_counters->TxAbt);
1332 qemu_get_be16s(f, &tally_counters->TxUndrn);
1333 }
1334
1335 /* Saves values of tally counters to VM state file */
1336 static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1337 {
1338 qemu_put_be64s(f, &tally_counters->TxOk);
1339 qemu_put_be64s(f, &tally_counters->RxOk);
1340 qemu_put_be64s(f, &tally_counters->TxERR);
1341 qemu_put_be32s(f, &tally_counters->RxERR);
1342 qemu_put_be16s(f, &tally_counters->MissPkt);
1343 qemu_put_be16s(f, &tally_counters->FAE);
1344 qemu_put_be32s(f, &tally_counters->Tx1Col);
1345 qemu_put_be32s(f, &tally_counters->TxMCol);
1346 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1347 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1348 qemu_put_be32s(f, &tally_counters->RxOkMul);
1349 qemu_put_be16s(f, &tally_counters->TxAbt);
1350 qemu_put_be16s(f, &tally_counters->TxUndrn);
1351 }
1352
1353 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1354 {
1355 val &= 0xff;
1356
1357 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1358
1359 if (val & CmdReset)
1360 {
1361 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1362 rtl8139_reset(s);
1363 }
1364 if (val & CmdRxEnb)
1365 {
1366 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1367 }
1368 if (val & CmdTxEnb)
1369 {
1370 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1371 }
1372
1373 /* mask unwriteable bits */
1374 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1375
1376 /* Deassert reset pin before next read */
1377 val &= ~CmdReset;
1378
1379 s->bChipCmdState = val;
1380 }
1381
1382 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1383 {
1384 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1385
1386 if (unread != 0)
1387 {
1388 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1389 return 0;
1390 }
1391
1392 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1393
1394 return 1;
1395 }
1396
1397 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1398 {
1399 uint32_t ret = s->bChipCmdState;
1400
1401 if (rtl8139_RxBufferEmpty(s))
1402 ret |= RxBufEmpty;
1403
1404 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1405
1406 return ret;
1407 }
1408
1409 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1410 {
1411 val &= 0xffff;
1412
1413 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1414
1415 /* mask unwriteable bits */
1416 val = SET_MASKED(val, 0xff84, s->CpCmd);
1417
1418 s->CpCmd = val;
1419 }
1420
1421 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1422 {
1423 uint32_t ret = s->CpCmd;
1424
1425 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1426
1427 return ret;
1428 }
1429
1430 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1431 {
1432 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1433 }
1434
1435 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1436 {
1437 uint32_t ret = 0;
1438
1439 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1440
1441 return ret;
1442 }
1443
1444 int rtl8139_config_writeable(RTL8139State *s)
1445 {
1446 if (s->Cfg9346 & Cfg9346_Unlock)
1447 {
1448 return 1;
1449 }
1450
1451 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1452
1453 return 0;
1454 }
1455
1456 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1457 {
1458 val &= 0xffff;
1459
1460 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1461
1462 /* mask unwriteable bits */
1463 uint32 mask = 0x4cff;
1464
1465 if (1 || !rtl8139_config_writeable(s))
1466 {
1467 /* Speed setting and autonegotiation enable bits are read-only */
1468 mask |= 0x3000;
1469 /* Duplex mode setting is read-only */
1470 mask |= 0x0100;
1471 }
1472
1473 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1474
1475 s->BasicModeCtrl = val;
1476 }
1477
1478 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1479 {
1480 uint32_t ret = s->BasicModeCtrl;
1481
1482 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1483
1484 return ret;
1485 }
1486
1487 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1488 {
1489 val &= 0xffff;
1490
1491 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1492
1493 /* mask unwriteable bits */
1494 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1495
1496 s->BasicModeStatus = val;
1497 }
1498
1499 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1500 {
1501 uint32_t ret = s->BasicModeStatus;
1502
1503 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1504
1505 return ret;
1506 }
1507
1508 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1509 {
1510 val &= 0xff;
1511
1512 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1513
1514 /* mask unwriteable bits */
1515 val = SET_MASKED(val, 0x31, s->Cfg9346);
1516
1517 uint32_t opmode = val & 0xc0;
1518 uint32_t eeprom_val = val & 0xf;
1519
1520 if (opmode == 0x80) {
1521 /* eeprom access */
1522 int eecs = (eeprom_val & 0x08)?1:0;
1523 int eesk = (eeprom_val & 0x04)?1:0;
1524 int eedi = (eeprom_val & 0x02)?1:0;
1525 prom9346_set_wire(s, eecs, eesk, eedi);
1526 } else if (opmode == 0x40) {
1527 /* Reset. */
1528 val = 0;
1529 rtl8139_reset(s);
1530 }
1531
1532 s->Cfg9346 = val;
1533 }
1534
1535 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1536 {
1537 uint32_t ret = s->Cfg9346;
1538
1539 uint32_t opmode = ret & 0xc0;
1540
1541 if (opmode == 0x80)
1542 {
1543 /* eeprom access */
1544 int eedo = prom9346_get_wire(s);
1545 if (eedo)
1546 {
1547 ret |= 0x01;
1548 }
1549 else
1550 {
1551 ret &= ~0x01;
1552 }
1553 }
1554
1555 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1556
1557 return ret;
1558 }
1559
1560 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1561 {
1562 val &= 0xff;
1563
1564 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1565
1566 if (!rtl8139_config_writeable(s))
1567 return;
1568
1569 /* mask unwriteable bits */
1570 val = SET_MASKED(val, 0xf8, s->Config0);
1571
1572 s->Config0 = val;
1573 }
1574
1575 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1576 {
1577 uint32_t ret = s->Config0;
1578
1579 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1580
1581 return ret;
1582 }
1583
1584 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1585 {
1586 val &= 0xff;
1587
1588 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1589
1590 if (!rtl8139_config_writeable(s))
1591 return;
1592
1593 /* mask unwriteable bits */
1594 val = SET_MASKED(val, 0xC, s->Config1);
1595
1596 s->Config1 = val;
1597 }
1598
1599 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1600 {
1601 uint32_t ret = s->Config1;
1602
1603 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1604
1605 return ret;
1606 }
1607
1608 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1609 {
1610 val &= 0xff;
1611
1612 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1613
1614 if (!rtl8139_config_writeable(s))
1615 return;
1616
1617 /* mask unwriteable bits */
1618 val = SET_MASKED(val, 0x8F, s->Config3);
1619
1620 s->Config3 = val;
1621 }
1622
1623 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1624 {
1625 uint32_t ret = s->Config3;
1626
1627 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1628
1629 return ret;
1630 }
1631
1632 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1633 {
1634 val &= 0xff;
1635
1636 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1637
1638 if (!rtl8139_config_writeable(s))
1639 return;
1640
1641 /* mask unwriteable bits */
1642 val = SET_MASKED(val, 0x0a, s->Config4);
1643
1644 s->Config4 = val;
1645 }
1646
1647 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1648 {
1649 uint32_t ret = s->Config4;
1650
1651 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1652
1653 return ret;
1654 }
1655
1656 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1657 {
1658 val &= 0xff;
1659
1660 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1661
1662 /* mask unwriteable bits */
1663 val = SET_MASKED(val, 0x80, s->Config5);
1664
1665 s->Config5 = val;
1666 }
1667
1668 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1669 {
1670 uint32_t ret = s->Config5;
1671
1672 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1673
1674 return ret;
1675 }
1676
1677 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1678 {
1679 if (!rtl8139_transmitter_enabled(s))
1680 {
1681 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1682 return;
1683 }
1684
1685 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1686
1687 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1688
1689 s->TxConfig = val;
1690 }
1691
1692 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1693 {
1694 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1695
1696 uint32_t tc = s->TxConfig;
1697 tc &= 0xFFFFFF00;
1698 tc |= (val & 0x000000FF);
1699 rtl8139_TxConfig_write(s, tc);
1700 }
1701
1702 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1703 {
1704 uint32_t ret = s->TxConfig;
1705
1706 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1707
1708 return ret;
1709 }
1710
1711 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1712 {
1713 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1714
1715 /* mask unwriteable bits */
1716 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1717
1718 s->RxConfig = val;
1719
1720 /* reset buffer size and read/write pointers */
1721 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1722
1723 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1724 }
1725
1726 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1727 {
1728 uint32_t ret = s->RxConfig;
1729
1730 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1731
1732 return ret;
1733 }
1734
1735 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1736 {
1737 if (!rtl8139_transmitter_enabled(s))
1738 {
1739 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1740 descriptor));
1741 return 0;
1742 }
1743
1744 if (s->TxStatus[descriptor] & TxHostOwns)
1745 {
1746 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1747 descriptor, s->TxStatus[descriptor]));
1748 return 0;
1749 }
1750
1751 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1752
1753 int txsize = s->TxStatus[descriptor] & 0x1fff;
1754 uint8_t txbuffer[0x2000];
1755
1756 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1757 txsize, s->TxAddr[descriptor]));
1758
1759 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1760
1761 /* Mark descriptor as transferred */
1762 s->TxStatus[descriptor] |= TxHostOwns;
1763 s->TxStatus[descriptor] |= TxStatOK;
1764
1765 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1766 {
1767 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1768 rtl8139_do_receive(s, txbuffer, txsize, 0);
1769 }
1770 else
1771 {
1772 qemu_send_packet(s->vc, txbuffer, txsize);
1773 }
1774
1775 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1776
1777 /* update interrupt */
1778 s->IntrStatus |= TxOK;
1779 rtl8139_update_irq(s);
1780
1781 return 1;
1782 }
1783
1784 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1785 {
1786 if (!rtl8139_transmitter_enabled(s))
1787 {
1788 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1789 return 0;
1790 }
1791
1792 if (!rtl8139_cp_transmitter_enabled(s))
1793 {
1794 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1795 return 0 ;
1796 }
1797
1798 int descriptor = s->currCPlusTxDesc;
1799
1800 target_phys_addr_t cplus_tx_ring_desc =
1801 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1802
1803 /* Normal priority ring */
1804 cplus_tx_ring_desc += 16 * descriptor;
1805
1806 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1807 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1808
1809 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1810
1811 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1812 txdw0 = le32_to_cpu(val);
1813 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1814 txdw1 = le32_to_cpu(val);
1815 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1816 txbufLO = le32_to_cpu(val);
1817 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1818 txbufHI = le32_to_cpu(val);
1819
1820 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1821 descriptor,
1822 txdw0, txdw1, txbufLO, txbufHI));
1823
1824 /* w0 ownership flag */
1825 #define CP_TX_OWN (1<<31)
1826 /* w0 end of ring flag */
1827 #define CP_TX_EOR (1<<30)
1828 /* first segment of received packet flag */
1829 #define CP_TX_FS (1<<29)
1830 /* last segment of received packet flag */
1831 #define CP_TX_LS (1<<28)
1832 /* large send packet flag */
1833 #define CP_TX_LGSEN (1<<27)
1834 /* IP checksum offload flag */
1835 #define CP_TX_IPCS (1<<18)
1836 /* UDP checksum offload flag */
1837 #define CP_TX_UDPCS (1<<17)
1838 /* TCP checksum offload flag */
1839 #define CP_TX_TCPCS (1<<16)
1840
1841 /* w0 bits 0...15 : buffer size */
1842 #define CP_TX_BUFFER_SIZE (1<<16)
1843 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1844 /* w1 tag available flag */
1845 #define CP_RX_TAGC (1<<17)
1846 /* w1 bits 0...15 : VLAN tag */
1847 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1848 /* w2 low 32bit of Rx buffer ptr */
1849 /* w3 high 32bit of Rx buffer ptr */
1850
1851 /* set after transmission */
1852 /* FIFO underrun flag */
1853 #define CP_TX_STATUS_UNF (1<<25)
1854 /* transmit error summary flag, valid if set any of three below */
1855 #define CP_TX_STATUS_TES (1<<23)
1856 /* out-of-window collision flag */
1857 #define CP_TX_STATUS_OWC (1<<22)
1858 /* link failure flag */
1859 #define CP_TX_STATUS_LNKF (1<<21)
1860 /* excessive collisions flag */
1861 #define CP_TX_STATUS_EXC (1<<20)
1862
1863 if (!(txdw0 & CP_TX_OWN))
1864 {
1865 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1866 return 0 ;
1867 }
1868
1869 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1870
1871 if (txdw0 & CP_TX_FS)
1872 {
1873 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1874
1875 /* reset internal buffer offset */
1876 s->cplus_txbuffer_offset = 0;
1877 }
1878
1879 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1880 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1881
1882 /* make sure we have enough space to assemble the packet */
1883 if (!s->cplus_txbuffer)
1884 {
1885 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1886 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
1887 s->cplus_txbuffer_offset = 0;
1888 }
1889
1890 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1891 {
1892 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
1893 s->cplus_txbuffer = realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
1894
1895 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
1896 }
1897
1898 if (!s->cplus_txbuffer)
1899 {
1900 /* out of memory */
1901
1902 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
1903
1904 /* update tally counter */
1905 ++s->tally_counters.TxERR;
1906 ++s->tally_counters.TxAbt;
1907
1908 return 0;
1909 }
1910
1911 /* append more data to the packet */
1912
1913 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
1914 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
1915
1916 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
1917 s->cplus_txbuffer_offset += txsize;
1918
1919 /* seek to next Rx descriptor */
1920 if (txdw0 & CP_TX_EOR)
1921 {
1922 s->currCPlusTxDesc = 0;
1923 }
1924 else
1925 {
1926 ++s->currCPlusTxDesc;
1927 if (s->currCPlusTxDesc >= 64)
1928 s->currCPlusTxDesc = 0;
1929 }
1930
1931 /* transfer ownership to target */
1932 txdw0 &= ~CP_RX_OWN;
1933
1934 /* reset error indicator bits */
1935 txdw0 &= ~CP_TX_STATUS_UNF;
1936 txdw0 &= ~CP_TX_STATUS_TES;
1937 txdw0 &= ~CP_TX_STATUS_OWC;
1938 txdw0 &= ~CP_TX_STATUS_LNKF;
1939 txdw0 &= ~CP_TX_STATUS_EXC;
1940
1941 /* update ring data */
1942 val = cpu_to_le32(txdw0);
1943 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1944 // val = cpu_to_le32(txdw1);
1945 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
1946
1947 /* Now decide if descriptor being processed is holding the last segment of packet */
1948 if (txdw0 & CP_TX_LS)
1949 {
1950 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
1951
1952 /* can transfer fully assembled packet */
1953
1954 uint8_t *saved_buffer = s->cplus_txbuffer;
1955 int saved_size = s->cplus_txbuffer_offset;
1956 int saved_buffer_len = s->cplus_txbuffer_len;
1957
1958 /* reset the card space to protect from recursive call */
1959 s->cplus_txbuffer = NULL;
1960 s->cplus_txbuffer_offset = 0;
1961 s->cplus_txbuffer_len = 0;
1962
1963 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS))
1964 {
1965 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
1966
1967 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
1968 #define ETH_HLEN 14
1969
1970 /* ip packet header */
1971 register struct ip *ip = 0;
1972 int hlen = 0;
1973
1974 struct mbuf local_m;
1975
1976 int proto = ntohs(*(uint16_t *)(saved_buffer + 12));
1977 if (proto == ETH_P_IP)
1978 {
1979 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
1980
1981 /* not aligned */
1982 local_m.m_data = saved_buffer + ETH_HLEN;
1983 local_m.m_len = saved_size - ETH_HLEN;
1984
1985 ip = mtod(&local_m, struct ip *);
1986
1987 if (ip->ip_v != IPVERSION) {
1988 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", ip->ip_v, IPVERSION));
1989 ip = NULL;
1990 } else {
1991 hlen = ip->ip_hl << 2;
1992 }
1993 }
1994
1995 if (ip)
1996 {
1997 if (txdw0 & CP_TX_IPCS)
1998 {
1999 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2000
2001 if (hlen<sizeof(struct ip ) || hlen>local_m.m_len) {/* min header length */
2002 /* bad packet header len */
2003 /* or packet too short */
2004 }
2005 else
2006 {
2007 ip->ip_sum = 0;
2008 ip->ip_sum = cksum(&local_m, hlen);
2009 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2010 }
2011 }
2012
2013 if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2014 {
2015 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2016
2017 u_int8_t ip_protocol = ip->ip_p;
2018 u_int16_t ip_data_len = ntohs(ip->ip_len) - hlen;
2019
2020 /* maximum IP header length is 60 bytes */
2021 uint8_t saved_ip_header[60];
2022 memcpy(saved_ip_header, local_m.m_data, hlen);
2023
2024 struct mbuf local_checksum_m;
2025
2026 local_checksum_m.m_data = local_m.m_data + hlen - 12;
2027 local_checksum_m.m_len = local_m.m_len - hlen + 12;
2028
2029 /* add 4 TCP pseudoheader fields */
2030 /* copy IP source and destination fields */
2031 memcpy(local_checksum_m.m_data, saved_ip_header + 12, 8);
2032
2033 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IPPROTO_TCP)
2034 {
2035 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2036
2037 struct tcpiphdr * p_tcpip_hdr = (struct tcpiphdr *)local_checksum_m.m_data;
2038 p_tcpip_hdr->ti_x1 = 0;
2039 p_tcpip_hdr->ti_pr = IPPROTO_TCP;
2040 p_tcpip_hdr->ti_len = htons(ip_data_len);
2041
2042 struct tcphdr* p_tcp_hdr = (struct tcphdr*) (local_checksum_m.m_data+12);
2043
2044 p_tcp_hdr->th_sum = 0;
2045
2046 int tcp_checksum = cksum(&local_checksum_m, ip_data_len + 12);
2047 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2048
2049 p_tcp_hdr->th_sum = tcp_checksum;
2050 }
2051 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IPPROTO_UDP)
2052 {
2053 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2054
2055 struct udpiphdr * p_udpip_hdr = (struct udpiphdr *)local_checksum_m.m_data;
2056 p_udpip_hdr->ui_x1 = 0;
2057 p_udpip_hdr->ui_pr = IPPROTO_UDP;
2058 p_udpip_hdr->ui_len = htons(ip_data_len);
2059
2060 struct udphdr* p_udp_hdr = (struct udphdr*) (local_checksum_m.m_data+12);
2061
2062 int old_csum = p_udp_hdr->uh_sum;
2063 p_udp_hdr->uh_sum = 0;
2064
2065 int udp_checksum = cksum(&local_checksum_m, ip_data_len + 12);
2066 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2067
2068 if (old_csum != udp_checksum)
2069 {
2070 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum mismatch old=%04x new=%04x\n",
2071 old_csum, udp_checksum));
2072 }
2073
2074 p_udp_hdr->uh_sum = udp_checksum;
2075 }
2076
2077 /* restore IP header */
2078 memcpy(local_m.m_data, saved_ip_header, hlen);
2079 }
2080 }
2081 }
2082
2083 /* update tally counter */
2084 ++s->tally_counters.TxOk;
2085
2086 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2087
2088 if (TxLoopBack == (s->TxConfig & TxLoopBack))
2089 {
2090 DEBUG_PRINT(("RTL8139: +++ C+ transmit loopback mode\n"));
2091 rtl8139_receive(s, saved_buffer, saved_size);
2092 }
2093 else
2094 {
2095 /* transmit the packet */
2096 qemu_send_packet(s->vc, saved_buffer, saved_size);
2097 }
2098
2099 /* restore card space if there was no recursion and reset offset */
2100 if (!s->cplus_txbuffer)
2101 {
2102 s->cplus_txbuffer = saved_buffer;
2103 s->cplus_txbuffer_len = saved_buffer_len;
2104 s->cplus_txbuffer_offset = 0;
2105 }
2106 else
2107 {
2108 free(saved_buffer);
2109 }
2110 }
2111 else
2112 {
2113 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2114 }
2115
2116 return 1;
2117 }
2118
2119 static void rtl8139_cplus_transmit(RTL8139State *s)
2120 {
2121 int txcount = 0;
2122
2123 while (rtl8139_cplus_transmit_one(s))
2124 {
2125 ++txcount;
2126 }
2127
2128 /* Mark transfer completed */
2129 if (!txcount)
2130 {
2131 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2132 s->currCPlusTxDesc));
2133 }
2134 else
2135 {
2136 /* update interrupt status */
2137 s->IntrStatus |= TxOK;
2138 rtl8139_update_irq(s);
2139 }
2140 }
2141
2142 static void rtl8139_transmit(RTL8139State *s)
2143 {
2144 int descriptor = s->currTxDesc, txcount = 0;
2145
2146 /*while*/
2147 if (rtl8139_transmit_one(s, descriptor))
2148 {
2149 ++s->currTxDesc;
2150 s->currTxDesc %= 4;
2151 ++txcount;
2152 }
2153
2154 /* Mark transfer completed */
2155 if (!txcount)
2156 {
2157 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2158 }
2159 }
2160
2161 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2162 {
2163
2164 int descriptor = txRegOffset/4;
2165
2166 /* handle C+ transmit mode register configuration */
2167
2168 if (rtl8139_cp_transmitter_enabled(s))
2169 {
2170 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2171
2172 /* handle Dump Tally Counters command */
2173 s->TxStatus[descriptor] = val;
2174
2175 if (descriptor == 0 && (val & 0x8))
2176 {
2177 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2178
2179 /* dump tally counters to specified memory location */
2180 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2181
2182 /* mark dump completed */
2183 s->TxStatus[0] &= ~0x8;
2184 }
2185
2186 return;
2187 }
2188
2189 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2190
2191 /* mask only reserved bits */
2192 val &= ~0xff00c000; /* these bits are reset on write */
2193 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2194
2195 s->TxStatus[descriptor] = val;
2196
2197 /* attempt to start transmission */
2198 rtl8139_transmit(s);
2199 }
2200
2201 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2202 {
2203 uint32_t ret = s->TxStatus[txRegOffset/4];
2204
2205 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2206
2207 return ret;
2208 }
2209
2210 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2211 {
2212 uint16_t ret = 0;
2213
2214 /* Simulate TSAD, it is read only anyway */
2215
2216 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2217 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2218 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2219 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2220
2221 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2222 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2223 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2224 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2225
2226 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2227 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2228 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2229 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2230
2231 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2232 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2233 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2234 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2235
2236
2237 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2238
2239 return ret;
2240 }
2241
2242 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2243 {
2244 uint16_t ret = s->CSCR;
2245
2246 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2247
2248 return ret;
2249 }
2250
2251 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2252 {
2253 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2254
2255 s->TxAddr[txAddrOffset/4] = le32_to_cpu(val);
2256
2257 s->currCPlusTxDesc = 0;
2258 }
2259
2260 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2261 {
2262 uint32_t ret = cpu_to_le32(s->TxAddr[txAddrOffset/4]);
2263
2264 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2265
2266 return ret;
2267 }
2268
2269 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2270 {
2271 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2272
2273 /* this value is off by 16 */
2274 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2275
2276 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2277 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2278 }
2279
2280 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2281 {
2282 /* this value is off by 16 */
2283 uint32_t ret = s->RxBufPtr - 0x10;
2284
2285 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2286
2287 return ret;
2288 }
2289
2290 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2291 {
2292 /* this value is NOT off by 16 */
2293 uint32_t ret = s->RxBufAddr;
2294
2295 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2296
2297 return ret;
2298 }
2299
2300 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2301 {
2302 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2303
2304 s->RxBuf = val;
2305
2306 /* may need to reset rxring here */
2307 }
2308
2309 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2310 {
2311 uint32_t ret = s->RxBuf;
2312
2313 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2314
2315 return ret;
2316 }
2317
2318 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2319 {
2320 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2321
2322 /* mask unwriteable bits */
2323 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2324
2325 s->IntrMask = val;
2326
2327 rtl8139_update_irq(s);
2328 }
2329
2330 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2331 {
2332 uint32_t ret = s->IntrMask;
2333
2334 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2335
2336 return ret;
2337 }
2338
2339 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2340 {
2341 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2342
2343 #if 0
2344
2345 /* writing to ISR has no effect */
2346
2347 return;
2348
2349 #else
2350 uint16_t newStatus = s->IntrStatus & ~val;
2351
2352 /* mask unwriteable bits */
2353 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2354
2355 /* writing 1 to interrupt status register bit clears it */
2356 s->IntrStatus = 0;
2357 rtl8139_update_irq(s);
2358
2359 s->IntrStatus = newStatus;
2360 rtl8139_update_irq(s);
2361 #endif
2362 }
2363
2364 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2365 {
2366 uint32_t ret = s->IntrStatus;
2367
2368 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2369
2370 #if 0
2371
2372 /* reading ISR clears all interrupts */
2373 s->IntrStatus = 0;
2374
2375 rtl8139_update_irq(s);
2376
2377 #endif
2378
2379 return ret;
2380 }
2381
2382 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2383 {
2384 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2385
2386 /* mask unwriteable bits */
2387 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2388
2389 s->MultiIntr = val;
2390 }
2391
2392 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2393 {
2394 uint32_t ret = s->MultiIntr;
2395
2396 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2397
2398 return ret;
2399 }
2400
2401 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2402 {
2403 RTL8139State *s = opaque;
2404
2405 addr &= 0xff;
2406
2407 switch (addr)
2408 {
2409 case MAC0 ... MAC0+5:
2410 s->phys[addr - MAC0] = val;
2411 break;
2412 case MAC0+6 ... MAC0+7:
2413 /* reserved */
2414 break;
2415 case MAR0 ... MAR0+7:
2416 s->mult[addr - MAR0] = val;
2417 break;
2418 case ChipCmd:
2419 rtl8139_ChipCmd_write(s, val);
2420 break;
2421 case Cfg9346:
2422 rtl8139_Cfg9346_write(s, val);
2423 break;
2424 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2425 rtl8139_TxConfig_writeb(s, val);
2426 break;
2427 case Config0:
2428 rtl8139_Config0_write(s, val);
2429 break;
2430 case Config1:
2431 rtl8139_Config1_write(s, val);
2432 break;
2433 case Config3:
2434 rtl8139_Config3_write(s, val);
2435 break;
2436 case Config4:
2437 rtl8139_Config4_write(s, val);
2438 break;
2439 case Config5:
2440 rtl8139_Config5_write(s, val);
2441 break;
2442 case MediaStatus:
2443 /* ignore */
2444 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2445 break;
2446
2447 case HltClk:
2448 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2449 if (val == 'R')
2450 {
2451 s->clock_enabled = 1;
2452 }
2453 else if (val == 'H')
2454 {
2455 s->clock_enabled = 0;
2456 }
2457 break;
2458
2459 case TxThresh:
2460 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2461 s->TxThresh = val;
2462 break;
2463
2464 case TxPoll:
2465 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2466 if (val & (1 << 7))
2467 {
2468 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2469 //rtl8139_cplus_transmit(s);
2470 }
2471 if (val & (1 << 6))
2472 {
2473 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2474 rtl8139_cplus_transmit(s);
2475 }
2476
2477 break;
2478
2479 default:
2480 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2481 break;
2482 }
2483 }
2484
2485 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2486 {
2487 RTL8139State *s = opaque;
2488
2489 addr &= 0xfe;
2490
2491 switch (addr)
2492 {
2493 case IntrMask:
2494 rtl8139_IntrMask_write(s, val);
2495 break;
2496
2497 case IntrStatus:
2498 rtl8139_IntrStatus_write(s, val);
2499 break;
2500
2501 case MultiIntr:
2502 rtl8139_MultiIntr_write(s, val);
2503 break;
2504
2505 case RxBufPtr:
2506 rtl8139_RxBufPtr_write(s, val);
2507 break;
2508
2509 case BasicModeCtrl:
2510 rtl8139_BasicModeCtrl_write(s, val);
2511 break;
2512 case BasicModeStatus:
2513 rtl8139_BasicModeStatus_write(s, val);
2514 break;
2515 case NWayAdvert:
2516 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2517 s->NWayAdvert = val;
2518 break;
2519 case NWayLPAR:
2520 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2521 break;
2522 case NWayExpansion:
2523 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2524 s->NWayExpansion = val;
2525 break;
2526
2527 case CpCmd:
2528 rtl8139_CpCmd_write(s, val);
2529 break;
2530
2531 case IntrMitigate:
2532 rtl8139_IntrMitigate_write(s, val);
2533 break;
2534
2535 default:
2536 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2537
2538 #ifdef TARGET_WORDS_BIGENDIAN
2539 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2540 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2541 #else
2542 rtl8139_io_writeb(opaque, addr, val & 0xff);
2543 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2544 #endif
2545 break;
2546 }
2547 }
2548
2549 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2550 {
2551 RTL8139State *s = opaque;
2552
2553 addr &= 0xfc;
2554
2555 switch (addr)
2556 {
2557 case RxMissed:
2558 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2559 s->RxMissed = 0;
2560 break;
2561
2562 case TxConfig:
2563 rtl8139_TxConfig_write(s, val);
2564 break;
2565
2566 case RxConfig:
2567 rtl8139_RxConfig_write(s, val);
2568 break;
2569
2570 case TxStatus0 ... TxStatus0+4*4-1:
2571 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2572 break;
2573
2574 case TxAddr0 ... TxAddr0+4*4-1:
2575 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2576 break;
2577
2578 case RxBuf:
2579 rtl8139_RxBuf_write(s, val);
2580 break;
2581
2582 case RxRingAddrLO:
2583 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2584 s->RxRingAddrLO = val;
2585 break;
2586
2587 case RxRingAddrHI:
2588 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2589 s->RxRingAddrHI = val;
2590 break;
2591
2592 case Timer:
2593 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2594 s->TCTR = 0;
2595 s->TCTR_base = qemu_get_clock(vm_clock);
2596 break;
2597
2598 case FlashReg:
2599 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2600 s->TimerInt = val;
2601 break;
2602
2603 default:
2604 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2605 #ifdef TARGET_WORDS_BIGENDIAN
2606 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2607 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2608 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2609 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2610 #else
2611 rtl8139_io_writeb(opaque, addr, val & 0xff);
2612 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2613 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2614 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2615 #endif
2616 break;
2617 }
2618 }
2619
2620 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2621 {
2622 RTL8139State *s = opaque;
2623 int ret;
2624
2625 addr &= 0xff;
2626
2627 switch (addr)
2628 {
2629 case MAC0 ... MAC0+5:
2630 ret = s->phys[addr - MAC0];
2631 break;
2632 case MAC0+6 ... MAC0+7:
2633 ret = 0;
2634 break;
2635 case MAR0 ... MAR0+7:
2636 ret = s->mult[addr - MAR0];
2637 break;
2638 case ChipCmd:
2639 ret = rtl8139_ChipCmd_read(s);
2640 break;
2641 case Cfg9346:
2642 ret = rtl8139_Cfg9346_read(s);
2643 break;
2644 case Config0:
2645 ret = rtl8139_Config0_read(s);
2646 break;
2647 case Config1:
2648 ret = rtl8139_Config1_read(s);
2649 break;
2650 case Config3:
2651 ret = rtl8139_Config3_read(s);
2652 break;
2653 case Config4:
2654 ret = rtl8139_Config4_read(s);
2655 break;
2656 case Config5:
2657 ret = rtl8139_Config5_read(s);
2658 break;
2659
2660 case MediaStatus:
2661 ret = 0xd0;
2662 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2663 break;
2664
2665 case HltClk:
2666 ret = s->clock_enabled;
2667 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2668 break;
2669
2670 case PCIRevisionID:
2671 ret = RTL8139_PCI_REVID;
2672 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2673 break;
2674
2675 case TxThresh:
2676 ret = s->TxThresh;
2677 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2678 break;
2679
2680 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2681 ret = s->TxConfig >> 24;
2682 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2683 break;
2684
2685 default:
2686 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2687 ret = 0;
2688 break;
2689 }
2690
2691 return ret;
2692 }
2693
2694 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2695 {
2696 RTL8139State *s = opaque;
2697 uint32_t ret;
2698
2699 addr &= 0xfe; /* mask lower bit */
2700
2701 switch (addr)
2702 {
2703 case IntrMask:
2704 ret = rtl8139_IntrMask_read(s);
2705 break;
2706
2707 case IntrStatus:
2708 ret = rtl8139_IntrStatus_read(s);
2709 break;
2710
2711 case MultiIntr:
2712 ret = rtl8139_MultiIntr_read(s);
2713 break;
2714
2715 case RxBufPtr:
2716 ret = rtl8139_RxBufPtr_read(s);
2717 break;
2718
2719 case RxBufAddr:
2720 ret = rtl8139_RxBufAddr_read(s);
2721 break;
2722
2723 case BasicModeCtrl:
2724 ret = rtl8139_BasicModeCtrl_read(s);
2725 break;
2726 case BasicModeStatus:
2727 ret = rtl8139_BasicModeStatus_read(s);
2728 break;
2729 case NWayAdvert:
2730 ret = s->NWayAdvert;
2731 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2732 break;
2733 case NWayLPAR:
2734 ret = s->NWayLPAR;
2735 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2736 break;
2737 case NWayExpansion:
2738 ret = s->NWayExpansion;
2739 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2740 break;
2741
2742 case CpCmd:
2743 ret = rtl8139_CpCmd_read(s);
2744 break;
2745
2746 case IntrMitigate:
2747 ret = rtl8139_IntrMitigate_read(s);
2748 break;
2749
2750 case TxSummary:
2751 ret = rtl8139_TSAD_read(s);
2752 break;
2753
2754 case CSCR:
2755 ret = rtl8139_CSCR_read(s);
2756 break;
2757
2758 default:
2759 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2760
2761 #ifdef TARGET_WORDS_BIGENDIAN
2762 ret = rtl8139_io_readb(opaque, addr) << 8;
2763 ret |= rtl8139_io_readb(opaque, addr + 1);
2764 #else
2765 ret = rtl8139_io_readb(opaque, addr);
2766 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2767 #endif
2768
2769 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2770 break;
2771 }
2772
2773 return ret;
2774 }
2775
2776 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2777 {
2778 RTL8139State *s = opaque;
2779 uint32_t ret;
2780
2781 addr &= 0xfc; /* also mask low 2 bits */
2782
2783 switch (addr)
2784 {
2785 case RxMissed:
2786 ret = s->RxMissed;
2787
2788 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
2789 break;
2790
2791 case TxConfig:
2792 ret = rtl8139_TxConfig_read(s);
2793 break;
2794
2795 case RxConfig:
2796 ret = rtl8139_RxConfig_read(s);
2797 break;
2798
2799 case TxStatus0 ... TxStatus0+4*4-1:
2800 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2801 break;
2802
2803 case TxAddr0 ... TxAddr0+4*4-1:
2804 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
2805 break;
2806
2807 case RxBuf:
2808 ret = rtl8139_RxBuf_read(s);
2809 break;
2810
2811 case RxRingAddrLO:
2812 ret = s->RxRingAddrLO;
2813 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
2814 break;
2815
2816 case RxRingAddrHI:
2817 ret = s->RxRingAddrHI;
2818 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
2819 break;
2820
2821 case Timer:
2822 ret = s->TCTR;
2823 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
2824 break;
2825
2826 case FlashReg:
2827 ret = s->TimerInt;
2828 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
2829 break;
2830
2831 default:
2832 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
2833
2834 #ifdef TARGET_WORDS_BIGENDIAN
2835 ret = rtl8139_io_readb(opaque, addr) << 24;
2836 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
2837 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
2838 ret |= rtl8139_io_readb(opaque, addr + 3);
2839 #else
2840 ret = rtl8139_io_readb(opaque, addr);
2841 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2842 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
2843 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
2844 #endif
2845
2846 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
2847 break;
2848 }
2849
2850 return ret;
2851 }
2852
2853 /* */
2854
2855 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
2856 {
2857 rtl8139_io_writeb(opaque, addr & 0xFF, val);
2858 }
2859
2860 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
2861 {
2862 rtl8139_io_writew(opaque, addr & 0xFF, val);
2863 }
2864
2865 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
2866 {
2867 rtl8139_io_writel(opaque, addr & 0xFF, val);
2868 }
2869
2870 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
2871 {
2872 return rtl8139_io_readb(opaque, addr & 0xFF);
2873 }
2874
2875 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
2876 {
2877 return rtl8139_io_readw(opaque, addr & 0xFF);
2878 }
2879
2880 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
2881 {
2882 return rtl8139_io_readl(opaque, addr & 0xFF);
2883 }
2884
2885 /* */
2886
2887 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2888 {
2889 rtl8139_io_writeb(opaque, addr & 0xFF, val);
2890 }
2891
2892 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2893 {
2894 rtl8139_io_writew(opaque, addr & 0xFF, val);
2895 }
2896
2897 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2898 {
2899 rtl8139_io_writel(opaque, addr & 0xFF, val);
2900 }
2901
2902 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
2903 {
2904 return rtl8139_io_readb(opaque, addr & 0xFF);
2905 }
2906
2907 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
2908 {
2909 return rtl8139_io_readw(opaque, addr & 0xFF);
2910 }
2911
2912 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
2913 {
2914 return rtl8139_io_readl(opaque, addr & 0xFF);
2915 }
2916
2917 /* */
2918
2919 static void rtl8139_save(QEMUFile* f,void* opaque)
2920 {
2921 RTL8139State* s=(RTL8139State*)opaque;
2922 int i;
2923
2924 qemu_put_buffer(f, s->phys, 6);
2925 qemu_put_buffer(f, s->mult, 8);
2926
2927 for (i=0; i<4; ++i)
2928 {
2929 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
2930 }
2931 for (i=0; i<4; ++i)
2932 {
2933 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
2934 }
2935
2936 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
2937 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
2938 qemu_put_be32s(f, &s->RxBufPtr);
2939 qemu_put_be32s(f, &s->RxBufAddr);
2940
2941 qemu_put_be16s(f, &s->IntrStatus);
2942 qemu_put_be16s(f, &s->IntrMask);
2943
2944 qemu_put_be32s(f, &s->TxConfig);
2945 qemu_put_be32s(f, &s->RxConfig);
2946 qemu_put_be32s(f, &s->RxMissed);
2947 qemu_put_be16s(f, &s->CSCR);
2948
2949 qemu_put_8s(f, &s->Cfg9346);
2950 qemu_put_8s(f, &s->Config0);
2951 qemu_put_8s(f, &s->Config1);
2952 qemu_put_8s(f, &s->Config3);
2953 qemu_put_8s(f, &s->Config4);
2954 qemu_put_8s(f, &s->Config5);
2955
2956 qemu_put_8s(f, &s->clock_enabled);
2957 qemu_put_8s(f, &s->bChipCmdState);
2958
2959 qemu_put_be16s(f, &s->MultiIntr);
2960
2961 qemu_put_be16s(f, &s->BasicModeCtrl);
2962 qemu_put_be16s(f, &s->BasicModeStatus);
2963 qemu_put_be16s(f, &s->NWayAdvert);
2964 qemu_put_be16s(f, &s->NWayLPAR);
2965 qemu_put_be16s(f, &s->NWayExpansion);
2966
2967 qemu_put_be16s(f, &s->CpCmd);
2968 qemu_put_8s(f, &s->TxThresh);
2969
2970 qemu_put_be32s(f, &s->irq);
2971 qemu_put_buffer(f, s->macaddr, 6);
2972 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
2973
2974 qemu_put_be32s(f, &s->currTxDesc);
2975 qemu_put_be32s(f, &s->currCPlusRxDesc);
2976 qemu_put_be32s(f, &s->currCPlusTxDesc);
2977 qemu_put_be32s(f, &s->RxRingAddrLO);
2978 qemu_put_be32s(f, &s->RxRingAddrHI);
2979
2980 for (i=0; i<EEPROM_9346_SIZE; ++i)
2981 {
2982 qemu_put_be16s(f, &s->eeprom.contents[i]);
2983 }
2984 qemu_put_be32s(f, &s->eeprom.mode);
2985 qemu_put_be32s(f, &s->eeprom.tick);
2986 qemu_put_8s(f, &s->eeprom.address);
2987 qemu_put_be16s(f, &s->eeprom.input);
2988 qemu_put_be16s(f, &s->eeprom.output);
2989
2990 qemu_put_8s(f, &s->eeprom.eecs);
2991 qemu_put_8s(f, &s->eeprom.eesk);
2992 qemu_put_8s(f, &s->eeprom.eedi);
2993 qemu_put_8s(f, &s->eeprom.eedo);
2994
2995 qemu_put_be32s(f, &s->TCTR);
2996 qemu_put_be32s(f, &s->TimerInt);
2997 qemu_put_be64s(f, &s->TCTR_base);
2998
2999 RTL8139TallyCounters_save(f, &s->tally_counters);
3000 }
3001
3002 static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3003 {
3004 RTL8139State* s=(RTL8139State*)opaque;
3005 int i;
3006
3007 /* just 2 versions for now */
3008 if (version_id > 2)
3009 return -EINVAL;
3010
3011 /* saved since version 1 */
3012 qemu_get_buffer(f, s->phys, 6);
3013 qemu_get_buffer(f, s->mult, 8);
3014
3015 for (i=0; i<4; ++i)
3016 {
3017 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3018 }
3019 for (i=0; i<4; ++i)
3020 {
3021 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3022 }
3023
3024 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3025 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3026 qemu_get_be32s(f, &s->RxBufPtr);
3027 qemu_get_be32s(f, &s->RxBufAddr);
3028
3029 qemu_get_be16s(f, &s->IntrStatus);
3030 qemu_get_be16s(f, &s->IntrMask);
3031
3032 qemu_get_be32s(f, &s->TxConfig);
3033 qemu_get_be32s(f, &s->RxConfig);
3034 qemu_get_be32s(f, &s->RxMissed);
3035 qemu_get_be16s(f, &s->CSCR);
3036
3037 qemu_get_8s(f, &s->Cfg9346);
3038 qemu_get_8s(f, &s->Config0);
3039 qemu_get_8s(f, &s->Config1);
3040 qemu_get_8s(f, &s->Config3);
3041 qemu_get_8s(f, &s->Config4);
3042 qemu_get_8s(f, &s->Config5);
3043
3044 qemu_get_8s(f, &s->clock_enabled);
3045 qemu_get_8s(f, &s->bChipCmdState);
3046
3047 qemu_get_be16s(f, &s->MultiIntr);
3048
3049 qemu_get_be16s(f, &s->BasicModeCtrl);
3050 qemu_get_be16s(f, &s->BasicModeStatus);
3051 qemu_get_be16s(f, &s->NWayAdvert);
3052 qemu_get_be16s(f, &s->NWayLPAR);
3053 qemu_get_be16s(f, &s->NWayExpansion);
3054
3055 qemu_get_be16s(f, &s->CpCmd);
3056 qemu_get_8s(f, &s->TxThresh);
3057
3058 qemu_get_be32s(f, &s->irq);
3059 qemu_get_buffer(f, s->macaddr, 6);
3060 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3061
3062 qemu_get_be32s(f, &s->currTxDesc);
3063 qemu_get_be32s(f, &s->currCPlusRxDesc);
3064 qemu_get_be32s(f, &s->currCPlusTxDesc);
3065 qemu_get_be32s(f, &s->RxRingAddrLO);
3066 qemu_get_be32s(f, &s->RxRingAddrHI);
3067
3068 for (i=0; i<EEPROM_9346_SIZE; ++i)
3069 {
3070 qemu_get_be16s(f, &s->eeprom.contents[i]);
3071 }
3072 qemu_get_be32s(f, &s->eeprom.mode);
3073 qemu_get_be32s(f, &s->eeprom.tick);
3074 qemu_get_8s(f, &s->eeprom.address);
3075 qemu_get_be16s(f, &s->eeprom.input);
3076 qemu_get_be16s(f, &s->eeprom.output);
3077
3078 qemu_get_8s(f, &s->eeprom.eecs);
3079 qemu_get_8s(f, &s->eeprom.eesk);
3080 qemu_get_8s(f, &s->eeprom.eedi);
3081 qemu_get_8s(f, &s->eeprom.eedo);
3082
3083 /* saved since version 2 */
3084 if (version_id >= 2)
3085 {
3086 qemu_get_be32s(f, &s->TCTR);
3087 qemu_get_be32s(f, &s->TimerInt);
3088 qemu_get_be64s(f, &s->TCTR_base);
3089
3090 RTL8139TallyCounters_load(f, &s->tally_counters);
3091 }
3092 else
3093 {
3094 /* not saved, use default */
3095 s->TCTR = 0;
3096 s->TimerInt = 0;
3097 s->TCTR_base = 0;
3098
3099 RTL8139TallyCounters_clear(&s->tally_counters);
3100 }
3101
3102 return 0;
3103 }
3104
3105 /***********************************************************/
3106 /* PCI RTL8139 definitions */
3107
3108 typedef struct PCIRTL8139State {
3109 PCIDevice dev;
3110 RTL8139State rtl8139;
3111 } PCIRTL8139State;
3112
3113 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3114 uint32_t addr, uint32_t size, int type)
3115 {
3116 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3117 RTL8139State *s = &d->rtl8139;
3118
3119 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3120 }
3121
3122 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3123 uint32_t addr, uint32_t size, int type)
3124 {
3125 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3126 RTL8139State *s = &d->rtl8139;
3127
3128 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3129 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3130
3131 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3132 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3133
3134 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3135 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3136 }
3137
3138 static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3139 rtl8139_mmio_readb,
3140 rtl8139_mmio_readw,
3141 rtl8139_mmio_readl,
3142 };
3143
3144 static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3145 rtl8139_mmio_writeb,
3146 rtl8139_mmio_writew,
3147 rtl8139_mmio_writel,
3148 };
3149
3150 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3151 {
3152 int64_t next_time = current_time +
3153 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3154 if (next_time <= current_time)
3155 next_time = current_time + 1;
3156 return next_time;
3157 }
3158
3159 #if RTL8139_ONBOARD_TIMER
3160 static void rtl8139_timer(void *opaque)
3161 {
3162 RTL8139State *s = opaque;
3163
3164 int is_timeout = 0;
3165
3166 int64_t curr_time;
3167 uint32_t curr_tick;
3168
3169 if (!s->clock_enabled)
3170 {
3171 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3172 return;
3173 }
3174
3175 curr_time = qemu_get_clock(vm_clock);
3176
3177 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3178
3179 if (s->TimerInt && curr_tick >= s->TimerInt)
3180 {
3181 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3182 {
3183 is_timeout = 1;
3184 }
3185 }
3186
3187 s->TCTR = curr_tick;
3188
3189 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3190
3191 if (is_timeout)
3192 {
3193 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3194 s->IntrStatus |= PCSTimeout;
3195 rtl8139_update_irq(s);
3196 }
3197
3198 qemu_mod_timer(s->timer,
3199 rtl8139_get_next_tctr_time(s,curr_time));
3200 }
3201 #endif /* RTL8139_ONBOARD_TIMER */
3202
3203 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd)
3204 {
3205 PCIRTL8139State *d;
3206 RTL8139State *s;
3207 uint8_t *pci_conf;
3208
3209 d = (PCIRTL8139State *)pci_register_device(bus,
3210 "RTL8139", sizeof(PCIRTL8139State),
3211 -1,
3212 NULL, NULL);
3213 pci_conf = d->dev.config;
3214 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3215 pci_conf[0x01] = 0x10;
3216 pci_conf[0x02] = 0x39;
3217 pci_conf[0x03] = 0x81;
3218 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3219 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3220 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3221 pci_conf[0x0b] = 0x02;
3222 pci_conf[0x0e] = 0x00; /* header_type */
3223 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3224 pci_conf[0x34] = 0xdc;
3225
3226 s = &d->rtl8139;
3227
3228 /* I/O handler for memory-mapped I/O */
3229 s->rtl8139_mmio_io_addr =
3230 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3231
3232 pci_register_io_region(&d->dev, 0, 0x100,
3233 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3234
3235 pci_register_io_region(&d->dev, 1, 0x100,
3236 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3237
3238 s->irq = 16; /* PCI interrupt */
3239 s->pci_dev = (PCIDevice *)d;
3240 memcpy(s->macaddr, nd->macaddr, 6);
3241 rtl8139_reset(s);
3242 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3243 rtl8139_can_receive, s);
3244
3245 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3246 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3247 s->macaddr[0],
3248 s->macaddr[1],
3249 s->macaddr[2],
3250 s->macaddr[3],
3251 s->macaddr[4],
3252 s->macaddr[5]);
3253
3254 s->cplus_txbuffer = NULL;
3255 s->cplus_txbuffer_len = 0;
3256 s->cplus_txbuffer_offset = 0;
3257
3258 /* XXX: instance number ? */
3259 register_savevm("rtl8139", 0, 2, rtl8139_save, rtl8139_load, s);
3260 register_savevm("rtl8139_pci", 0, 1, generic_pci_save, generic_pci_load,
3261 &d->dev);
3262
3263 #if RTL8139_ONBOARD_TIMER
3264 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3265
3266 qemu_mod_timer(s->timer,
3267 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3268 #endif /* RTL8139_ONBOARD_TIMER */
3269 }
3270
Samsung s3c2440 and arm920t support for the mini2440 dev board