target-mips/op_mem.c

   1 /*
   2  *  MIPS emulation memory micro-operations for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* Standard loads and stores */
  22 void glue(op_lb, MEMSUFFIX) (void)
  23 {
  24     T0 = glue(ldsb, MEMSUFFIX)(T0);
  25     RETURN();
  26 }
  27
  28 void glue(op_lbu, MEMSUFFIX) (void)
  29 {
  30     T0 = glue(ldub, MEMSUFFIX)(T0);
  31     RETURN();
  32 }
  33
  34 void glue(op_sb, MEMSUFFIX) (void)
  35 {
  36     glue(stb, MEMSUFFIX)(T0, T1);
  37     RETURN();
  38 }
  39
  40 void glue(op_lh, MEMSUFFIX) (void)
  41 {
  42     T0 = glue(ldsw, MEMSUFFIX)(T0);
  43     RETURN();
  44 }
  45
  46 void glue(op_lhu, MEMSUFFIX) (void)
  47 {
  48     T0 = glue(lduw, MEMSUFFIX)(T0);
  49     RETURN();
  50 }
  51
  52 void glue(op_sh, MEMSUFFIX) (void)
  53 {
  54     glue(stw, MEMSUFFIX)(T0, T1);
  55     RETURN();
  56 }
  57
  58 void glue(op_lw, MEMSUFFIX) (void)
  59 {
  60     T0 = glue(ldl, MEMSUFFIX)(T0);
  61     RETURN();
  62 }
  63
  64 void glue(op_lwu, MEMSUFFIX) (void)
  65 {
  66     T0 = glue(ldl, MEMSUFFIX)(T0);
  67     RETURN();
  68 }
  69
  70 void glue(op_sw, MEMSUFFIX) (void)
  71 {
  72     glue(stl, MEMSUFFIX)(T0, T1);
  73     RETURN();
  74 }
  75
  76 /* "half" load and stores.  We must do the memory access inline,
  77    or fault handling won't work.  */
  78 void glue(op_lwl, MEMSUFFIX) (void)
  79 {
  80     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  81     CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp);
  82     RETURN();
  83 }
  84
  85 void glue(op_lwr, MEMSUFFIX) (void)
  86 {
  87     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  88     CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp);
  89     RETURN();
  90 }
  91
  92 void glue(op_swl, MEMSUFFIX) (void)
  93 {
  94     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  95     tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp);
  96     glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
  97     RETURN();
  98 }
  99
 100 void glue(op_swr, MEMSUFFIX) (void)
 101 {
 102     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
 103     tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp);
 104     glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
 105     RETURN();
 106 }
 107
 108 void glue(op_ll, MEMSUFFIX) (void)
 109 {
 110     T1 = T0;
 111     T0 = glue(ldl, MEMSUFFIX)(T0);
 112     env->CP0_LLAddr = T1;
 113     RETURN();
 114 }
 115
 116 void glue(op_sc, MEMSUFFIX) (void)
 117 {
 118     CALL_FROM_TB0(dump_sc);
 119     if (T0 == env->CP0_LLAddr) {
 120         glue(stl, MEMSUFFIX)(T0, T1);
 121         T0 = 1;
 122     } else {
 123         T0 = 0;
 124     }
 125     RETURN();
 126 }
 127
 128 #ifdef MIPS_USES_FPU
 129 void glue(op_lwc1, MEMSUFFIX) (void)
 130 {
 131     WT0 = glue(ldl, MEMSUFFIX)(T0);
 132     RETURN();
 133 }
 134 void glue(op_swc1, MEMSUFFIX) (void)
 135 {
 136     glue(stl, MEMSUFFIX)(T0, WT0);
 137     RETURN();
 138 }
 139 void glue(op_ldc1, MEMSUFFIX) (void)
 140 {
 141     DT0 = glue(ldq, MEMSUFFIX)(T0);
 142     RETURN();
 143 }
 144 void glue(op_sdc1, MEMSUFFIX) (void)
 145 {
 146     glue(stq, MEMSUFFIX)(T0, DT0);
 147     RETURN();
 148 }
 149 #endif