Add unassigned memory debugging code.
[qemu/mini2440.git] / hw / slavio_serial.c
blob404138d4b00efb608ea8063e82e32c34f8c99b8d
1 /*
2 * QEMU Sparc SLAVIO serial port emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "vl.h"
25 /* debug serial */
26 //#define DEBUG_SERIAL
28 /* debug keyboard */
29 //#define DEBUG_KBD
31 /* debug mouse */
32 //#define DEBUG_MOUSE
35 * This is the serial port, mouse and keyboard part of chip STP2001
36 * (Slave I/O), also produced as NCR89C105. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
39 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
40 * mouse and keyboard ports don't implement all functions and they are
41 * only asynchronous. There is no DMA.
46 * Modifications:
47 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
48 * serial mouse queue.
49 * Implemented serial mouse protocol.
52 #ifdef DEBUG_SERIAL
53 #define SER_DPRINTF(fmt, args...) \
54 do { printf("SER: " fmt , ##args); } while (0)
55 #define pic_set_irq(irq, level) \
56 do { printf("SER: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
57 #else
58 #define SER_DPRINTF(fmt, args...)
59 #endif
60 #ifdef DEBUG_KBD
61 #define KBD_DPRINTF(fmt, args...) \
62 do { printf("KBD: " fmt , ##args); } while (0)
63 #else
64 #define KBD_DPRINTF(fmt, args...)
65 #endif
66 #ifdef DEBUG_MOUSE
67 #define MS_DPRINTF(fmt, args...) \
68 do { printf("MSC: " fmt , ##args); } while (0)
69 #else
70 #define MS_DPRINTF(fmt, args...)
71 #endif
73 typedef enum {
74 chn_a, chn_b,
75 } chn_id_t;
77 #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
79 typedef enum {
80 ser, kbd, mouse,
81 } chn_type_t;
83 #define SERIO_QUEUE_SIZE 256
85 typedef struct {
86 uint8_t data[SERIO_QUEUE_SIZE];
87 int rptr, wptr, count;
88 } SERIOQueue;
90 typedef struct ChannelState {
91 int irq;
92 int reg;
93 int rxint, txint, rxint_under_svc, txint_under_svc;
94 chn_id_t chn; // this channel, A (base+4) or B (base+0)
95 chn_type_t type;
96 struct ChannelState *otherchn;
97 uint8_t rx, tx, wregs[16], rregs[16];
98 SERIOQueue queue;
99 CharDriverState *chr;
100 } ChannelState;
102 struct SerialState {
103 struct ChannelState chn[2];
106 #define SERIAL_MAXADDR 7
108 static void handle_kbd_command(ChannelState *s, int val);
109 static int serial_can_receive(void *opaque);
110 static void serial_receive_byte(ChannelState *s, int ch);
111 static inline void set_txint(ChannelState *s);
113 static void put_queue(void *opaque, int b)
115 ChannelState *s = opaque;
116 SERIOQueue *q = &s->queue;
118 SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
119 if (q->count >= SERIO_QUEUE_SIZE)
120 return;
121 q->data[q->wptr] = b;
122 if (++q->wptr == SERIO_QUEUE_SIZE)
123 q->wptr = 0;
124 q->count++;
125 serial_receive_byte(s, 0);
128 static uint32_t get_queue(void *opaque)
130 ChannelState *s = opaque;
131 SERIOQueue *q = &s->queue;
132 int val;
134 if (q->count == 0) {
135 return 0;
136 } else {
137 val = q->data[q->rptr];
138 if (++q->rptr == SERIO_QUEUE_SIZE)
139 q->rptr = 0;
140 q->count--;
142 KBD_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
143 if (q->count > 0)
144 serial_receive_byte(s, 0);
145 return val;
148 static int slavio_serial_update_irq_chn(ChannelState *s)
150 if ((s->wregs[1] & 1) && // interrupts enabled
151 (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
152 ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
153 s->rxint == 1) || // rx ints enabled, pending
154 ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
155 return 1;
157 return 0;
160 static void slavio_serial_update_irq(ChannelState *s)
162 int irq;
164 irq = slavio_serial_update_irq_chn(s);
165 irq |= slavio_serial_update_irq_chn(s->otherchn);
167 pic_set_irq(s->irq, irq);
170 static void slavio_serial_reset_chn(ChannelState *s)
172 int i;
174 s->reg = 0;
175 for (i = 0; i < SERIAL_MAXADDR; i++) {
176 s->rregs[i] = 0;
177 s->wregs[i] = 0;
179 s->wregs[4] = 4;
180 s->wregs[9] = 0xc0;
181 s->wregs[11] = 8;
182 s->wregs[14] = 0x30;
183 s->wregs[15] = 0xf8;
184 s->rregs[0] = 0x44;
185 s->rregs[1] = 6;
187 s->rx = s->tx = 0;
188 s->rxint = s->txint = 0;
189 s->rxint_under_svc = s->txint_under_svc = 0;
192 static void slavio_serial_reset(void *opaque)
194 SerialState *s = opaque;
195 slavio_serial_reset_chn(&s->chn[0]);
196 slavio_serial_reset_chn(&s->chn[1]);
199 static inline void clr_rxint(ChannelState *s)
201 s->rxint = 0;
202 s->rxint_under_svc = 0;
203 if (s->chn == chn_a)
204 s->rregs[3] &= ~0x20;
205 else
206 s->otherchn->rregs[3] &= ~4;
207 if (s->txint)
208 set_txint(s);
209 else
210 s->rregs[2] = 6;
211 slavio_serial_update_irq(s);
214 static inline void set_rxint(ChannelState *s)
216 s->rxint = 1;
217 if (!s->txint_under_svc) {
218 s->rxint_under_svc = 1;
219 if (s->chn == chn_a)
220 s->rregs[3] |= 0x20;
221 else
222 s->otherchn->rregs[3] |= 4;
223 s->rregs[2] = 4;
224 slavio_serial_update_irq(s);
228 static inline void clr_txint(ChannelState *s)
230 s->txint = 0;
231 s->txint_under_svc = 0;
232 if (s->chn == chn_a)
233 s->rregs[3] &= ~0x10;
234 else
235 s->otherchn->rregs[3] &= ~2;
236 if (s->rxint)
237 set_rxint(s);
238 else
239 s->rregs[2] = 6;
240 slavio_serial_update_irq(s);
243 static inline void set_txint(ChannelState *s)
245 s->txint = 1;
246 if (!s->rxint_under_svc) {
247 s->txint_under_svc = 1;
248 if (s->chn == chn_a)
249 s->rregs[3] |= 0x10;
250 else
251 s->otherchn->rregs[3] |= 2;
252 s->rregs[2] = 0;
253 slavio_serial_update_irq(s);
257 static void slavio_serial_update_parameters(ChannelState *s)
259 int speed, parity, data_bits, stop_bits;
260 QEMUSerialSetParams ssp;
262 if (!s->chr || s->type != ser)
263 return;
265 if (s->wregs[4] & 1) {
266 if (s->wregs[4] & 2)
267 parity = 'E';
268 else
269 parity = 'O';
270 } else {
271 parity = 'N';
273 if ((s->wregs[4] & 0x0c) == 0x0c)
274 stop_bits = 2;
275 else
276 stop_bits = 1;
277 switch (s->wregs[5] & 0x60) {
278 case 0x00:
279 data_bits = 5;
280 break;
281 case 0x20:
282 data_bits = 7;
283 break;
284 case 0x40:
285 data_bits = 6;
286 break;
287 default:
288 case 0x60:
289 data_bits = 8;
290 break;
292 speed = 2457600 / ((s->wregs[12] | (s->wregs[13] << 8)) + 2);
293 switch (s->wregs[4] & 0xc0) {
294 case 0x00:
295 break;
296 case 0x40:
297 speed /= 16;
298 break;
299 case 0x80:
300 speed /= 32;
301 break;
302 default:
303 case 0xc0:
304 speed /= 64;
305 break;
307 ssp.speed = speed;
308 ssp.parity = parity;
309 ssp.data_bits = data_bits;
310 ssp.stop_bits = stop_bits;
311 SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
312 speed, parity, data_bits, stop_bits);
313 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
316 static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
318 SerialState *ser = opaque;
319 ChannelState *s;
320 uint32_t saddr;
321 int newreg, channel;
323 val &= 0xff;
324 saddr = (addr & 3) >> 1;
325 channel = (addr & SERIAL_MAXADDR) >> 2;
326 s = &ser->chn[channel];
327 switch (saddr) {
328 case 0:
329 SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
330 newreg = 0;
331 switch (s->reg) {
332 case 0:
333 newreg = val & 7;
334 val &= 0x38;
335 switch (val) {
336 case 8:
337 newreg |= 0x8;
338 break;
339 case 0x28:
340 clr_txint(s);
341 break;
342 case 0x38:
343 if (s->rxint_under_svc)
344 clr_rxint(s);
345 else if (s->txint_under_svc)
346 clr_txint(s);
347 break;
348 default:
349 break;
351 break;
352 case 1 ... 3:
353 case 6 ... 8:
354 case 10 ... 11:
355 case 14 ... 15:
356 s->wregs[s->reg] = val;
357 break;
358 case 4:
359 case 5:
360 case 12:
361 case 13:
362 s->wregs[s->reg] = val;
363 slavio_serial_update_parameters(s);
364 break;
365 case 9:
366 switch (val & 0xc0) {
367 case 0:
368 default:
369 break;
370 case 0x40:
371 slavio_serial_reset_chn(&ser->chn[1]);
372 return;
373 case 0x80:
374 slavio_serial_reset_chn(&ser->chn[0]);
375 return;
376 case 0xc0:
377 slavio_serial_reset(ser);
378 return;
380 break;
381 default:
382 break;
384 if (s->reg == 0)
385 s->reg = newreg;
386 else
387 s->reg = 0;
388 break;
389 case 1:
390 SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
391 if (s->wregs[5] & 8) { // tx enabled
392 s->tx = val;
393 if (s->chr)
394 qemu_chr_write(s->chr, &s->tx, 1);
395 else if (s->type == kbd) {
396 handle_kbd_command(s, val);
398 s->rregs[0] |= 4; // Tx buffer empty
399 s->rregs[1] |= 1; // All sent
400 set_txint(s);
402 break;
403 default:
404 break;
408 static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
410 SerialState *ser = opaque;
411 ChannelState *s;
412 uint32_t saddr;
413 uint32_t ret;
414 int channel;
416 saddr = (addr & 3) >> 1;
417 channel = (addr & SERIAL_MAXADDR) >> 2;
418 s = &ser->chn[channel];
419 switch (saddr) {
420 case 0:
421 SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
422 ret = s->rregs[s->reg];
423 s->reg = 0;
424 return ret;
425 case 1:
426 s->rregs[0] &= ~1;
427 clr_rxint(s);
428 if (s->type == kbd || s->type == mouse)
429 ret = get_queue(s);
430 else
431 ret = s->rx;
432 SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
433 return ret;
434 default:
435 break;
437 return 0;
440 static int serial_can_receive(void *opaque)
442 ChannelState *s = opaque;
443 int ret;
445 if (((s->wregs[3] & 1) == 0) // Rx not enabled
446 || ((s->rregs[0] & 1) == 1)) // char already available
447 ret = 0;
448 else
449 ret = 1;
450 //SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret);
451 return ret;
454 static void serial_receive_byte(ChannelState *s, int ch)
456 SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
457 s->rregs[0] |= 1;
458 s->rx = ch;
459 set_rxint(s);
462 static void serial_receive_break(ChannelState *s)
464 s->rregs[0] |= 0x80;
465 slavio_serial_update_irq(s);
468 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
470 ChannelState *s = opaque;
471 serial_receive_byte(s, buf[0]);
474 static void serial_event(void *opaque, int event)
476 ChannelState *s = opaque;
477 if (event == CHR_EVENT_BREAK)
478 serial_receive_break(s);
481 static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
482 slavio_serial_mem_readb,
483 slavio_serial_mem_readb,
484 slavio_serial_mem_readb,
487 static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
488 slavio_serial_mem_writeb,
489 slavio_serial_mem_writeb,
490 slavio_serial_mem_writeb,
493 static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
495 qemu_put_be32s(f, &s->irq);
496 qemu_put_be32s(f, &s->reg);
497 qemu_put_be32s(f, &s->rxint);
498 qemu_put_be32s(f, &s->txint);
499 qemu_put_be32s(f, &s->rxint_under_svc);
500 qemu_put_be32s(f, &s->txint_under_svc);
501 qemu_put_8s(f, &s->rx);
502 qemu_put_8s(f, &s->tx);
503 qemu_put_buffer(f, s->wregs, 16);
504 qemu_put_buffer(f, s->rregs, 16);
507 static void slavio_serial_save(QEMUFile *f, void *opaque)
509 SerialState *s = opaque;
511 slavio_serial_save_chn(f, &s->chn[0]);
512 slavio_serial_save_chn(f, &s->chn[1]);
515 static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)
517 if (version_id > 2)
518 return -EINVAL;
520 qemu_get_be32s(f, &s->irq);
521 qemu_get_be32s(f, &s->reg);
522 qemu_get_be32s(f, &s->rxint);
523 qemu_get_be32s(f, &s->txint);
524 if (version_id >= 2) {
525 qemu_get_be32s(f, &s->rxint_under_svc);
526 qemu_get_be32s(f, &s->txint_under_svc);
528 qemu_get_8s(f, &s->rx);
529 qemu_get_8s(f, &s->tx);
530 qemu_get_buffer(f, s->wregs, 16);
531 qemu_get_buffer(f, s->rregs, 16);
532 return 0;
535 static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
537 SerialState *s = opaque;
538 int ret;
540 ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
541 if (ret != 0)
542 return ret;
543 ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
544 return ret;
548 SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2)
550 int slavio_serial_io_memory, i;
551 SerialState *s;
553 s = qemu_mallocz(sizeof(SerialState));
554 if (!s)
555 return NULL;
557 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
558 cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
560 s->chn[0].chr = chr1;
561 s->chn[1].chr = chr2;
563 for (i = 0; i < 2; i++) {
564 s->chn[i].irq = irq;
565 s->chn[i].chn = 1 - i;
566 s->chn[i].type = ser;
567 if (s->chn[i].chr) {
568 qemu_chr_add_read_handler(s->chn[i].chr, serial_can_receive, serial_receive1, &s->chn[i]);
569 qemu_chr_add_event_handler(s->chn[i].chr, serial_event);
572 s->chn[0].otherchn = &s->chn[1];
573 s->chn[1].otherchn = &s->chn[0];
574 register_savevm("slavio_serial", base, 2, slavio_serial_save, slavio_serial_load, s);
575 qemu_register_reset(slavio_serial_reset, s);
576 slavio_serial_reset(s);
577 return s;
580 static const uint8_t keycodes[128] = {
581 127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53,
582 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78,
583 79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103,
584 104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12,
585 14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112,
586 113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0,
587 90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66,
588 0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67,
591 static void sunkbd_event(void *opaque, int ch)
593 ChannelState *s = opaque;
594 int release = ch & 0x80;
596 ch = keycodes[ch & 0x7f];
597 KBD_DPRINTF("Keycode %d (%s)\n", ch, release? "release" : "press");
598 put_queue(s, ch | release);
601 static void handle_kbd_command(ChannelState *s, int val)
603 KBD_DPRINTF("Command %d\n", val);
604 switch (val) {
605 case 1: // Reset, return type code
606 put_queue(s, 0xff);
607 put_queue(s, 5); // Type 5
608 break;
609 case 7: // Query layout
610 put_queue(s, 0xfe);
611 put_queue(s, 0x20); // XXX, layout?
612 break;
613 default:
614 break;
618 static void sunmouse_event(void *opaque,
619 int dx, int dy, int dz, int buttons_state)
621 ChannelState *s = opaque;
622 int ch;
624 /* XXX: SDL sometimes generates nul events: we delete them */
625 if (dx == 0 && dy == 0 && dz == 0 && buttons_state == 0)
626 return;
627 MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
629 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
631 if (buttons_state & MOUSE_EVENT_LBUTTON)
632 ch ^= 0x4;
633 if (buttons_state & MOUSE_EVENT_MBUTTON)
634 ch ^= 0x2;
635 if (buttons_state & MOUSE_EVENT_RBUTTON)
636 ch ^= 0x1;
638 put_queue(s, ch);
640 ch = dx;
642 if (ch > 127)
643 ch=127;
644 else if (ch < -127)
645 ch=-127;
647 put_queue(s, ch & 0xff);
649 ch = -dy;
651 if (ch > 127)
652 ch=127;
653 else if (ch < -127)
654 ch=-127;
656 put_queue(s, ch & 0xff);
658 // MSC protocol specify two extra motion bytes
660 put_queue(s, 0);
661 put_queue(s, 0);
664 void slavio_serial_ms_kbd_init(int base, int irq)
666 int slavio_serial_io_memory, i;
667 SerialState *s;
669 s = qemu_mallocz(sizeof(SerialState));
670 if (!s)
671 return;
672 for (i = 0; i < 2; i++) {
673 s->chn[i].irq = irq;
674 s->chn[i].chn = 1 - i;
675 s->chn[i].chr = NULL;
677 s->chn[0].otherchn = &s->chn[1];
678 s->chn[1].otherchn = &s->chn[0];
679 s->chn[0].type = mouse;
680 s->chn[1].type = kbd;
682 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
683 cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
685 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0);
686 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
687 qemu_register_reset(slavio_serial_reset, s);
688 slavio_serial_reset(s);