vl.h

   1 /*
   2  * QEMU System Emulator header
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #ifndef VL_H
  25 #define VL_H
  26
  27 #include "qemu-common.h"
  28
  29 /* FIXME: Remove this.  */
  30 #include "block.h"
  31
  32 #ifndef glue
  33 #define xglue(x, y) x ## y
  34 #define glue(x, y) xglue(x, y)
  35 #define stringify(s)    tostring(s)
  36 #define tostring(s)     #s
  37 #endif
  38
  39 #ifndef likely
  40 #if __GNUC__ < 3
  41 #define __builtin_expect(x, n) (x)
  42 #endif
  43
  44 #define likely(x)   __builtin_expect(!!(x), 1)
  45 #define unlikely(x)   __builtin_expect(!!(x), 0)
  46 #endif
  47
  48 #ifndef MIN
  49 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
  50 #endif
  51 #ifndef MAX
  52 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
  53 #endif
  54
  55 #ifndef always_inline
  56 #if (__GNUC__ < 3) || defined(__APPLE__)
  57 #define always_inline inline
  58 #else
  59 #define always_inline __attribute__ (( always_inline )) inline
  60 #endif
  61 #endif
  62
  63 #include "audio/audio.h"
  64
  65 /* vl.c */
  66 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
  67
  68 void hw_error(const char *fmt, ...);
  69
  70 extern const char *bios_dir;
  71 extern const char *bios_name;
  72
  73 extern int vm_running;
  74 extern const char *qemu_name;
  75
  76 typedef struct vm_change_state_entry VMChangeStateEntry;
  77 typedef void VMChangeStateHandler(void *opaque, int running);
  78 typedef void VMStopHandler(void *opaque, int reason);
  79
  80 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
  81                                                      void *opaque);
  82 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
  83
  84 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
  85 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
  86
  87 void vm_start(void);
  88 void vm_stop(int reason);
  89
  90 typedef void QEMUResetHandler(void *opaque);
  91
  92 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
  93 void qemu_system_reset_request(void);
  94 void qemu_system_shutdown_request(void);
  95 void qemu_system_powerdown_request(void);
  96 #if !defined(TARGET_SPARC)
  97 // Please implement a power failure function to signal the OS
  98 #define qemu_system_powerdown() do{}while(0)
  99 #else
 100 void qemu_system_powerdown(void);
 101 #endif
 102
 103 void main_loop_wait(int timeout);
 104
 105 extern int ram_size;
 106 extern int bios_size;
 107 extern int rtc_utc;
 108 extern int rtc_start_date;
 109 extern int cirrus_vga_enabled;
 110 extern int vmsvga_enabled;
 111 extern int graphic_width;
 112 extern int graphic_height;
 113 extern int graphic_depth;
 114 extern const char *keyboard_layout;
 115 extern int kqemu_allowed;
 116 extern int win2k_install_hack;
 117 extern int alt_grab;
 118 extern int usb_enabled;
 119 extern int smp_cpus;
 120 extern int cursor_hide;
 121 extern int graphic_rotate;
 122 extern int no_quit;
 123 extern int semihosting_enabled;
 124 extern int autostart;
 125 extern int old_param;
 126 extern const char *bootp_filename;
 127
 128 #define MAX_OPTION_ROMS 16
 129 extern const char *option_rom[MAX_OPTION_ROMS];
 130 extern int nb_option_roms;
 131
 132 #ifdef TARGET_SPARC
 133 #define MAX_PROM_ENVS 128
 134 extern const char *prom_envs[MAX_PROM_ENVS];
 135 extern unsigned int nb_prom_envs;
 136 #endif
 137
 138 /* XXX: make it dynamic */
 139 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
 140 #if defined (TARGET_PPC)
 141 #define BIOS_SIZE (1024 * 1024)
 142 #elif defined (TARGET_SPARC64)
 143 #define BIOS_SIZE ((512 + 32) * 1024)
 144 #elif defined(TARGET_MIPS)
 145 #define BIOS_SIZE (4 * 1024 * 1024)
 146 #endif
 147
 148 /* keyboard/mouse support */
 149
 150 #define MOUSE_EVENT_LBUTTON 0x01
 151 #define MOUSE_EVENT_RBUTTON 0x02
 152 #define MOUSE_EVENT_MBUTTON 0x04
 153
 154 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
 155 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
 156
 157 typedef struct QEMUPutMouseEntry {
 158     QEMUPutMouseEvent *qemu_put_mouse_event;
 159     void *qemu_put_mouse_event_opaque;
 160     int qemu_put_mouse_event_absolute;
 161     char *qemu_put_mouse_event_name;
 162
 163     /* used internally by qemu for handling mice */
 164     struct QEMUPutMouseEntry *next;
 165 } QEMUPutMouseEntry;
 166
 167 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
 168 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
 169                                                 void *opaque, int absolute,
 170                                                 const char *name);
 171 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
 172
 173 void kbd_put_keycode(int keycode);
 174 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
 175 int kbd_mouse_is_absolute(void);
 176
 177 void do_info_mice(void);
 178 void do_mouse_set(int index);
 179
 180 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
 181    constants) */
 182 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
 183 #define QEMU_KEY_BACKSPACE  0x007f
 184 #define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
 185 #define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
 186 #define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
 187 #define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
 188 #define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
 189 #define QEMU_KEY_END        QEMU_KEY_ESC1(4)
 190 #define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
 191 #define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
 192 #define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
 193
 194 #define QEMU_KEY_CTRL_UP         0xe400
 195 #define QEMU_KEY_CTRL_DOWN       0xe401
 196 #define QEMU_KEY_CTRL_LEFT       0xe402
 197 #define QEMU_KEY_CTRL_RIGHT      0xe403
 198 #define QEMU_KEY_CTRL_HOME       0xe404
 199 #define QEMU_KEY_CTRL_END        0xe405
 200 #define QEMU_KEY_CTRL_PAGEUP     0xe406
 201 #define QEMU_KEY_CTRL_PAGEDOWN   0xe407
 202
 203 void kbd_put_keysym(int keysym);
 204
 205 /* async I/O support */
 206
 207 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
 208 typedef int IOCanRWHandler(void *opaque);
 209 typedef void IOHandler(void *opaque);
 210
 211 int qemu_set_fd_handler2(int fd,
 212                          IOCanRWHandler *fd_read_poll,
 213                          IOHandler *fd_read,
 214                          IOHandler *fd_write,
 215                          void *opaque);
 216 int qemu_set_fd_handler(int fd,
 217                         IOHandler *fd_read,
 218                         IOHandler *fd_write,
 219                         void *opaque);
 220
 221 /* Polling handling */
 222
 223 /* return TRUE if no sleep should be done afterwards */
 224 typedef int PollingFunc(void *opaque);
 225
 226 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
 227 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
 228
 229 #ifdef _WIN32
 230 /* Wait objects handling */
 231 typedef void WaitObjectFunc(void *opaque);
 232
 233 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
 234 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
 235 #endif
 236
 237 /* character device */
 238
 239 #define CHR_EVENT_BREAK 0 /* serial break char */
 240 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
 241 #define CHR_EVENT_RESET 2 /* new connection established */
 242
 243
 244 #define CHR_IOCTL_SERIAL_SET_PARAMS   1
 245 typedef struct {
 246     int speed;
 247     int parity;
 248     int data_bits;
 249     int stop_bits;
 250 } QEMUSerialSetParams;
 251
 252 #define CHR_IOCTL_SERIAL_SET_BREAK    2
 253
 254 #define CHR_IOCTL_PP_READ_DATA        3
 255 #define CHR_IOCTL_PP_WRITE_DATA       4
 256 #define CHR_IOCTL_PP_READ_CONTROL     5
 257 #define CHR_IOCTL_PP_WRITE_CONTROL    6
 258 #define CHR_IOCTL_PP_READ_STATUS      7
 259 #define CHR_IOCTL_PP_EPP_READ_ADDR    8
 260 #define CHR_IOCTL_PP_EPP_READ         9
 261 #define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
 262 #define CHR_IOCTL_PP_EPP_WRITE       11
 263
 264 typedef void IOEventHandler(void *opaque, int event);
 265
 266 typedef struct CharDriverState {
 267     int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
 268     void (*chr_update_read_handler)(struct CharDriverState *s);
 269     int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
 270     IOEventHandler *chr_event;
 271     IOCanRWHandler *chr_can_read;
 272     IOReadHandler *chr_read;
 273     void *handler_opaque;
 274     void (*chr_send_event)(struct CharDriverState *chr, int event);
 275     void (*chr_close)(struct CharDriverState *chr);
 276     void *opaque;
 277     int focus;
 278     QEMUBH *bh;
 279 } CharDriverState;
 280
 281 CharDriverState *qemu_chr_open(const char *filename);
 282 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
 283 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
 284 void qemu_chr_send_event(CharDriverState *s, int event);
 285 void qemu_chr_add_handlers(CharDriverState *s,
 286                            IOCanRWHandler *fd_can_read,
 287                            IOReadHandler *fd_read,
 288                            IOEventHandler *fd_event,
 289                            void *opaque);
 290 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
 291 void qemu_chr_reset(CharDriverState *s);
 292 int qemu_chr_can_read(CharDriverState *s);
 293 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
 294
 295 /* consoles */
 296
 297 typedef struct DisplayState DisplayState;
 298 typedef struct TextConsole TextConsole;
 299
 300 struct DisplayState {
 301     uint8_t *data;
 302     int linesize;
 303     int depth;
 304     int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
 305     int width;
 306     int height;
 307     void *opaque;
 308     struct QEMUTimer *gui_timer;
 309
 310     void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
 311     void (*dpy_resize)(struct DisplayState *s, int w, int h);
 312     void (*dpy_refresh)(struct DisplayState *s);
 313     void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
 314                      int dst_x, int dst_y, int w, int h);
 315     void (*dpy_fill)(struct DisplayState *s, int x, int y,
 316                      int w, int h, uint32_t c);
 317     void (*mouse_set)(int x, int y, int on);
 318     void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
 319                           uint8_t *image, uint8_t *mask);
 320 };
 321
 322 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
 323 {
 324     s->dpy_update(s, x, y, w, h);
 325 }
 326
 327 static inline void dpy_resize(DisplayState *s, int w, int h)
 328 {
 329     s->dpy_resize(s, w, h);
 330 }
 331
 332 typedef void (*vga_hw_update_ptr)(void *);
 333 typedef void (*vga_hw_invalidate_ptr)(void *);
 334 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
 335
 336 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
 337                                   vga_hw_invalidate_ptr invalidate,
 338                                   vga_hw_screen_dump_ptr screen_dump,
 339                                   void *opaque);
 340 void vga_hw_update(void);
 341 void vga_hw_invalidate(void);
 342 void vga_hw_screen_dump(const char *filename);
 343
 344 int is_graphic_console(void);
 345 CharDriverState *text_console_init(DisplayState *ds, const char *p);
 346 void console_select(unsigned int index);
 347 void console_color_init(DisplayState *ds);
 348
 349 /* serial ports */
 350
 351 #define MAX_SERIAL_PORTS 4
 352
 353 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
 354
 355 /* parallel ports */
 356
 357 #define MAX_PARALLEL_PORTS 3
 358
 359 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
 360
 361 struct ParallelIOArg {
 362     void *buffer;
 363     int count;
 364 };
 365
 366 /* VLANs support */
 367
 368 typedef struct VLANClientState VLANClientState;
 369
 370 struct VLANClientState {
 371     IOReadHandler *fd_read;
 372     /* Packets may still be sent if this returns zero.  It's used to
 373        rate-limit the slirp code.  */
 374     IOCanRWHandler *fd_can_read;
 375     void *opaque;
 376     struct VLANClientState *next;
 377     struct VLANState *vlan;
 378     char info_str[256];
 379 };
 380
 381 typedef struct VLANState {
 382     int id;
 383     VLANClientState *first_client;
 384     struct VLANState *next;
 385     unsigned int nb_guest_devs, nb_host_devs;
 386 } VLANState;
 387
 388 VLANState *qemu_find_vlan(int id);
 389 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
 390                                       IOReadHandler *fd_read,
 391                                       IOCanRWHandler *fd_can_read,
 392                                       void *opaque);
 393 int qemu_can_send_packet(VLANClientState *vc);
 394 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
 395 void qemu_handler_true(void *opaque);
 396
 397 void do_info_network(void);
 398
 399 /* TAP win32 */
 400 int tap_win32_init(VLANState *vlan, const char *ifname);
 401
 402 /* NIC info */
 403
 404 #define MAX_NICS 8
 405
 406 typedef struct NICInfo {
 407     uint8_t macaddr[6];
 408     const char *model;
 409     VLANState *vlan;
 410 } NICInfo;
 411
 412 extern int nb_nics;
 413 extern NICInfo nd_table[MAX_NICS];
 414
 415 /* SLIRP */
 416 void do_info_slirp(void);
 417
 418 /* timers */
 419
 420 typedef struct QEMUClock QEMUClock;
 421 typedef struct QEMUTimer QEMUTimer;
 422 typedef void QEMUTimerCB(void *opaque);
 423
 424 /* The real time clock should be used only for stuff which does not
 425    change the virtual machine state, as it is run even if the virtual
 426    machine is stopped. The real time clock has a frequency of 1000
 427    Hz. */
 428 extern QEMUClock *rt_clock;
 429
 430 /* The virtual clock is only run during the emulation. It is stopped
 431    when the virtual machine is stopped. Virtual timers use a high
 432    precision clock, usually cpu cycles (use ticks_per_sec). */
 433 extern QEMUClock *vm_clock;
 434
 435 int64_t qemu_get_clock(QEMUClock *clock);
 436
 437 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
 438 void qemu_free_timer(QEMUTimer *ts);
 439 void qemu_del_timer(QEMUTimer *ts);
 440 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
 441 int qemu_timer_pending(QEMUTimer *ts);
 442
 443 extern int64_t ticks_per_sec;
 444
 445 int64_t cpu_get_ticks(void);
 446 void cpu_enable_ticks(void);
 447 void cpu_disable_ticks(void);
 448
 449 /* VM Load/Save */
 450
 451 typedef struct QEMUFile QEMUFile;
 452
 453 QEMUFile *qemu_fopen(const char *filename, const char *mode);
 454 void qemu_fflush(QEMUFile *f);
 455 void qemu_fclose(QEMUFile *f);
 456 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
 457 void qemu_put_byte(QEMUFile *f, int v);
 458 void qemu_put_be16(QEMUFile *f, unsigned int v);
 459 void qemu_put_be32(QEMUFile *f, unsigned int v);
 460 void qemu_put_be64(QEMUFile *f, uint64_t v);
 461 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
 462 int qemu_get_byte(QEMUFile *f);
 463 unsigned int qemu_get_be16(QEMUFile *f);
 464 unsigned int qemu_get_be32(QEMUFile *f);
 465 uint64_t qemu_get_be64(QEMUFile *f);
 466
 467 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
 468 {
 469     qemu_put_be64(f, *pv);
 470 }
 471
 472 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
 473 {
 474     qemu_put_be32(f, *pv);
 475 }
 476
 477 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
 478 {
 479     qemu_put_be16(f, *pv);
 480 }
 481
 482 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
 483 {
 484     qemu_put_byte(f, *pv);
 485 }
 486
 487 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
 488 {
 489     *pv = qemu_get_be64(f);
 490 }
 491
 492 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
 493 {
 494     *pv = qemu_get_be32(f);
 495 }
 496
 497 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
 498 {
 499     *pv = qemu_get_be16(f);
 500 }
 501
 502 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
 503 {
 504     *pv = qemu_get_byte(f);
 505 }
 506
 507 #if TARGET_LONG_BITS == 64
 508 #define qemu_put_betl qemu_put_be64
 509 #define qemu_get_betl qemu_get_be64
 510 #define qemu_put_betls qemu_put_be64s
 511 #define qemu_get_betls qemu_get_be64s
 512 #else
 513 #define qemu_put_betl qemu_put_be32
 514 #define qemu_get_betl qemu_get_be32
 515 #define qemu_put_betls qemu_put_be32s
 516 #define qemu_get_betls qemu_get_be32s
 517 #endif
 518
 519 int64_t qemu_ftell(QEMUFile *f);
 520 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
 521
 522 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
 523 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
 524
 525 int register_savevm(const char *idstr,
 526                     int instance_id,
 527                     int version_id,
 528                     SaveStateHandler *save_state,
 529                     LoadStateHandler *load_state,
 530                     void *opaque);
 531 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
 532 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
 533
 534 void cpu_save(QEMUFile *f, void *opaque);
 535 int cpu_load(QEMUFile *f, void *opaque, int version_id);
 536
 537 void do_savevm(const char *name);
 538 void do_loadvm(const char *name);
 539 void do_delvm(const char *name);
 540 void do_info_snapshots(void);
 541
 542 /* monitor.c */
 543 void monitor_init(CharDriverState *hd, int show_banner);
 544 void term_puts(const char *str);
 545 void term_vprintf(const char *fmt, va_list ap);
 546 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
 547 void term_print_filename(const char *filename);
 548 void term_flush(void);
 549 void term_print_help(void);
 550 void monitor_readline(const char *prompt, int is_password,
 551                       char *buf, int buf_size);
 552
 553 /* readline.c */
 554 typedef void ReadLineFunc(void *opaque, const char *str);
 555
 556 extern int completion_index;
 557 void add_completion(const char *str);
 558 void readline_handle_byte(int ch);
 559 void readline_find_completion(const char *cmdline);
 560 const char *readline_get_history(unsigned int index);
 561 void readline_start(const char *prompt, int is_password,
 562                     ReadLineFunc *readline_func, void *opaque);
 563
 564 void kqemu_record_dump(void);
 565
 566 /* sdl.c */
 567 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
 568
 569 /* cocoa.m */
 570 void cocoa_display_init(DisplayState *ds, int full_screen);
 571
 572 /* vnc.c */
 573 void vnc_display_init(DisplayState *ds);
 574 void vnc_display_close(DisplayState *ds);
 575 int vnc_display_open(DisplayState *ds, const char *display);
 576 int vnc_display_password(DisplayState *ds, const char *password);
 577 void do_info_vnc(void);
 578
 579 /* x_keymap.c */
 580 extern uint8_t _translate_keycode(const int key);
 581
 582 #ifdef NEED_CPU_H
 583
 584 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
 585                                  const char *boot_device,
 586              DisplayState *ds, const char **fd_filename, int snapshot,
 587              const char *kernel_filename, const char *kernel_cmdline,
 588              const char *initrd_filename, const char *cpu_model);
 589
 590 typedef struct QEMUMachine {
 591     const char *name;
 592     const char *desc;
 593     QEMUMachineInitFunc *init;
 594     struct QEMUMachine *next;
 595 } QEMUMachine;
 596
 597 int qemu_register_machine(QEMUMachine *m);
 598
 599 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
 600
 601 #include "hw/irq.h"
 602
 603 /* ISA bus */
 604
 605 extern target_phys_addr_t isa_mem_base;
 606
 607 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
 608 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
 609
 610 int register_ioport_read(int start, int length, int size,
 611                          IOPortReadFunc *func, void *opaque);
 612 int register_ioport_write(int start, int length, int size,
 613                           IOPortWriteFunc *func, void *opaque);
 614 void isa_unassign_ioport(int start, int length);
 615
 616 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
 617
 618 /* PCI bus */
 619
 620 extern target_phys_addr_t pci_mem_base;
 621
 622 typedef struct PCIBus PCIBus;
 623 typedef struct PCIDevice PCIDevice;
 624
 625 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 626                                 uint32_t address, uint32_t data, int len);
 627 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 628                                    uint32_t address, int len);
 629 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 630                                 uint32_t addr, uint32_t size, int type);
 631
 632 #define PCI_ADDRESS_SPACE_MEM           0x00
 633 #define PCI_ADDRESS_SPACE_IO            0x01
 634 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
 635
 636 typedef struct PCIIORegion {
 637     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
 638     uint32_t size;
 639     uint8_t type;
 640     PCIMapIORegionFunc *map_func;
 641 } PCIIORegion;
 642
 643 #define PCI_ROM_SLOT 6
 644 #define PCI_NUM_REGIONS 7
 645
 646 #define PCI_DEVICES_MAX 64
 647
 648 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 649 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 650 #define PCI_COMMAND             0x04    /* 16 bits */
 651 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 652 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 653 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 654 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 655 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 656 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 657 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 658
 659 struct PCIDevice {
 660     /* PCI config space */
 661     uint8_t config[256];
 662
 663     /* the following fields are read only */
 664     PCIBus *bus;
 665     int devfn;
 666     char name[64];
 667     PCIIORegion io_regions[PCI_NUM_REGIONS];
 668
 669     /* do not access the following fields */
 670     PCIConfigReadFunc *config_read;
 671     PCIConfigWriteFunc *config_write;
 672     /* ??? This is a PC-specific hack, and should be removed.  */
 673     int irq_index;
 674
 675     /* IRQ objects for the INTA-INTD pins.  */
 676     qemu_irq *irq;
 677
 678     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 679     int irq_state[4];
 680 };
 681
 682 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 683                                int instance_size, int devfn,
 684                                PCIConfigReadFunc *config_read,
 685                                PCIConfigWriteFunc *config_write);
 686
 687 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 688                             uint32_t size, int type,
 689                             PCIMapIORegionFunc *map_func);
 690
 691 uint32_t pci_default_read_config(PCIDevice *d,
 692                                  uint32_t address, int len);
 693 void pci_default_write_config(PCIDevice *d,
 694                               uint32_t address, uint32_t val, int len);
 695 void pci_device_save(PCIDevice *s, QEMUFile *f);
 696 int pci_device_load(PCIDevice *s, QEMUFile *f);
 697
 698 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 699 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 700 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 701                          qemu_irq *pic, int devfn_min, int nirq);
 702
 703 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
 704 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 705 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 706 int pci_bus_num(PCIBus *s);
 707 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 708
 709 void pci_info(void);
 710 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 711                         pci_map_irq_fn map_irq, const char *name);
 712
 713 /* prep_pci.c */
 714 PCIBus *pci_prep_init(qemu_irq *pic);
 715
 716 /* apb_pci.c */
 717 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
 718                      qemu_irq *pic);
 719
 720 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
 721
 722 /* piix_pci.c */
 723 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 724 void i440fx_set_smm(PCIDevice *d, int val);
 725 int piix3_init(PCIBus *bus, int devfn);
 726 void i440fx_init_memory_mappings(PCIDevice *d);
 727
 728 int piix4_init(PCIBus *bus, int devfn);
 729
 730 /* openpic.c */
 731 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
 732 enum {
 733     OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
 734     OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
 735     OPENPIC_OUTPUT_MCK,     /* Machine check event       */
 736     OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
 737     OPENPIC_OUTPUT_RESET,   /* Core reset event          */
 738     OPENPIC_OUTPUT_NB,
 739 };
 740 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
 741                         qemu_irq **irqs, qemu_irq irq_out);
 742
 743 /* gt64xxx.c */
 744 PCIBus *pci_gt64120_init(qemu_irq *pic);
 745
 746 #ifdef HAS_AUDIO
 747 struct soundhw {
 748     const char *name;
 749     const char *descr;
 750     int enabled;
 751     int isa;
 752     union {
 753         int (*init_isa) (AudioState *s, qemu_irq *pic);
 754         int (*init_pci) (PCIBus *bus, AudioState *s);
 755     } init;
 756 };
 757
 758 extern struct soundhw soundhw[];
 759 #endif
 760
 761 /* vga.c */
 762
 763 #ifndef TARGET_SPARC
 764 #define VGA_RAM_SIZE (8192 * 1024)
 765 #else
 766 #define VGA_RAM_SIZE (9 * 1024 * 1024)
 767 #endif
 768
 769 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 770                  unsigned long vga_ram_offset, int vga_ram_size);
 771 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 772                  unsigned long vga_ram_offset, int vga_ram_size,
 773                  unsigned long vga_bios_offset, int vga_bios_size);
 774 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
 775                     unsigned long vga_ram_offset, int vga_ram_size,
 776                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 777                     int it_shift);
 778
 779 /* cirrus_vga.c */
 780 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 781                          unsigned long vga_ram_offset, int vga_ram_size);
 782 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 783                          unsigned long vga_ram_offset, int vga_ram_size);
 784
 785 /* vmware_vga.c */
 786 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 787                      unsigned long vga_ram_offset, int vga_ram_size);
 788
 789 /* ide.c */
 790 #define MAX_DISKS 4
 791
 792 extern BlockDriverState *bs_table[MAX_DISKS + 1];
 793 extern BlockDriverState *sd_bdrv;
 794 extern BlockDriverState *mtd_bdrv;
 795
 796 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 797                   BlockDriverState *hd0, BlockDriverState *hd1);
 798 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 799                          int secondary_ide_enabled);
 800 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 801                         qemu_irq *pic);
 802 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 803                         qemu_irq *pic);
 804
 805 /* cdrom.c */
 806 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
 807 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
 808
 809 /* ds1225y.c */
 810 typedef struct ds1225y_t ds1225y_t;
 811 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
 812
 813 /* es1370.c */
 814 int es1370_init (PCIBus *bus, AudioState *s);
 815
 816 /* sb16.c */
 817 int SB16_init (AudioState *s, qemu_irq *pic);
 818
 819 /* adlib.c */
 820 int Adlib_init (AudioState *s, qemu_irq *pic);
 821
 822 /* gus.c */
 823 int GUS_init (AudioState *s, qemu_irq *pic);
 824
 825 /* dma.c */
 826 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
 827 int DMA_get_channel_mode (int nchan);
 828 int DMA_read_memory (int nchan, void *buf, int pos, int size);
 829 int DMA_write_memory (int nchan, void *buf, int pos, int size);
 830 void DMA_hold_DREQ (int nchan);
 831 void DMA_release_DREQ (int nchan);
 832 void DMA_schedule(int nchan);
 833 void DMA_run (void);
 834 void DMA_init (int high_page_enable);
 835 void DMA_register_channel (int nchan,
 836                            DMA_transfer_handler transfer_handler,
 837                            void *opaque);
 838 /* fdc.c */
 839 #define MAX_FD 2
 840 extern BlockDriverState *fd_table[MAX_FD];
 841
 842 typedef struct fdctrl_t fdctrl_t;
 843
 844 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
 845                        target_phys_addr_t io_base,
 846                        BlockDriverState **fds);
 847 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
 848                              BlockDriverState **fds);
 849 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
 850
 851 /* eepro100.c */
 852
 853 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 854 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 855 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 856
 857 /* ne2000.c */
 858
 859 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 860 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 861
 862 /* rtl8139.c */
 863
 864 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 865
 866 /* pcnet.c */
 867
 868 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 869 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
 870                 qemu_irq irq, qemu_irq *reset);
 871
 872 /* mipsnet.c */
 873 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
 874
 875 /* vmmouse.c */
 876 void *vmmouse_init(void *m);
 877
 878 /* vmport.c */
 879 #ifdef TARGET_I386
 880 void vmport_init(CPUState *env);
 881 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
 882 #endif
 883
 884 /* pckbd.c */
 885
 886 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 887 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 888                    target_phys_addr_t base, int it_shift);
 889
 890 /* mc146818rtc.c */
 891
 892 typedef struct RTCState RTCState;
 893
 894 RTCState *rtc_init(int base, qemu_irq irq);
 895 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
 896 void rtc_set_memory(RTCState *s, int addr, int val);
 897 void rtc_set_date(RTCState *s, const struct tm *tm);
 898
 899 /* serial.c */
 900
 901 typedef struct SerialState SerialState;
 902 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
 903 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 904                              qemu_irq irq, CharDriverState *chr,
 905                              int ioregister);
 906 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
 907 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
 908 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
 909 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
 910 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
 911 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
 912
 913 /* parallel.c */
 914
 915 typedef struct ParallelState ParallelState;
 916 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
 917 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
 918
 919 /* i8259.c */
 920
 921 typedef struct PicState2 PicState2;
 922 extern PicState2 *isa_pic;
 923 void pic_set_irq(int irq, int level);
 924 void pic_set_irq_new(void *opaque, int irq, int level);
 925 qemu_irq *i8259_init(qemu_irq parent_irq);
 926 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 927                           void *alt_irq_opaque);
 928 int pic_read_irq(PicState2 *s);
 929 void pic_update_irq(PicState2 *s);
 930 uint32_t pic_intack_read(PicState2 *s);
 931 void pic_info(void);
 932 void irq_info(void);
 933
 934 /* APIC */
 935 typedef struct IOAPICState IOAPICState;
 936
 937 int apic_init(CPUState *env);
 938 int apic_accept_pic_intr(CPUState *env);
 939 int apic_get_interrupt(CPUState *env);
 940 IOAPICState *ioapic_init(void);
 941 void ioapic_set_irq(void *opaque, int vector, int level);
 942
 943 /* i8254.c */
 944
 945 #define PIT_FREQ 1193182
 946
 947 typedef struct PITState PITState;
 948
 949 PITState *pit_init(int base, qemu_irq irq);
 950 void pit_set_gate(PITState *pit, int channel, int val);
 951 int pit_get_gate(PITState *pit, int channel);
 952 int pit_get_initial_count(PITState *pit, int channel);
 953 int pit_get_mode(PITState *pit, int channel);
 954 int pit_get_out(PITState *pit, int channel, int64_t current_time);
 955
 956 /* jazz_led.c */
 957 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
 958
 959 /* pcspk.c */
 960 void pcspk_init(PITState *);
 961 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 962
 963 #include "hw/i2c.h"
 964
 965 #include "hw/smbus.h"
 966
 967 /* acpi.c */
 968 extern int acpi_enabled;
 969 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
 970 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 971 void acpi_bios_init(void);
 972
 973 /* Axis ETRAX.  */
 974 extern QEMUMachine bareetraxfs_machine;
 975
 976 /* pc.c */
 977 extern QEMUMachine pc_machine;
 978 extern QEMUMachine isapc_machine;
 979 extern int fd_bootchk;
 980
 981 void ioport_set_a20(int enable);
 982 int ioport_get_a20(void);
 983
 984 /* ppc.c */
 985 extern QEMUMachine prep_machine;
 986 extern QEMUMachine core99_machine;
 987 extern QEMUMachine heathrow_machine;
 988 extern QEMUMachine ref405ep_machine;
 989 extern QEMUMachine taihu_machine;
 990
 991 /* mips_r4k.c */
 992 extern QEMUMachine mips_machine;
 993
 994 /* mips_malta.c */
 995 extern QEMUMachine mips_malta_machine;
 996
 997 /* mips_pica61.c */
 998 extern QEMUMachine mips_pica61_machine;
 999
1000 /* mips_mipssim.c */
1001 extern QEMUMachine mips_mipssim_machine;
1002
1003 /* mips_int.c */
1004 extern void cpu_mips_irq_init_cpu(CPUState *env);
1005
1006 /* mips_timer.c */
1007 extern void cpu_mips_clock_init(CPUState *);
1008 extern void cpu_mips_irqctrl_init (void);
1009
1010 /* shix.c */
1011 extern QEMUMachine shix_machine;
1012
1013 /* r2d.c */
1014 extern QEMUMachine r2d_machine;
1015
1016 #ifdef TARGET_PPC
1017 /* PowerPC hardware exceptions management helpers */
1018 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1019 typedef struct clk_setup_t clk_setup_t;
1020 struct clk_setup_t {
1021     clk_setup_cb cb;
1022     void *opaque;
1023 };
1024 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1025 {
1026     if (clk->cb != NULL)
1027         (*clk->cb)(clk->opaque, freq);
1028 }
1029
1030 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1031 /* Embedded PowerPC DCR management */
1032 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1033 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1034 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1035                   int (*dcr_write_error)(int dcrn));
1036 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1037                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
1038 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1039 /* Embedded PowerPC reset */
1040 void ppc40x_core_reset (CPUState *env);
1041 void ppc40x_chip_reset (CPUState *env);
1042 void ppc40x_system_reset (CPUState *env);
1043 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1044
1045 extern CPUWriteMemoryFunc *PPC_io_write[];
1046 extern CPUReadMemoryFunc *PPC_io_read[];
1047 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1048 #endif
1049
1050 /* sun4m.c */
1051 extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
1052
1053 /* iommu.c */
1054 void *iommu_init(target_phys_addr_t addr);
1055 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1056                                  uint8_t *buf, int len, int is_write);
1057 static inline void sparc_iommu_memory_read(void *opaque,
1058                                            target_phys_addr_t addr,
1059                                            uint8_t *buf, int len)
1060 {
1061     sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1062 }
1063
1064 static inline void sparc_iommu_memory_write(void *opaque,
1065                                             target_phys_addr_t addr,
1066                                             uint8_t *buf, int len)
1067 {
1068     sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1069 }
1070
1071 /* tcx.c */
1072 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1073               unsigned long vram_offset, int vram_size, int width, int height,
1074               int depth);
1075
1076 /* slavio_intctl.c */
1077 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1078                          const uint32_t *intbit_to_level,
1079                          qemu_irq **irq, qemu_irq **cpu_irq,
1080                          qemu_irq **parent_irq, unsigned int cputimer);
1081 void slavio_pic_info(void *opaque);
1082 void slavio_irq_info(void *opaque);
1083
1084 /* loader.c */
1085 int get_image_size(const char *filename);
1086 int load_image(const char *filename, uint8_t *addr);
1087 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1088              uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1089 int load_aout(const char *filename, uint8_t *addr);
1090 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1091
1092 /* slavio_timer.c */
1093 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1094                            qemu_irq *cpu_irqs);
1095
1096 /* slavio_serial.c */
1097 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1098                                 CharDriverState *chr1, CharDriverState *chr2);
1099 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1100
1101 /* slavio_misc.c */
1102 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1103                        qemu_irq irq);
1104 void slavio_set_power_fail(void *opaque, int power_failing);
1105
1106 /* esp.c */
1107 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1108 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1109                void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1110
1111 /* sparc32_dma.c */
1112 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1113                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1114 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1115                        uint8_t *buf, int len, int do_bswap);
1116 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1117                         uint8_t *buf, int len, int do_bswap);
1118 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1119 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1120
1121 /* cs4231.c */
1122 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1123
1124 /* sun4u.c */
1125 extern QEMUMachine sun4u_machine;
1126
1127 /* NVRAM helpers */
1128 typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1129 typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1130 typedef struct nvram_t {
1131     void *opaque;
1132     nvram_read_t read_fn;
1133     nvram_write_t write_fn;
1134 } nvram_t;
1135
1136 #include "hw/m48t59.h"
1137
1138 void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1139 uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1140 void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1141 uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1142 void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1143 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1144 void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1145                        const unsigned char *str, uint32_t max);
1146 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1147 void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1148                     uint32_t start, uint32_t count);
1149 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1150                           const unsigned char *arch,
1151                           uint32_t RAM_size, int boot_device,
1152                           uint32_t kernel_image, uint32_t kernel_size,
1153                           const char *cmdline,
1154                           uint32_t initrd_image, uint32_t initrd_size,
1155                           uint32_t NVRAM_image,
1156                           int width, int height, int depth);
1157
1158 /* adb.c */
1159
1160 #define MAX_ADB_DEVICES 16
1161
1162 #define ADB_MAX_OUT_LEN 16
1163
1164 typedef struct ADBDevice ADBDevice;
1165
1166 /* buf = NULL means polling */
1167 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1168                               const uint8_t *buf, int len);
1169 typedef int ADBDeviceReset(ADBDevice *d);
1170
1171 struct ADBDevice {
1172     struct ADBBusState *bus;
1173     int devaddr;
1174     int handler;
1175     ADBDeviceRequest *devreq;
1176     ADBDeviceReset *devreset;
1177     void *opaque;
1178 };
1179
1180 typedef struct ADBBusState {
1181     ADBDevice devices[MAX_ADB_DEVICES];
1182     int nb_devices;
1183     int poll_index;
1184 } ADBBusState;
1185
1186 int adb_request(ADBBusState *s, uint8_t *buf_out,
1187                 const uint8_t *buf, int len);
1188 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1189
1190 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1191                                ADBDeviceRequest *devreq,
1192                                ADBDeviceReset *devreset,
1193                                void *opaque);
1194 void adb_kbd_init(ADBBusState *bus);
1195 void adb_mouse_init(ADBBusState *bus);
1196
1197 extern ADBBusState adb_bus;
1198
1199 #include "hw/usb.h"
1200
1201 /* usb ports of the VM */
1202
1203 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1204                             usb_attachfn attach);
1205
1206 #define VM_USB_HUB_SIZE 8
1207
1208 void do_usb_add(const char *devname);
1209 void do_usb_del(const char *devname);
1210 void usb_info(void);
1211
1212 /* scsi-disk.c */
1213 enum scsi_reason {
1214     SCSI_REASON_DONE, /* Command complete.  */
1215     SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1216 };
1217
1218 typedef struct SCSIDevice SCSIDevice;
1219 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1220                                   uint32_t arg);
1221
1222 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1223                            int tcq,
1224                            scsi_completionfn completion,
1225                            void *opaque);
1226 void scsi_disk_destroy(SCSIDevice *s);
1227
1228 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1229 /* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1230    layer the completion routine may be called directly by
1231    scsi_{read,write}_data.  */
1232 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1233 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1234 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1235 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1236
1237 /* lsi53c895a.c */
1238 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1239 void *lsi_scsi_init(PCIBus *bus, int devfn);
1240
1241 /* integratorcp.c */
1242 extern QEMUMachine integratorcp_machine;
1243
1244 /* versatilepb.c */
1245 extern QEMUMachine versatilepb_machine;
1246 extern QEMUMachine versatileab_machine;
1247
1248 /* realview.c */
1249 extern QEMUMachine realview_machine;
1250
1251 /* spitz.c */
1252 extern QEMUMachine akitapda_machine;
1253 extern QEMUMachine spitzpda_machine;
1254 extern QEMUMachine borzoipda_machine;
1255 extern QEMUMachine terrierpda_machine;
1256
1257 /* palm.c */
1258 extern QEMUMachine palmte_machine;
1259
1260 /* armv7m.c */
1261 qemu_irq *armv7m_init(int flash_size, int sram_size,
1262                       const char *kernel_filename, const char *cpu_model);
1263
1264 /* stellaris.c */
1265 extern QEMUMachine lm3s811evb_machine;
1266 extern QEMUMachine lm3s6965evb_machine;
1267
1268 /* ps2.c */
1269 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1270 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1271 void ps2_write_mouse(void *, int val);
1272 void ps2_write_keyboard(void *, int val);
1273 uint32_t ps2_read_data(void *);
1274 void ps2_queue(void *, int b);
1275 void ps2_keyboard_set_translation(void *opaque, int mode);
1276 void ps2_mouse_fake_event(void *opaque);
1277
1278 /* smc91c111.c */
1279 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1280
1281 /* pl031.c */
1282 void pl031_init(uint32_t base, qemu_irq irq);
1283
1284 /* pl110.c */
1285 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1286
1287 /* pl011.c */
1288 enum pl011_type {
1289     PL011_ARM,
1290     PL011_LUMINARY
1291 };
1292
1293 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr,
1294                 enum pl011_type type);
1295
1296 /* pl022.c */
1297 void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int),
1298                 void *opaque);
1299
1300 /* pl050.c */
1301 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1302
1303 /* pl061.c */
1304 qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
1305
1306 /* pl080.c */
1307 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1308
1309 /* pl181.c */
1310 void pl181_init(uint32_t base, BlockDriverState *bd,
1311                 qemu_irq irq0, qemu_irq irq1);
1312
1313 /* pl190.c */
1314 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1315
1316 /* arm-timer.c */
1317 void sp804_init(uint32_t base, qemu_irq irq);
1318 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1319
1320 /* arm_sysctl.c */
1321 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1322
1323 /* realview_gic.c */
1324 qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
1325
1326 /* mpcore.c */
1327 extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
1328
1329 /* arm_boot.c */
1330
1331 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1332                      const char *kernel_cmdline, const char *initrd_filename,
1333                      int board_id, target_phys_addr_t loader_start);
1334
1335 /* armv7m_nvic.c */
1336 qemu_irq *armv7m_nvic_init(CPUState *env);
1337
1338 /* ssd0303.c */
1339 void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address);
1340
1341 /* ssd0323.c */
1342 int ssd0323_xfer_ssi(void *opaque, int data);
1343 void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
1344
1345 /* sh7750.c */
1346 struct SH7750State;
1347
1348 struct SH7750State *sh7750_init(CPUState * cpu);
1349
1350 typedef struct {
1351     /* The callback will be triggered if any of the designated lines change */
1352     uint16_t portamask_trigger;
1353     uint16_t portbmask_trigger;
1354     /* Return 0 if no action was taken */
1355     int (*port_change_cb) (uint16_t porta, uint16_t portb,
1356                            uint16_t * periph_pdtra,
1357                            uint16_t * periph_portdira,
1358                            uint16_t * periph_pdtrb,
1359                            uint16_t * periph_portdirb);
1360 } sh7750_io_device;
1361
1362 int sh7750_register_io_device(struct SH7750State *s,
1363                               sh7750_io_device * device);
1364 /* sh_timer.c */
1365 #define TMU012_FEAT_TOCR   (1 << 0)
1366 #define TMU012_FEAT_3CHAN  (1 << 1)
1367 #define TMU012_FEAT_EXTCLK (1 << 2)
1368 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1369
1370 /* sh_serial.c */
1371 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1372 void sh_serial_init (target_phys_addr_t base, int feat,
1373                      uint32_t freq, CharDriverState *chr);
1374
1375 /* tc58128.c */
1376 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1377
1378 /* NOR flash devices */
1379 #define MAX_PFLASH 4
1380 extern BlockDriverState *pflash_table[MAX_PFLASH];
1381 typedef struct pflash_t pflash_t;
1382
1383 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1384                            BlockDriverState *bs,
1385                            uint32_t sector_len, int nb_blocs, int width,
1386                            uint16_t id0, uint16_t id1,
1387                            uint16_t id2, uint16_t id3);
1388
1389 /* nand.c */
1390 struct nand_flash_s;
1391 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1392 void nand_done(struct nand_flash_s *s);
1393 void nand_setpins(struct nand_flash_s *s,
1394                 int cle, int ale, int ce, int wp, int gnd);
1395 void nand_getpins(struct nand_flash_s *s, int *rb);
1396 void nand_setio(struct nand_flash_s *s, uint8_t value);
1397 uint8_t nand_getio(struct nand_flash_s *s);
1398
1399 #define NAND_MFR_TOSHIBA        0x98
1400 #define NAND_MFR_SAMSUNG        0xec
1401 #define NAND_MFR_FUJITSU        0x04
1402 #define NAND_MFR_NATIONAL       0x8f
1403 #define NAND_MFR_RENESAS        0x07
1404 #define NAND_MFR_STMICRO        0x20
1405 #define NAND_MFR_HYNIX          0xad
1406 #define NAND_MFR_MICRON         0x2c
1407
1408 /* ecc.c */
1409 struct ecc_state_s {
1410     uint8_t cp;         /* Column parity */
1411     uint16_t lp[2];     /* Line parity */
1412     uint16_t count;
1413 };
1414
1415 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1416 void ecc_reset(struct ecc_state_s *s);
1417 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1418 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1419
1420 /* GPIO */
1421 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1422
1423 /* ads7846.c */
1424 struct ads7846_state_s;
1425 uint32_t ads7846_read(void *opaque);
1426 void ads7846_write(void *opaque, uint32_t value);
1427 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1428
1429 /* max111x.c */
1430 struct max111x_s;
1431 uint32_t max111x_read(void *opaque);
1432 void max111x_write(void *opaque, uint32_t value);
1433 struct max111x_s *max1110_init(qemu_irq cb);
1434 struct max111x_s *max1111_init(qemu_irq cb);
1435 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1436
1437 /* PCMCIA/Cardbus */
1438
1439 struct pcmcia_socket_s {
1440     qemu_irq irq;
1441     int attached;
1442     const char *slot_string;
1443     const char *card_string;
1444 };
1445
1446 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1447 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1448 void pcmcia_info(void);
1449
1450 struct pcmcia_card_s {
1451     void *state;
1452     struct pcmcia_socket_s *slot;
1453     int (*attach)(void *state);
1454     int (*detach)(void *state);
1455     const uint8_t *cis;
1456     int cis_len;
1457
1458     /* Only valid if attached */
1459     uint8_t (*attr_read)(void *state, uint32_t address);
1460     void (*attr_write)(void *state, uint32_t address, uint8_t value);
1461     uint16_t (*common_read)(void *state, uint32_t address);
1462     void (*common_write)(void *state, uint32_t address, uint16_t value);
1463     uint16_t (*io_read)(void *state, uint32_t address);
1464     void (*io_write)(void *state, uint32_t address, uint16_t value);
1465 };
1466
1467 #define CISTPL_DEVICE           0x01    /* 5V Device Information Tuple */
1468 #define CISTPL_NO_LINK          0x14    /* No Link Tuple */
1469 #define CISTPL_VERS_1           0x15    /* Level 1 Version Tuple */
1470 #define CISTPL_JEDEC_C          0x18    /* JEDEC ID Tuple */
1471 #define CISTPL_JEDEC_A          0x19    /* JEDEC ID Tuple */
1472 #define CISTPL_CONFIG           0x1a    /* Configuration Tuple */
1473 #define CISTPL_CFTABLE_ENTRY    0x1b    /* 16-bit PCCard Configuration */
1474 #define CISTPL_DEVICE_OC        0x1c    /* Additional Device Information */
1475 #define CISTPL_DEVICE_OA        0x1d    /* Additional Device Information */
1476 #define CISTPL_DEVICE_GEO       0x1e    /* Additional Device Information */
1477 #define CISTPL_DEVICE_GEO_A     0x1f    /* Additional Device Information */
1478 #define CISTPL_MANFID           0x20    /* Manufacture ID Tuple */
1479 #define CISTPL_FUNCID           0x21    /* Function ID Tuple */
1480 #define CISTPL_FUNCE            0x22    /* Function Extension Tuple */
1481 #define CISTPL_END              0xff    /* Tuple End */
1482 #define CISTPL_ENDMARK          0xff
1483
1484 /* dscm1xxxx.c */
1485 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1486
1487 /* ptimer.c */
1488 typedef struct ptimer_state ptimer_state;
1489 typedef void (*ptimer_cb)(void *opaque);
1490
1491 ptimer_state *ptimer_init(QEMUBH *bh);
1492 void ptimer_set_period(ptimer_state *s, int64_t period);
1493 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1494 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1495 uint64_t ptimer_get_count(ptimer_state *s);
1496 void ptimer_set_count(ptimer_state *s, uint64_t count);
1497 void ptimer_run(ptimer_state *s, int oneshot);
1498 void ptimer_stop(ptimer_state *s);
1499 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1500 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1501
1502 #include "hw/pxa.h"
1503
1504 #include "hw/omap.h"
1505
1506 /* tsc210x.c */
1507 struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
1508 struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
1509
1510 /* mcf_uart.c */
1511 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1512 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1513 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1514 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1515                       CharDriverState *chr);
1516
1517 /* mcf_intc.c */
1518 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1519
1520 /* mcf_fec.c */
1521 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1522
1523 /* mcf5206.c */
1524 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1525
1526 /* an5206.c */
1527 extern QEMUMachine an5206_machine;
1528
1529 /* mcf5208.c */
1530 extern QEMUMachine mcf5208evb_machine;
1531
1532 /* dummy_m68k.c */
1533 extern QEMUMachine dummy_m68k_machine;
1534
1535 #include "gdbstub.h"
1536
1537 #endif /* defined(NEED_CPU_H) */
1538 #endif /* VL_H */