exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #ifndef likely
  32 #if __GNUC__ < 3
  33 #define __builtin_expect(x, n) (x)
  34 #endif
  35
  36 #define likely(x)   __builtin_expect(!!(x), 1)
  37 #define unlikely(x)   __builtin_expect(!!(x), 0)
  38 #endif
  39
  40 #ifndef always_inline
  41 #if (__GNUC__ < 3) || defined(__APPLE__)
  42 #define always_inline inline
  43 #else
  44 #define always_inline __attribute__ (( always_inline )) inline
  45 #endif
  46 #endif
  47
  48 #ifdef __i386__
  49 #define REGPARM(n) __attribute((regparm(n)))
  50 #else
  51 #define REGPARM(n)
  52 #endif
  53
  54 /* is_jmp field values */
  55 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  56 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  57 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  58 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  59
  60 struct TranslationBlock;
  61
  62 /* XXX: make safe guess about sizes */
  63 #define MAX_OP_PER_INSTR 32
  64 #define OPC_BUF_SIZE 512
  65 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  66
  67 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  68
  69 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  70 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  71 extern long gen_labels[OPC_BUF_SIZE];
  72 extern int nb_gen_labels;
  73 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  74 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  75 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  76 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  77 extern target_ulong gen_opc_jump_pc[2];
  78 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  79
  80 typedef void (GenOpFunc)(void);
  81 typedef void (GenOpFunc1)(long);
  82 typedef void (GenOpFunc2)(long, long);
  83 typedef void (GenOpFunc3)(long, long, long);
  84
  85 #if defined(TARGET_I386)
  86
  87 void optimize_flags_init(void);
  88
  89 #endif
  90
  91 extern FILE *logfile;
  92 extern int loglevel;
  93
  94 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  95 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  96 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  97 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  98                  int max_code_size, int *gen_code_size_ptr);
  99 int cpu_restore_state(struct TranslationBlock *tb,
 100                       CPUState *env, unsigned long searched_pc,
 101                       void *puc);
 102 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
 103                       int max_code_size, int *gen_code_size_ptr);
 104 int cpu_restore_state_copy(struct TranslationBlock *tb,
 105                            CPUState *env, unsigned long searched_pc,
 106                            void *puc);
 107 void cpu_resume_from_signal(CPUState *env1, void *puc);
 108 void cpu_exec_init(CPUState *env);
 109 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
 110 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
 111                                    int is_cpu_write_access);
 112 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 113 void tlb_flush_page(CPUState *env, target_ulong addr);
 114 void tlb_flush(CPUState *env, int flush_global);
 115 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
 116                       target_phys_addr_t paddr, int prot,
 117                       int mmu_idx, int is_softmmu);
 118 static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
 119                                target_phys_addr_t paddr, int prot,
 120                                int mmu_idx, int is_softmmu)
 121 {
 122     if (prot & PAGE_READ)
 123         prot |= PAGE_EXEC;
 124     return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 125 }
 126
 127 #define CODE_GEN_MAX_SIZE        65536
 128 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 129
 130 #define CODE_GEN_PHYS_HASH_BITS     15
 131 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 132
 133 /* maximum total translate dcode allocated */
 134
 135 /* NOTE: the translated code area cannot be too big because on some
 136    archs the range of "fast" function calls is limited. Here is a
 137    summary of the ranges:
 138
 139    i386  : signed 32 bits
 140    arm   : signed 26 bits
 141    ppc   : signed 24 bits
 142    sparc : signed 32 bits
 143    alpha : signed 23 bits
 144 */
 145
 146 #if defined(__alpha__)
 147 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 148 #elif defined(__ia64)
 149 #define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)      /* range of addl */
 150 #elif defined(__powerpc__)
 151 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 152 #else
 153 #define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
 154 #endif
 155
 156 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 157
 158 /* estimated block size for TB allocation */
 159 /* XXX: use a per code average code fragment size and modulate it
 160    according to the host CPU */
 161 #if defined(CONFIG_SOFTMMU)
 162 #define CODE_GEN_AVG_BLOCK_SIZE 128
 163 #else
 164 #define CODE_GEN_AVG_BLOCK_SIZE 64
 165 #endif
 166
 167 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 168
 169 #if defined(__powerpc__)
 170 #define USE_DIRECT_JUMP
 171 #endif
 172 #if defined(__i386__) && !defined(_WIN32)
 173 #define USE_DIRECT_JUMP
 174 #endif
 175
 176 typedef struct TranslationBlock {
 177     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 178     target_ulong cs_base; /* CS base for this block */
 179     uint64_t flags; /* flags defining in which context the code was generated */
 180     uint16_t size;      /* size of target code for this block (1 <=
 181                            size <= TARGET_PAGE_SIZE) */
 182     uint16_t cflags;    /* compile flags */
 183 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 184 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 185 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 186 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 187
 188     uint8_t *tc_ptr;    /* pointer to the translated code */
 189     /* next matching tb for physical address. */
 190     struct TranslationBlock *phys_hash_next;
 191     /* first and second physical page containing code. The lower bit
 192        of the pointer tells the index in page_next[] */
 193     struct TranslationBlock *page_next[2];
 194     target_ulong page_addr[2];
 195
 196     /* the following data are used to directly call another TB from
 197        the code of this one. */
 198     uint16_t tb_next_offset[2]; /* offset of original jump target */
 199 #ifdef USE_DIRECT_JUMP
 200     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 201 #else
 202     uint32_t tb_next[2]; /* address of jump generated code */
 203 #endif
 204     /* list of TBs jumping to this one. This is a circular list using
 205        the two least significant bits of the pointers to tell what is
 206        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 207        jmp_first */
 208     struct TranslationBlock *jmp_next[2];
 209     struct TranslationBlock *jmp_first;
 210 } TranslationBlock;
 211
 212 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 213 {
 214     target_ulong tmp;
 215     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 216     return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
 217 }
 218
 219 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 220 {
 221     target_ulong tmp;
 222     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 223     return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
 224             (tmp & TB_JMP_ADDR_MASK));
 225 }
 226
 227 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 228 {
 229     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 230 }
 231
 232 TranslationBlock *tb_alloc(target_ulong pc);
 233 void tb_flush(CPUState *env);
 234 void tb_link_phys(TranslationBlock *tb,
 235                   target_ulong phys_pc, target_ulong phys_page2);
 236
 237 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 238
 239 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 240 extern uint8_t *code_gen_ptr;
 241
 242 #if defined(USE_DIRECT_JUMP)
 243
 244 #if defined(__powerpc__)
 245 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 246 {
 247     uint32_t val, *ptr;
 248
 249     /* patch the branch destination */
 250     ptr = (uint32_t *)jmp_addr;
 251     val = *ptr;
 252     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 253     *ptr = val;
 254     /* flush icache */
 255     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 256     asm volatile ("sync" : : : "memory");
 257     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 258     asm volatile ("sync" : : : "memory");
 259     asm volatile ("isync" : : : "memory");
 260 }
 261 #elif defined(__i386__)
 262 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 263 {
 264     /* patch the branch destination */
 265     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 266     /* no need to flush icache explicitely */
 267 }
 268 #endif
 269
 270 static inline void tb_set_jmp_target(TranslationBlock *tb,
 271                                      int n, unsigned long addr)
 272 {
 273     unsigned long offset;
 274
 275     offset = tb->tb_jmp_offset[n];
 276     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 277     offset = tb->tb_jmp_offset[n + 2];
 278     if (offset != 0xffff)
 279         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 280 }
 281
 282 #else
 283
 284 /* set the jump target */
 285 static inline void tb_set_jmp_target(TranslationBlock *tb,
 286                                      int n, unsigned long addr)
 287 {
 288     tb->tb_next[n] = addr;
 289 }
 290
 291 #endif
 292
 293 static inline void tb_add_jump(TranslationBlock *tb, int n,
 294                                TranslationBlock *tb_next)
 295 {
 296     /* NOTE: this test is only needed for thread safety */
 297     if (!tb->jmp_next[n]) {
 298         /* patch the native jump address */
 299         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 300
 301         /* add in TB jmp circular list */
 302         tb->jmp_next[n] = tb_next->jmp_first;
 303         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 304     }
 305 }
 306
 307 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 308
 309 #ifndef offsetof
 310 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 311 #endif
 312
 313 #if defined(_WIN32)
 314 #define ASM_DATA_SECTION ".section \".data\"\n"
 315 #define ASM_PREVIOUS_SECTION ".section .text\n"
 316 #elif defined(__APPLE__)
 317 #define ASM_DATA_SECTION ".data\n"
 318 #define ASM_PREVIOUS_SECTION ".text\n"
 319 #else
 320 #define ASM_DATA_SECTION ".section \".data\"\n"
 321 #define ASM_PREVIOUS_SECTION ".previous\n"
 322 #endif
 323
 324 #define ASM_OP_LABEL_NAME(n, opname) \
 325     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 326
 327 #if defined(__powerpc__)
 328
 329 /* we patch the jump instruction directly */
 330 #define GOTO_TB(opname, tbparam, n)\
 331 do {\
 332     asm volatile (ASM_DATA_SECTION\
 333                   ASM_OP_LABEL_NAME(n, opname) ":\n"\
 334                   ".long 1f\n"\
 335                   ASM_PREVIOUS_SECTION \
 336                   "b " ASM_NAME(__op_jmp) #n "\n"\
 337                   "1:\n");\
 338 } while (0)
 339
 340 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 341
 342 /* we patch the jump instruction directly */
 343 #define GOTO_TB(opname, tbparam, n)\
 344 do {\
 345     asm volatile (".section .data\n"\
 346                   ASM_OP_LABEL_NAME(n, opname) ":\n"\
 347                   ".long 1f\n"\
 348                   ASM_PREVIOUS_SECTION \
 349                   "jmp " ASM_NAME(__op_jmp) #n "\n"\
 350                   "1:\n");\
 351 } while (0)
 352
 353 #elif defined(__s390__)
 354 /* GCC spills R13, so we have to restore it before branching away */
 355
 356 #define GOTO_TB(opname, tbparam, n)\
 357 do {\
 358     static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
 359     static void __attribute__((used)) *__op_label ## n \
 360         __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
 361         __asm__ __volatile__ ( \
 362                 "l %%r13,52(%%r15)\n" \
 363                 "br %0\n" \
 364         : : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\
 365         \
 366         for(;*((int*)0);); /* just to keep GCC busy */ \
 367 label ## n: ;\
 368 dummy_label ## n: ;\
 369 } while(0)
 370
 371 #else
 372
 373 /* jump to next block operations (more portable code, does not need
 374    cache flushing, but slower because of indirect jump) */
 375 #define GOTO_TB(opname, tbparam, n)\
 376 do {\
 377     static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
 378     static void __attribute__((used)) *__op_label ## n \
 379         __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
 380     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 381 label ## n: ;\
 382 dummy_label ## n: ;\
 383 } while (0)
 384
 385 #endif
 386
 387 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 388 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 389 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 390
 391 #if defined(__powerpc__)
 392 static inline int testandset (int *p)
 393 {
 394     int ret;
 395     __asm__ __volatile__ (
 396                           "0:    lwarx %0,0,%1\n"
 397                           "      xor. %0,%3,%0\n"
 398                           "      bne 1f\n"
 399                           "      stwcx. %2,0,%1\n"
 400                           "      bne- 0b\n"
 401                           "1:    "
 402                           : "=&r" (ret)
 403                           : "r" (p), "r" (1), "r" (0)
 404                           : "cr0", "memory");
 405     return ret;
 406 }
 407 #elif defined(__i386__)
 408 static inline int testandset (int *p)
 409 {
 410     long int readval = 0;
 411
 412     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 413                           : "+m" (*p), "+a" (readval)
 414                           : "r" (1)
 415                           : "cc");
 416     return readval;
 417 }
 418 #elif defined(__x86_64__)
 419 static inline int testandset (int *p)
 420 {
 421     long int readval = 0;
 422
 423     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 424                           : "+m" (*p), "+a" (readval)
 425                           : "r" (1)
 426                           : "cc");
 427     return readval;
 428 }
 429 #elif defined(__s390__)
 430 static inline int testandset (int *p)
 431 {
 432     int ret;
 433
 434     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 435                           "   jl    0b"
 436                           : "=&d" (ret)
 437                           : "r" (1), "a" (p), "0" (*p)
 438                           : "cc", "memory" );
 439     return ret;
 440 }
 441 #elif defined(__alpha__)
 442 static inline int testandset (int *p)
 443 {
 444     int ret;
 445     unsigned long one;
 446
 447     __asm__ __volatile__ ("0:   mov 1,%2\n"
 448                           "     ldl_l %0,%1\n"
 449                           "     stl_c %2,%1\n"
 450                           "     beq %2,1f\n"
 451                           ".subsection 2\n"
 452                           "1:   br 0b\n"
 453                           ".previous"
 454                           : "=r" (ret), "=m" (*p), "=r" (one)
 455                           : "m" (*p));
 456     return ret;
 457 }
 458 #elif defined(__sparc__)
 459 static inline int testandset (int *p)
 460 {
 461         int ret;
 462
 463         __asm__ __volatile__("ldstub    [%1], %0"
 464                              : "=r" (ret)
 465                              : "r" (p)
 466                              : "memory");
 467
 468         return (ret ? 1 : 0);
 469 }
 470 #elif defined(__arm__)
 471 static inline int testandset (int *spinlock)
 472 {
 473     register unsigned int ret;
 474     __asm__ __volatile__("swp %0, %1, [%2]"
 475                          : "=r"(ret)
 476                          : "0"(1), "r"(spinlock));
 477
 478     return ret;
 479 }
 480 #elif defined(__mc68000)
 481 static inline int testandset (int *p)
 482 {
 483     char ret;
 484     __asm__ __volatile__("tas %1; sne %0"
 485                          : "=r" (ret)
 486                          : "m" (p)
 487                          : "cc","memory");
 488     return ret;
 489 }
 490 #elif defined(__ia64)
 491
 492 #include <ia64intrin.h>
 493
 494 static inline int testandset (int *p)
 495 {
 496     return __sync_lock_test_and_set (p, 1);
 497 }
 498 #elif defined(__mips__)
 499 static inline int testandset (int *p)
 500 {
 501     int ret;
 502
 503     __asm__ __volatile__ (
 504         "       .set push               \n"
 505         "       .set noat               \n"
 506         "       .set mips2              \n"
 507         "1:     li      $1, 1           \n"
 508         "       ll      %0, %1          \n"
 509         "       sc      $1, %1          \n"
 510         "       beqz    $1, 1b          \n"
 511         "       .set pop                "
 512         : "=r" (ret), "+R" (*p)
 513         :
 514         : "memory");
 515
 516     return ret;
 517 }
 518 #else
 519 #error unimplemented CPU support
 520 #endif
 521
 522 typedef int spinlock_t;
 523
 524 #define SPIN_LOCK_UNLOCKED 0
 525
 526 #if defined(CONFIG_USER_ONLY)
 527 static inline void spin_lock(spinlock_t *lock)
 528 {
 529     while (testandset(lock));
 530 }
 531
 532 static inline void spin_unlock(spinlock_t *lock)
 533 {
 534     *lock = 0;
 535 }
 536
 537 static inline int spin_trylock(spinlock_t *lock)
 538 {
 539     return !testandset(lock);
 540 }
 541 #else
 542 static inline void spin_lock(spinlock_t *lock)
 543 {
 544 }
 545
 546 static inline void spin_unlock(spinlock_t *lock)
 547 {
 548 }
 549
 550 static inline int spin_trylock(spinlock_t *lock)
 551 {
 552     return 1;
 553 }
 554 #endif
 555
 556 extern spinlock_t tb_lock;
 557
 558 extern int tb_invalidated_flag;
 559
 560 #if !defined(CONFIG_USER_ONLY)
 561
 562 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 563               void *retaddr);
 564
 565 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 566 #define MEMSUFFIX _code
 567 #define env cpu_single_env
 568
 569 #define DATA_SIZE 1
 570 #include "softmmu_header.h"
 571
 572 #define DATA_SIZE 2
 573 #include "softmmu_header.h"
 574
 575 #define DATA_SIZE 4
 576 #include "softmmu_header.h"
 577
 578 #define DATA_SIZE 8
 579 #include "softmmu_header.h"
 580
 581 #undef ACCESS_TYPE
 582 #undef MEMSUFFIX
 583 #undef env
 584
 585 #endif
 586
 587 #if defined(CONFIG_USER_ONLY)
 588 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 589 {
 590     return addr;
 591 }
 592 #else
 593 /* NOTE: this function can trigger an exception */
 594 /* NOTE2: the returned address is not exactly the physical address: it
 595    is the offset relative to phys_ram_base */
 596 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 597 {
 598     int mmu_idx, index, pd;
 599
 600     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 601     mmu_idx = cpu_mmu_index(env);
 602     if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
 603                          (addr & TARGET_PAGE_MASK), 0)) {
 604         ldub_code(addr);
 605     }
 606     pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
 607     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 608 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 609         do_unassigned_access(addr, 0, 1, 0);
 610 #else
 611         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 612 #endif
 613     }
 614     return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
 615 }
 616 #endif
 617
 618 #ifdef USE_KQEMU
 619 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 620
 621 int kqemu_init(CPUState *env);
 622 int kqemu_cpu_exec(CPUState *env);
 623 void kqemu_flush_page(CPUState *env, target_ulong addr);
 624 void kqemu_flush(CPUState *env, int global);
 625 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 626 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 627 void kqemu_cpu_interrupt(CPUState *env);
 628 void kqemu_record_dump(void);
 629
 630 static inline int kqemu_is_ok(CPUState *env)
 631 {
 632     return(env->kqemu_enabled &&
 633            (env->cr[0] & CR0_PE_MASK) &&
 634            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 635            (env->eflags & IF_MASK) &&
 636            !(env->eflags & VM_MASK) &&
 637            (env->kqemu_enabled == 2 ||
 638             ((env->hflags & HF_CPL_MASK) == 3 &&
 639              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 640 }
 641
 642 #endif