4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #define MMU_ITLB_MISS (-1)
33 #define MMU_ITLB_MULTIPLE (-2)
34 #define MMU_ITLB_VIOLATION (-3)
35 #define MMU_DTLB_MISS_READ (-4)
36 #define MMU_DTLB_MISS_WRITE (-5)
37 #define MMU_DTLB_INITIAL_WRITE (-6)
38 #define MMU_DTLB_VIOLATION_READ (-7)
39 #define MMU_DTLB_VIOLATION_WRITE (-8)
40 #define MMU_DTLB_MULTIPLE (-9)
41 #define MMU_DTLB_MISS (-10)
43 void do_interrupt(CPUState
* env
)
45 if (loglevel
& CPU_LOG_INT
) {
47 switch (env
->exception_index
) {
49 expname
= "addr_error";
55 expname
= "tlb_violation";
58 expname
= "illegal_instruction";
61 expname
= "slot_illegal_instruction";
64 expname
= "fpu_disable";
70 expname
= "data_write";
73 expname
= "dtlb_miss_write";
76 expname
= "dtlb_violation_write";
79 expname
= "fpu_exception";
82 expname
= "initial_page_write";
91 fprintf(logfile
, "exception 0x%03x [%s] raised\n",
92 env
->exception_index
, expname
);
93 cpu_dump_state(env
, logfile
, fprintf
, 0);
98 env
->sgr
= env
->gregs
[15];
99 env
->sr
|= SR_BL
| SR_MD
| SR_RB
;
101 env
->expevt
= env
->exception_index
& 0x7ff;
102 switch (env
->exception_index
) {
106 env
->pc
= env
->vbr
+ 0x400;
109 env
->pc
= 0xa0000000;
112 env
->pc
= env
->vbr
+ 0x100;
117 static void update_itlb_use(CPUState
* env
, int itlbnb
)
119 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
138 env
->mmucr
&= (and_mask
<< 24);
139 env
->mmucr
|= (or_mask
<< 24);
142 static int itlb_replacement(CPUState
* env
)
144 if ((env
->mmucr
& 0xe0000000) == 0xe0000000)
146 if ((env
->mmucr
& 0x98000000) == 0x08000000)
148 if ((env
->mmucr
& 0x54000000) == 0x04000000)
150 if ((env
->mmucr
& 0x2c000000) == 0x00000000)
155 /* Find the corresponding entry in the right TLB
156 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
158 static int find_tlb_entry(CPUState
* env
, target_ulong address
,
159 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
161 int match
= MMU_DTLB_MISS
;
166 asid
= env
->pteh
& 0xff;
168 for (i
= 0; i
< nbtlb
; i
++) {
170 continue; /* Invalid entry */
171 if (use_asid
&& entries
[i
].asid
!= asid
&& !entries
[i
].sh
)
172 continue; /* Bad ASID */
174 switch (entries
[i
].sz
) {
176 size
= 1024; /* 1kB */
179 size
= 4 * 1024; /* 4kB */
182 size
= 64 * 1024; /* 64kB */
185 size
= 1024 * 1024; /* 1MB */
191 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
192 end
= start
+ entries
[i
].size
- 1;
193 if (address
>= start
&& address
<= end
) { /* Match */
195 return MMU_DTLB_MULTIPLE
; /* Multiple match */
202 /* Find itlb entry - update itlb from utlb if necessary and asked for
203 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
204 Update the itlb from utlb if update is not 0
206 int find_itlb_entry(CPUState
* env
, target_ulong address
,
207 int use_asid
, int update
)
211 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
212 if (e
== MMU_DTLB_MULTIPLE
)
213 e
= MMU_ITLB_MULTIPLE
;
214 else if (e
== MMU_DTLB_MISS
&& update
) {
215 e
= find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
217 n
= itlb_replacement(env
);
218 env
->itlb
[n
] = env
->utlb
[e
];
223 update_itlb_use(env
, e
);
228 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
229 int find_utlb_entry(CPUState
* env
, target_ulong address
, int use_asid
)
234 urb
= ((env
->mmucr
) >> 18) & 0x3f;
235 urc
= ((env
->mmucr
) >> 10) & 0x3f;
237 if (urc
== urb
|| urc
== UTLB_SIZE
- 1)
239 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
242 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
245 /* Match address against MMU
246 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
247 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
248 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
249 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
251 static int get_mmu_address(CPUState
* env
, target_ulong
* physical
,
252 int *prot
, target_ulong address
,
253 int rw
, int access_type
)
255 int use_asid
, is_code
, n
;
256 tlb_t
*matching
= NULL
;
258 use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 && (env
->sr
& SR_MD
) == 0;
259 is_code
= env
->pc
== address
; /* Hack */
261 /* Use a hack to find if this is an instruction or data access */
262 if (env
->pc
== address
&& !(rw
& PAGE_WRITE
)) {
263 n
= find_itlb_entry(env
, address
, use_asid
, 1);
265 matching
= &env
->itlb
[n
];
266 if ((env
->sr
& SR_MD
) & !(matching
->pr
& 2))
267 n
= MMU_ITLB_VIOLATION
;
272 n
= find_utlb_entry(env
, address
, use_asid
);
274 matching
= &env
->utlb
[n
];
275 switch ((matching
->pr
<< 1) | ((env
->sr
& SR_MD
) ? 1 : 0)) {
278 n
= (rw
& PAGE_WRITE
) ? MMU_DTLB_VIOLATION_WRITE
:
279 MMU_DTLB_VIOLATION_READ
;
285 n
= MMU_DTLB_VIOLATION_WRITE
;
292 *prot
= rw
& (PAGE_READ
| PAGE_WRITE
);
295 } else if (n
== MMU_DTLB_MISS
) {
296 n
= (rw
& PAGE_WRITE
) ? MMU_DTLB_MISS_WRITE
:
301 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1)) |
302 (address
& (matching
->size
- 1));
303 if ((rw
& PAGE_WRITE
) & !matching
->d
)
304 n
= MMU_DTLB_INITIAL_WRITE
;
311 int get_physical_address(CPUState
* env
, target_ulong
* physical
,
312 int *prot
, target_ulong address
,
313 int rw
, int access_type
)
315 /* P1, P2 and P4 areas do not use translation */
316 if ((address
>= 0x80000000 && address
< 0xc0000000) ||
317 address
>= 0xe0000000) {
318 if (!(env
->sr
& SR_MD
)
319 && (address
< 0xe0000000 || address
> 0xe4000000)) {
320 /* Unauthorized access in user mode (only store queues are available) */
321 fprintf(stderr
, "Unauthorized access\n");
322 return (rw
& PAGE_WRITE
) ? MMU_DTLB_MISS_WRITE
:
325 /* Mask upper 3 bits */
326 *physical
= address
& 0x1FFFFFFF;
327 *prot
= PAGE_READ
| PAGE_WRITE
;
331 /* If MMU is disabled, return the corresponding physical page */
332 if (!env
->mmucr
& MMUCR_AT
) {
333 *physical
= address
& 0x1FFFFFFF;
334 *prot
= PAGE_READ
| PAGE_WRITE
;
338 /* We need to resort to the MMU */
339 return get_mmu_address(env
, physical
, prot
, address
, rw
, access_type
);
342 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
343 int is_user
, int is_softmmu
)
345 target_ulong physical
, page_offset
, page_size
;
346 int prot
, ret
, access_type
;
350 fprintf(stderr
, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
351 __func__
, env
->pc
, address
, rw
, is_user
, is_softmmu
);
354 access_type
= ACCESS_INT
;
356 get_physical_address(env
, &physical
, &prot
, address
, rw
,
363 case MMU_DTLB_MISS_READ
:
364 env
->exception_index
= 0x040;
366 case MMU_DTLB_MULTIPLE
:
367 case MMU_ITLB_MULTIPLE
:
368 env
->exception_index
= 0x140;
370 case MMU_ITLB_VIOLATION
:
371 env
->exception_index
= 0x0a0;
373 case MMU_DTLB_MISS_WRITE
:
374 env
->exception_index
= 0x060;
376 case MMU_DTLB_INITIAL_WRITE
:
377 env
->exception_index
= 0x080;
379 case MMU_DTLB_VIOLATION_READ
:
380 env
->exception_index
= 0x0a0;
382 case MMU_DTLB_VIOLATION_WRITE
:
383 env
->exception_index
= 0x0c0;
391 page_size
= TARGET_PAGE_SIZE
;
393 (address
- (address
& TARGET_PAGE_MASK
)) & ~(page_size
- 1);
394 address
= (address
& TARGET_PAGE_MASK
) + page_offset
;
395 physical
= (physical
& TARGET_PAGE_MASK
) + page_offset
;
397 return tlb_set_page(env
, address
, physical
, prot
, is_user
, is_softmmu
);