2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 const char *tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
35 int tcg_target_reg_alloc_order
[] = {
45 const int tcg_target_call_iarg_regs
[3] = { TCG_REG_EAX
, TCG_REG_EDX
, TCG_REG_ECX
};
46 const int tcg_target_call_oarg_regs
[2] = { TCG_REG_EAX
, TCG_REG_EDX
};
48 static uint8_t *tb_ret_addr
;
50 static void patch_reloc(uint8_t *code_ptr
, int type
,
51 tcg_target_long value
, tcg_target_long addend
)
56 *(uint32_t *)code_ptr
= value
;
59 *(uint32_t *)code_ptr
= value
- (long)code_ptr
;
66 /* maximum number of register used for input function arguments */
67 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
69 flags
&= TCG_CALL_TYPE_MASK
;
71 case TCG_CALL_TYPE_STD
:
73 case TCG_CALL_TYPE_REGPARM_1
:
74 case TCG_CALL_TYPE_REGPARM_2
:
75 case TCG_CALL_TYPE_REGPARM
:
76 return flags
- TCG_CALL_TYPE_REGPARM_1
+ 1;
82 /* parse target specific constraints */
83 int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
91 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EAX
);
95 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EBX
);
99 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_ECX
);
102 ct
->ct
|= TCG_CT_REG
;
103 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EDX
);
106 ct
->ct
|= TCG_CT_REG
;
107 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_ESI
);
110 ct
->ct
|= TCG_CT_REG
;
111 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_EDI
);
114 ct
->ct
|= TCG_CT_REG
;
115 tcg_regset_set32(ct
->u
.regs
, 0, 0xf);
118 ct
->ct
|= TCG_CT_REG
;
119 tcg_regset_set32(ct
->u
.regs
, 0, 0xff);
122 /* qemu_ld/st address constraint */
124 ct
->ct
|= TCG_CT_REG
;
125 tcg_regset_set32(ct
->u
.regs
, 0, 0xff);
126 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_EAX
);
127 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_EDX
);
137 /* test if a constant matches the constraint */
138 static inline int tcg_target_const_match(tcg_target_long val
,
139 const TCGArgConstraint
*arg_ct
)
143 if (ct
& TCG_CT_CONST
)
180 #define P_EXT 0x100 /* 0x0f opcode prefix */
182 static const uint8_t tcg_cond_to_jcc
[10] = {
183 [TCG_COND_EQ
] = JCC_JE
,
184 [TCG_COND_NE
] = JCC_JNE
,
185 [TCG_COND_LT
] = JCC_JL
,
186 [TCG_COND_GE
] = JCC_JGE
,
187 [TCG_COND_LE
] = JCC_JLE
,
188 [TCG_COND_GT
] = JCC_JG
,
189 [TCG_COND_LTU
] = JCC_JB
,
190 [TCG_COND_GEU
] = JCC_JAE
,
191 [TCG_COND_LEU
] = JCC_JBE
,
192 [TCG_COND_GTU
] = JCC_JA
,
195 static inline void tcg_out_opc(TCGContext
*s
, int opc
)
202 static inline void tcg_out_modrm(TCGContext
*s
, int opc
, int r
, int rm
)
205 tcg_out8(s
, 0xc0 | (r
<< 3) | rm
);
208 /* rm == -1 means no register index */
209 static inline void tcg_out_modrm_offset(TCGContext
*s
, int opc
, int r
, int rm
,
214 tcg_out8(s
, 0x05 | (r
<< 3));
215 tcg_out32(s
, offset
);
216 } else if (offset
== 0 && rm
!= TCG_REG_EBP
) {
217 if (rm
== TCG_REG_ESP
) {
218 tcg_out8(s
, 0x04 | (r
<< 3));
221 tcg_out8(s
, 0x00 | (r
<< 3) | rm
);
223 } else if ((int8_t)offset
== offset
) {
224 if (rm
== TCG_REG_ESP
) {
225 tcg_out8(s
, 0x44 | (r
<< 3));
228 tcg_out8(s
, 0x40 | (r
<< 3) | rm
);
232 if (rm
== TCG_REG_ESP
) {
233 tcg_out8(s
, 0x84 | (r
<< 3));
236 tcg_out8(s
, 0x80 | (r
<< 3) | rm
);
238 tcg_out32(s
, offset
);
242 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
245 tcg_out_modrm(s
, 0x8b, ret
, arg
);
248 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
249 int ret
, int32_t arg
)
253 tcg_out_modrm(s
, 0x01 | (ARITH_XOR
<< 3), ret
, ret
);
255 tcg_out8(s
, 0xb8 + ret
);
260 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int ret
,
261 int arg1
, tcg_target_long arg2
)
264 tcg_out_modrm_offset(s
, 0x8b, ret
, arg1
, arg2
);
267 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
268 int arg1
, tcg_target_long arg2
)
271 tcg_out_modrm_offset(s
, 0x89, arg
, arg1
, arg2
);
274 static inline void tgen_arithi(TCGContext
*s
, int c
, int r0
, int32_t val
)
276 if (val
== (int8_t)val
) {
277 tcg_out_modrm(s
, 0x83, c
, r0
);
280 tcg_out_modrm(s
, 0x81, c
, r0
);
285 void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
288 tgen_arithi(s
, ARITH_ADD
, reg
, val
);
291 static void tcg_out_jxx(TCGContext
*s
, int opc
, int label_index
)
294 TCGLabel
*l
= &s
->labels
[label_index
];
297 val
= l
->u
.value
- (tcg_target_long
)s
->code_ptr
;
299 if ((int8_t)val1
== val1
) {
303 tcg_out8(s
, 0x70 + opc
);
308 tcg_out32(s
, val
- 5);
311 tcg_out8(s
, 0x80 + opc
);
312 tcg_out32(s
, val
- 6);
320 tcg_out8(s
, 0x80 + opc
);
322 tcg_out_reloc(s
, s
->code_ptr
, R_386_PC32
, label_index
, -4);
327 static void tcg_out_brcond(TCGContext
*s
, int cond
,
328 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
334 tcg_out_modrm(s
, 0x85, arg1
, arg1
);
336 tgen_arithi(s
, ARITH_CMP
, arg1
, arg2
);
339 tcg_out_modrm(s
, 0x01 | (ARITH_CMP
<< 3), arg2
, arg1
);
341 tcg_out_jxx(s
, tcg_cond_to_jcc
[cond
], label_index
);
344 /* XXX: we implement it at the target level to avoid having to
345 handle cross basic blocks temporaries */
346 static void tcg_out_brcond2(TCGContext
*s
,
347 const TCGArg
*args
, const int *const_args
)
350 label_next
= gen_new_label();
353 tcg_out_brcond(s
, TCG_COND_NE
, args
[0], args
[2], const_args
[2], label_next
);
354 tcg_out_brcond(s
, TCG_COND_EQ
, args
[1], args
[3], const_args
[3], args
[5]);
357 tcg_out_brcond(s
, TCG_COND_NE
, args
[0], args
[2], const_args
[2], args
[5]);
358 tcg_out_brcond(s
, TCG_COND_NE
, args
[1], args
[3], const_args
[3], args
[5]);
361 tcg_out_brcond(s
, TCG_COND_LT
, args
[1], args
[3], const_args
[3], args
[5]);
362 tcg_out_jxx(s
, JCC_JNE
, label_next
);
363 tcg_out_brcond(s
, TCG_COND_LTU
, args
[0], args
[2], const_args
[2], args
[5]);
366 tcg_out_brcond(s
, TCG_COND_LT
, args
[1], args
[3], const_args
[3], args
[5]);
367 tcg_out_jxx(s
, JCC_JNE
, label_next
);
368 tcg_out_brcond(s
, TCG_COND_LEU
, args
[0], args
[2], const_args
[2], args
[5]);
371 tcg_out_brcond(s
, TCG_COND_GT
, args
[1], args
[3], const_args
[3], args
[5]);
372 tcg_out_jxx(s
, JCC_JNE
, label_next
);
373 tcg_out_brcond(s
, TCG_COND_GTU
, args
[0], args
[2], const_args
[2], args
[5]);
376 tcg_out_brcond(s
, TCG_COND_GT
, args
[1], args
[3], const_args
[3], args
[5]);
377 tcg_out_jxx(s
, JCC_JNE
, label_next
);
378 tcg_out_brcond(s
, TCG_COND_GEU
, args
[0], args
[2], const_args
[2], args
[5]);
381 tcg_out_brcond(s
, TCG_COND_LTU
, args
[1], args
[3], const_args
[3], args
[5]);
382 tcg_out_jxx(s
, JCC_JNE
, label_next
);
383 tcg_out_brcond(s
, TCG_COND_LTU
, args
[0], args
[2], const_args
[2], args
[5]);
386 tcg_out_brcond(s
, TCG_COND_LTU
, args
[1], args
[3], const_args
[3], args
[5]);
387 tcg_out_jxx(s
, JCC_JNE
, label_next
);
388 tcg_out_brcond(s
, TCG_COND_LEU
, args
[0], args
[2], const_args
[2], args
[5]);
391 tcg_out_brcond(s
, TCG_COND_GTU
, args
[1], args
[3], const_args
[3], args
[5]);
392 tcg_out_jxx(s
, JCC_JNE
, label_next
);
393 tcg_out_brcond(s
, TCG_COND_GTU
, args
[0], args
[2], const_args
[2], args
[5]);
396 tcg_out_brcond(s
, TCG_COND_GTU
, args
[1], args
[3], const_args
[3], args
[5]);
397 tcg_out_jxx(s
, JCC_JNE
, label_next
);
398 tcg_out_brcond(s
, TCG_COND_GEU
, args
[0], args
[2], const_args
[2], args
[5]);
403 tcg_out_label(s
, label_next
, (tcg_target_long
)s
->code_ptr
);
406 #if defined(CONFIG_SOFTMMU)
407 extern void __ldb_mmu(void);
408 extern void __ldw_mmu(void);
409 extern void __ldl_mmu(void);
410 extern void __ldq_mmu(void);
412 extern void __stb_mmu(void);
413 extern void __stw_mmu(void);
414 extern void __stl_mmu(void);
415 extern void __stq_mmu(void);
417 static void *qemu_ld_helpers
[4] = {
424 static void *qemu_st_helpers
[4] = {
432 /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
433 EAX. It will be useful once fixed registers globals are less
435 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
,
438 int addr_reg
, data_reg
, data_reg2
, r0
, r1
, mem_index
, s_bits
, bswap
;
439 #if defined(CONFIG_SOFTMMU)
440 uint8_t *label1_ptr
, *label2_ptr
;
442 #if TARGET_LONG_BITS == 64
443 #if defined(CONFIG_SOFTMMU)
455 #if TARGET_LONG_BITS == 64
464 #if defined(CONFIG_SOFTMMU)
465 tcg_out_mov(s
, r1
, addr_reg
);
467 tcg_out_mov(s
, r0
, addr_reg
);
469 tcg_out_modrm(s
, 0xc1, 5, r1
); /* shr $x, r1 */
470 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
472 tcg_out_modrm(s
, 0x81, 4, r0
); /* andl $x, r0 */
473 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
475 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
476 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
478 tcg_out_opc(s
, 0x8d); /* lea offset(r1, %ebp), r1 */
479 tcg_out8(s
, 0x80 | (r1
<< 3) | 0x04);
480 tcg_out8(s
, (5 << 3) | r1
);
481 tcg_out32(s
, offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
));
484 tcg_out_modrm_offset(s
, 0x3b, r0
, r1
, 0);
486 tcg_out_mov(s
, r0
, addr_reg
);
488 #if TARGET_LONG_BITS == 32
490 tcg_out8(s
, 0x70 + JCC_JE
);
491 label1_ptr
= s
->code_ptr
;
495 tcg_out8(s
, 0x70 + JCC_JNE
);
496 label3_ptr
= s
->code_ptr
;
499 /* cmp 4(r1), addr_reg2 */
500 tcg_out_modrm_offset(s
, 0x3b, addr_reg2
, r1
, 4);
503 tcg_out8(s
, 0x70 + JCC_JE
);
504 label1_ptr
= s
->code_ptr
;
508 *label3_ptr
= s
->code_ptr
- label3_ptr
- 1;
511 /* XXX: move that code at the end of the TB */
512 #if TARGET_LONG_BITS == 32
513 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_EDX
, mem_index
);
515 tcg_out_mov(s
, TCG_REG_EDX
, addr_reg2
);
516 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_ECX
, mem_index
);
519 tcg_out32(s
, (tcg_target_long
)qemu_ld_helpers
[s_bits
] -
520 (tcg_target_long
)s
->code_ptr
- 4);
525 tcg_out_modrm(s
, 0xbe | P_EXT
, data_reg
, TCG_REG_EAX
);
529 tcg_out_modrm(s
, 0xbf | P_EXT
, data_reg
, TCG_REG_EAX
);
535 tcg_out_mov(s
, data_reg
, TCG_REG_EAX
);
538 if (data_reg
== TCG_REG_EDX
) {
539 tcg_out_opc(s
, 0x90 + TCG_REG_EDX
); /* xchg %edx, %eax */
540 tcg_out_mov(s
, data_reg2
, TCG_REG_EAX
);
542 tcg_out_mov(s
, data_reg
, TCG_REG_EAX
);
543 tcg_out_mov(s
, data_reg2
, TCG_REG_EDX
);
550 label2_ptr
= s
->code_ptr
;
554 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
557 tcg_out_modrm_offset(s
, 0x03, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
558 offsetof(CPUTLBEntry
, addr_read
));
563 #ifdef TARGET_WORDS_BIGENDIAN
571 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, data_reg
, r0
, 0);
575 tcg_out_modrm_offset(s
, 0xbe | P_EXT
, data_reg
, r0
, 0);
579 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, data_reg
, r0
, 0);
581 /* rolw $8, data_reg */
583 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
589 tcg_out_modrm_offset(s
, 0xbf | P_EXT
, data_reg
, r0
, 0);
591 /* rolw $8, data_reg */
593 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
596 /* movswl data_reg, data_reg */
597 tcg_out_modrm(s
, 0xbf | P_EXT
, data_reg
, data_reg
);
601 /* movl (r0), data_reg */
602 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, 0);
605 tcg_out_opc(s
, (0xc8 + data_reg
) | P_EXT
);
609 /* XXX: could be nicer */
610 if (r0
== data_reg
) {
614 tcg_out_mov(s
, r1
, r0
);
618 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, 0);
619 tcg_out_modrm_offset(s
, 0x8b, data_reg2
, r0
, 4);
621 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, 4);
622 tcg_out_opc(s
, (0xc8 + data_reg
) | P_EXT
);
624 tcg_out_modrm_offset(s
, 0x8b, data_reg2
, r0
, 0);
626 tcg_out_opc(s
, (0xc8 + data_reg2
) | P_EXT
);
633 #if defined(CONFIG_SOFTMMU)
635 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
640 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
,
643 int addr_reg
, data_reg
, data_reg2
, r0
, r1
, mem_index
, s_bits
, bswap
;
644 #if defined(CONFIG_SOFTMMU)
645 uint8_t *label1_ptr
, *label2_ptr
;
647 #if TARGET_LONG_BITS == 64
648 #if defined(CONFIG_SOFTMMU)
660 #if TARGET_LONG_BITS == 64
670 #if defined(CONFIG_SOFTMMU)
671 tcg_out_mov(s
, r1
, addr_reg
);
673 tcg_out_mov(s
, r0
, addr_reg
);
675 tcg_out_modrm(s
, 0xc1, 5, r1
); /* shr $x, r1 */
676 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
678 tcg_out_modrm(s
, 0x81, 4, r0
); /* andl $x, r0 */
679 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
681 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
682 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
684 tcg_out_opc(s
, 0x8d); /* lea offset(r1, %ebp), r1 */
685 tcg_out8(s
, 0x80 | (r1
<< 3) | 0x04);
686 tcg_out8(s
, (5 << 3) | r1
);
687 tcg_out32(s
, offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
));
690 tcg_out_modrm_offset(s
, 0x3b, r0
, r1
, 0);
692 tcg_out_mov(s
, r0
, addr_reg
);
694 #if TARGET_LONG_BITS == 32
696 tcg_out8(s
, 0x70 + JCC_JE
);
697 label1_ptr
= s
->code_ptr
;
701 tcg_out8(s
, 0x70 + JCC_JNE
);
702 label3_ptr
= s
->code_ptr
;
705 /* cmp 4(r1), addr_reg2 */
706 tcg_out_modrm_offset(s
, 0x3b, addr_reg2
, r1
, 4);
709 tcg_out8(s
, 0x70 + JCC_JE
);
710 label1_ptr
= s
->code_ptr
;
714 *label3_ptr
= s
->code_ptr
- label3_ptr
- 1;
717 /* XXX: move that code at the end of the TB */
718 #if TARGET_LONG_BITS == 32
720 tcg_out_mov(s
, TCG_REG_EDX
, data_reg
);
721 tcg_out_mov(s
, TCG_REG_ECX
, data_reg2
);
722 tcg_out8(s
, 0x6a); /* push Ib */
723 tcg_out8(s
, mem_index
);
725 tcg_out32(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
] -
726 (tcg_target_long
)s
->code_ptr
- 4);
727 tcg_out_addi(s
, TCG_REG_ESP
, 4);
732 tcg_out_modrm(s
, 0xb6 | P_EXT
, TCG_REG_EDX
, data_reg
);
736 tcg_out_modrm(s
, 0xb7 | P_EXT
, TCG_REG_EDX
, data_reg
);
739 tcg_out_mov(s
, TCG_REG_EDX
, data_reg
);
742 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_ECX
, mem_index
);
744 tcg_out32(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
] -
745 (tcg_target_long
)s
->code_ptr
- 4);
749 tcg_out_mov(s
, TCG_REG_EDX
, addr_reg2
);
750 tcg_out8(s
, 0x6a); /* push Ib */
751 tcg_out8(s
, mem_index
);
752 tcg_out_opc(s
, 0x50 + data_reg2
); /* push */
753 tcg_out_opc(s
, 0x50 + data_reg
); /* push */
755 tcg_out32(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
] -
756 (tcg_target_long
)s
->code_ptr
- 4);
757 tcg_out_addi(s
, TCG_REG_ESP
, 12);
759 tcg_out_mov(s
, TCG_REG_EDX
, addr_reg2
);
763 tcg_out_modrm(s
, 0xb6 | P_EXT
, TCG_REG_ECX
, data_reg
);
767 tcg_out_modrm(s
, 0xb7 | P_EXT
, TCG_REG_ECX
, data_reg
);
770 tcg_out_mov(s
, TCG_REG_ECX
, data_reg
);
773 tcg_out8(s
, 0x6a); /* push Ib */
774 tcg_out8(s
, mem_index
);
776 tcg_out32(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
] -
777 (tcg_target_long
)s
->code_ptr
- 4);
778 tcg_out_addi(s
, TCG_REG_ESP
, 4);
784 label2_ptr
= s
->code_ptr
;
788 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
791 tcg_out_modrm_offset(s
, 0x03, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
792 offsetof(CPUTLBEntry
, addr_write
));
797 #ifdef TARGET_WORDS_BIGENDIAN
805 tcg_out_modrm_offset(s
, 0x88, data_reg
, r0
, 0);
809 tcg_out_mov(s
, r1
, data_reg
);
810 tcg_out8(s
, 0x66); /* rolw $8, %ecx */
811 tcg_out_modrm(s
, 0xc1, 0, r1
);
817 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, 0);
821 tcg_out_mov(s
, r1
, data_reg
);
823 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
);
827 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, 0);
831 tcg_out_mov(s
, r1
, data_reg2
);
833 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
);
834 tcg_out_modrm_offset(s
, 0x89, r1
, r0
, 0);
835 tcg_out_mov(s
, r1
, data_reg
);
837 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
);
838 tcg_out_modrm_offset(s
, 0x89, r1
, r0
, 4);
840 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, 0);
841 tcg_out_modrm_offset(s
, 0x89, data_reg2
, r0
, 4);
848 #if defined(CONFIG_SOFTMMU)
850 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
854 static inline void tcg_out_op(TCGContext
*s
, int opc
,
855 const TCGArg
*args
, const int *const_args
)
860 case INDEX_op_exit_tb
:
861 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_EAX
, args
[0]);
862 tcg_out8(s
, 0xe9); /* jmp tb_ret_addr */
863 tcg_out32(s
, tb_ret_addr
- s
->code_ptr
- 4);
865 case INDEX_op_goto_tb
:
866 if (s
->tb_jmp_offset
) {
867 /* direct jump method */
868 tcg_out8(s
, 0xe9); /* jmp im */
869 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
872 /* indirect jump method */
874 tcg_out_modrm_offset(s
, 0xff, 4, -1,
875 (tcg_target_long
)(s
->tb_next
+ args
[0]));
877 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
882 tcg_out32(s
, args
[0] - (tcg_target_long
)s
->code_ptr
- 4);
884 tcg_out_modrm(s
, 0xff, 2, args
[0]);
890 tcg_out32(s
, args
[0] - (tcg_target_long
)s
->code_ptr
- 4);
892 tcg_out_modrm(s
, 0xff, 4, args
[0]);
896 tcg_out_jxx(s
, JCC_JMP
, args
[0]);
898 case INDEX_op_movi_i32
:
899 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
901 case INDEX_op_ld8u_i32
:
903 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, args
[0], args
[1], args
[2]);
905 case INDEX_op_ld8s_i32
:
907 tcg_out_modrm_offset(s
, 0xbe | P_EXT
, args
[0], args
[1], args
[2]);
909 case INDEX_op_ld16u_i32
:
911 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, args
[0], args
[1], args
[2]);
913 case INDEX_op_ld16s_i32
:
915 tcg_out_modrm_offset(s
, 0xbf | P_EXT
, args
[0], args
[1], args
[2]);
917 case INDEX_op_ld_i32
:
919 tcg_out_modrm_offset(s
, 0x8b, args
[0], args
[1], args
[2]);
921 case INDEX_op_st8_i32
:
923 tcg_out_modrm_offset(s
, 0x88, args
[0], args
[1], args
[2]);
925 case INDEX_op_st16_i32
:
928 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
930 case INDEX_op_st_i32
:
932 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
934 case INDEX_op_sub_i32
:
937 case INDEX_op_and_i32
:
940 case INDEX_op_or_i32
:
943 case INDEX_op_xor_i32
:
946 case INDEX_op_add_i32
:
950 tgen_arithi(s
, c
, args
[0], args
[2]);
952 tcg_out_modrm(s
, 0x01 | (c
<< 3), args
[2], args
[0]);
955 case INDEX_op_mul_i32
:
959 if (val
== (int8_t)val
) {
960 tcg_out_modrm(s
, 0x6b, args
[0], args
[0]);
963 tcg_out_modrm(s
, 0x69, args
[0], args
[0]);
967 tcg_out_modrm(s
, 0xaf | P_EXT
, args
[0], args
[2]);
970 case INDEX_op_mulu2_i32
:
971 tcg_out_modrm(s
, 0xf7, 4, args
[3]);
973 case INDEX_op_div2_i32
:
974 tcg_out_modrm(s
, 0xf7, 7, args
[4]);
976 case INDEX_op_divu2_i32
:
977 tcg_out_modrm(s
, 0xf7, 6, args
[4]);
979 case INDEX_op_shl_i32
:
984 tcg_out_modrm(s
, 0xd1, c
, args
[0]);
986 tcg_out_modrm(s
, 0xc1, c
, args
[0]);
987 tcg_out8(s
, args
[2]);
990 tcg_out_modrm(s
, 0xd3, c
, args
[0]);
993 case INDEX_op_shr_i32
:
996 case INDEX_op_sar_i32
:
1000 case INDEX_op_add2_i32
:
1002 tgen_arithi(s
, ARITH_ADD
, args
[0], args
[4]);
1004 tcg_out_modrm(s
, 0x01 | (ARITH_ADD
<< 3), args
[4], args
[0]);
1006 tgen_arithi(s
, ARITH_ADC
, args
[1], args
[5]);
1008 tcg_out_modrm(s
, 0x01 | (ARITH_ADC
<< 3), args
[5], args
[1]);
1010 case INDEX_op_sub2_i32
:
1012 tgen_arithi(s
, ARITH_SUB
, args
[0], args
[4]);
1014 tcg_out_modrm(s
, 0x01 | (ARITH_SUB
<< 3), args
[4], args
[0]);
1016 tgen_arithi(s
, ARITH_SBB
, args
[1], args
[5]);
1018 tcg_out_modrm(s
, 0x01 | (ARITH_SBB
<< 3), args
[5], args
[1]);
1020 case INDEX_op_brcond_i32
:
1021 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1], args
[3]);
1023 case INDEX_op_brcond2_i32
:
1024 tcg_out_brcond2(s
, args
, const_args
);
1027 case INDEX_op_qemu_ld8u
:
1028 tcg_out_qemu_ld(s
, args
, 0);
1030 case INDEX_op_qemu_ld8s
:
1031 tcg_out_qemu_ld(s
, args
, 0 | 4);
1033 case INDEX_op_qemu_ld16u
:
1034 tcg_out_qemu_ld(s
, args
, 1);
1036 case INDEX_op_qemu_ld16s
:
1037 tcg_out_qemu_ld(s
, args
, 1 | 4);
1039 case INDEX_op_qemu_ld32u
:
1040 tcg_out_qemu_ld(s
, args
, 2);
1042 case INDEX_op_qemu_ld64
:
1043 tcg_out_qemu_ld(s
, args
, 3);
1046 case INDEX_op_qemu_st8
:
1047 tcg_out_qemu_st(s
, args
, 0);
1049 case INDEX_op_qemu_st16
:
1050 tcg_out_qemu_st(s
, args
, 1);
1052 case INDEX_op_qemu_st32
:
1053 tcg_out_qemu_st(s
, args
, 2);
1055 case INDEX_op_qemu_st64
:
1056 tcg_out_qemu_st(s
, args
, 3);
1064 static const TCGTargetOpDef x86_op_defs
[] = {
1065 { INDEX_op_exit_tb
, { } },
1066 { INDEX_op_goto_tb
, { } },
1067 { INDEX_op_call
, { "ri" } },
1068 { INDEX_op_jmp
, { "ri" } },
1069 { INDEX_op_br
, { } },
1070 { INDEX_op_mov_i32
, { "r", "r" } },
1071 { INDEX_op_movi_i32
, { "r" } },
1072 { INDEX_op_ld8u_i32
, { "r", "r" } },
1073 { INDEX_op_ld8s_i32
, { "r", "r" } },
1074 { INDEX_op_ld16u_i32
, { "r", "r" } },
1075 { INDEX_op_ld16s_i32
, { "r", "r" } },
1076 { INDEX_op_ld_i32
, { "r", "r" } },
1077 { INDEX_op_st8_i32
, { "q", "r" } },
1078 { INDEX_op_st16_i32
, { "r", "r" } },
1079 { INDEX_op_st_i32
, { "r", "r" } },
1081 { INDEX_op_add_i32
, { "r", "0", "ri" } },
1082 { INDEX_op_sub_i32
, { "r", "0", "ri" } },
1083 { INDEX_op_mul_i32
, { "r", "0", "ri" } },
1084 { INDEX_op_mulu2_i32
, { "a", "d", "a", "r" } },
1085 { INDEX_op_div2_i32
, { "a", "d", "0", "1", "r" } },
1086 { INDEX_op_divu2_i32
, { "a", "d", "0", "1", "r" } },
1087 { INDEX_op_and_i32
, { "r", "0", "ri" } },
1088 { INDEX_op_or_i32
, { "r", "0", "ri" } },
1089 { INDEX_op_xor_i32
, { "r", "0", "ri" } },
1091 { INDEX_op_shl_i32
, { "r", "0", "ci" } },
1092 { INDEX_op_shr_i32
, { "r", "0", "ci" } },
1093 { INDEX_op_sar_i32
, { "r", "0", "ci" } },
1095 { INDEX_op_brcond_i32
, { "r", "ri" } },
1097 { INDEX_op_add2_i32
, { "r", "r", "0", "1", "ri", "ri" } },
1098 { INDEX_op_sub2_i32
, { "r", "r", "0", "1", "ri", "ri" } },
1099 { INDEX_op_brcond2_i32
, { "r", "r", "ri", "ri" } },
1101 #if TARGET_LONG_BITS == 32
1102 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1103 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1104 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1105 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1106 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1107 { INDEX_op_qemu_ld64
, { "r", "r", "L" } },
1109 { INDEX_op_qemu_st8
, { "cb", "L" } },
1110 { INDEX_op_qemu_st16
, { "L", "L" } },
1111 { INDEX_op_qemu_st32
, { "L", "L" } },
1112 { INDEX_op_qemu_st64
, { "L", "L", "L" } },
1114 { INDEX_op_qemu_ld8u
, { "r", "L", "L" } },
1115 { INDEX_op_qemu_ld8s
, { "r", "L", "L" } },
1116 { INDEX_op_qemu_ld16u
, { "r", "L", "L" } },
1117 { INDEX_op_qemu_ld16s
, { "r", "L", "L" } },
1118 { INDEX_op_qemu_ld32u
, { "r", "L", "L" } },
1119 { INDEX_op_qemu_ld64
, { "r", "r", "L", "L" } },
1121 { INDEX_op_qemu_st8
, { "cb", "L", "L" } },
1122 { INDEX_op_qemu_st16
, { "L", "L", "L" } },
1123 { INDEX_op_qemu_st32
, { "L", "L", "L" } },
1124 { INDEX_op_qemu_st64
, { "L", "L", "L", "L" } },
1129 static int tcg_target_callee_save_regs
[] = {
1130 /* TCG_REG_EBP, */ /* currently used for the global env, so no
1137 static inline void tcg_out_push(TCGContext
*s
, int reg
)
1139 tcg_out_opc(s
, 0x50 + reg
);
1142 static inline void tcg_out_pop(TCGContext
*s
, int reg
)
1144 tcg_out_opc(s
, 0x58 + reg
);
1147 /* Generate global QEMU prologue and epilogue code */
1148 void tcg_target_qemu_prologue(TCGContext
*s
)
1150 int i
, frame_size
, push_size
, stack_addend
;
1153 /* save all callee saved registers */
1154 for(i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
1155 tcg_out_push(s
, tcg_target_callee_save_regs
[i
]);
1157 /* reserve some stack space */
1158 push_size
= 4 + ARRAY_SIZE(tcg_target_callee_save_regs
) * 4;
1159 frame_size
= push_size
+ TCG_STATIC_CALL_ARGS_SIZE
;
1160 frame_size
= (frame_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
1161 ~(TCG_TARGET_STACK_ALIGN
- 1);
1162 stack_addend
= frame_size
- push_size
;
1163 tcg_out_addi(s
, TCG_REG_ESP
, -stack_addend
);
1165 tcg_out_modrm(s
, 0xff, 4, TCG_REG_EAX
); /* jmp *%eax */
1168 tb_ret_addr
= s
->code_ptr
;
1169 tcg_out_addi(s
, TCG_REG_ESP
, stack_addend
);
1170 for(i
= ARRAY_SIZE(tcg_target_callee_save_regs
) - 1; i
>= 0; i
--) {
1171 tcg_out_pop(s
, tcg_target_callee_save_regs
[i
]);
1173 tcg_out8(s
, 0xc3); /* ret */
1176 void tcg_target_init(TCGContext
*s
)
1179 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1182 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xff);
1183 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1184 (1 << TCG_REG_EAX
) |
1185 (1 << TCG_REG_EDX
) |
1186 (1 << TCG_REG_ECX
));
1188 tcg_regset_clear(s
->reserved_regs
);
1189 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_ESP
);
1191 tcg_add_target_add_op_defs(x86_op_defs
);