4 * Copyright (c) 2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Based on OpenPic implementations:
27 * - Intel GW80314 I/O compagnion chip developper's manual
28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
37 //#define DEBUG_OPENPIC
40 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...) do { } while (0)
44 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
46 #define USE_MPCxxx /* Intel model is broken, for now */
48 #if defined (USE_INTEL_GW80314)
49 /* Intel GW80314 I/O Companion chip */
59 #define VID (0x00000000)
61 #define OPENPIC_LITTLE_ENDIAN 1
62 #define OPENPIC_BIG_ENDIAN 0
64 #elif defined(USE_MPCxxx)
74 #define VID 0x03 /* MPIC version ID */
75 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_LITTLE_ENDIAN 1
83 #define OPENPIC_BIG_ENDIAN 0
86 #error "Please select which OpenPic implementation is to be emulated"
89 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
90 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN)
94 /* Interrupt definitions */
95 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
96 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */
97 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
99 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
100 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
102 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
103 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
106 #define BF_WIDTH(_bits_) \
107 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
109 static inline void set_bit (uint32_t *field
, int bit
)
111 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
114 static inline void reset_bit (uint32_t *field
, int bit
)
116 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
119 static inline int test_bit (uint32_t *field
, int bit
)
121 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
131 typedef struct IRQ_queue_t
{
132 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
137 typedef struct IRQ_src_t
{
138 uint32_t ipvp
; /* IRQ vector/priority register */
139 uint32_t ide
; /* IRQ destination register */
142 int pending
; /* TRUE if IRQ is pending */
152 #define IPVP_PRIORITY_MASK (0x1F << 16)
153 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
154 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
155 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
157 typedef struct IRQ_dst_t
{
158 uint32_t pctp
; /* CPU current task priority */
159 uint32_t pcsr
; /* CPU sensitivity register */
161 IRQ_queue_t servicing
;
162 CPUState
*env
; /* Needed if we did SMP */
168 /* Global registers */
169 uint32_t frep
; /* Feature reporting register */
170 uint32_t glbc
; /* Global configuration register */
171 uint32_t micr
; /* MPIC interrupt configuration register */
172 uint32_t veni
; /* Vendor identification register */
173 uint32_t spve
; /* Spurious vector register */
174 uint32_t tifr
; /* Timer frequency reporting register */
175 /* Source registers */
176 IRQ_src_t src
[MAX_IRQ
];
177 /* Local registers per output pin */
178 IRQ_dst_t dst
[MAX_CPU
];
180 /* Timer registers */
182 uint32_t ticc
; /* Global timer current count register */
183 uint32_t tibc
; /* Global timer base count register */
186 /* Doorbell registers */
187 uint32_t dar
; /* Doorbell activate register */
189 uint32_t dmr
; /* Doorbell messaging register */
190 } doorbells
[MAX_DBL
];
193 /* Mailbox registers */
195 uint32_t mbr
; /* Mailbox register */
196 } mailboxes
[MAX_MAILBOXES
];
200 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
202 set_bit(q
->queue
, n_IRQ
);
205 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
207 reset_bit(q
->queue
, n_IRQ
);
210 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
212 return test_bit(q
->queue
, n_IRQ
);
215 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
222 for (i
= 0; i
< MAX_IRQ
; i
++) {
223 if (IRQ_testbit(q
, i
)) {
224 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
225 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
226 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
228 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
233 q
->priority
= priority
;
236 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
246 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
252 dst
= &opp
->dst
[n_CPU
];
253 src
= &opp
->src
[n_IRQ
];
254 priority
= IPVP_PRIORITY(src
->ipvp
);
255 if (priority
<= dst
->pctp
) {
256 /* Too low priority */
259 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
263 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
264 IRQ_setbit(&dst
->raised
, n_IRQ
);
265 if (priority
> dst
->raised
.priority
) {
266 IRQ_get_next(opp
, &dst
->raised
);
267 DPRINTF("Raise CPU IRQ\n");
268 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
272 /* update pic state because registers for n_IRQ have changed value */
273 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
278 src
= &opp
->src
[n_IRQ
];
284 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
285 /* Interrupt source is disabled */
288 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
289 /* Priority set to zero */
292 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
293 /* IRQ already active */
296 if (src
->ide
== 0x00000000) {
301 if (!test_bit(&src
->ipvp
, IPVP_MODE
) ||
302 src
->ide
== (1 << src
->last_cpu
)) {
303 /* Directed delivery mode */
304 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
305 if (test_bit(&src
->ide
, i
))
306 IRQ_local_pipe(opp
, i
, n_IRQ
);
309 /* Distributed delivery mode */
310 /* XXX: incorrect code */
311 for (i
= src
->last_cpu
; i
< src
->last_cpu
; i
++) {
314 if (test_bit(&src
->ide
, i
)) {
315 IRQ_local_pipe(opp
, i
, n_IRQ
);
323 void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
325 openpic_t
*opp
= opaque
;
328 src
= &opp
->src
[n_IRQ
];
329 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
330 n_IRQ
, level
, src
->ipvp
);
331 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
332 /* level-sensitive irq */
333 src
->pending
= level
;
335 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
337 /* edge-sensitive irq */
341 openpic_update_irq(opp
, n_IRQ
);
344 static void openpic_reset (openpic_t
*opp
)
348 opp
->glbc
= 0x80000000;
349 /* Initialise controller registers */
350 opp
->frep
= ((EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
352 opp
->spve
= 0x000000FF;
353 opp
->tifr
= 0x003F7A00;
355 opp
->micr
= 0x00000000;
356 /* Initialise IRQ sources */
357 for (i
= 0; i
< MAX_IRQ
; i
++) {
358 opp
->src
[i
].ipvp
= 0xA0000000;
359 opp
->src
[i
].ide
= 0x00000000;
361 /* Initialise IRQ destinations */
362 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
363 opp
->dst
[i
].pctp
= 0x0000000F;
364 opp
->dst
[i
].pcsr
= 0x00000000;
365 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
366 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
368 /* Initialise timers */
369 for (i
= 0; i
< MAX_TMR
; i
++) {
370 opp
->timers
[i
].ticc
= 0x00000000;
371 opp
->timers
[i
].tibc
= 0x80000000;
373 /* Initialise doorbells */
375 opp
->dar
= 0x00000000;
376 for (i
= 0; i
< MAX_DBL
; i
++) {
377 opp
->doorbells
[i
].dmr
= 0x00000000;
380 /* Initialise mailboxes */
382 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
383 opp
->mailboxes
[i
].mbr
= 0x00000000;
386 /* Go out of RESET state */
387 opp
->glbc
= 0x00000000;
390 static inline uint32_t read_IRQreg (openpic_t
*opp
, int n_IRQ
, uint32_t reg
)
396 retval
= opp
->src
[n_IRQ
].ipvp
;
399 retval
= opp
->src
[n_IRQ
].ide
;
406 static inline void write_IRQreg (openpic_t
*opp
, int n_IRQ
,
407 uint32_t reg
, uint32_t val
)
413 /* NOTE: not fully accurate for special IRQs, but simple and
415 /* ACTIVITY bit is read-only */
416 opp
->src
[n_IRQ
].ipvp
=
417 (opp
->src
[n_IRQ
].ipvp
& 0x40000000) |
419 openpic_update_irq(opp
, n_IRQ
);
420 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
421 n_IRQ
, val
, opp
->src
[n_IRQ
].ipvp
);
424 tmp
= val
& 0xC0000000;
425 tmp
|= val
& ((1 << MAX_CPU
) - 1);
426 opp
->src
[n_IRQ
].ide
= tmp
;
427 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
432 #if 0 // Code provision for Intel model
434 static uint32_t read_doorbell_register (openpic_t
*opp
,
435 int n_dbl
, uint32_t offset
)
440 case DBL_IPVP_OFFSET
:
441 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
);
444 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
);
447 retval
= opp
->doorbells
[n_dbl
].dmr
;
454 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
455 uint32_t offset
, uint32_t value
)
458 case DBL_IVPR_OFFSET
:
459 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
, value
);
462 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
, value
);
465 opp
->doorbells
[n_dbl
].dmr
= value
;
472 static uint32_t read_mailbox_register (openpic_t
*opp
,
473 int n_mbx
, uint32_t offset
)
479 retval
= opp
->mailboxes
[n_mbx
].mbr
;
481 case MBX_IVPR_OFFSET
:
482 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
);
485 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
);
492 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
493 uint32_t address
, uint32_t value
)
497 opp
->mailboxes
[n_mbx
].mbr
= value
;
499 case MBX_IVPR_OFFSET
:
500 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
, value
);
503 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
, value
);
508 #endif /* 0 : Code provision for Intel model */
510 static void openpic_gbl_write (void *opaque
, uint32_t addr
, uint32_t val
)
512 openpic_t
*opp
= opaque
;
514 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
517 #if defined OPENPIC_SWAP
522 case 0x00: /* FREP */
524 case 0x20: /* GLBC */
525 if (val
& 0x80000000)
527 opp
->glbc
= val
& ~0x80000000;
529 case 0x80: /* VENI */
531 case 0x90: /* PINT */
532 /* XXX: Should be able to reset any CPU */
534 DPRINTF("Reset CPU IRQ\n");
535 // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
539 case 0xA0: /* IPI_IPVP */
545 idx
= (addr
- 0xA0) >> 4;
546 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
, val
);
550 case 0xE0: /* SPVE */
551 opp
->spve
= val
& 0x000000FF;
553 case 0xF0: /* TIFR */
561 static uint32_t openpic_gbl_read (void *opaque
, uint32_t addr
)
563 openpic_t
*opp
= opaque
;
566 DPRINTF("%s: addr %08x\n", __func__
, addr
);
572 case 0x00: /* FREP */
575 case 0x20: /* GLBC */
578 case 0x80: /* VENI */
581 case 0x90: /* PINT */
585 case 0xA0: /* IPI_IPVP */
591 idx
= (addr
- 0xA0) >> 4;
592 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
);
596 case 0xE0: /* SPVE */
599 case 0xF0: /* TIFR */
605 DPRINTF("%s: => %08x\n", __func__
, retval
);
606 #if defined OPENPIC_SWAP
607 retval
= bswap32(retval
);
613 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
615 openpic_t
*opp
= opaque
;
618 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
621 #if defined OPENPIC_SWAP
626 idx
= (addr
& 0xFFF0) >> 6;
629 case 0x00: /* TICC */
631 case 0x10: /* TIBC */
632 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
633 (val
& 0x80000000) == 0 &&
634 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
635 opp
->timers
[idx
].ticc
&= ~0x80000000;
636 opp
->timers
[idx
].tibc
= val
;
638 case 0x20: /* TIVP */
639 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
, val
);
641 case 0x30: /* TIDE */
642 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
, val
);
647 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
649 openpic_t
*opp
= opaque
;
653 DPRINTF("%s: addr %08x\n", __func__
, addr
);
659 idx
= (addr
& 0xFFF0) >> 6;
662 case 0x00: /* TICC */
663 retval
= opp
->timers
[idx
].ticc
;
665 case 0x10: /* TIBC */
666 retval
= opp
->timers
[idx
].tibc
;
668 case 0x20: /* TIPV */
669 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
);
671 case 0x30: /* TIDE */
672 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
);
675 DPRINTF("%s: => %08x\n", __func__
, retval
);
676 #if defined OPENPIC_SWAP
677 retval
= bswap32(retval
);
683 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
685 openpic_t
*opp
= opaque
;
688 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
691 #if defined OPENPIC_SWAP
694 addr
= addr
& 0xFFF0;
697 /* EXDE / IFEDE / IEEDE */
698 write_IRQreg(opp
, idx
, IRQ_IDE
, val
);
700 /* EXVP / IFEVP / IEEVP */
701 write_IRQreg(opp
, idx
, IRQ_IPVP
, val
);
705 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
707 openpic_t
*opp
= opaque
;
711 DPRINTF("%s: addr %08x\n", __func__
, addr
);
715 addr
= addr
& 0xFFF0;
718 /* EXDE / IFEDE / IEEDE */
719 retval
= read_IRQreg(opp
, idx
, IRQ_IDE
);
721 /* EXVP / IFEVP / IEEVP */
722 retval
= read_IRQreg(opp
, idx
, IRQ_IPVP
);
724 DPRINTF("%s: => %08x\n", __func__
, retval
);
725 #if defined OPENPIC_SWAP
726 retval
= tswap32(retval
);
732 static void openpic_cpu_write (void *opaque
, uint32_t addr
, uint32_t val
)
734 openpic_t
*opp
= opaque
;
739 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
742 #if defined OPENPIC_SWAP
747 dst
= &opp
->dst
[idx
];
751 case 0x40: /* PIPD */
755 idx
= (addr
- 0x40) >> 4;
756 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
, val
);
757 openpic_set_irq(opp
, IRQ_IPI0
+ idx
, 1);
758 openpic_set_irq(opp
, IRQ_IPI0
+ idx
, 0);
761 case 0x80: /* PCTP */
762 dst
->pctp
= val
& 0x0000000F;
764 case 0x90: /* WHOAMI */
765 /* Read-only register */
767 case 0xA0: /* PIAC */
768 /* Read-only register */
770 case 0xB0: /* PEOI */
772 n_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
773 IRQ_resetbit(&dst
->servicing
, n_IRQ
);
774 dst
->servicing
.next
= -1;
775 src
= &opp
->src
[n_IRQ
];
776 /* Set up next servicing IRQ */
777 IRQ_get_next(opp
, &dst
->servicing
);
778 /* Check queued interrupts. */
779 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
781 src
= &opp
->src
[n_IRQ
];
782 if (IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
) {
783 DPRINTF("Raise CPU IRQ\n");
784 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
793 static uint32_t openpic_cpu_read (void *opaque
, uint32_t addr
)
795 openpic_t
*opp
= opaque
;
801 DPRINTF("%s: addr %08x\n", __func__
, addr
);
807 dst
= &opp
->dst
[idx
];
810 case 0x80: /* PCTP */
813 case 0x90: /* WHOAMI */
816 case 0xA0: /* PIAC */
817 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
818 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
820 /* No more interrupt pending */
823 src
= &opp
->src
[n_IRQ
];
824 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
825 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
826 /* - Spurious level-sensitive IRQ
827 * - Priorities has been changed
828 * and the pending IRQ isn't allowed anymore
830 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
831 retval
= IPVP_VECTOR(opp
->spve
);
833 /* IRQ enter servicing state */
834 IRQ_setbit(&dst
->servicing
, n_IRQ
);
835 retval
= IPVP_VECTOR(src
->ipvp
);
837 IRQ_resetbit(&dst
->raised
, n_IRQ
);
838 dst
->raised
.next
= -1;
839 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
840 /* edge-sensitive IRQ */
841 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
846 case 0xB0: /* PEOI */
852 idx
= (addr
- 0x40) >> 4;
853 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
);
859 DPRINTF("%s: => %08x\n", __func__
, retval
);
860 #if defined OPENPIC_SWAP
861 retval
= bswap32(retval
);
867 static void openpic_buggy_write (void *opaque
,
868 target_phys_addr_t addr
, uint32_t val
)
870 printf("Invalid OPENPIC write access !\n");
873 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
875 printf("Invalid OPENPIC read access !\n");
880 static void openpic_writel (void *opaque
,
881 target_phys_addr_t addr
, uint32_t val
)
883 openpic_t
*opp
= opaque
;
886 DPRINTF("%s: offset %08x val: %08x\n", __func__
, (int)addr
, val
);
888 /* Global registers */
889 openpic_gbl_write(opp
, addr
, val
);
890 } else if (addr
< 0x10000) {
891 /* Timers registers */
892 openpic_timer_write(opp
, addr
, val
);
893 } else if (addr
< 0x20000) {
894 /* Source registers */
895 openpic_src_write(opp
, addr
, val
);
898 openpic_cpu_write(opp
, addr
, val
);
902 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
904 openpic_t
*opp
= opaque
;
908 DPRINTF("%s: offset %08x\n", __func__
, (int)addr
);
910 /* Global registers */
911 retval
= openpic_gbl_read(opp
, addr
);
912 } else if (addr
< 0x10000) {
913 /* Timers registers */
914 retval
= openpic_timer_read(opp
, addr
);
915 } else if (addr
< 0x20000) {
916 /* Source registers */
917 retval
= openpic_src_read(opp
, addr
);
920 retval
= openpic_cpu_read(opp
, addr
);
926 static CPUWriteMemoryFunc
*openpic_write
[] = {
927 &openpic_buggy_write
,
928 &openpic_buggy_write
,
932 static CPUReadMemoryFunc
*openpic_read
[] = {
938 static void openpic_map(PCIDevice
*pci_dev
, int region_num
,
939 uint32_t addr
, uint32_t size
, int type
)
943 DPRINTF("Map OpenPIC\n");
944 opp
= (openpic_t
*)pci_dev
;
945 /* Global registers */
946 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
947 addr
+ 0x1000, addr
+ 0x1000 + 0x100);
948 /* Timer registers */
949 DPRINTF("Register OPENPIC timer %08x => %08x\n",
950 addr
+ 0x1100, addr
+ 0x1100 + 0x40 * MAX_TMR
);
951 /* Interrupt source registers */
952 DPRINTF("Register OPENPIC src %08x => %08x\n",
953 addr
+ 0x10000, addr
+ 0x10000 + 0x20 * (EXT_IRQ
+ 2));
954 /* Per CPU registers */
955 DPRINTF("Register OPENPIC dst %08x => %08x\n",
956 addr
+ 0x20000, addr
+ 0x20000 + 0x1000 * MAX_CPU
);
957 cpu_register_physical_memory(addr
, 0x40000, opp
->mem_index
);
958 #if 0 // Don't implement ISU for now
959 opp_io_memory
= cpu_register_io_memory(0, openpic_src_read
,
961 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
966 openpic_t
*openpic_init (PCIBus
*bus
, int *pmem_index
, int nb_cpus
)
972 /* XXX: for now, only one CPU is supported */
976 opp
= (openpic_t
*)pci_register_device(bus
, "OpenPIC", sizeof(openpic_t
),
980 pci_conf
= opp
->pci_dev
.config
;
981 pci_conf
[0x00] = 0x14; // IBM MPIC2
982 pci_conf
[0x01] = 0x10;
983 pci_conf
[0x02] = 0xFF;
984 pci_conf
[0x03] = 0xFF;
985 pci_conf
[0x0a] = 0x80; // PIC
986 pci_conf
[0x0b] = 0x08;
987 pci_conf
[0x0e] = 0x00; // header_type
988 pci_conf
[0x3d] = 0x00; // no interrupt pin
990 /* Register I/O spaces */
991 pci_register_io_region((PCIDevice
*)opp
, 0, 0x40000,
992 PCI_ADDRESS_SPACE_MEM
, &openpic_map
);
994 opp
= qemu_mallocz(sizeof(openpic_t
));
997 opp
->mem_index
= cpu_register_io_memory(0, openpic_read
,
1000 // isu_base &= 0xFFFC0000;
1001 opp
->nb_cpus
= nb_cpus
;
1003 for (i
= 0; i
< EXT_IRQ
; i
++) {
1004 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1006 for (; i
< IRQ_TIM0
; i
++) {
1007 opp
->src
[i
].type
= IRQ_SPECIAL
;
1014 for (; i
< m
; i
++) {
1015 opp
->src
[i
].type
= IRQ_TIMER
;
1017 for (; i
< MAX_IRQ
; i
++) {
1018 opp
->src
[i
].type
= IRQ_INTERNAL
;
1022 *pmem_index
= opp
->mem_index
;