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Add safety net against potential infinite loop
[qemu/mini2440.git] / tcg / ppc64 / tcg-target.c
blob4943514b02f664652d774bc55e340b51375dea9e
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_PHYS_ADDR_BITS == 32
32 #define LD_ADDEND LWZ
33 #else
34 #define LD_ADDEND LD
35 #endif
36
37 #if TARGET_LONG_BITS == 32
38 #define LD_ADDR LWZU
39 #define CMP_L 0
40 #else
41 #define LD_ADDR LDU
42 #define CMP_L (1<<21)
43 #endif
44
45 #ifndef NDEBUG
46 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
47 "r0",
48 "r1",
49 "rp",
50 "r3",
51 "r4",
52 "r5",
53 "r6",
54 "r7",
55 "r8",
56 "r9",
57 "r10",
58 "r11",
59 "r12",
60 "r13",
61 "r14",
62 "r15",
63 "r16",
64 "r17",
65 "r18",
66 "r19",
67 "r20",
68 "r21",
69 "r22",
70 "r23",
71 "r24",
72 "r25",
73 "r26",
74 "r27",
75 "r28",
76 "r29",
77 "r30",
78 "r31"
79 };
80 #endif
81
82 static const int tcg_target_reg_alloc_order[] = {
83 TCG_REG_R14,
84 TCG_REG_R15,
85 TCG_REG_R16,
86 TCG_REG_R17,
87 TCG_REG_R18,
88 TCG_REG_R19,
89 TCG_REG_R20,
90 TCG_REG_R21,
91 TCG_REG_R22,
92 TCG_REG_R23,
93 TCG_REG_R28,
94 TCG_REG_R29,
95 TCG_REG_R30,
96 TCG_REG_R31,
97 TCG_REG_R3,
98 TCG_REG_R4,
99 TCG_REG_R5,
100 TCG_REG_R6,
101 TCG_REG_R7,
102 TCG_REG_R8,
103 TCG_REG_R9,
104 TCG_REG_R10,
105 TCG_REG_R11,
106 TCG_REG_R12,
107 TCG_REG_R13,
108 TCG_REG_R0,
109 TCG_REG_R1,
110 TCG_REG_R2,
111 TCG_REG_R24,
112 TCG_REG_R25,
113 TCG_REG_R26,
114 TCG_REG_R27
115 };
116
117 static const int tcg_target_call_iarg_regs[] = {
118 TCG_REG_R3,
119 TCG_REG_R4,
120 TCG_REG_R5,
121 TCG_REG_R6,
122 TCG_REG_R7,
123 TCG_REG_R8,
124 TCG_REG_R9,
125 TCG_REG_R10
126 };
127
128 static const int tcg_target_call_oarg_regs[2] = {
129 TCG_REG_R3
130 };
131
132 static const int tcg_target_callee_save_regs[] = {
133 TCG_REG_R14,
134 TCG_REG_R15,
135 TCG_REG_R16,
136 TCG_REG_R17,
137 TCG_REG_R18,
138 TCG_REG_R19,
139 TCG_REG_R20,
140 TCG_REG_R21,
141 TCG_REG_R22,
142 TCG_REG_R23,
143 TCG_REG_R28,
144 TCG_REG_R29,
145 TCG_REG_R30,
146 TCG_REG_R31
147 };
148
149 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
150 {
151 tcg_target_long disp;
152
153 disp = target - (tcg_target_long) pc;
154 if ((disp << 38) >> 38 != disp)
155 tcg_abort ();
156
157 return disp & 0x3fffffc;
158 }
159
160 static void reloc_pc24 (void *pc, tcg_target_long target)
161 {
162 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
163 | reloc_pc24_val (pc, target);
164 }
165
166 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
167 {
168 tcg_target_long disp;
169
170 disp = target - (tcg_target_long) pc;
171 if (disp != (int16_t) disp)
172 tcg_abort ();
173
174 return disp & 0xfffc;
175 }
176
177 static void reloc_pc14 (void *pc, tcg_target_long target)
178 {
179 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
180 | reloc_pc14_val (pc, target);
181 }
182
183 static void patch_reloc (uint8_t *code_ptr, int type,
184 tcg_target_long value, tcg_target_long addend)
185 {
186 value += addend;
187 switch (type) {
188 case R_PPC_REL14:
189 reloc_pc14 (code_ptr, value);
190 break;
191 case R_PPC_REL24:
192 reloc_pc24 (code_ptr, value);
193 break;
194 default:
195 tcg_abort ();
196 }
197 }
198
199 /* maximum number of register used for input function arguments */
200 static int tcg_target_get_call_iarg_regs_count (int flags)
201 {
202 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
203 }
204
205 /* parse target specific constraints */
206 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
207 {
208 const char *ct_str;
209
210 ct_str = *pct_str;
211 switch (ct_str[0]) {
212 case 'A': case 'B': case 'C': case 'D':
213 ct->ct |= TCG_CT_REG;
214 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
215 break;
216 case 'r':
217 ct->ct |= TCG_CT_REG;
218 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
219 break;
220 case 'L': /* qemu_ld constraint */
221 ct->ct |= TCG_CT_REG;
222 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
223 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
224 #ifdef CONFIG_SOFTMMU
225 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
226 #endif
227 break;
228 case 'S': /* qemu_st constraint */
229 ct->ct |= TCG_CT_REG;
230 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
231 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
232 #ifdef CONFIG_SOFTMMU
233 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
234 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
235 #endif
236 break;
237 case 'Z':
238 ct->ct |= TCG_CT_CONST_U32;
239 break;
240 default:
241 return -1;
242 }
243 ct_str++;
244 *pct_str = ct_str;
245 return 0;
246 }
247
248 /* test if a constant matches the constraint */
249 static int tcg_target_const_match (tcg_target_long val,
250 const TCGArgConstraint *arg_ct)
251 {
252 int ct;
253
254 ct = arg_ct->ct;
255 if (ct & TCG_CT_CONST)
256 return 1;
257 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
258 return 1;
259 return 0;
260 }
261
262 #define OPCD(opc) ((opc)<<26)
263 #define XO19(opc) (OPCD(19)|((opc)<<1))
264 #define XO30(opc) (OPCD(30)|((opc)<<2))
265 #define XO31(opc) (OPCD(31)|((opc)<<1))
266 #define XO58(opc) (OPCD(58)|(opc))
267 #define XO62(opc) (OPCD(62)|(opc))
268
269 #define B OPCD( 18)
270 #define BC OPCD( 16)
271 #define LBZ OPCD( 34)
272 #define LHZ OPCD( 40)
273 #define LHA OPCD( 42)
274 #define LWZ OPCD( 32)
275 #define STB OPCD( 38)
276 #define STH OPCD( 44)
277 #define STW OPCD( 36)
278
279 #define STD XO62( 0)
280 #define STDU XO62( 1)
281 #define STDX XO31(149)
282
283 #define LD XO58( 0)
284 #define LDX XO31( 21)
285 #define LDU XO58( 1)
286 #define LWA XO58( 2)
287 #define LWAX XO31(341)
288
289 #define ADDI OPCD( 14)
290 #define ADDIS OPCD( 15)
291 #define ORI OPCD( 24)
292 #define ORIS OPCD( 25)
293 #define XORI OPCD( 26)
294 #define XORIS OPCD( 27)
295 #define ANDI OPCD( 28)
296 #define ANDIS OPCD( 29)
297 #define MULLI OPCD( 7)
298 #define CMPLI OPCD( 10)
299 #define CMPI OPCD( 11)
300
301 #define LWZU OPCD( 33)
302 #define STWU OPCD( 37)
303
304 #define RLWINM OPCD( 21)
305
306 #define RLDICL XO30( 0)
307 #define RLDICR XO30( 1)
308 #define RLDIMI XO30( 3)
309
310 #define BCLR XO19( 16)
311 #define BCCTR XO19(528)
312 #define CRAND XO19(257)
313 #define CRANDC XO19(129)
314 #define CRNAND XO19(225)
315 #define CROR XO19(449)
316
317 #define EXTSB XO31(954)
318 #define EXTSH XO31(922)
319 #define EXTSW XO31(986)
320 #define ADD XO31(266)
321 #define ADDE XO31(138)
322 #define ADDC XO31( 10)
323 #define AND XO31( 28)
324 #define SUBF XO31( 40)
325 #define SUBFC XO31( 8)
326 #define SUBFE XO31(136)
327 #define OR XO31(444)
328 #define XOR XO31(316)
329 #define MULLW XO31(235)
330 #define MULHWU XO31( 11)
331 #define DIVW XO31(491)
332 #define DIVWU XO31(459)
333 #define CMP XO31( 0)
334 #define CMPL XO31( 32)
335 #define LHBRX XO31(790)
336 #define LWBRX XO31(534)
337 #define STHBRX XO31(918)
338 #define STWBRX XO31(662)
339 #define MFSPR XO31(339)
340 #define MTSPR XO31(467)
341 #define SRAWI XO31(824)
342 #define NEG XO31(104)
343
344 #define MULLD XO31(233)
345 #define MULHD XO31( 73)
346 #define MULHDU XO31( 9)
347 #define DIVD XO31(489)
348 #define DIVDU XO31(457)
349
350 #define LBZX XO31( 87)
351 #define LHZX XO31(276)
352 #define LHAX XO31(343)
353 #define LWZX XO31( 23)
354 #define STBX XO31(215)
355 #define STHX XO31(407)
356 #define STWX XO31(151)
357
358 #define SPR(a,b) ((((a)<<5)|(b))<<11)
359 #define LR SPR(8, 0)
360 #define CTR SPR(9, 0)
361
362 #define SLW XO31( 24)
363 #define SRW XO31(536)
364 #define SRAW XO31(792)
365
366 #define SLD XO31( 27)
367 #define SRD XO31(539)
368 #define SRAD XO31(794)
369 #define SRADI XO31(413<<1)
370
371 #define LMW OPCD( 46)
372 #define STMW OPCD( 47)
373
374 #define TW XO31( 4)
375 #define TRAP (TW | TO (31))
376
377 #define RT(r) ((r)<<21)
378 #define RS(r) ((r)<<21)
379 #define RA(r) ((r)<<16)
380 #define RB(r) ((r)<<11)
381 #define TO(t) ((t)<<21)
382 #define SH(s) ((s)<<11)
383 #define MB(b) ((b)<<6)
384 #define ME(e) ((e)<<1)
385 #define BO(o) ((o)<<21)
386 #define MB64(b) ((b)<<5)
387
388 #define LK 1
389
390 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
391 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
392
393 #define BF(n) ((n)<<23)
394 #define BI(n, c) (((c)+((n)*4))<<16)
395 #define BT(n, c) (((c)+((n)*4))<<21)
396 #define BA(n, c) (((c)+((n)*4))<<16)
397 #define BB(n, c) (((c)+((n)*4))<<11)
398
399 #define BO_COND_TRUE BO (12)
400 #define BO_COND_FALSE BO ( 4)
401 #define BO_ALWAYS BO (20)
402
403 enum {
404 CR_LT,
405 CR_GT,
406 CR_EQ,
407 CR_SO
408 };
409
410 static const uint32_t tcg_to_bc[10] = {
411 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
412 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
413 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
414 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
415 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
416 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
417 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
418 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
419 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
420 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
421 };
422
423 static void tcg_out_mov (TCGContext *s, int ret, int arg)
424 {
425 tcg_out32 (s, OR | SAB (arg, ret, arg));
426 }
427
428 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
429 {
430 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
431 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
432 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
433 }
434
435 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
436 {
437 if (arg == (int16_t) arg)
438 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
439 else {
440 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
441 if (arg & 0xffff)
442 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
443 }
444 }
445
446 static void tcg_out_movi (TCGContext *s, TCGType type,
447 int ret, tcg_target_long arg)
448 {
449 int32_t arg32 = arg;
450
451 if (type == TCG_TYPE_I32 || arg == arg32) {
452 tcg_out_movi32 (s, ret, arg32);
453 }
454 else {
455 if ((uint64_t) arg >> 32) {
456 uint16_t h16 = arg >> 16;
457 uint16_t l16 = arg;
458
459 tcg_out_movi32 (s, ret, arg >> 32);
460 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
461 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
462 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
463 }
464 else {
465 tcg_out_movi32 (s, ret, arg32);
466 if (arg32 < 0)
467 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
468 }
469 }
470 }
471
472 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
473 {
474 int reg;
475
476 if (const_arg) {
477 reg = 2;
478 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
479 }
480 else reg = arg;
481
482 tcg_out32 (s, LD | RT (0) | RA (reg));
483 tcg_out32 (s, MTSPR | RA (0) | CTR);
484 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
485 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
486 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
487 }
488
489 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
490 int offset, int op1, int op2)
491 {
492 if (offset == (int16_t) offset)
493 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
494 else {
495 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
496 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
497 }
498 }
499
500 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
501 {
502 tcg_target_long disp;
503
504 disp = target - (tcg_target_long) s->code_ptr;
505 if ((disp << 38) >> 38 == disp)
506 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
507 else {
508 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
509 tcg_out32 (s, MTSPR | RS (0) | CTR);
510 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
511 }
512 }
513
514 #if defined (CONFIG_SOFTMMU)
515
516 #include "../../softmmu_defs.h"
517
518 static void *qemu_ld_helpers[4] = {
519 __ldb_mmu,
520 __ldw_mmu,
521 __ldl_mmu,
522 __ldq_mmu,
523 };
524
525 static void *qemu_st_helpers[4] = {
526 __stb_mmu,
527 __stw_mmu,
528 __stl_mmu,
529 __stq_mmu,
530 };
531
532 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
533 int addr_reg, int s_bits, int offset)
534 {
535 #if TARGET_LONG_BITS == 32
536 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
537
538 tcg_out32 (s, (RLWINM
539 | RA (r0)
540 | RS (addr_reg)
541 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
542 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
543 | ME (31 - CPU_TLB_ENTRY_BITS)
544 )
545 );
546 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
547 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
548 tcg_out32 (s, (RLWINM
549 | RA (r2)
550 | RS (addr_reg)
551 | SH (0)
552 | MB ((32 - s_bits) & 31)
553 | ME (31 - TARGET_PAGE_BITS)
554 )
555 );
556 #else
557 tcg_out_rld (s, RLDICL, r0, addr_reg,
558 64 - TARGET_PAGE_BITS,
559 64 - CPU_TLB_BITS);
560 tcg_out_rld (s, RLDICR, r0, r0,
561 CPU_TLB_ENTRY_BITS,
562 63 - CPU_TLB_ENTRY_BITS);
563
564 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
565 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
566
567 if (!s_bits) {
568 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
569 }
570 else {
571 tcg_out_rld (s, RLDICL, r2, addr_reg,
572 64 - TARGET_PAGE_BITS,
573 TARGET_PAGE_BITS - s_bits);
574 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
575 }
576 #endif
577 }
578 #endif
579
580 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
581 {
582 int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap;
583 #ifdef CONFIG_SOFTMMU
584 int r2;
585 void *label1_ptr, *label2_ptr;
586 #endif
587
588 data_reg = *args++;
589 addr_reg = *args++;
590 mem_index = *args;
591 s_bits = opc & 3;
592
593 #ifdef CONFIG_SOFTMMU
594 r0 = 3;
595 r1 = 4;
596 r2 = 0;
597
598 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
599 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
600
601 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
602
603 label1_ptr = s->code_ptr;
604 #ifdef FAST_PATH
605 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
606 #endif
607
608 /* slow path */
609 tcg_out_mov (s, 3, addr_reg);
610 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
611
612 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
613
614 switch (opc) {
615 case 0|4:
616 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
617 break;
618 case 1|4:
619 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
620 break;
621 case 2|4:
622 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
623 break;
624 case 0:
625 case 1:
626 case 2:
627 case 3:
628 if (data_reg != 3)
629 tcg_out_mov (s, data_reg, 3);
630 break;
631 }
632 label2_ptr = s->code_ptr;
633 tcg_out32 (s, B);
634
635 /* label1: fast path */
636 #ifdef FAST_PATH
637 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
638 #endif
639
640 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
641 tcg_out32 (s, (LD_ADDEND
642 | RT (r0)
643 | RA (r0)
644 | (offsetof (CPUTLBEntry, addend)
645 - offsetof (CPUTLBEntry, addr_read))
646 ));
647 /* r0 = env->tlb_table[mem_index][index].addend */
648 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
649 /* r0 = env->tlb_table[mem_index][index].addend + addr */
650
651 #else /* !CONFIG_SOFTMMU */
652 #if TARGET_LONG_BITS == 32
653 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
654 #endif
655 r0 = addr_reg;
656 r1 = 3;
657 #endif
658
659 #ifdef TARGET_WORDS_BIGENDIAN
660 bswap = 0;
661 #else
662 bswap = 1;
663 #endif
664 switch (opc) {
665 default:
666 case 0:
667 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
668 break;
669 case 0|4:
670 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
671 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
672 break;
673 case 1:
674 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
675 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
676 break;
677 case 1|4:
678 if (bswap) {
679 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
680 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
681 }
682 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
683 break;
684 case 2:
685 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
686 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
687 break;
688 case 2|4:
689 if (bswap) {
690 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
691 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
692 }
693 else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
694 break;
695 case 3:
696 if (bswap) {
697 tcg_out_movi32 (s, 0, 4);
698 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
699 tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
700 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
701 }
702 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
703 break;
704 }
705
706 #ifdef CONFIG_SOFTMMU
707 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
708 #endif
709 }
710
711 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
712 {
713 int addr_reg, r0, r1, data_reg, mem_index, bswap;
714 #ifdef CONFIG_SOFTMMU
715 int r2;
716 void *label1_ptr, *label2_ptr;
717 #endif
718
719 data_reg = *args++;
720 addr_reg = *args++;
721 mem_index = *args;
722
723 #ifdef CONFIG_SOFTMMU
724 r0 = 3;
725 r1 = 4;
726 r2 = 0;
727
728 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
729 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
730
731 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
732
733 label1_ptr = s->code_ptr;
734 #ifdef FAST_PATH
735 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
736 #endif
737
738 /* slow path */
739 tcg_out_mov (s, 3, addr_reg);
740 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
741 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
742
743 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
744
745 label2_ptr = s->code_ptr;
746 tcg_out32 (s, B);
747
748 /* label1: fast path */
749 #ifdef FAST_PATH
750 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
751 #endif
752
753 tcg_out32 (s, (LD_ADDEND
754 | RT (r0)
755 | RA (r0)
756 | (offsetof (CPUTLBEntry, addend)
757 - offsetof (CPUTLBEntry, addr_write))
758 ));
759 /* r0 = env->tlb_table[mem_index][index].addend */
760 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
761 /* r0 = env->tlb_table[mem_index][index].addend + addr */
762
763 #else /* !CONFIG_SOFTMMU */
764 #if TARGET_LONG_BITS == 32
765 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
766 #endif
767 r1 = 3;
768 r0 = addr_reg;
769 #endif
770
771 #ifdef TARGET_WORDS_BIGENDIAN
772 bswap = 0;
773 #else
774 bswap = 1;
775 #endif
776 switch (opc) {
777 case 0:
778 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
779 break;
780 case 1:
781 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
782 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
783 break;
784 case 2:
785 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
786 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
787 break;
788 case 3:
789 if (bswap) {
790 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
791 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
792 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
793 tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r1));
794 }
795 else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
796 break;
797 }
798
799 #ifdef CONFIG_SOFTMMU
800 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
801 #endif
802 }
803
804 void tcg_target_qemu_prologue (TCGContext *s)
805 {
806 int i, frame_size;
807 uint64_t addr;
808
809 frame_size = 0
810 + 8 /* back chain */
811 + 8 /* CR */
812 + 8 /* LR */
813 + 8 /* compiler doubleword */
814 + 8 /* link editor doubleword */
815 + 8 /* TOC save area */
816 + TCG_STATIC_CALL_ARGS_SIZE
817 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
818 ;
819 frame_size = (frame_size + 15) & ~15;
820
821 /* First emit adhoc function descriptor */
822 addr = (uint64_t) s->code_ptr + 24;
823 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
824 s->code_ptr += 16; /* skip TOC and environment pointer */
825
826 /* Prologue */
827 tcg_out32 (s, MFSPR | RT (0) | LR);
828 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
829 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
830 tcg_out32 (s, (STD
831 | RS (tcg_target_callee_save_regs[i])
832 | RA (1)
833 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
834 )
835 );
836 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
837
838 tcg_out32 (s, MTSPR | RS (3) | CTR);
839 tcg_out32 (s, BCCTR | BO_ALWAYS);
840
841 /* Epilogue */
842 tb_ret_addr = s->code_ptr;
843
844 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
845 tcg_out32 (s, (LD
846 | RT (tcg_target_callee_save_regs[i])
847 | RA (1)
848 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
849 )
850 );
851 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
852 tcg_out32 (s, MTSPR | RS (0) | LR);
853 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
854 tcg_out32 (s, BCLR | BO_ALWAYS);
855 }
856
857 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
858 tcg_target_long arg2)
859 {
860 if (type == TCG_TYPE_I32)
861 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
862 else
863 tcg_out_ldst (s, ret, arg1, arg2, LD, LDX);
864 }
865
866 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
867 tcg_target_long arg2)
868 {
869 if (type == TCG_TYPE_I32)
870 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
871 else
872 tcg_out_ldst (s, arg, arg1, arg2, STD, STDX);
873 }
874
875 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
876 {
877 if (!si && rt == ra)
878 return;
879
880 if (si == (int16_t) si)
881 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
882 else {
883 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
884 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
885 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
886 }
887 }
888
889 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
890 {
891 /* XXX: suboptimal */
892 if (si == (int16_t) si
893 || (((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0)
894 ppc_addi32 (s, rt, ra, si);
895 else {
896 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
897 tcg_out32 (s, ADD | RT (rt) | RA (ra));
898 }
899 }
900
901 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
902 {
903 ppc_addi64 (s, reg, reg, val);
904 }
905
906 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
907 int const_arg2, int cr, int arch64)
908 {
909 int imm;
910 uint32_t op;
911
912 switch (cond) {
913 case TCG_COND_EQ:
914 case TCG_COND_NE:
915 if (const_arg2) {
916 if ((int16_t) arg2 == arg2) {
917 op = CMPI;
918 imm = 1;
919 break;
920 }
921 else if ((uint16_t) arg2 == arg2) {
922 op = CMPLI;
923 imm = 1;
924 break;
925 }
926 }
927 op = CMPL;
928 imm = 0;
929 break;
930
931 case TCG_COND_LT:
932 case TCG_COND_GE:
933 case TCG_COND_LE:
934 case TCG_COND_GT:
935 if (const_arg2) {
936 if ((int16_t) arg2 == arg2) {
937 op = CMPI;
938 imm = 1;
939 break;
940 }
941 }
942 op = CMP;
943 imm = 0;
944 break;
945
946 case TCG_COND_LTU:
947 case TCG_COND_GEU:
948 case TCG_COND_LEU:
949 case TCG_COND_GTU:
950 if (const_arg2) {
951 if ((uint16_t) arg2 == arg2) {
952 op = CMPLI;
953 imm = 1;
954 break;
955 }
956 }
957 op = CMPL;
958 imm = 0;
959 break;
960
961 default:
962 tcg_abort ();
963 }
964 op |= BF (cr) | (arch64 << 21);
965
966 if (imm)
967 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
968 else {
969 if (const_arg2) {
970 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
971 tcg_out32 (s, op | RA (arg1) | RB (0));
972 }
973 else
974 tcg_out32 (s, op | RA (arg1) | RB (arg2));
975 }
976
977 }
978
979 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
980 {
981 TCGLabel *l = &s->labels[label_index];
982
983 if (l->has_value)
984 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
985 else {
986 uint16_t val = *(uint16_t *) &s->code_ptr[2];
987
988 /* Thanks to Andrzej Zaborowski */
989 tcg_out32 (s, bc | (val & 0xfffc));
990 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
991 }
992 }
993
994 static void tcg_out_brcond (TCGContext *s, int cond,
995 TCGArg arg1, TCGArg arg2, int const_arg2,
996 int label_index, int arch64)
997 {
998 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
999 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1000 }
1001
1002 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1003 {
1004 TCGContext s;
1005 unsigned long patch_size;
1006
1007 s.code_ptr = (uint8_t *) jmp_addr;
1008 tcg_out_b (&s, 0, addr);
1009 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1010 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1011 }
1012
1013 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
1014 const int *const_args)
1015 {
1016 int c;
1017
1018 switch (opc) {
1019 case INDEX_op_exit_tb:
1020 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1021 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1022 break;
1023 case INDEX_op_goto_tb:
1024 if (s->tb_jmp_offset) {
1025 /* direct jump method */
1026
1027 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1028 s->code_ptr += 28;
1029 }
1030 else {
1031 tcg_abort ();
1032 }
1033 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1034 break;
1035 case INDEX_op_br:
1036 {
1037 TCGLabel *l = &s->labels[args[0]];
1038
1039 if (l->has_value) {
1040 tcg_out_b (s, 0, l->u.value);
1041 }
1042 else {
1043 uint32_t val = *(uint32_t *) s->code_ptr;
1044
1045 /* Thanks to Andrzej Zaborowski */
1046 tcg_out32 (s, B | (val & 0x3fffffc));
1047 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1048 }
1049 }
1050 break;
1051 case INDEX_op_call:
1052 tcg_out_call (s, args[0], const_args[0]);
1053 break;
1054 case INDEX_op_jmp:
1055 if (const_args[0]) {
1056 tcg_out_b (s, 0, args[0]);
1057 }
1058 else {
1059 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1060 tcg_out32 (s, BCCTR | BO_ALWAYS);
1061 }
1062 break;
1063 case INDEX_op_movi_i32:
1064 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1065 break;
1066 case INDEX_op_movi_i64:
1067 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1068 break;
1069 case INDEX_op_ld8u_i32:
1070 case INDEX_op_ld8u_i64:
1071 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1072 break;
1073 case INDEX_op_ld8s_i32:
1074 case INDEX_op_ld8s_i64:
1075 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1076 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1077 break;
1078 case INDEX_op_ld16u_i32:
1079 case INDEX_op_ld16u_i64:
1080 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1081 break;
1082 case INDEX_op_ld16s_i32:
1083 case INDEX_op_ld16s_i64:
1084 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1085 break;
1086 case INDEX_op_ld_i32:
1087 case INDEX_op_ld32u_i64:
1088 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1089 break;
1090 case INDEX_op_ld32s_i64:
1091 tcg_out_ldst (s, args[0], args[1], args[2], LWA, LWAX);
1092 break;
1093 case INDEX_op_ld_i64:
1094 tcg_out_ldst (s, args[0], args[1], args[2], LD, LDX);
1095 break;
1096 case INDEX_op_st8_i32:
1097 case INDEX_op_st8_i64:
1098 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1099 break;
1100 case INDEX_op_st16_i32:
1101 case INDEX_op_st16_i64:
1102 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1103 break;
1104 case INDEX_op_st_i32:
1105 case INDEX_op_st32_i64:
1106 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1107 break;
1108 case INDEX_op_st_i64:
1109 tcg_out_ldst (s, args[0], args[1], args[2], STD, STDX);
1110 break;
1111
1112 case INDEX_op_add_i32:
1113 if (const_args[2])
1114 ppc_addi32 (s, args[0], args[1], args[2]);
1115 else
1116 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1117 break;
1118 case INDEX_op_sub_i32:
1119 if (const_args[2])
1120 ppc_addi32 (s, args[0], args[1], -args[2]);
1121 else
1122 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1123 break;
1124
1125 case INDEX_op_and_i64:
1126 case INDEX_op_and_i32:
1127 if (const_args[2]) {
1128 if ((args[2] & 0xffff) == args[2])
1129 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1130 else if ((args[2] & 0xffff0000) == args[2])
1131 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1132 | ((args[2] >> 16) & 0xffff));
1133 else {
1134 tcg_out_movi (s, (opc == INDEX_op_and_i32
1135 ? TCG_TYPE_I32
1136 : TCG_TYPE_I64),
1137 0, args[2]);
1138 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1139 }
1140 }
1141 else
1142 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1143 break;
1144 case INDEX_op_or_i64:
1145 case INDEX_op_or_i32:
1146 if (const_args[2]) {
1147 if (args[2] & 0xffff) {
1148 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1149 | (args[2] & 0xffff));
1150 if (args[2] >> 16)
1151 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1152 | ((args[2] >> 16) & 0xffff));
1153 }
1154 else {
1155 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1156 | ((args[2] >> 16) & 0xffff));
1157 }
1158 }
1159 else
1160 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1161 break;
1162 case INDEX_op_xor_i64:
1163 case INDEX_op_xor_i32:
1164 if (const_args[2]) {
1165 if ((args[2] & 0xffff) == args[2])
1166 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1167 | (args[2] & 0xffff));
1168 else if ((args[2] & 0xffff0000) == args[2])
1169 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1170 | ((args[2] >> 16) & 0xffff));
1171 else {
1172 tcg_out_movi (s, (opc == INDEX_op_and_i32
1173 ? TCG_TYPE_I32
1174 : TCG_TYPE_I64),
1175 0, args[2]);
1176 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1177 }
1178 }
1179 else
1180 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1181 break;
1182
1183 case INDEX_op_mul_i32:
1184 if (const_args[2]) {
1185 if (args[2] == (int16_t) args[2])
1186 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1187 | (args[2] & 0xffff));
1188 else {
1189 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1190 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1191 }
1192 }
1193 else
1194 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1195 break;
1196
1197 case INDEX_op_div_i32:
1198 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1199 break;
1200
1201 case INDEX_op_divu_i32:
1202 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1203 break;
1204
1205 case INDEX_op_rem_i32:
1206 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1207 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1208 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1209 break;
1210
1211 case INDEX_op_remu_i32:
1212 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1213 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1214 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1215 break;
1216
1217 case INDEX_op_shl_i32:
1218 if (const_args[2]) {
1219 tcg_out32 (s, (RLWINM
1220 | RA (args[0])
1221 | RS (args[1])
1222 | SH (args[2])
1223 | MB (0)
1224 | ME (31 - args[2])
1225 )
1226 );
1227 }
1228 else
1229 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1230 break;
1231 case INDEX_op_shr_i32:
1232 if (const_args[2]) {
1233 tcg_out32 (s, (RLWINM
1234 | RA (args[0])
1235 | RS (args[1])
1236 | SH (32 - args[2])
1237 | MB (args[2])
1238 | ME (31)
1239 )
1240 );
1241 }
1242 else
1243 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1244 break;
1245 case INDEX_op_sar_i32:
1246 if (const_args[2])
1247 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1248 else
1249 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1250 break;
1251
1252 case INDEX_op_brcond_i32:
1253 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1254 break;
1255
1256 case INDEX_op_brcond_i64:
1257 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1258 break;
1259
1260 case INDEX_op_neg_i32:
1261 case INDEX_op_neg_i64:
1262 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1263 break;
1264
1265 case INDEX_op_add_i64:
1266 if (const_args[2])
1267 ppc_addi64 (s, args[0], args[1], args[2]);
1268 else
1269 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1270 break;
1271 case INDEX_op_sub_i64:
1272 if (const_args[2])
1273 ppc_addi64 (s, args[0], args[1], -args[2]);
1274 else
1275 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1276 break;
1277
1278 case INDEX_op_shl_i64:
1279 if (const_args[2])
1280 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1281 else
1282 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1283 break;
1284 case INDEX_op_shr_i64:
1285 if (const_args[2])
1286 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1287 else
1288 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1289 break;
1290 case INDEX_op_sar_i64:
1291 if (const_args[2]) {
1292 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1293 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1294 }
1295 else
1296 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1297 break;
1298
1299 case INDEX_op_mul_i64:
1300 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1301 break;
1302 case INDEX_op_div_i64:
1303 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1304 break;
1305 case INDEX_op_divu_i64:
1306 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1307 break;
1308 case INDEX_op_rem_i64:
1309 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1310 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1311 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1312 break;
1313 case INDEX_op_remu_i64:
1314 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1315 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1316 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1317 break;
1318
1319 case INDEX_op_qemu_ld8u:
1320 tcg_out_qemu_ld (s, args, 0);
1321 break;
1322 case INDEX_op_qemu_ld8s:
1323 tcg_out_qemu_ld (s, args, 0 | 4);
1324 break;
1325 case INDEX_op_qemu_ld16u:
1326 tcg_out_qemu_ld (s, args, 1);
1327 break;
1328 case INDEX_op_qemu_ld16s:
1329 tcg_out_qemu_ld (s, args, 1 | 4);
1330 break;
1331 case INDEX_op_qemu_ld32u:
1332 tcg_out_qemu_ld (s, args, 2);
1333 break;
1334 case INDEX_op_qemu_ld32s:
1335 tcg_out_qemu_ld (s, args, 2 | 4);
1336 break;
1337 case INDEX_op_qemu_ld64:
1338 tcg_out_qemu_ld (s, args, 3);
1339 break;
1340 case INDEX_op_qemu_st8:
1341 tcg_out_qemu_st (s, args, 0);
1342 break;
1343 case INDEX_op_qemu_st16:
1344 tcg_out_qemu_st (s, args, 1);
1345 break;
1346 case INDEX_op_qemu_st32:
1347 tcg_out_qemu_st (s, args, 2);
1348 break;
1349 case INDEX_op_qemu_st64:
1350 tcg_out_qemu_st (s, args, 3);
1351 break;
1352
1353 case INDEX_op_ext8s_i32:
1354 case INDEX_op_ext8s_i64:
1355 c = EXTSB;
1356 goto gen_ext;
1357 case INDEX_op_ext16s_i32:
1358 case INDEX_op_ext16s_i64:
1359 c = EXTSH;
1360 goto gen_ext;
1361 case INDEX_op_ext32s_i64:
1362 c = EXTSW;
1363 goto gen_ext;
1364 gen_ext:
1365 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1366 break;
1367
1368 default:
1369 tcg_dump_ops (s, stderr);
1370 tcg_abort ();
1371 }
1372 }
1373
1374 static const TCGTargetOpDef ppc_op_defs[] = {
1375 { INDEX_op_exit_tb, { } },
1376 { INDEX_op_goto_tb, { } },
1377 { INDEX_op_call, { "ri" } },
1378 { INDEX_op_jmp, { "ri" } },
1379 { INDEX_op_br, { } },
1380
1381 { INDEX_op_mov_i32, { "r", "r" } },
1382 { INDEX_op_mov_i64, { "r", "r" } },
1383 { INDEX_op_movi_i32, { "r" } },
1384 { INDEX_op_movi_i64, { "r" } },
1385
1386 { INDEX_op_ld8u_i32, { "r", "r" } },
1387 { INDEX_op_ld8s_i32, { "r", "r" } },
1388 { INDEX_op_ld16u_i32, { "r", "r" } },
1389 { INDEX_op_ld16s_i32, { "r", "r" } },
1390 { INDEX_op_ld_i32, { "r", "r" } },
1391 { INDEX_op_ld_i64, { "r", "r" } },
1392 { INDEX_op_st8_i32, { "r", "r" } },
1393 { INDEX_op_st8_i64, { "r", "r" } },
1394 { INDEX_op_st16_i32, { "r", "r" } },
1395 { INDEX_op_st16_i64, { "r", "r" } },
1396 { INDEX_op_st_i32, { "r", "r" } },
1397 { INDEX_op_st_i64, { "r", "r" } },
1398 { INDEX_op_st32_i64, { "r", "r" } },
1399
1400 { INDEX_op_ld8u_i64, { "r", "r" } },
1401 { INDEX_op_ld8s_i64, { "r", "r" } },
1402 { INDEX_op_ld16u_i64, { "r", "r" } },
1403 { INDEX_op_ld16s_i64, { "r", "r" } },
1404 { INDEX_op_ld32u_i64, { "r", "r" } },
1405 { INDEX_op_ld32s_i64, { "r", "r" } },
1406 { INDEX_op_ld_i64, { "r", "r" } },
1407
1408 { INDEX_op_add_i32, { "r", "r", "ri" } },
1409 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1410 { INDEX_op_div_i32, { "r", "r", "r" } },
1411 { INDEX_op_divu_i32, { "r", "r", "r" } },
1412 { INDEX_op_rem_i32, { "r", "r", "r" } },
1413 { INDEX_op_remu_i32, { "r", "r", "r" } },
1414 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1415 { INDEX_op_and_i32, { "r", "r", "ri" } },
1416 { INDEX_op_or_i32, { "r", "r", "ri" } },
1417 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1418
1419 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1420 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1421 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1422
1423 { INDEX_op_brcond_i32, { "r", "ri" } },
1424 { INDEX_op_brcond_i64, { "r", "ri" } },
1425
1426 { INDEX_op_neg_i32, { "r", "r" } },
1427
1428 { INDEX_op_add_i64, { "r", "r", "ri" } },
1429 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1430 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1431 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1432 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1433
1434 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1435 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1436 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1437
1438 { INDEX_op_mul_i64, { "r", "r", "r" } },
1439 { INDEX_op_div_i64, { "r", "r", "r" } },
1440 { INDEX_op_divu_i64, { "r", "r", "r" } },
1441 { INDEX_op_rem_i64, { "r", "r", "r" } },
1442 { INDEX_op_remu_i64, { "r", "r", "r" } },
1443
1444 { INDEX_op_neg_i64, { "r", "r" } },
1445
1446 { INDEX_op_qemu_ld8u, { "r", "L" } },
1447 { INDEX_op_qemu_ld8s, { "r", "L" } },
1448 { INDEX_op_qemu_ld16u, { "r", "L" } },
1449 { INDEX_op_qemu_ld16s, { "r", "L" } },
1450 { INDEX_op_qemu_ld32u, { "r", "L" } },
1451 { INDEX_op_qemu_ld32s, { "r", "L" } },
1452 { INDEX_op_qemu_ld64, { "r", "L" } },
1453
1454 { INDEX_op_qemu_st8, { "S", "S" } },
1455 { INDEX_op_qemu_st16, { "S", "S" } },
1456 { INDEX_op_qemu_st32, { "S", "S" } },
1457 { INDEX_op_qemu_st64, { "S", "S", "S" } },
1458
1459 { INDEX_op_ext8s_i32, { "r", "r" } },
1460 { INDEX_op_ext16s_i32, { "r", "r" } },
1461 { INDEX_op_ext8s_i64, { "r", "r" } },
1462 { INDEX_op_ext16s_i64, { "r", "r" } },
1463 { INDEX_op_ext32s_i64, { "r", "r" } },
1464
1465 { -1 },
1466 };
1467
1468 void tcg_target_init (TCGContext *s)
1469 {
1470 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1471 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1472 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1473 (1 << TCG_REG_R0) |
1474 (1 << TCG_REG_R3) |
1475 (1 << TCG_REG_R4) |
1476 (1 << TCG_REG_R5) |
1477 (1 << TCG_REG_R6) |
1478 (1 << TCG_REG_R7) |
1479 (1 << TCG_REG_R8) |
1480 (1 << TCG_REG_R9) |
1481 (1 << TCG_REG_R10) |
1482 (1 << TCG_REG_R11) |
1483 (1 << TCG_REG_R12)
1484 );
1485
1486 tcg_regset_clear (s->reserved_regs);
1487 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1488 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1489 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1490 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1491
1492 tcg_add_target_add_op_defs (ppc_op_defs);
1493 }
Samsung s3c2440 and arm920t support for the mini2440 dev board