hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26
  27 //#define DEBUG
  28
  29 /* i82731AB (PIIX4) compatible power management function */
  30 #define PM_FREQ 3579545
  31
  32 #define ACPI_DBG_IO_ADDR  0xb044
  33
  34 typedef struct PIIX4PMState {
  35     PCIDevice dev;
  36     uint16_t pmsts;
  37     uint16_t pmen;
  38     uint16_t pmcntrl;
  39     uint8_t apmc;
  40     uint8_t apms;
  41     QEMUTimer *tmr_timer;
  42     int64_t tmr_overflow_time;
  43     i2c_bus *smbus;
  44     uint8_t smb_stat;
  45     uint8_t smb_ctl;
  46     uint8_t smb_cmd;
  47     uint8_t smb_addr;
  48     uint8_t smb_data0;
  49     uint8_t smb_data1;
  50     uint8_t smb_data[32];
  51     uint8_t smb_index;
  52     qemu_irq irq;
  53 } PIIX4PMState;
  54
  55 #define RTC_EN (1 << 10)
  56 #define PWRBTN_EN (1 << 8)
  57 #define GBL_EN (1 << 5)
  58 #define TMROF_EN (1 << 0)
  59
  60 #define SCI_EN (1 << 0)
  61
  62 #define SUS_EN (1 << 13)
  63
  64 #define ACPI_ENABLE 0xf1
  65 #define ACPI_DISABLE 0xf0
  66
  67 #define SMBHSTSTS 0x00
  68 #define SMBHSTCNT 0x02
  69 #define SMBHSTCMD 0x03
  70 #define SMBHSTADD 0x04
  71 #define SMBHSTDAT0 0x05
  72 #define SMBHSTDAT1 0x06
  73 #define SMBBLKDAT 0x07
  74
  75 PIIX4PMState *pm_state;
  76
  77 static uint32_t get_pmtmr(PIIX4PMState *s)
  78 {
  79     uint32_t d;
  80     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  81     return d & 0xffffff;
  82 }
  83
  84 static int get_pmsts(PIIX4PMState *s)
  85 {
  86     int64_t d;
  87     int pmsts;
  88     pmsts = s->pmsts;
  89     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  90     if (d >= s->tmr_overflow_time)
  91         s->pmsts |= TMROF_EN;
  92     return pmsts;
  93 }
  94
  95 static void pm_update_sci(PIIX4PMState *s)
  96 {
  97     int sci_level, pmsts;
  98     int64_t expire_time;
  99
 100     pmsts = get_pmsts(s);
 101     sci_level = (((pmsts & s->pmen) &
 102                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 103     qemu_set_irq(s->irq, sci_level);
 104     /* schedule a timer interruption if needed */
 105     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 106         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 107         qemu_mod_timer(s->tmr_timer, expire_time);
 108     } else {
 109         qemu_del_timer(s->tmr_timer);
 110     }
 111 }
 112
 113 static void pm_tmr_timer(void *opaque)
 114 {
 115     PIIX4PMState *s = opaque;
 116     pm_update_sci(s);
 117 }
 118
 119 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 120 {
 121     PIIX4PMState *s = opaque;
 122     addr &= 0x3f;
 123     switch(addr) {
 124     case 0x00:
 125         {
 126             int64_t d;
 127             int pmsts;
 128             pmsts = get_pmsts(s);
 129             if (pmsts & val & TMROF_EN) {
 130                 /* if TMRSTS is reset, then compute the new overflow time */
 131                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 132                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 133             }
 134             s->pmsts &= ~val;
 135             pm_update_sci(s);
 136         }
 137         break;
 138     case 0x02:
 139         s->pmen = val;
 140         pm_update_sci(s);
 141         break;
 142     case 0x04:
 143         {
 144             int sus_typ;
 145             s->pmcntrl = val & ~(SUS_EN);
 146             if (val & SUS_EN) {
 147                 /* change suspend type */
 148                 sus_typ = (val >> 10) & 7;
 149                 switch(sus_typ) {
 150                 case 0: /* soft power off */
 151                     qemu_system_shutdown_request();
 152                     break;
 153                 default:
 154                     break;
 155                 }
 156             }
 157         }
 158         break;
 159     default:
 160         break;
 161     }
 162 #ifdef DEBUG
 163     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 164 #endif
 165 }
 166
 167 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 168 {
 169     PIIX4PMState *s = opaque;
 170     uint32_t val;
 171
 172     addr &= 0x3f;
 173     switch(addr) {
 174     case 0x00:
 175         val = get_pmsts(s);
 176         break;
 177     case 0x02:
 178         val = s->pmen;
 179         break;
 180     case 0x04:
 181         val = s->pmcntrl;
 182         break;
 183     default:
 184         val = 0;
 185         break;
 186     }
 187 #ifdef DEBUG
 188     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 189 #endif
 190     return val;
 191 }
 192
 193 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 194 {
 195     //    PIIX4PMState *s = opaque;
 196     addr &= 0x3f;
 197 #ifdef DEBUG
 198     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 199 #endif
 200 }
 201
 202 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 203 {
 204     PIIX4PMState *s = opaque;
 205     uint32_t val;
 206
 207     addr &= 0x3f;
 208     switch(addr) {
 209     case 0x08:
 210         val = get_pmtmr(s);
 211         break;
 212     default:
 213         val = 0;
 214         break;
 215     }
 216 #ifdef DEBUG
 217     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 218 #endif
 219     return val;
 220 }
 221
 222 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 223 {
 224     PIIX4PMState *s = opaque;
 225     addr &= 1;
 226 #ifdef DEBUG
 227     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 228 #endif
 229     if (addr == 0) {
 230         s->apmc = val;
 231
 232         /* ACPI specs 3.0, 4.7.2.5 */
 233         if (val == ACPI_ENABLE) {
 234             s->pmcntrl |= SCI_EN;
 235         } else if (val == ACPI_DISABLE) {
 236             s->pmcntrl &= ~SCI_EN;
 237         }
 238
 239         if (s->dev.config[0x5b] & (1 << 1)) {
 240             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 241         }
 242     } else {
 243         s->apms = val;
 244     }
 245 }
 246
 247 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 248 {
 249     PIIX4PMState *s = opaque;
 250     uint32_t val;
 251
 252     addr &= 1;
 253     if (addr == 0) {
 254         val = s->apmc;
 255     } else {
 256         val = s->apms;
 257     }
 258 #ifdef DEBUG
 259     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 260 #endif
 261     return val;
 262 }
 263
 264 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 265 {
 266 #if defined(DEBUG)
 267     printf("ACPI: DBG: 0x%08x\n", val);
 268 #endif
 269 }
 270
 271 static void smb_transaction(PIIX4PMState *s)
 272 {
 273     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 274     uint8_t read = s->smb_addr & 0x01;
 275     uint8_t cmd = s->smb_cmd;
 276     uint8_t addr = s->smb_addr >> 1;
 277     i2c_bus *bus = s->smbus;
 278
 279 #ifdef DEBUG
 280     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 281 #endif
 282     switch(prot) {
 283     case 0x0:
 284         smbus_quick_command(bus, addr, read);
 285         break;
 286     case 0x1:
 287         if (read) {
 288             s->smb_data0 = smbus_receive_byte(bus, addr);
 289         } else {
 290             smbus_send_byte(bus, addr, cmd);
 291         }
 292         break;
 293     case 0x2:
 294         if (read) {
 295             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 296         } else {
 297             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 298         }
 299         break;
 300     case 0x3:
 301         if (read) {
 302             uint16_t val;
 303             val = smbus_read_word(bus, addr, cmd);
 304             s->smb_data0 = val;
 305             s->smb_data1 = val >> 8;
 306         } else {
 307             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 308         }
 309         break;
 310     case 0x5:
 311         if (read) {
 312             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 313         } else {
 314             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 315         }
 316         break;
 317     default:
 318         goto error;
 319     }
 320     return;
 321
 322   error:
 323     s->smb_stat |= 0x04;
 324 }
 325
 326 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 327 {
 328     PIIX4PMState *s = opaque;
 329     addr &= 0x3f;
 330 #ifdef DEBUG
 331     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 332 #endif
 333     switch(addr) {
 334     case SMBHSTSTS:
 335         s->smb_stat = 0;
 336         s->smb_index = 0;
 337         break;
 338     case SMBHSTCNT:
 339         s->smb_ctl = val;
 340         if (val & 0x40)
 341             smb_transaction(s);
 342         break;
 343     case SMBHSTCMD:
 344         s->smb_cmd = val;
 345         break;
 346     case SMBHSTADD:
 347         s->smb_addr = val;
 348         break;
 349     case SMBHSTDAT0:
 350         s->smb_data0 = val;
 351         break;
 352     case SMBHSTDAT1:
 353         s->smb_data1 = val;
 354         break;
 355     case SMBBLKDAT:
 356         s->smb_data[s->smb_index++] = val;
 357         if (s->smb_index > 31)
 358             s->smb_index = 0;
 359         break;
 360     default:
 361         break;
 362     }
 363 }
 364
 365 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 366 {
 367     PIIX4PMState *s = opaque;
 368     uint32_t val;
 369
 370     addr &= 0x3f;
 371     switch(addr) {
 372     case SMBHSTSTS:
 373         val = s->smb_stat;
 374         break;
 375     case SMBHSTCNT:
 376         s->smb_index = 0;
 377         val = s->smb_ctl & 0x1f;
 378         break;
 379     case SMBHSTCMD:
 380         val = s->smb_cmd;
 381         break;
 382     case SMBHSTADD:
 383         val = s->smb_addr;
 384         break;
 385     case SMBHSTDAT0:
 386         val = s->smb_data0;
 387         break;
 388     case SMBHSTDAT1:
 389         val = s->smb_data1;
 390         break;
 391     case SMBBLKDAT:
 392         val = s->smb_data[s->smb_index++];
 393         if (s->smb_index > 31)
 394             s->smb_index = 0;
 395         break;
 396     default:
 397         val = 0;
 398         break;
 399     }
 400 #ifdef DEBUG
 401     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 402 #endif
 403     return val;
 404 }
 405
 406 static void pm_io_space_update(PIIX4PMState *s)
 407 {
 408     uint32_t pm_io_base;
 409
 410     if (s->dev.config[0x80] & 1) {
 411         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 412         pm_io_base &= 0xffc0;
 413
 414         /* XXX: need to improve memory and ioport allocation */
 415 #if defined(DEBUG)
 416         printf("PM: mapping to 0x%x\n", pm_io_base);
 417 #endif
 418         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 419         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 420         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 421         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 422     }
 423 }
 424
 425 static void pm_write_config(PCIDevice *d,
 426                             uint32_t address, uint32_t val, int len)
 427 {
 428     pci_default_write_config(d, address, val, len);
 429     if (address == 0x80)
 430         pm_io_space_update((PIIX4PMState *)d);
 431 }
 432
 433 static void pm_save(QEMUFile* f,void *opaque)
 434 {
 435     PIIX4PMState *s = opaque;
 436
 437     pci_device_save(&s->dev, f);
 438
 439     qemu_put_be16s(f, &s->pmsts);
 440     qemu_put_be16s(f, &s->pmen);
 441     qemu_put_be16s(f, &s->pmcntrl);
 442     qemu_put_8s(f, &s->apmc);
 443     qemu_put_8s(f, &s->apms);
 444     qemu_put_timer(f, s->tmr_timer);
 445     qemu_put_be64(f, s->tmr_overflow_time);
 446 }
 447
 448 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 449 {
 450     PIIX4PMState *s = opaque;
 451     int ret;
 452
 453     if (version_id > 1)
 454         return -EINVAL;
 455
 456     ret = pci_device_load(&s->dev, f);
 457     if (ret < 0)
 458         return ret;
 459
 460     qemu_get_be16s(f, &s->pmsts);
 461     qemu_get_be16s(f, &s->pmen);
 462     qemu_get_be16s(f, &s->pmcntrl);
 463     qemu_get_8s(f, &s->apmc);
 464     qemu_get_8s(f, &s->apms);
 465     qemu_get_timer(f, s->tmr_timer);
 466     s->tmr_overflow_time=qemu_get_be64(f);
 467
 468     pm_io_space_update(s);
 469
 470     return 0;
 471 }
 472
 473 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 474                        qemu_irq sci_irq)
 475 {
 476     PIIX4PMState *s;
 477     uint8_t *pci_conf;
 478
 479     s = (PIIX4PMState *)pci_register_device(bus,
 480                                          "PM", sizeof(PIIX4PMState),
 481                                          devfn, NULL, pm_write_config);
 482     pm_state = s;
 483     pci_conf = s->dev.config;
 484     pci_conf[0x00] = 0x86;
 485     pci_conf[0x01] = 0x80;
 486     pci_conf[0x02] = 0x13;
 487     pci_conf[0x03] = 0x71;
 488     pci_conf[0x06] = 0x80;
 489     pci_conf[0x07] = 0x02;
 490     pci_conf[0x08] = 0x03; // revision number
 491     pci_conf[0x09] = 0x00;
 492     pci_conf[0x0a] = 0x80; // other bridge device
 493     pci_conf[0x0b] = 0x06; // bridge device
 494     pci_conf[0x0e] = 0x00; // header_type
 495     pci_conf[0x3d] = 0x01; // interrupt pin 1
 496
 497     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 498
 499     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 500     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 501
 502     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 503
 504     /* XXX: which specification is used ? The i82731AB has different
 505        mappings */
 506     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 507     pci_conf[0x63] = 0x60;
 508     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 509         (serial_hds[1] != NULL ? 0x90 : 0);
 510
 511     pci_conf[0x90] = smb_io_base | 1;
 512     pci_conf[0x91] = smb_io_base >> 8;
 513     pci_conf[0xd2] = 0x09;
 514     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 515     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 516
 517     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 518
 519     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 520
 521     s->smbus = i2c_init_bus();
 522     s->irq = sci_irq;
 523     return s->smbus;
 524 }
 525
 526 #if defined(TARGET_I386)
 527 void qemu_system_powerdown(void)
 528 {
 529     if(pm_state->pmen & PWRBTN_EN) {
 530         pm_state->pmsts |= PWRBTN_EN;
 531         pm_update_sci(pm_state);
 532     }
 533 }
 534 #endif