Include assert.h from qemu-common.h
[qemu/mini2440.git] / target-mips / helper.c
blobfecbcb2f176cc68cc33e48e581c975376a6a47b1
1 /*
2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
27 #include "cpu.h"
28 #include "exec-all.h"
30 enum {
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
38 /* no MMU emulation */
39 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
40 target_ulong address, int rw, int access_type)
42 *physical = address;
43 *prot = PAGE_READ | PAGE_WRITE;
44 return TLBRET_MATCH;
47 /* fixed mapping MMU emulation */
48 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
49 target_ulong address, int rw, int access_type)
51 if (address <= (int32_t)0x7FFFFFFFUL) {
52 if (!(env->CP0_Status & (1 << CP0St_ERL)))
53 *physical = address + 0x40000000UL;
54 else
55 *physical = address;
56 } else if (address <= (int32_t)0xBFFFFFFFUL)
57 *physical = address & 0x1FFFFFFF;
58 else
59 *physical = address;
61 *prot = PAGE_READ | PAGE_WRITE;
62 return TLBRET_MATCH;
65 /* MIPS32/MIPS64 R4000-style MMU emulation */
66 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
67 target_ulong address, int rw, int access_type)
69 uint8_t ASID = env->CP0_EntryHi & 0xFF;
70 int i;
72 for (i = 0; i < env->tlb->tlb_in_use; i++) {
73 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
74 /* 1k pages are not supported. */
75 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
76 target_ulong tag = address & ~mask;
77 target_ulong VPN = tlb->VPN & ~mask;
78 #if defined(TARGET_MIPS64)
79 tag &= env->SEGMask;
80 #endif
82 /* Check ASID, virtual page number & size */
83 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
84 /* TLB match */
85 int n = !!(address & mask & ~(mask >> 1));
86 /* Check access rights */
87 if (!(n ? tlb->V1 : tlb->V0))
88 return TLBRET_INVALID;
89 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
90 *physical = tlb->PFN[n] | (address & (mask >> 1));
91 *prot = PAGE_READ;
92 if (n ? tlb->D1 : tlb->D0)
93 *prot |= PAGE_WRITE;
94 return TLBRET_MATCH;
96 return TLBRET_DIRTY;
99 return TLBRET_NOMATCH;
102 #if !defined(CONFIG_USER_ONLY)
103 static int get_physical_address (CPUState *env, target_ulong *physical,
104 int *prot, target_ulong address,
105 int rw, int access_type)
107 /* User mode can only access useg/xuseg */
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110 int kernel_mode = !user_mode && !supervisor_mode;
111 #if defined(TARGET_MIPS64)
112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
115 #endif
116 int ret = TLBRET_MATCH;
118 #if 0
119 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
120 #endif
122 if (address <= (int32_t)0x7FFFFFFFUL) {
123 /* useg */
124 if (env->CP0_Status & (1 << CP0St_ERL)) {
125 *physical = address & 0xFFFFFFFF;
126 *prot = PAGE_READ | PAGE_WRITE;
127 } else {
128 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
130 #if defined(TARGET_MIPS64)
131 } else if (address < 0x4000000000000000ULL) {
132 /* xuseg */
133 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
134 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
135 } else {
136 ret = TLBRET_BADADDR;
138 } else if (address < 0x8000000000000000ULL) {
139 /* xsseg */
140 if ((supervisor_mode || kernel_mode) &&
141 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
142 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
143 } else {
144 ret = TLBRET_BADADDR;
146 } else if (address < 0xC000000000000000ULL) {
147 /* xkphys */
148 if (kernel_mode && KX &&
149 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
150 *physical = address & env->PAMask;
151 *prot = PAGE_READ | PAGE_WRITE;
152 } else {
153 ret = TLBRET_BADADDR;
155 } else if (address < 0xFFFFFFFF80000000ULL) {
156 /* xkseg */
157 if (kernel_mode && KX &&
158 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
159 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
160 } else {
161 ret = TLBRET_BADADDR;
163 #endif
164 } else if (address < (int32_t)0xA0000000UL) {
165 /* kseg0 */
166 if (kernel_mode) {
167 *physical = address - (int32_t)0x80000000UL;
168 *prot = PAGE_READ | PAGE_WRITE;
169 } else {
170 ret = TLBRET_BADADDR;
172 } else if (address < (int32_t)0xC0000000UL) {
173 /* kseg1 */
174 if (kernel_mode) {
175 *physical = address - (int32_t)0xA0000000UL;
176 *prot = PAGE_READ | PAGE_WRITE;
177 } else {
178 ret = TLBRET_BADADDR;
180 } else if (address < (int32_t)0xE0000000UL) {
181 /* sseg (kseg2) */
182 if (supervisor_mode || kernel_mode) {
183 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
184 } else {
185 ret = TLBRET_BADADDR;
187 } else {
188 /* kseg3 */
189 /* XXX: debug segment is not emulated */
190 if (kernel_mode) {
191 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
192 } else {
193 ret = TLBRET_BADADDR;
196 #if 0
197 qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
198 address, rw, access_type, *physical, *prot, ret);
200 #endif
202 return ret;
204 #endif
206 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
208 #if defined(CONFIG_USER_ONLY)
209 return addr;
210 #else
211 target_ulong phys_addr;
212 int prot;
214 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
215 return -1;
216 return phys_addr;
217 #endif
220 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
221 int mmu_idx, int is_softmmu)
223 #if !defined(CONFIG_USER_ONLY)
224 target_ulong physical;
225 int prot;
226 #endif
227 int exception = 0, error_code = 0;
228 int access_type;
229 int ret = 0;
231 #if 0
232 log_cpu_state(env, 0);
233 #endif
234 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
235 __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
237 rw &= 1;
239 /* data access */
240 /* XXX: put correct access by using cpu_restore_state()
241 correctly */
242 access_type = ACCESS_INT;
243 #if defined(CONFIG_USER_ONLY)
244 ret = TLBRET_NOMATCH;
245 #else
246 ret = get_physical_address(env, &physical, &prot,
247 address, rw, access_type);
248 qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
249 __func__, address, ret, physical, prot);
250 if (ret == TLBRET_MATCH) {
251 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
252 physical & TARGET_PAGE_MASK, prot,
253 mmu_idx, is_softmmu);
254 } else if (ret < 0)
255 #endif
257 switch (ret) {
258 default:
259 case TLBRET_BADADDR:
260 /* Reference to kernel address from user mode or supervisor mode */
261 /* Reference to supervisor address from user mode */
262 if (rw)
263 exception = EXCP_AdES;
264 else
265 exception = EXCP_AdEL;
266 break;
267 case TLBRET_NOMATCH:
268 /* No TLB match for a mapped address */
269 if (rw)
270 exception = EXCP_TLBS;
271 else
272 exception = EXCP_TLBL;
273 error_code = 1;
274 break;
275 case TLBRET_INVALID:
276 /* TLB match with no valid bit */
277 if (rw)
278 exception = EXCP_TLBS;
279 else
280 exception = EXCP_TLBL;
281 break;
282 case TLBRET_DIRTY:
283 /* TLB match but 'D' bit is cleared */
284 exception = EXCP_LTLBL;
285 break;
288 /* Raise exception */
289 env->CP0_BadVAddr = address;
290 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
291 ((address >> 9) & 0x007ffff0);
292 env->CP0_EntryHi =
293 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
294 #if defined(TARGET_MIPS64)
295 env->CP0_EntryHi &= env->SEGMask;
296 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
297 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
298 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
299 #endif
300 env->exception_index = exception;
301 env->error_code = error_code;
302 ret = 1;
305 return ret;
308 static const char * const excp_names[EXCP_LAST + 1] = {
309 [EXCP_RESET] = "reset",
310 [EXCP_SRESET] = "soft reset",
311 [EXCP_DSS] = "debug single step",
312 [EXCP_DINT] = "debug interrupt",
313 [EXCP_NMI] = "non-maskable interrupt",
314 [EXCP_MCHECK] = "machine check",
315 [EXCP_EXT_INTERRUPT] = "interrupt",
316 [EXCP_DFWATCH] = "deferred watchpoint",
317 [EXCP_DIB] = "debug instruction breakpoint",
318 [EXCP_IWATCH] = "instruction fetch watchpoint",
319 [EXCP_AdEL] = "address error load",
320 [EXCP_AdES] = "address error store",
321 [EXCP_TLBF] = "TLB refill",
322 [EXCP_IBE] = "instruction bus error",
323 [EXCP_DBp] = "debug breakpoint",
324 [EXCP_SYSCALL] = "syscall",
325 [EXCP_BREAK] = "break",
326 [EXCP_CpU] = "coprocessor unusable",
327 [EXCP_RI] = "reserved instruction",
328 [EXCP_OVERFLOW] = "arithmetic overflow",
329 [EXCP_TRAP] = "trap",
330 [EXCP_FPE] = "floating point",
331 [EXCP_DDBS] = "debug data break store",
332 [EXCP_DWATCH] = "data watchpoint",
333 [EXCP_LTLBL] = "TLB modify",
334 [EXCP_TLBL] = "TLB load",
335 [EXCP_TLBS] = "TLB store",
336 [EXCP_DBE] = "data bus error",
337 [EXCP_DDBL] = "debug data break load",
338 [EXCP_THREAD] = "thread",
339 [EXCP_MDMX] = "MDMX",
340 [EXCP_C2E] = "precise coprocessor 2",
341 [EXCP_CACHE] = "cache error",
344 void do_interrupt (CPUState *env)
346 #if !defined(CONFIG_USER_ONLY)
347 target_ulong offset;
348 int cause = -1;
349 const char *name;
351 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
352 if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
353 name = "unknown";
354 else
355 name = excp_names[env->exception_index];
357 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
358 __func__, env->active_tc.PC, env->CP0_EPC, name);
360 if (env->exception_index == EXCP_EXT_INTERRUPT &&
361 (env->hflags & MIPS_HFLAG_DM))
362 env->exception_index = EXCP_DINT;
363 offset = 0x180;
364 switch (env->exception_index) {
365 case EXCP_DSS:
366 env->CP0_Debug |= 1 << CP0DB_DSS;
367 /* Debug single step cannot be raised inside a delay slot and
368 resume will always occur on the next instruction
369 (but we assume the pc has always been updated during
370 code translation). */
371 env->CP0_DEPC = env->active_tc.PC;
372 goto enter_debug_mode;
373 case EXCP_DINT:
374 env->CP0_Debug |= 1 << CP0DB_DINT;
375 goto set_DEPC;
376 case EXCP_DIB:
377 env->CP0_Debug |= 1 << CP0DB_DIB;
378 goto set_DEPC;
379 case EXCP_DBp:
380 env->CP0_Debug |= 1 << CP0DB_DBp;
381 goto set_DEPC;
382 case EXCP_DDBS:
383 env->CP0_Debug |= 1 << CP0DB_DDBS;
384 goto set_DEPC;
385 case EXCP_DDBL:
386 env->CP0_Debug |= 1 << CP0DB_DDBL;
387 set_DEPC:
388 if (env->hflags & MIPS_HFLAG_BMASK) {
389 /* If the exception was raised from a delay slot,
390 come back to the jump. */
391 env->CP0_DEPC = env->active_tc.PC - 4;
392 env->hflags &= ~MIPS_HFLAG_BMASK;
393 } else {
394 env->CP0_DEPC = env->active_tc.PC;
396 enter_debug_mode:
397 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
398 env->hflags &= ~(MIPS_HFLAG_KSU);
399 /* EJTAG probe trap enable is not implemented... */
400 if (!(env->CP0_Status & (1 << CP0St_EXL)))
401 env->CP0_Cause &= ~(1 << CP0Ca_BD);
402 env->active_tc.PC = (int32_t)0xBFC00480;
403 break;
404 case EXCP_RESET:
405 cpu_reset(env);
406 break;
407 case EXCP_SRESET:
408 env->CP0_Status |= (1 << CP0St_SR);
409 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
410 goto set_error_EPC;
411 case EXCP_NMI:
412 env->CP0_Status |= (1 << CP0St_NMI);
413 set_error_EPC:
414 if (env->hflags & MIPS_HFLAG_BMASK) {
415 /* If the exception was raised from a delay slot,
416 come back to the jump. */
417 env->CP0_ErrorEPC = env->active_tc.PC - 4;
418 env->hflags &= ~MIPS_HFLAG_BMASK;
419 } else {
420 env->CP0_ErrorEPC = env->active_tc.PC;
422 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
423 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
424 env->hflags &= ~(MIPS_HFLAG_KSU);
425 if (!(env->CP0_Status & (1 << CP0St_EXL)))
426 env->CP0_Cause &= ~(1 << CP0Ca_BD);
427 env->active_tc.PC = (int32_t)0xBFC00000;
428 break;
429 case EXCP_EXT_INTERRUPT:
430 cause = 0;
431 if (env->CP0_Cause & (1 << CP0Ca_IV))
432 offset = 0x200;
433 goto set_EPC;
434 case EXCP_LTLBL:
435 cause = 1;
436 goto set_EPC;
437 case EXCP_TLBL:
438 cause = 2;
439 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
440 #if defined(TARGET_MIPS64)
441 int R = env->CP0_BadVAddr >> 62;
442 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
443 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
444 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
446 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
447 offset = 0x080;
448 else
449 #endif
450 offset = 0x000;
452 goto set_EPC;
453 case EXCP_TLBS:
454 cause = 3;
455 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
456 #if defined(TARGET_MIPS64)
457 int R = env->CP0_BadVAddr >> 62;
458 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
459 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
460 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
462 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
463 offset = 0x080;
464 else
465 #endif
466 offset = 0x000;
468 goto set_EPC;
469 case EXCP_AdEL:
470 cause = 4;
471 goto set_EPC;
472 case EXCP_AdES:
473 cause = 5;
474 goto set_EPC;
475 case EXCP_IBE:
476 cause = 6;
477 goto set_EPC;
478 case EXCP_DBE:
479 cause = 7;
480 goto set_EPC;
481 case EXCP_SYSCALL:
482 cause = 8;
483 goto set_EPC;
484 case EXCP_BREAK:
485 cause = 9;
486 goto set_EPC;
487 case EXCP_RI:
488 cause = 10;
489 goto set_EPC;
490 case EXCP_CpU:
491 cause = 11;
492 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
493 (env->error_code << CP0Ca_CE);
494 goto set_EPC;
495 case EXCP_OVERFLOW:
496 cause = 12;
497 goto set_EPC;
498 case EXCP_TRAP:
499 cause = 13;
500 goto set_EPC;
501 case EXCP_FPE:
502 cause = 15;
503 goto set_EPC;
504 case EXCP_C2E:
505 cause = 18;
506 goto set_EPC;
507 case EXCP_MDMX:
508 cause = 22;
509 goto set_EPC;
510 case EXCP_DWATCH:
511 cause = 23;
512 /* XXX: TODO: manage defered watch exceptions */
513 goto set_EPC;
514 case EXCP_MCHECK:
515 cause = 24;
516 goto set_EPC;
517 case EXCP_THREAD:
518 cause = 25;
519 goto set_EPC;
520 case EXCP_CACHE:
521 cause = 30;
522 if (env->CP0_Status & (1 << CP0St_BEV)) {
523 offset = 0x100;
524 } else {
525 offset = 0x20000100;
527 set_EPC:
528 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
529 if (env->hflags & MIPS_HFLAG_BMASK) {
530 /* If the exception was raised from a delay slot,
531 come back to the jump. */
532 env->CP0_EPC = env->active_tc.PC - 4;
533 env->CP0_Cause |= (1 << CP0Ca_BD);
534 } else {
535 env->CP0_EPC = env->active_tc.PC;
536 env->CP0_Cause &= ~(1 << CP0Ca_BD);
538 env->CP0_Status |= (1 << CP0St_EXL);
539 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
540 env->hflags &= ~(MIPS_HFLAG_KSU);
542 env->hflags &= ~MIPS_HFLAG_BMASK;
543 if (env->CP0_Status & (1 << CP0St_BEV)) {
544 env->active_tc.PC = (int32_t)0xBFC00200;
545 } else {
546 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
548 env->active_tc.PC += offset;
549 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
550 break;
551 default:
552 qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
553 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
554 exit(1);
556 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
557 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
558 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
559 __func__, env->active_tc.PC, env->CP0_EPC, cause,
560 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
561 env->CP0_DEPC);
563 #endif
564 env->exception_index = EXCP_NONE;
567 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
569 r4k_tlb_t *tlb;
570 target_ulong addr;
571 target_ulong end;
572 uint8_t ASID = env->CP0_EntryHi & 0xFF;
573 target_ulong mask;
575 tlb = &env->tlb->mmu.r4k.tlb[idx];
576 /* The qemu TLB is flushed when the ASID changes, so no need to
577 flush these entries again. */
578 if (tlb->G == 0 && tlb->ASID != ASID) {
579 return;
582 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
583 /* For tlbwr, we can shadow the discarded entry into
584 a new (fake) TLB entry, as long as the guest can not
585 tell that it's there. */
586 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
587 env->tlb->tlb_in_use++;
588 return;
591 /* 1k pages are not supported. */
592 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
593 if (tlb->V0) {
594 addr = tlb->VPN & ~mask;
595 #if defined(TARGET_MIPS64)
596 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
597 addr |= 0x3FFFFF0000000000ULL;
599 #endif
600 end = addr | (mask >> 1);
601 while (addr < end) {
602 tlb_flush_page (env, addr);
603 addr += TARGET_PAGE_SIZE;
606 if (tlb->V1) {
607 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
608 #if defined(TARGET_MIPS64)
609 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
610 addr |= 0x3FFFFF0000000000ULL;
612 #endif
613 end = addr | mask;
614 while (addr - 1 < end) {
615 tlb_flush_page (env, addr);
616 addr += TARGET_PAGE_SIZE;