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Stellaris SSI qdev conversion
[qemu/mini2440.git] / hw / pxa2xx.c
blobb1ffa9f8ff831c8e23fe7e8e5558f7857e38507b
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "hw.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "qemu-timer.h"
16 #include "qemu-char.h"
17
18 static struct {
19 target_phys_addr_t io_base;
20 int irqn;
21 } pxa255_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0x41600000, PXA25X_PIC_HWUART },
26 { 0, 0 }
27 }, pxa270_serial[] = {
28 { 0x40100000, PXA2XX_PIC_FFUART },
29 { 0x40200000, PXA2XX_PIC_BTUART },
30 { 0x40700000, PXA2XX_PIC_STUART },
31 { 0, 0 }
32 };
33
34 typedef struct PXASSPDef {
35 target_phys_addr_t io_base;
36 int irqn;
37 } PXASSPDef;
38
39 #if 0
40 static PXASSPDef pxa250_ssp[] = {
41 { 0x41000000, PXA2XX_PIC_SSP },
42 { 0, 0 }
43 };
44 #endif
45
46 static PXASSPDef pxa255_ssp[] = {
47 { 0x41000000, PXA2XX_PIC_SSP },
48 { 0x41400000, PXA25X_PIC_NSSP },
49 { 0, 0 }
50 };
51
52 #if 0
53 static PXASSPDef pxa26x_ssp[] = {
54 { 0x41000000, PXA2XX_PIC_SSP },
55 { 0x41400000, PXA25X_PIC_NSSP },
56 { 0x41500000, PXA26X_PIC_ASSP },
57 { 0, 0 }
58 };
59 #endif
60
61 static PXASSPDef pxa27x_ssp[] = {
62 { 0x41000000, PXA2XX_PIC_SSP },
63 { 0x41700000, PXA27X_PIC_SSP2 },
64 { 0x41900000, PXA2XX_PIC_SSP3 },
65 { 0, 0 }
66 };
67
68 #define PMCR 0x00 /* Power Manager Control register */
69 #define PSSR 0x04 /* Power Manager Sleep Status register */
70 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
71 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
72 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
73 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
74 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
75 #define PCFR 0x1c /* Power Manager General Configuration register */
76 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
77 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
78 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
79 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
80 #define RCSR 0x30 /* Reset Controller Status register */
81 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
82 #define PTSR 0x38 /* Power Manager Standby Configuration register */
83 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
84 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
85 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
86 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
87 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
88 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
89
90 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
91 {
92 PXA2xxState *s = (PXA2xxState *) opaque;
93
94 switch (addr) {
95 case PMCR ... PCMD31:
96 if (addr & 3)
97 goto fail;
98
99 return s->pm_regs[addr >> 2];
100 default:
101 fail:
102 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
103 break;
104 }
105 return 0;
106 }
107
108 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
109 uint32_t value)
110 {
111 PXA2xxState *s = (PXA2xxState *) opaque;
112
113 switch (addr) {
114 case PMCR:
115 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
116 s->pm_regs[addr >> 2] |= value & 0x15;
117 break;
118
119 case PSSR: /* Read-clean registers */
120 case RCSR:
121 case PKSR:
122 s->pm_regs[addr >> 2] &= ~value;
123 break;
124
125 default: /* Read-write registers */
126 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
127 s->pm_regs[addr >> 2] = value;
128 break;
129 }
130
131 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
132 break;
133 }
134 }
135
136 static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
137 pxa2xx_pm_read,
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140 };
141
142 static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
143 pxa2xx_pm_write,
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146 };
147
148 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
149 {
150 PXA2xxState *s = (PXA2xxState *) opaque;
151 int i;
152
153 for (i = 0; i < 0x40; i ++)
154 qemu_put_be32s(f, &s->pm_regs[i]);
155 }
156
157 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
158 {
159 PXA2xxState *s = (PXA2xxState *) opaque;
160 int i;
161
162 for (i = 0; i < 0x40; i ++)
163 qemu_get_be32s(f, &s->pm_regs[i]);
164
165 return 0;
166 }
167
168 #define CCCR 0x00 /* Core Clock Configuration register */
169 #define CKEN 0x04 /* Clock Enable register */
170 #define OSCC 0x08 /* Oscillator Configuration register */
171 #define CCSR 0x0c /* Core Clock Status register */
172
173 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
174 {
175 PXA2xxState *s = (PXA2xxState *) opaque;
176
177 switch (addr) {
178 case CCCR:
179 case CKEN:
180 case OSCC:
181 return s->cm_regs[addr >> 2];
182
183 case CCSR:
184 return s->cm_regs[CCCR >> 2] | (3 << 28);
185
186 default:
187 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
188 break;
189 }
190 return 0;
191 }
192
193 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
194 uint32_t value)
195 {
196 PXA2xxState *s = (PXA2xxState *) opaque;
197
198 switch (addr) {
199 case CCCR:
200 case CKEN:
201 s->cm_regs[addr >> 2] = value;
202 break;
203
204 case OSCC:
205 s->cm_regs[addr >> 2] &= ~0x6c;
206 s->cm_regs[addr >> 2] |= value & 0x6e;
207 if ((value >> 1) & 1) /* OON */
208 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
209 break;
210
211 default:
212 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
213 break;
214 }
215 }
216
217 static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
218 pxa2xx_cm_read,
219 pxa2xx_cm_read,
220 pxa2xx_cm_read,
221 };
222
223 static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
224 pxa2xx_cm_write,
225 pxa2xx_cm_write,
226 pxa2xx_cm_write,
227 };
228
229 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
230 {
231 PXA2xxState *s = (PXA2xxState *) opaque;
232 int i;
233
234 for (i = 0; i < 4; i ++)
235 qemu_put_be32s(f, &s->cm_regs[i]);
236 qemu_put_be32s(f, &s->clkcfg);
237 qemu_put_be32s(f, &s->pmnc);
238 }
239
240 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
241 {
242 PXA2xxState *s = (PXA2xxState *) opaque;
243 int i;
244
245 for (i = 0; i < 4; i ++)
246 qemu_get_be32s(f, &s->cm_regs[i]);
247 qemu_get_be32s(f, &s->clkcfg);
248 qemu_get_be32s(f, &s->pmnc);
249
250 return 0;
251 }
252
253 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
254 {
255 PXA2xxState *s = (PXA2xxState *) opaque;
256
257 switch (reg) {
258 case 6: /* Clock Configuration register */
259 return s->clkcfg;
260
261 case 7: /* Power Mode register */
262 return 0;
263
264 default:
265 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
266 break;
267 }
268 return 0;
269 }
270
271 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
272 uint32_t value)
273 {
274 PXA2xxState *s = (PXA2xxState *) opaque;
275 static const char *pwrmode[8] = {
276 "Normal", "Idle", "Deep-idle", "Standby",
277 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
278 };
279
280 switch (reg) {
281 case 6: /* Clock Configuration register */
282 s->clkcfg = value & 0xf;
283 if (value & 2)
284 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
285 break;
286
287 case 7: /* Power Mode register */
288 if (value & 8)
289 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
290 switch (value & 7) {
291 case 0:
292 /* Do nothing */
293 break;
294
295 case 1:
296 /* Idle */
297 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
298 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
299 break;
300 }
301 /* Fall through. */
302
303 case 2:
304 /* Deep-Idle */
305 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
306 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
307 goto message;
308
309 case 3:
310 s->env->uncached_cpsr =
311 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
312 s->env->cp15.c1_sys = 0;
313 s->env->cp15.c1_coproc = 0;
314 s->env->cp15.c2_base0 = 0;
315 s->env->cp15.c3 = 0;
316 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
317 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
318
319 /*
320 * The scratch-pad register is almost universally used
321 * for storing the return address on suspend. For the
322 * lack of a resuming bootloader, perform a jump
323 * directly to that address.
324 */
325 memset(s->env->regs, 0, 4 * 15);
326 s->env->regs[15] = s->pm_regs[PSPR >> 2];
327
328 #if 0
329 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
330 cpu_physical_memory_write(0, &buffer, 4);
331 buffer = s->pm_regs[PSPR >> 2];
332 cpu_physical_memory_write(8, &buffer, 4);
333 #endif
334
335 /* Suspend */
336 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
337
338 goto message;
339
340 default:
341 message:
342 printf("%s: machine entered %s mode\n", __FUNCTION__,
343 pwrmode[value & 7]);
344 }
345 break;
346
347 default:
348 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
349 break;
350 }
351 }
352
353 /* Performace Monitoring Registers */
354 #define CPPMNC 0 /* Performance Monitor Control register */
355 #define CPCCNT 1 /* Clock Counter register */
356 #define CPINTEN 4 /* Interrupt Enable register */
357 #define CPFLAG 5 /* Overflow Flag register */
358 #define CPEVTSEL 8 /* Event Selection register */
359
360 #define CPPMN0 0 /* Performance Count register 0 */
361 #define CPPMN1 1 /* Performance Count register 1 */
362 #define CPPMN2 2 /* Performance Count register 2 */
363 #define CPPMN3 3 /* Performance Count register 3 */
364
365 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
366 {
367 PXA2xxState *s = (PXA2xxState *) opaque;
368
369 switch (reg) {
370 case CPPMNC:
371 return s->pmnc;
372 case CPCCNT:
373 if (s->pmnc & 1)
374 return qemu_get_clock(vm_clock);
375 else
376 return 0;
377 case CPINTEN:
378 case CPFLAG:
379 case CPEVTSEL:
380 return 0;
381
382 default:
383 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
384 break;
385 }
386 return 0;
387 }
388
389 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
390 uint32_t value)
391 {
392 PXA2xxState *s = (PXA2xxState *) opaque;
393
394 switch (reg) {
395 case CPPMNC:
396 s->pmnc = value;
397 break;
398
399 case CPCCNT:
400 case CPINTEN:
401 case CPFLAG:
402 case CPEVTSEL:
403 break;
404
405 default:
406 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
407 break;
408 }
409 }
410
411 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
412 {
413 switch (crm) {
414 case 0:
415 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
416 case 1:
417 return pxa2xx_perf_read(opaque, op2, reg, crm);
418 case 2:
419 switch (reg) {
420 case CPPMN0:
421 case CPPMN1:
422 case CPPMN2:
423 case CPPMN3:
424 return 0;
425 }
426 /* Fall through */
427 default:
428 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
429 break;
430 }
431 return 0;
432 }
433
434 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
435 uint32_t value)
436 {
437 switch (crm) {
438 case 0:
439 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
440 break;
441 case 1:
442 pxa2xx_perf_write(opaque, op2, reg, crm, value);
443 break;
444 case 2:
445 switch (reg) {
446 case CPPMN0:
447 case CPPMN1:
448 case CPPMN2:
449 case CPPMN3:
450 return;
451 }
452 /* Fall through */
453 default:
454 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
455 break;
456 }
457 }
458
459 #define MDCNFG 0x00 /* SDRAM Configuration register */
460 #define MDREFR 0x04 /* SDRAM Refresh Control register */
461 #define MSC0 0x08 /* Static Memory Control register 0 */
462 #define MSC1 0x0c /* Static Memory Control register 1 */
463 #define MSC2 0x10 /* Static Memory Control register 2 */
464 #define MECR 0x14 /* Expansion Memory Bus Config register */
465 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
466 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
467 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
468 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
469 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
470 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
471 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
472 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
473 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
474 #define ARB_CNTL 0x48 /* Arbiter Control register */
475 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
476 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
477 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
478 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
479 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
480 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
481 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
482
483 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
484 {
485 PXA2xxState *s = (PXA2xxState *) opaque;
486
487 switch (addr) {
488 case MDCNFG ... SA1110:
489 if ((addr & 3) == 0)
490 return s->mm_regs[addr >> 2];
491
492 default:
493 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
494 break;
495 }
496 return 0;
497 }
498
499 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
500 uint32_t value)
501 {
502 PXA2xxState *s = (PXA2xxState *) opaque;
503
504 switch (addr) {
505 case MDCNFG ... SA1110:
506 if ((addr & 3) == 0) {
507 s->mm_regs[addr >> 2] = value;
508 break;
509 }
510
511 default:
512 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
513 break;
514 }
515 }
516
517 static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
518 pxa2xx_mm_read,
519 pxa2xx_mm_read,
520 pxa2xx_mm_read,
521 };
522
523 static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
524 pxa2xx_mm_write,
525 pxa2xx_mm_write,
526 pxa2xx_mm_write,
527 };
528
529 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
530 {
531 PXA2xxState *s = (PXA2xxState *) opaque;
532 int i;
533
534 for (i = 0; i < 0x1a; i ++)
535 qemu_put_be32s(f, &s->mm_regs[i]);
536 }
537
538 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
539 {
540 PXA2xxState *s = (PXA2xxState *) opaque;
541 int i;
542
543 for (i = 0; i < 0x1a; i ++)
544 qemu_get_be32s(f, &s->mm_regs[i]);
545
546 return 0;
547 }
548
549 /* Synchronous Serial Ports */
550 struct PXA2xxSSPState {
551 qemu_irq irq;
552 int enable;
553
554 uint32_t sscr[2];
555 uint32_t sspsp;
556 uint32_t ssto;
557 uint32_t ssitr;
558 uint32_t sssr;
559 uint8_t sstsa;
560 uint8_t ssrsa;
561 uint8_t ssacd;
562
563 uint32_t rx_fifo[16];
564 int rx_level;
565 int rx_start;
566
567 uint32_t (*readfn)(void *opaque);
568 void (*writefn)(void *opaque, uint32_t value);
569 void *opaque;
570 };
571
572 #define SSCR0 0x00 /* SSP Control register 0 */
573 #define SSCR1 0x04 /* SSP Control register 1 */
574 #define SSSR 0x08 /* SSP Status register */
575 #define SSITR 0x0c /* SSP Interrupt Test register */
576 #define SSDR 0x10 /* SSP Data register */
577 #define SSTO 0x28 /* SSP Time-Out register */
578 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
579 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
580 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
581 #define SSTSS 0x38 /* SSP Time Slot Status register */
582 #define SSACD 0x3c /* SSP Audio Clock Divider register */
583
584 /* Bitfields for above registers */
585 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
586 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
587 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
588 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
589 #define SSCR0_SSE (1 << 7)
590 #define SSCR0_RIM (1 << 22)
591 #define SSCR0_TIM (1 << 23)
592 #define SSCR0_MOD (1 << 31)
593 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
594 #define SSCR1_RIE (1 << 0)
595 #define SSCR1_TIE (1 << 1)
596 #define SSCR1_LBM (1 << 2)
597 #define SSCR1_MWDS (1 << 5)
598 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
599 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
600 #define SSCR1_EFWR (1 << 14)
601 #define SSCR1_PINTE (1 << 18)
602 #define SSCR1_TINTE (1 << 19)
603 #define SSCR1_RSRE (1 << 20)
604 #define SSCR1_TSRE (1 << 21)
605 #define SSCR1_EBCEI (1 << 29)
606 #define SSITR_INT (7 << 5)
607 #define SSSR_TNF (1 << 2)
608 #define SSSR_RNE (1 << 3)
609 #define SSSR_TFS (1 << 5)
610 #define SSSR_RFS (1 << 6)
611 #define SSSR_ROR (1 << 7)
612 #define SSSR_PINT (1 << 18)
613 #define SSSR_TINT (1 << 19)
614 #define SSSR_EOC (1 << 20)
615 #define SSSR_TUR (1 << 21)
616 #define SSSR_BCE (1 << 23)
617 #define SSSR_RW 0x00bc0080
618
619 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
620 {
621 int level = 0;
622
623 level |= s->ssitr & SSITR_INT;
624 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
625 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
626 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
627 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
628 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
629 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
630 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
631 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
632 qemu_set_irq(s->irq, !!level);
633 }
634
635 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
636 {
637 s->sssr &= ~(0xf << 12); /* Clear RFL */
638 s->sssr &= ~(0xf << 8); /* Clear TFL */
639 s->sssr &= ~SSSR_TNF;
640 if (s->enable) {
641 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
642 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
643 s->sssr |= SSSR_RFS;
644 else
645 s->sssr &= ~SSSR_RFS;
646 if (0 <= SSCR1_TFT(s->sscr[1]))
647 s->sssr |= SSSR_TFS;
648 else
649 s->sssr &= ~SSSR_TFS;
650 if (s->rx_level)
651 s->sssr |= SSSR_RNE;
652 else
653 s->sssr &= ~SSSR_RNE;
654 s->sssr |= SSSR_TNF;
655 }
656
657 pxa2xx_ssp_int_update(s);
658 }
659
660 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
661 {
662 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
663 uint32_t retval;
664
665 switch (addr) {
666 case SSCR0:
667 return s->sscr[0];
668 case SSCR1:
669 return s->sscr[1];
670 case SSPSP:
671 return s->sspsp;
672 case SSTO:
673 return s->ssto;
674 case SSITR:
675 return s->ssitr;
676 case SSSR:
677 return s->sssr | s->ssitr;
678 case SSDR:
679 if (!s->enable)
680 return 0xffffffff;
681 if (s->rx_level < 1) {
682 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
683 return 0xffffffff;
684 }
685 s->rx_level --;
686 retval = s->rx_fifo[s->rx_start ++];
687 s->rx_start &= 0xf;
688 pxa2xx_ssp_fifo_update(s);
689 return retval;
690 case SSTSA:
691 return s->sstsa;
692 case SSRSA:
693 return s->ssrsa;
694 case SSTSS:
695 return 0;
696 case SSACD:
697 return s->ssacd;
698 default:
699 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700 break;
701 }
702 return 0;
703 }
704
705 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
706 uint32_t value)
707 {
708 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
709
710 switch (addr) {
711 case SSCR0:
712 s->sscr[0] = value & 0xc7ffffff;
713 s->enable = value & SSCR0_SSE;
714 if (value & SSCR0_MOD)
715 printf("%s: Attempt to use network mode\n", __FUNCTION__);
716 if (s->enable && SSCR0_DSS(value) < 4)
717 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
718 SSCR0_DSS(value));
719 if (!(value & SSCR0_SSE)) {
720 s->sssr = 0;
721 s->ssitr = 0;
722 s->rx_level = 0;
723 }
724 pxa2xx_ssp_fifo_update(s);
725 break;
726
727 case SSCR1:
728 s->sscr[1] = value;
729 if (value & (SSCR1_LBM | SSCR1_EFWR))
730 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
731 pxa2xx_ssp_fifo_update(s);
732 break;
733
734 case SSPSP:
735 s->sspsp = value;
736 break;
737
738 case SSTO:
739 s->ssto = value;
740 break;
741
742 case SSITR:
743 s->ssitr = value & SSITR_INT;
744 pxa2xx_ssp_int_update(s);
745 break;
746
747 case SSSR:
748 s->sssr &= ~(value & SSSR_RW);
749 pxa2xx_ssp_int_update(s);
750 break;
751
752 case SSDR:
753 if (SSCR0_UWIRE(s->sscr[0])) {
754 if (s->sscr[1] & SSCR1_MWDS)
755 value &= 0xffff;
756 else
757 value &= 0xff;
758 } else
759 /* Note how 32bits overflow does no harm here */
760 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
761
762 /* Data goes from here to the Tx FIFO and is shifted out from
763 * there directly to the slave, no need to buffer it.
764 */
765 if (s->enable) {
766 if (s->writefn)
767 s->writefn(s->opaque, value);
768
769 if (s->rx_level < 0x10) {
770 if (s->readfn)
771 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
772 s->readfn(s->opaque);
773 else
774 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
775 } else
776 s->sssr |= SSSR_ROR;
777 }
778 pxa2xx_ssp_fifo_update(s);
779 break;
780
781 case SSTSA:
782 s->sstsa = value;
783 break;
784
785 case SSRSA:
786 s->ssrsa = value;
787 break;
788
789 case SSACD:
790 s->ssacd = value;
791 break;
792
793 default:
794 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
795 break;
796 }
797 }
798
799 void pxa2xx_ssp_attach(PXA2xxSSPState *port,
800 uint32_t (*readfn)(void *opaque),
801 void (*writefn)(void *opaque, uint32_t value), void *opaque)
802 {
803 if (!port) {
804 printf("%s: no such SSP\n", __FUNCTION__);
805 exit(-1);
806 }
807
808 port->opaque = opaque;
809 port->readfn = readfn;
810 port->writefn = writefn;
811 }
812
813 static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
814 pxa2xx_ssp_read,
815 pxa2xx_ssp_read,
816 pxa2xx_ssp_read,
817 };
818
819 static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
820 pxa2xx_ssp_write,
821 pxa2xx_ssp_write,
822 pxa2xx_ssp_write,
823 };
824
825 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
826 {
827 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
828 int i;
829
830 qemu_put_be32(f, s->enable);
831
832 qemu_put_be32s(f, &s->sscr[0]);
833 qemu_put_be32s(f, &s->sscr[1]);
834 qemu_put_be32s(f, &s->sspsp);
835 qemu_put_be32s(f, &s->ssto);
836 qemu_put_be32s(f, &s->ssitr);
837 qemu_put_be32s(f, &s->sssr);
838 qemu_put_8s(f, &s->sstsa);
839 qemu_put_8s(f, &s->ssrsa);
840 qemu_put_8s(f, &s->ssacd);
841
842 qemu_put_byte(f, s->rx_level);
843 for (i = 0; i < s->rx_level; i ++)
844 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
845 }
846
847 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
848 {
849 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
850 int i;
851
852 s->enable = qemu_get_be32(f);
853
854 qemu_get_be32s(f, &s->sscr[0]);
855 qemu_get_be32s(f, &s->sscr[1]);
856 qemu_get_be32s(f, &s->sspsp);
857 qemu_get_be32s(f, &s->ssto);
858 qemu_get_be32s(f, &s->ssitr);
859 qemu_get_be32s(f, &s->sssr);
860 qemu_get_8s(f, &s->sstsa);
861 qemu_get_8s(f, &s->ssrsa);
862 qemu_get_8s(f, &s->ssacd);
863
864 s->rx_level = qemu_get_byte(f);
865 s->rx_start = 0;
866 for (i = 0; i < s->rx_level; i ++)
867 s->rx_fifo[i] = qemu_get_byte(f);
868
869 return 0;
870 }
871
872 /* Real-Time Clock */
873 #define RCNR 0x00 /* RTC Counter register */
874 #define RTAR 0x04 /* RTC Alarm register */
875 #define RTSR 0x08 /* RTC Status register */
876 #define RTTR 0x0c /* RTC Timer Trim register */
877 #define RDCR 0x10 /* RTC Day Counter register */
878 #define RYCR 0x14 /* RTC Year Counter register */
879 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
880 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
881 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
882 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
883 #define SWCR 0x28 /* RTC Stopwatch Counter register */
884 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
885 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
886 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
887 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
888
889 static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
890 {
891 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
892 }
893
894 static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
895 {
896 int64_t rt = qemu_get_clock(rt_clock);
897 s->last_rcnr += ((rt - s->last_hz) << 15) /
898 (1000 * ((s->rttr & 0xffff) + 1));
899 s->last_rdcr += ((rt - s->last_hz) << 15) /
900 (1000 * ((s->rttr & 0xffff) + 1));
901 s->last_hz = rt;
902 }
903
904 static void pxa2xx_rtc_swupdate(PXA2xxState *s)
905 {
906 int64_t rt = qemu_get_clock(rt_clock);
907 if (s->rtsr & (1 << 12))
908 s->last_swcr += (rt - s->last_sw) / 10;
909 s->last_sw = rt;
910 }
911
912 static void pxa2xx_rtc_piupdate(PXA2xxState *s)
913 {
914 int64_t rt = qemu_get_clock(rt_clock);
915 if (s->rtsr & (1 << 15))
916 s->last_swcr += rt - s->last_pi;
917 s->last_pi = rt;
918 }
919
920 static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
921 uint32_t rtsr)
922 {
923 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
924 qemu_mod_timer(s->rtc_hz, s->last_hz +
925 (((s->rtar - s->last_rcnr) * 1000 *
926 ((s->rttr & 0xffff) + 1)) >> 15));
927 else
928 qemu_del_timer(s->rtc_hz);
929
930 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
931 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
932 (((s->rdar1 - s->last_rdcr) * 1000 *
933 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
934 else
935 qemu_del_timer(s->rtc_rdal1);
936
937 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
938 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
939 (((s->rdar2 - s->last_rdcr) * 1000 *
940 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
941 else
942 qemu_del_timer(s->rtc_rdal2);
943
944 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
945 qemu_mod_timer(s->rtc_swal1, s->last_sw +
946 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
947 else
948 qemu_del_timer(s->rtc_swal1);
949
950 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
951 qemu_mod_timer(s->rtc_swal2, s->last_sw +
952 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
953 else
954 qemu_del_timer(s->rtc_swal2);
955
956 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
957 qemu_mod_timer(s->rtc_pi, s->last_pi +
958 (s->piar & 0xffff) - s->last_rtcpicr);
959 else
960 qemu_del_timer(s->rtc_pi);
961 }
962
963 static inline void pxa2xx_rtc_hz_tick(void *opaque)
964 {
965 PXA2xxState *s = (PXA2xxState *) opaque;
966 s->rtsr |= (1 << 0);
967 pxa2xx_rtc_alarm_update(s, s->rtsr);
968 pxa2xx_rtc_int_update(s);
969 }
970
971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
972 {
973 PXA2xxState *s = (PXA2xxState *) opaque;
974 s->rtsr |= (1 << 4);
975 pxa2xx_rtc_alarm_update(s, s->rtsr);
976 pxa2xx_rtc_int_update(s);
977 }
978
979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
980 {
981 PXA2xxState *s = (PXA2xxState *) opaque;
982 s->rtsr |= (1 << 6);
983 pxa2xx_rtc_alarm_update(s, s->rtsr);
984 pxa2xx_rtc_int_update(s);
985 }
986
987 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
988 {
989 PXA2xxState *s = (PXA2xxState *) opaque;
990 s->rtsr |= (1 << 8);
991 pxa2xx_rtc_alarm_update(s, s->rtsr);
992 pxa2xx_rtc_int_update(s);
993 }
994
995 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
996 {
997 PXA2xxState *s = (PXA2xxState *) opaque;
998 s->rtsr |= (1 << 10);
999 pxa2xx_rtc_alarm_update(s, s->rtsr);
1000 pxa2xx_rtc_int_update(s);
1001 }
1002
1003 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1004 {
1005 PXA2xxState *s = (PXA2xxState *) opaque;
1006 s->rtsr |= (1 << 13);
1007 pxa2xx_rtc_piupdate(s);
1008 s->last_rtcpicr = 0;
1009 pxa2xx_rtc_alarm_update(s, s->rtsr);
1010 pxa2xx_rtc_int_update(s);
1011 }
1012
1013 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1014 {
1015 PXA2xxState *s = (PXA2xxState *) opaque;
1016
1017 switch (addr) {
1018 case RTTR:
1019 return s->rttr;
1020 case RTSR:
1021 return s->rtsr;
1022 case RTAR:
1023 return s->rtar;
1024 case RDAR1:
1025 return s->rdar1;
1026 case RDAR2:
1027 return s->rdar2;
1028 case RYAR1:
1029 return s->ryar1;
1030 case RYAR2:
1031 return s->ryar2;
1032 case SWAR1:
1033 return s->swar1;
1034 case SWAR2:
1035 return s->swar2;
1036 case PIAR:
1037 return s->piar;
1038 case RCNR:
1039 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1040 (1000 * ((s->rttr & 0xffff) + 1));
1041 case RDCR:
1042 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1043 (1000 * ((s->rttr & 0xffff) + 1));
1044 case RYCR:
1045 return s->last_rycr;
1046 case SWCR:
1047 if (s->rtsr & (1 << 12))
1048 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1049 else
1050 return s->last_swcr;
1051 default:
1052 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1053 break;
1054 }
1055 return 0;
1056 }
1057
1058 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1059 uint32_t value)
1060 {
1061 PXA2xxState *s = (PXA2xxState *) opaque;
1062
1063 switch (addr) {
1064 case RTTR:
1065 if (!(s->rttr & (1 << 31))) {
1066 pxa2xx_rtc_hzupdate(s);
1067 s->rttr = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 }
1070 break;
1071
1072 case RTSR:
1073 if ((s->rtsr ^ value) & (1 << 15))
1074 pxa2xx_rtc_piupdate(s);
1075
1076 if ((s->rtsr ^ value) & (1 << 12))
1077 pxa2xx_rtc_swupdate(s);
1078
1079 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1080 pxa2xx_rtc_alarm_update(s, value);
1081
1082 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1083 pxa2xx_rtc_int_update(s);
1084 break;
1085
1086 case RTAR:
1087 s->rtar = value;
1088 pxa2xx_rtc_alarm_update(s, s->rtsr);
1089 break;
1090
1091 case RDAR1:
1092 s->rdar1 = value;
1093 pxa2xx_rtc_alarm_update(s, s->rtsr);
1094 break;
1095
1096 case RDAR2:
1097 s->rdar2 = value;
1098 pxa2xx_rtc_alarm_update(s, s->rtsr);
1099 break;
1100
1101 case RYAR1:
1102 s->ryar1 = value;
1103 pxa2xx_rtc_alarm_update(s, s->rtsr);
1104 break;
1105
1106 case RYAR2:
1107 s->ryar2 = value;
1108 pxa2xx_rtc_alarm_update(s, s->rtsr);
1109 break;
1110
1111 case SWAR1:
1112 pxa2xx_rtc_swupdate(s);
1113 s->swar1 = value;
1114 s->last_swcr = 0;
1115 pxa2xx_rtc_alarm_update(s, s->rtsr);
1116 break;
1117
1118 case SWAR2:
1119 s->swar2 = value;
1120 pxa2xx_rtc_alarm_update(s, s->rtsr);
1121 break;
1122
1123 case PIAR:
1124 s->piar = value;
1125 pxa2xx_rtc_alarm_update(s, s->rtsr);
1126 break;
1127
1128 case RCNR:
1129 pxa2xx_rtc_hzupdate(s);
1130 s->last_rcnr = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case RDCR:
1135 pxa2xx_rtc_hzupdate(s);
1136 s->last_rdcr = value;
1137 pxa2xx_rtc_alarm_update(s, s->rtsr);
1138 break;
1139
1140 case RYCR:
1141 s->last_rycr = value;
1142 break;
1143
1144 case SWCR:
1145 pxa2xx_rtc_swupdate(s);
1146 s->last_swcr = value;
1147 pxa2xx_rtc_alarm_update(s, s->rtsr);
1148 break;
1149
1150 case RTCPICR:
1151 pxa2xx_rtc_piupdate(s);
1152 s->last_rtcpicr = value & 0xffff;
1153 pxa2xx_rtc_alarm_update(s, s->rtsr);
1154 break;
1155
1156 default:
1157 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1158 }
1159 }
1160
1161 static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1162 pxa2xx_rtc_read,
1163 pxa2xx_rtc_read,
1164 pxa2xx_rtc_read,
1165 };
1166
1167 static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1168 pxa2xx_rtc_write,
1169 pxa2xx_rtc_write,
1170 pxa2xx_rtc_write,
1171 };
1172
1173 static void pxa2xx_rtc_init(PXA2xxState *s)
1174 {
1175 struct tm tm;
1176 int wom;
1177
1178 s->rttr = 0x7fff;
1179 s->rtsr = 0;
1180
1181 qemu_get_timedate(&tm, 0);
1182 wom = ((tm.tm_mday - 1) / 7) + 1;
1183
1184 s->last_rcnr = (uint32_t) mktimegm(&tm);
1185 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1186 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1187 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1188 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1189 s->last_swcr = (tm.tm_hour << 19) |
1190 (tm.tm_min << 13) | (tm.tm_sec << 7);
1191 s->last_rtcpicr = 0;
1192 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1193
1194 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1195 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1196 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1197 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1198 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1199 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1200 }
1201
1202 static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1203 {
1204 PXA2xxState *s = (PXA2xxState *) opaque;
1205
1206 pxa2xx_rtc_hzupdate(s);
1207 pxa2xx_rtc_piupdate(s);
1208 pxa2xx_rtc_swupdate(s);
1209
1210 qemu_put_be32s(f, &s->rttr);
1211 qemu_put_be32s(f, &s->rtsr);
1212 qemu_put_be32s(f, &s->rtar);
1213 qemu_put_be32s(f, &s->rdar1);
1214 qemu_put_be32s(f, &s->rdar2);
1215 qemu_put_be32s(f, &s->ryar1);
1216 qemu_put_be32s(f, &s->ryar2);
1217 qemu_put_be32s(f, &s->swar1);
1218 qemu_put_be32s(f, &s->swar2);
1219 qemu_put_be32s(f, &s->piar);
1220 qemu_put_be32s(f, &s->last_rcnr);
1221 qemu_put_be32s(f, &s->last_rdcr);
1222 qemu_put_be32s(f, &s->last_rycr);
1223 qemu_put_be32s(f, &s->last_swcr);
1224 qemu_put_be32s(f, &s->last_rtcpicr);
1225 qemu_put_sbe64s(f, &s->last_hz);
1226 qemu_put_sbe64s(f, &s->last_sw);
1227 qemu_put_sbe64s(f, &s->last_pi);
1228 }
1229
1230 static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1231 {
1232 PXA2xxState *s = (PXA2xxState *) opaque;
1233
1234 qemu_get_be32s(f, &s->rttr);
1235 qemu_get_be32s(f, &s->rtsr);
1236 qemu_get_be32s(f, &s->rtar);
1237 qemu_get_be32s(f, &s->rdar1);
1238 qemu_get_be32s(f, &s->rdar2);
1239 qemu_get_be32s(f, &s->ryar1);
1240 qemu_get_be32s(f, &s->ryar2);
1241 qemu_get_be32s(f, &s->swar1);
1242 qemu_get_be32s(f, &s->swar2);
1243 qemu_get_be32s(f, &s->piar);
1244 qemu_get_be32s(f, &s->last_rcnr);
1245 qemu_get_be32s(f, &s->last_rdcr);
1246 qemu_get_be32s(f, &s->last_rycr);
1247 qemu_get_be32s(f, &s->last_swcr);
1248 qemu_get_be32s(f, &s->last_rtcpicr);
1249 qemu_get_sbe64s(f, &s->last_hz);
1250 qemu_get_sbe64s(f, &s->last_sw);
1251 qemu_get_sbe64s(f, &s->last_pi);
1252
1253 pxa2xx_rtc_alarm_update(s, s->rtsr);
1254
1255 return 0;
1256 }
1257
1258 /* I2C Interface */
1259 typedef struct {
1260 i2c_slave i2c;
1261 PXA2xxI2CState *host;
1262 } PXA2xxI2CSlaveState;
1263
1264 struct PXA2xxI2CState {
1265 PXA2xxI2CSlaveState *slave;
1266 i2c_bus *bus;
1267 qemu_irq irq;
1268 target_phys_addr_t offset;
1269
1270 uint16_t control;
1271 uint16_t status;
1272 uint8_t ibmr;
1273 uint8_t data;
1274 };
1275
1276 #define IBMR 0x80 /* I2C Bus Monitor register */
1277 #define IDBR 0x88 /* I2C Data Buffer register */
1278 #define ICR 0x90 /* I2C Control register */
1279 #define ISR 0x98 /* I2C Status register */
1280 #define ISAR 0xa0 /* I2C Slave Address register */
1281
1282 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1283 {
1284 uint16_t level = 0;
1285 level |= s->status & s->control & (1 << 10); /* BED */
1286 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1287 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1288 level |= s->status & (1 << 9); /* SAD */
1289 qemu_set_irq(s->irq, !!level);
1290 }
1291
1292 /* These are only stubs now. */
1293 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1294 {
1295 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1296 PXA2xxI2CState *s = slave->host;
1297
1298 switch (event) {
1299 case I2C_START_SEND:
1300 s->status |= (1 << 9); /* set SAD */
1301 s->status &= ~(1 << 0); /* clear RWM */
1302 break;
1303 case I2C_START_RECV:
1304 s->status |= (1 << 9); /* set SAD */
1305 s->status |= 1 << 0; /* set RWM */
1306 break;
1307 case I2C_FINISH:
1308 s->status |= (1 << 4); /* set SSD */
1309 break;
1310 case I2C_NACK:
1311 s->status |= 1 << 1; /* set ACKNAK */
1312 break;
1313 }
1314 pxa2xx_i2c_update(s);
1315 }
1316
1317 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1318 {
1319 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1320 PXA2xxI2CState *s = slave->host;
1321 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1322 return 0;
1323
1324 if (s->status & (1 << 0)) { /* RWM */
1325 s->status |= 1 << 6; /* set ITE */
1326 }
1327 pxa2xx_i2c_update(s);
1328
1329 return s->data;
1330 }
1331
1332 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1333 {
1334 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1335 PXA2xxI2CState *s = slave->host;
1336 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1337 return 1;
1338
1339 if (!(s->status & (1 << 0))) { /* RWM */
1340 s->status |= 1 << 7; /* set IRF */
1341 s->data = data;
1342 }
1343 pxa2xx_i2c_update(s);
1344
1345 return 1;
1346 }
1347
1348 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1349 {
1350 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1351
1352 addr -= s->offset;
1353 switch (addr) {
1354 case ICR:
1355 return s->control;
1356 case ISR:
1357 return s->status | (i2c_bus_busy(s->bus) << 2);
1358 case ISAR:
1359 return s->slave->i2c.address;
1360 case IDBR:
1361 return s->data;
1362 case IBMR:
1363 if (s->status & (1 << 2))
1364 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1365 else
1366 s->ibmr = 0;
1367 return s->ibmr;
1368 default:
1369 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1370 break;
1371 }
1372 return 0;
1373 }
1374
1375 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1376 uint32_t value)
1377 {
1378 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1379 int ack;
1380
1381 addr -= s->offset;
1382 switch (addr) {
1383 case ICR:
1384 s->control = value & 0xfff7;
1385 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1386 /* TODO: slave mode */
1387 if (value & (1 << 0)) { /* START condition */
1388 if (s->data & 1)
1389 s->status |= 1 << 0; /* set RWM */
1390 else
1391 s->status &= ~(1 << 0); /* clear RWM */
1392 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1393 } else {
1394 if (s->status & (1 << 0)) { /* RWM */
1395 s->data = i2c_recv(s->bus);
1396 if (value & (1 << 2)) /* ACKNAK */
1397 i2c_nack(s->bus);
1398 ack = 1;
1399 } else
1400 ack = !i2c_send(s->bus, s->data);
1401 }
1402
1403 if (value & (1 << 1)) /* STOP condition */
1404 i2c_end_transfer(s->bus);
1405
1406 if (ack) {
1407 if (value & (1 << 0)) /* START condition */
1408 s->status |= 1 << 6; /* set ITE */
1409 else
1410 if (s->status & (1 << 0)) /* RWM */
1411 s->status |= 1 << 7; /* set IRF */
1412 else
1413 s->status |= 1 << 6; /* set ITE */
1414 s->status &= ~(1 << 1); /* clear ACKNAK */
1415 } else {
1416 s->status |= 1 << 6; /* set ITE */
1417 s->status |= 1 << 10; /* set BED */
1418 s->status |= 1 << 1; /* set ACKNAK */
1419 }
1420 }
1421 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1422 if (value & (1 << 4)) /* MA */
1423 i2c_end_transfer(s->bus);
1424 pxa2xx_i2c_update(s);
1425 break;
1426
1427 case ISR:
1428 s->status &= ~(value & 0x07f0);
1429 pxa2xx_i2c_update(s);
1430 break;
1431
1432 case ISAR:
1433 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1434 break;
1435
1436 case IDBR:
1437 s->data = value & 0xff;
1438 break;
1439
1440 default:
1441 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1442 }
1443 }
1444
1445 static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1446 pxa2xx_i2c_read,
1447 pxa2xx_i2c_read,
1448 pxa2xx_i2c_read,
1449 };
1450
1451 static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1452 pxa2xx_i2c_write,
1453 pxa2xx_i2c_write,
1454 pxa2xx_i2c_write,
1455 };
1456
1457 static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1458 {
1459 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1460
1461 qemu_put_be16s(f, &s->control);
1462 qemu_put_be16s(f, &s->status);
1463 qemu_put_8s(f, &s->ibmr);
1464 qemu_put_8s(f, &s->data);
1465
1466 i2c_slave_save(f, &s->slave->i2c);
1467 }
1468
1469 static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1470 {
1471 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1472
1473 if (version_id != 1)
1474 return -EINVAL;
1475
1476 qemu_get_be16s(f, &s->control);
1477 qemu_get_be16s(f, &s->status);
1478 qemu_get_8s(f, &s->ibmr);
1479 qemu_get_8s(f, &s->data);
1480
1481 i2c_slave_load(f, &s->slave->i2c);
1482 return 0;
1483 }
1484
1485 static void pxa2xx_i2c_slave_init(i2c_slave *i2c)
1486 {
1487 /* Nothing to do. */
1488 }
1489
1490 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1491 .init = pxa2xx_i2c_slave_init,
1492 .event = pxa2xx_i2c_event,
1493 .recv = pxa2xx_i2c_rx,
1494 .send = pxa2xx_i2c_tx
1495 };
1496
1497 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1498 qemu_irq irq, uint32_t region_size)
1499 {
1500 int iomemtype;
1501 DeviceState *dev;
1502 PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));
1503
1504 /* FIXME: Should the slave device really be on a separate bus? */
1505 dev = i2c_create_slave(i2c_init_bus(), "pxa2xx-i2c-slave", 0);
1506 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1507 s->slave->host = s;
1508
1509 s->irq = irq;
1510 s->bus = i2c_init_bus();
1511 s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
1512
1513 iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1514 pxa2xx_i2c_writefn, s);
1515 cpu_register_physical_memory(base & ~region_size,
1516 region_size + 1, iomemtype);
1517
1518 register_savevm("pxa2xx_i2c", base, 1,
1519 pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1520
1521 return s;
1522 }
1523
1524 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1525 {
1526 return s->bus;
1527 }
1528
1529 /* PXA Inter-IC Sound Controller */
1530 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1531 {
1532 i2s->rx_len = 0;
1533 i2s->tx_len = 0;
1534 i2s->fifo_len = 0;
1535 i2s->clk = 0x1a;
1536 i2s->control[0] = 0x00;
1537 i2s->control[1] = 0x00;
1538 i2s->status = 0x00;
1539 i2s->mask = 0x00;
1540 }
1541
1542 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1543 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1544 #define SACR_DREC(val) (val & (1 << 3))
1545 #define SACR_DPRL(val) (val & (1 << 4))
1546
1547 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1548 {
1549 int rfs, tfs;
1550 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1551 !SACR_DREC(i2s->control[1]);
1552 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1553 i2s->enable && !SACR_DPRL(i2s->control[1]);
1554
1555 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1556 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1557
1558 i2s->status &= 0xe0;
1559 if (i2s->fifo_len < 16 || !i2s->enable)
1560 i2s->status |= 1 << 0; /* TNF */
1561 if (i2s->rx_len)
1562 i2s->status |= 1 << 1; /* RNE */
1563 if (i2s->enable)
1564 i2s->status |= 1 << 2; /* BSY */
1565 if (tfs)
1566 i2s->status |= 1 << 3; /* TFS */
1567 if (rfs)
1568 i2s->status |= 1 << 4; /* RFS */
1569 if (!(i2s->tx_len && i2s->enable))
1570 i2s->status |= i2s->fifo_len << 8; /* TFL */
1571 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1572
1573 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1574 }
1575
1576 #define SACR0 0x00 /* Serial Audio Global Control register */
1577 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1578 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1579 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1580 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1581 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1582 #define SADR 0x80 /* Serial Audio Data register */
1583
1584 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1585 {
1586 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1587
1588 switch (addr) {
1589 case SACR0:
1590 return s->control[0];
1591 case SACR1:
1592 return s->control[1];
1593 case SASR0:
1594 return s->status;
1595 case SAIMR:
1596 return s->mask;
1597 case SAICR:
1598 return 0;
1599 case SADIV:
1600 return s->clk;
1601 case SADR:
1602 if (s->rx_len > 0) {
1603 s->rx_len --;
1604 pxa2xx_i2s_update(s);
1605 return s->codec_in(s->opaque);
1606 }
1607 return 0;
1608 default:
1609 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1610 break;
1611 }
1612 return 0;
1613 }
1614
1615 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1616 uint32_t value)
1617 {
1618 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1619 uint32_t *sample;
1620
1621 switch (addr) {
1622 case SACR0:
1623 if (value & (1 << 3)) /* RST */
1624 pxa2xx_i2s_reset(s);
1625 s->control[0] = value & 0xff3d;
1626 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1627 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1628 s->codec_out(s->opaque, *sample);
1629 s->status &= ~(1 << 7); /* I2SOFF */
1630 }
1631 if (value & (1 << 4)) /* EFWR */
1632 printf("%s: Attempt to use special function\n", __FUNCTION__);
1633 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1634 pxa2xx_i2s_update(s);
1635 break;
1636 case SACR1:
1637 s->control[1] = value & 0x0039;
1638 if (value & (1 << 5)) /* ENLBF */
1639 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1640 if (value & (1 << 4)) /* DPRL */
1641 s->fifo_len = 0;
1642 pxa2xx_i2s_update(s);
1643 break;
1644 case SAIMR:
1645 s->mask = value & 0x0078;
1646 pxa2xx_i2s_update(s);
1647 break;
1648 case SAICR:
1649 s->status &= ~(value & (3 << 5));
1650 pxa2xx_i2s_update(s);
1651 break;
1652 case SADIV:
1653 s->clk = value & 0x007f;
1654 break;
1655 case SADR:
1656 if (s->tx_len && s->enable) {
1657 s->tx_len --;
1658 pxa2xx_i2s_update(s);
1659 s->codec_out(s->opaque, value);
1660 } else if (s->fifo_len < 16) {
1661 s->fifo[s->fifo_len ++] = value;
1662 pxa2xx_i2s_update(s);
1663 }
1664 break;
1665 default:
1666 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1667 }
1668 }
1669
1670 static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1671 pxa2xx_i2s_read,
1672 pxa2xx_i2s_read,
1673 pxa2xx_i2s_read,
1674 };
1675
1676 static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1677 pxa2xx_i2s_write,
1678 pxa2xx_i2s_write,
1679 pxa2xx_i2s_write,
1680 };
1681
1682 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1683 {
1684 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1685
1686 qemu_put_be32s(f, &s->control[0]);
1687 qemu_put_be32s(f, &s->control[1]);
1688 qemu_put_be32s(f, &s->status);
1689 qemu_put_be32s(f, &s->mask);
1690 qemu_put_be32s(f, &s->clk);
1691
1692 qemu_put_be32(f, s->enable);
1693 qemu_put_be32(f, s->rx_len);
1694 qemu_put_be32(f, s->tx_len);
1695 qemu_put_be32(f, s->fifo_len);
1696 }
1697
1698 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1699 {
1700 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1701
1702 qemu_get_be32s(f, &s->control[0]);
1703 qemu_get_be32s(f, &s->control[1]);
1704 qemu_get_be32s(f, &s->status);
1705 qemu_get_be32s(f, &s->mask);
1706 qemu_get_be32s(f, &s->clk);
1707
1708 s->enable = qemu_get_be32(f);
1709 s->rx_len = qemu_get_be32(f);
1710 s->tx_len = qemu_get_be32(f);
1711 s->fifo_len = qemu_get_be32(f);
1712
1713 return 0;
1714 }
1715
1716 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1717 {
1718 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1719 uint32_t *sample;
1720
1721 /* Signal FIFO errors */
1722 if (s->enable && s->tx_len)
1723 s->status |= 1 << 5; /* TUR */
1724 if (s->enable && s->rx_len)
1725 s->status |= 1 << 6; /* ROR */
1726
1727 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1728 * handle the cases where it makes a difference. */
1729 s->tx_len = tx - s->fifo_len;
1730 s->rx_len = rx;
1731 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1732 if (s->enable)
1733 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1734 s->codec_out(s->opaque, *sample);
1735 pxa2xx_i2s_update(s);
1736 }
1737
1738 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1739 qemu_irq irq, PXA2xxDMAState *dma)
1740 {
1741 int iomemtype;
1742 PXA2xxI2SState *s = (PXA2xxI2SState *)
1743 qemu_mallocz(sizeof(PXA2xxI2SState));
1744
1745 s->irq = irq;
1746 s->dma = dma;
1747 s->data_req = pxa2xx_i2s_data_req;
1748
1749 pxa2xx_i2s_reset(s);
1750
1751 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1752 pxa2xx_i2s_writefn, s);
1753 cpu_register_physical_memory(base, 0x100000, iomemtype);
1754
1755 register_savevm("pxa2xx_i2s", base, 0,
1756 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1757
1758 return s;
1759 }
1760
1761 /* PXA Fast Infra-red Communications Port */
1762 struct PXA2xxFIrState {
1763 qemu_irq irq;
1764 PXA2xxDMAState *dma;
1765 int enable;
1766 CharDriverState *chr;
1767
1768 uint8_t control[3];
1769 uint8_t status[2];
1770
1771 int rx_len;
1772 int rx_start;
1773 uint8_t rx_fifo[64];
1774 };
1775
1776 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1777 {
1778 s->control[0] = 0x00;
1779 s->control[1] = 0x00;
1780 s->control[2] = 0x00;
1781 s->status[0] = 0x00;
1782 s->status[1] = 0x00;
1783 s->enable = 0;
1784 }
1785
1786 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1787 {
1788 static const int tresh[4] = { 8, 16, 32, 0 };
1789 int intr = 0;
1790 if ((s->control[0] & (1 << 4)) && /* RXE */
1791 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1792 s->status[0] |= 1 << 4; /* RFS */
1793 else
1794 s->status[0] &= ~(1 << 4); /* RFS */
1795 if (s->control[0] & (1 << 3)) /* TXE */
1796 s->status[0] |= 1 << 3; /* TFS */
1797 else
1798 s->status[0] &= ~(1 << 3); /* TFS */
1799 if (s->rx_len)
1800 s->status[1] |= 1 << 2; /* RNE */
1801 else
1802 s->status[1] &= ~(1 << 2); /* RNE */
1803 if (s->control[0] & (1 << 4)) /* RXE */
1804 s->status[1] |= 1 << 0; /* RSY */
1805 else
1806 s->status[1] &= ~(1 << 0); /* RSY */
1807
1808 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1809 (s->status[0] & (1 << 4)); /* RFS */
1810 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1811 (s->status[0] & (1 << 3)); /* TFS */
1812 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1813 (s->status[0] & (1 << 6)); /* EOC */
1814 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1815 (s->status[0] & (1 << 1)); /* TUR */
1816 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1817
1818 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1819 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1820
1821 qemu_set_irq(s->irq, intr && s->enable);
1822 }
1823
1824 #define ICCR0 0x00 /* FICP Control register 0 */
1825 #define ICCR1 0x04 /* FICP Control register 1 */
1826 #define ICCR2 0x08 /* FICP Control register 2 */
1827 #define ICDR 0x0c /* FICP Data register */
1828 #define ICSR0 0x14 /* FICP Status register 0 */
1829 #define ICSR1 0x18 /* FICP Status register 1 */
1830 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1831
1832 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1833 {
1834 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1835 uint8_t ret;
1836
1837 switch (addr) {
1838 case ICCR0:
1839 return s->control[0];
1840 case ICCR1:
1841 return s->control[1];
1842 case ICCR2:
1843 return s->control[2];
1844 case ICDR:
1845 s->status[0] &= ~0x01;
1846 s->status[1] &= ~0x72;
1847 if (s->rx_len) {
1848 s->rx_len --;
1849 ret = s->rx_fifo[s->rx_start ++];
1850 s->rx_start &= 63;
1851 pxa2xx_fir_update(s);
1852 return ret;
1853 }
1854 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1855 break;
1856 case ICSR0:
1857 return s->status[0];
1858 case ICSR1:
1859 return s->status[1] | (1 << 3); /* TNF */
1860 case ICFOR:
1861 return s->rx_len;
1862 default:
1863 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1864 break;
1865 }
1866 return 0;
1867 }
1868
1869 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1870 uint32_t value)
1871 {
1872 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1873 uint8_t ch;
1874
1875 switch (addr) {
1876 case ICCR0:
1877 s->control[0] = value;
1878 if (!(value & (1 << 4))) /* RXE */
1879 s->rx_len = s->rx_start = 0;
1880 if (!(value & (1 << 3))) /* TXE */
1881 /* Nop */;
1882 s->enable = value & 1; /* ITR */
1883 if (!s->enable)
1884 s->status[0] = 0;
1885 pxa2xx_fir_update(s);
1886 break;
1887 case ICCR1:
1888 s->control[1] = value;
1889 break;
1890 case ICCR2:
1891 s->control[2] = value & 0x3f;
1892 pxa2xx_fir_update(s);
1893 break;
1894 case ICDR:
1895 if (s->control[2] & (1 << 2)) /* TXP */
1896 ch = value;
1897 else
1898 ch = ~value;
1899 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1900 qemu_chr_write(s->chr, &ch, 1);
1901 break;
1902 case ICSR0:
1903 s->status[0] &= ~(value & 0x66);
1904 pxa2xx_fir_update(s);
1905 break;
1906 case ICFOR:
1907 break;
1908 default:
1909 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1910 }
1911 }
1912
1913 static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1914 pxa2xx_fir_read,
1915 pxa2xx_fir_read,
1916 pxa2xx_fir_read,
1917 };
1918
1919 static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1920 pxa2xx_fir_write,
1921 pxa2xx_fir_write,
1922 pxa2xx_fir_write,
1923 };
1924
1925 static int pxa2xx_fir_is_empty(void *opaque)
1926 {
1927 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1928 return (s->rx_len < 64);
1929 }
1930
1931 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1932 {
1933 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1934 if (!(s->control[0] & (1 << 4))) /* RXE */
1935 return;
1936
1937 while (size --) {
1938 s->status[1] |= 1 << 4; /* EOF */
1939 if (s->rx_len >= 64) {
1940 s->status[1] |= 1 << 6; /* ROR */
1941 break;
1942 }
1943
1944 if (s->control[2] & (1 << 3)) /* RXP */
1945 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1946 else
1947 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1948 }
1949
1950 pxa2xx_fir_update(s);
1951 }
1952
1953 static void pxa2xx_fir_event(void *opaque, int event)
1954 {
1955 }
1956
1957 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1958 {
1959 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1960 int i;
1961
1962 qemu_put_be32(f, s->enable);
1963
1964 qemu_put_8s(f, &s->control[0]);
1965 qemu_put_8s(f, &s->control[1]);
1966 qemu_put_8s(f, &s->control[2]);
1967 qemu_put_8s(f, &s->status[0]);
1968 qemu_put_8s(f, &s->status[1]);
1969
1970 qemu_put_byte(f, s->rx_len);
1971 for (i = 0; i < s->rx_len; i ++)
1972 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1973 }
1974
1975 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1976 {
1977 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1978 int i;
1979
1980 s->enable = qemu_get_be32(f);
1981
1982 qemu_get_8s(f, &s->control[0]);
1983 qemu_get_8s(f, &s->control[1]);
1984 qemu_get_8s(f, &s->control[2]);
1985 qemu_get_8s(f, &s->status[0]);
1986 qemu_get_8s(f, &s->status[1]);
1987
1988 s->rx_len = qemu_get_byte(f);
1989 s->rx_start = 0;
1990 for (i = 0; i < s->rx_len; i ++)
1991 s->rx_fifo[i] = qemu_get_byte(f);
1992
1993 return 0;
1994 }
1995
1996 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
1997 qemu_irq irq, PXA2xxDMAState *dma,
1998 CharDriverState *chr)
1999 {
2000 int iomemtype;
2001 PXA2xxFIrState *s = (PXA2xxFIrState *)
2002 qemu_mallocz(sizeof(PXA2xxFIrState));
2003
2004 s->irq = irq;
2005 s->dma = dma;
2006 s->chr = chr;
2007
2008 pxa2xx_fir_reset(s);
2009
2010 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
2011 pxa2xx_fir_writefn, s);
2012 cpu_register_physical_memory(base, 0x1000, iomemtype);
2013
2014 if (chr)
2015 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2016 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2017
2018 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
2019
2020 return s;
2021 }
2022
2023 static void pxa2xx_reset(void *opaque, int line, int level)
2024 {
2025 PXA2xxState *s = (PXA2xxState *) opaque;
2026
2027 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2028 cpu_reset(s->env);
2029 /* TODO: reset peripherals */
2030 }
2031 }
2032
2033 /* Initialise a PXA270 integrated chip (ARM based core). */
2034 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2035 {
2036 PXA2xxState *s;
2037 PXA2xxSSPState *ssp;
2038 int iomemtype, i;
2039 int index;
2040 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2041
2042 if (revision && strncmp(revision, "pxa27", 5)) {
2043 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2044 exit(1);
2045 }
2046 if (!revision)
2047 revision = "pxa270";
2048
2049 s->env = cpu_init(revision);
2050 if (!s->env) {
2051 fprintf(stderr, "Unable to find CPU definition\n");
2052 exit(1);
2053 }
2054 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2055
2056 /* SDRAM & Internal Memory Storage */
2057 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2058 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2059 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2060 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2061
2062 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2063
2064 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2065
2066 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2067 s->pic[PXA27X_PIC_OST_4_11]);
2068
2069 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2070
2071 index = drive_get_index(IF_SD, 0, 0);
2072 if (index == -1) {
2073 fprintf(stderr, "qemu: missing SecureDigital device\n");
2074 exit(1);
2075 }
2076 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2077 s->pic[PXA2XX_PIC_MMC], s->dma);
2078
2079 for (i = 0; pxa270_serial[i].io_base; i ++)
2080 if (serial_hds[i])
2081 serial_mm_init(pxa270_serial[i].io_base, 2,
2082 s->pic[pxa270_serial[i].irqn], 14857000/16,
2083 serial_hds[i], 1);
2084 else
2085 break;
2086 if (serial_hds[i])
2087 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2088 s->dma, serial_hds[i]);
2089
2090 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2091
2092 s->cm_base = 0x41300000;
2093 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2094 s->clkcfg = 0x00000009; /* Turbo mode active */
2095 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2096 pxa2xx_cm_writefn, s);
2097 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2098 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2099
2100 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2101
2102 s->mm_base = 0x48000000;
2103 s->mm_regs[MDMRS >> 2] = 0x00020002;
2104 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2105 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2106 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2107 pxa2xx_mm_writefn, s);
2108 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2109 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2110
2111 s->pm_base = 0x40f00000;
2112 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2113 pxa2xx_pm_writefn, s);
2114 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2115 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2116
2117 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2118 s->ssp = (PXA2xxSSPState **)
2119 qemu_mallocz(sizeof(PXA2xxSSPState *) * i);
2120 ssp = (PXA2xxSSPState *)
2121 qemu_mallocz(sizeof(PXA2xxSSPState) * i);
2122 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2123 target_phys_addr_t ssp_base;
2124 s->ssp[i] = &ssp[i];
2125 ssp_base = pxa27x_ssp[i].io_base;
2126 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2127
2128 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2129 pxa2xx_ssp_writefn, &ssp[i]);
2130 cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
2131 register_savevm("pxa2xx_ssp", i, 0,
2132 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2133 }
2134
2135 if (usb_enabled) {
2136 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2137 }
2138
2139 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2140 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2141
2142 s->rtc_base = 0x40900000;
2143 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2144 pxa2xx_rtc_writefn, s);
2145 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2146 pxa2xx_rtc_init(s);
2147 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2148
2149 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2150 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2151
2152 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2153
2154 s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2155
2156 /* GPIO1 resets the processor */
2157 /* The handler can be overridden by board-specific code */
2158 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2159 return s;
2160 }
2161
2162 /* Initialise a PXA255 integrated chip (ARM based core). */
2163 PXA2xxState *pxa255_init(unsigned int sdram_size)
2164 {
2165 PXA2xxState *s;
2166 PXA2xxSSPState *ssp;
2167 int iomemtype, i;
2168 int index;
2169
2170 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2171
2172 s->env = cpu_init("pxa255");
2173 if (!s->env) {
2174 fprintf(stderr, "Unable to find CPU definition\n");
2175 exit(1);
2176 }
2177 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2178
2179 /* SDRAM & Internal Memory Storage */
2180 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2181 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2182 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2183 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2184
2185 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2186
2187 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2188
2189 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2190
2191 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2192
2193 index = drive_get_index(IF_SD, 0, 0);
2194 if (index == -1) {
2195 fprintf(stderr, "qemu: missing SecureDigital device\n");
2196 exit(1);
2197 }
2198 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2199 s->pic[PXA2XX_PIC_MMC], s->dma);
2200
2201 for (i = 0; pxa255_serial[i].io_base; i ++)
2202 if (serial_hds[i])
2203 serial_mm_init(pxa255_serial[i].io_base, 2,
2204 s->pic[pxa255_serial[i].irqn], 14745600/16,
2205 serial_hds[i], 1);
2206 else
2207 break;
2208 if (serial_hds[i])
2209 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2210 s->dma, serial_hds[i]);
2211
2212 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2213
2214 s->cm_base = 0x41300000;
2215 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2216 s->clkcfg = 0x00000009; /* Turbo mode active */
2217 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2218 pxa2xx_cm_writefn, s);
2219 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2220 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2221
2222 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2223
2224 s->mm_base = 0x48000000;
2225 s->mm_regs[MDMRS >> 2] = 0x00020002;
2226 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2227 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2228 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2229 pxa2xx_mm_writefn, s);
2230 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2231 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2232
2233 s->pm_base = 0x40f00000;
2234 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2235 pxa2xx_pm_writefn, s);
2236 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2237 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2238
2239 for (i = 0; pxa255_ssp[i].io_base; i ++);
2240 s->ssp = (PXA2xxSSPState **)
2241 qemu_mallocz(sizeof(PXA2xxSSPState *) * i);
2242 ssp = (PXA2xxSSPState *)
2243 qemu_mallocz(sizeof(PXA2xxSSPState) * i);
2244 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2245 target_phys_addr_t ssp_base;
2246 s->ssp[i] = &ssp[i];
2247 ssp_base = pxa255_ssp[i].io_base;
2248 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2249
2250 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2251 pxa2xx_ssp_writefn, &ssp[i]);
2252 cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
2253 register_savevm("pxa2xx_ssp", i, 0,
2254 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2255 }
2256
2257 if (usb_enabled) {
2258 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2259 }
2260
2261 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2262 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2263
2264 s->rtc_base = 0x40900000;
2265 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2266 pxa2xx_rtc_writefn, s);
2267 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2268 pxa2xx_rtc_init(s);
2269 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2270
2271 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2272 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2273
2274 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2275
2276 /* GPIO1 resets the processor */
2277 /* The handler can be overridden by board-specific code */
2278 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2279 return s;
2280 }
2281
2282 static void pxa2xx_register_devices(void)
2283 {
2284 i2c_register_slave("pxa2xx-i2c-slave", sizeof(PXA2xxI2CSlaveState),
2285 &pxa2xx_i2c_slave_info);
2286 }
2287
2288 device_init(pxa2xx_register_devices)
Samsung s3c2440 and arm920t support for the mini2440 dev board