2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 //#define MIPS_DEBUG_DISAS
33 //#define MIPS_SINGLE_STEP
35 #ifdef USE_DIRECT_JUMP
38 #define TBPARAM(x) (long)(x)
42 #define DEF(s, n, copy_size) INDEX_op_ ## s,
48 static uint16_t *gen_opc_ptr
;
49 static uint32_t *gen_opparam_ptr
;
54 #define EXT_SPECIAL 0x100
55 #define EXT_SPECIAL2 0x200
56 #define EXT_REGIMM 0x300
63 /* indirect opcode tables */
71 /* arithmetic with immediate */
80 /* Jump and branches */
83 OPC_BEQ
= 0x04, /* Unconditional if rs = rt = 0 (B) */
91 OPC_JALX
= 0x1D, /* MIPS 16 only */
108 /* Floating point load/store */
117 /* Cache and prefetch */
122 /* MIPS special opcodes */
125 OPC_SLL
= 0x00 | EXT_SPECIAL
,
126 /* NOP is SLL r0, r0, 0 */
127 /* SSNOP is SLL r0, r0, 1 */
128 OPC_SRL
= 0x02 | EXT_SPECIAL
,
129 OPC_SRA
= 0x03 | EXT_SPECIAL
,
130 OPC_SLLV
= 0x04 | EXT_SPECIAL
,
131 OPC_SRLV
= 0x06 | EXT_SPECIAL
,
132 OPC_SRAV
= 0x07 | EXT_SPECIAL
,
133 /* Multiplication / division */
134 OPC_MULT
= 0x18 | EXT_SPECIAL
,
135 OPC_MULTU
= 0x19 | EXT_SPECIAL
,
136 OPC_DIV
= 0x1A | EXT_SPECIAL
,
137 OPC_DIVU
= 0x1B | EXT_SPECIAL
,
138 /* 2 registers arithmetic / logic */
139 OPC_ADD
= 0x20 | EXT_SPECIAL
,
140 OPC_ADDU
= 0x21 | EXT_SPECIAL
,
141 OPC_SUB
= 0x22 | EXT_SPECIAL
,
142 OPC_SUBU
= 0x23 | EXT_SPECIAL
,
143 OPC_AND
= 0x24 | EXT_SPECIAL
,
144 OPC_OR
= 0x25 | EXT_SPECIAL
,
145 OPC_XOR
= 0x26 | EXT_SPECIAL
,
146 OPC_NOR
= 0x27 | EXT_SPECIAL
,
147 OPC_SLT
= 0x2A | EXT_SPECIAL
,
148 OPC_SLTU
= 0x2B | EXT_SPECIAL
,
150 OPC_JR
= 0x08 | EXT_SPECIAL
,
151 OPC_JALR
= 0x09 | EXT_SPECIAL
,
153 OPC_TGE
= 0x30 | EXT_SPECIAL
,
154 OPC_TGEU
= 0x31 | EXT_SPECIAL
,
155 OPC_TLT
= 0x32 | EXT_SPECIAL
,
156 OPC_TLTU
= 0x33 | EXT_SPECIAL
,
157 OPC_TEQ
= 0x34 | EXT_SPECIAL
,
158 OPC_TNE
= 0x36 | EXT_SPECIAL
,
159 /* HI / LO registers load & stores */
160 OPC_MFHI
= 0x10 | EXT_SPECIAL
,
161 OPC_MTHI
= 0x11 | EXT_SPECIAL
,
162 OPC_MFLO
= 0x12 | EXT_SPECIAL
,
163 OPC_MTLO
= 0x13 | EXT_SPECIAL
,
164 /* Conditional moves */
165 OPC_MOVZ
= 0x0A | EXT_SPECIAL
,
166 OPC_MOVN
= 0x0B | EXT_SPECIAL
,
168 OPC_MOVCI
= 0x01 | EXT_SPECIAL
,
171 OPC_PMON
= 0x05 | EXT_SPECIAL
,
172 OPC_SYSCALL
= 0x0C | EXT_SPECIAL
,
173 OPC_BREAK
= 0x0D | EXT_SPECIAL
,
174 OPC_SYNC
= 0x0F | EXT_SPECIAL
,
178 /* Mutiply & xxx operations */
179 OPC_MADD
= 0x00 | EXT_SPECIAL2
,
180 OPC_MADDU
= 0x01 | EXT_SPECIAL2
,
181 OPC_MUL
= 0x02 | EXT_SPECIAL2
,
182 OPC_MSUB
= 0x04 | EXT_SPECIAL2
,
183 OPC_MSUBU
= 0x05 | EXT_SPECIAL2
,
185 OPC_CLZ
= 0x20 | EXT_SPECIAL2
,
186 OPC_CLO
= 0x21 | EXT_SPECIAL2
,
188 OPC_SDBBP
= 0x3F | EXT_SPECIAL2
,
193 OPC_BLTZ
= 0x00 | EXT_REGIMM
,
194 OPC_BLTZL
= 0x02 | EXT_REGIMM
,
195 OPC_BGEZ
= 0x01 | EXT_REGIMM
,
196 OPC_BGEZL
= 0x03 | EXT_REGIMM
,
197 OPC_BLTZAL
= 0x10 | EXT_REGIMM
,
198 OPC_BLTZALL
= 0x12 | EXT_REGIMM
,
199 OPC_BGEZAL
= 0x11 | EXT_REGIMM
,
200 OPC_BGEZALL
= 0x13 | EXT_REGIMM
,
201 OPC_TGEI
= 0x08 | EXT_REGIMM
,
202 OPC_TGEIU
= 0x09 | EXT_REGIMM
,
203 OPC_TLTI
= 0x0A | EXT_REGIMM
,
204 OPC_TLTIU
= 0x0B | EXT_REGIMM
,
205 OPC_TEQI
= 0x0C | EXT_REGIMM
,
206 OPC_TNEI
= 0x0E | EXT_REGIMM
,
210 /* Coprocessor 0 (MMU) */
211 OPC_MFC0
= 0x00 | EXT_CP0
,
212 OPC_MTC0
= 0x04 | EXT_CP0
,
213 OPC_TLBR
= 0x01 | EXT_CP0
,
214 OPC_TLBWI
= 0x02 | EXT_CP0
,
215 OPC_TLBWR
= 0x06 | EXT_CP0
,
216 OPC_TLBP
= 0x08 | EXT_CP0
,
217 OPC_ERET
= 0x18 | EXT_CP0
,
218 OPC_DERET
= 0x1F | EXT_CP0
,
219 OPC_WAIT
= 0x20 | EXT_CP0
,
224 /* Coprocessor 1 (FPU) */
225 OPC_MFC1
= 0x00 | EXT_CP1
,
226 OPC_MTC1
= 0x04 | EXT_CP1
,
227 OPC_CFC1
= 0x02 | EXT_CP1
,
228 OPC_CTC1
= 0x06 | EXT_CP1
,
232 const unsigned char *regnames
[] =
233 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
234 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
235 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
236 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
238 /* Warning: no function for r0 register (hard wired to zero) */
239 #define GEN32(func, NAME) \
240 static GenOpFunc *NAME ## _table [32] = { \
241 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
242 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
243 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
244 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
245 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
246 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
247 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
248 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
250 static inline void func(int n) \
252 NAME ## _table[n](); \
255 /* General purpose registers moves */
256 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
257 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
258 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
260 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
261 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
264 const unsigned char *fregnames
[] =
265 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
266 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
267 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
268 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
270 # define SFGEN32(func, NAME) \
271 static GenOpFunc *NAME ## _table [32] = { \
272 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
273 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
274 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
275 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
276 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
277 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
278 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
279 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
281 static inline void func(int n) \
283 NAME ## _table[n](); \
286 # define DFGEN32(func, NAME) \
287 static GenOpFunc *NAME ## _table [32] = { \
288 NAME ## 0, 0, NAME ## 2, 0, \
289 NAME ## 4, 0, NAME ## 6, 0, \
290 NAME ## 8, 0, NAME ## 10, 0, \
291 NAME ## 12, 0, NAME ## 14, 0, \
292 NAME ## 16, 0, NAME ## 18, 0, \
293 NAME ## 20, 0, NAME ## 22, 0, \
294 NAME ## 24, 0, NAME ## 26, 0, \
295 NAME ## 28, 0, NAME ## 30, 0, \
297 static inline void func(int n) \
299 NAME ## _table[n](); \
302 SFGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
303 SFGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
305 SFGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
306 SFGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
308 SFGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
309 SFGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
311 DFGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
312 DFGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
314 DFGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
315 DFGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
317 DFGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
318 DFGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
320 #define FOP_CONDS(fmt) \
321 static GenOpFunc * cond_ ## fmt ## _table[16] = { \
322 gen_op_cmp_ ## fmt ## _f, \
323 gen_op_cmp_ ## fmt ## _un, \
324 gen_op_cmp_ ## fmt ## _eq, \
325 gen_op_cmp_ ## fmt ## _ueq, \
326 gen_op_cmp_ ## fmt ## _olt, \
327 gen_op_cmp_ ## fmt ## _ult, \
328 gen_op_cmp_ ## fmt ## _ole, \
329 gen_op_cmp_ ## fmt ## _ule, \
330 gen_op_cmp_ ## fmt ## _sf, \
331 gen_op_cmp_ ## fmt ## _ngle, \
332 gen_op_cmp_ ## fmt ## _seq, \
333 gen_op_cmp_ ## fmt ## _ngl, \
334 gen_op_cmp_ ## fmt ## _lt, \
335 gen_op_cmp_ ## fmt ## _nge, \
336 gen_op_cmp_ ## fmt ## _le, \
337 gen_op_cmp_ ## fmt ## _ngt, \
339 static inline void gen_cmp_ ## fmt(int n) \
341 cond_ ## fmt ## _table[n](); \
349 typedef struct DisasContext
{
350 struct TranslationBlock
*tb
;
351 target_ulong pc
, saved_pc
;
353 /* Routine used to access memory */
355 uint32_t hflags
, saved_hflags
;
358 target_ulong btarget
;
362 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
363 * exception condition
365 BS_STOP
= 1, /* We want to stop translation for any reason */
366 BS_BRANCH
= 2, /* We reached a branch condition */
367 BS_EXCP
= 3, /* We reached an exception condition */
370 #if defined MIPS_DEBUG_DISAS
371 #define MIPS_DEBUG(fmt, args...) \
373 if (loglevel & CPU_LOG_TB_IN_ASM) { \
374 fprintf(logfile, "%08x: %08x " fmt "\n", \
375 ctx->pc, ctx->opcode , ##args); \
379 #define MIPS_DEBUG(fmt, args...) do { } while(0)
382 #define MIPS_INVAL(op) \
384 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
385 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
388 #define GEN_LOAD_REG_TN(Tn, Rn) \
391 glue(gen_op_reset_, Tn)(); \
393 glue(gen_op_load_gpr_, Tn)(Rn); \
397 #define GEN_LOAD_IMM_TN(Tn, Imm) \
400 glue(gen_op_reset_, Tn)(); \
402 glue(gen_op_set_, Tn)(Imm); \
406 #define GEN_STORE_TN_REG(Rn, Tn) \
409 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
415 # define GEN_LOAD_FREG_FTN(FTn, Fn) \
417 glue(gen_op_load_fpr_, FTn)(Fn); \
420 #define GEN_STORE_FTN_FREG(Fn, FTn) \
422 glue(gen_op_store_fpr_, FTn)(Fn); \
427 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
429 #if defined MIPS_DEBUG_DISAS
430 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
431 fprintf(logfile
, "hflags %08x saved %08x\n",
432 ctx
->hflags
, ctx
->saved_hflags
);
435 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
436 gen_op_save_pc(ctx
->pc
);
437 ctx
->saved_pc
= ctx
->pc
;
439 if (ctx
->hflags
!= ctx
->saved_hflags
) {
440 gen_op_save_state(ctx
->hflags
);
441 ctx
->saved_hflags
= ctx
->hflags
;
442 if (ctx
->hflags
& MIPS_HFLAG_BR
) {
443 gen_op_save_breg_target();
444 } else if (ctx
->hflags
& MIPS_HFLAG_B
) {
445 gen_op_save_btarget(ctx
->btarget
);
446 } else if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
448 gen_op_save_btarget(ctx
->btarget
);
453 static inline void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
455 #if defined MIPS_DEBUG_DISAS
456 if (loglevel
& CPU_LOG_TB_IN_ASM
)
457 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
459 save_cpu_state(ctx
, 1);
461 gen_op_raise_exception(excp
);
463 gen_op_raise_exception_err(excp
, err
);
464 ctx
->bstate
= BS_EXCP
;
467 static inline void generate_exception (DisasContext
*ctx
, int excp
)
469 generate_exception_err (ctx
, excp
, 0);
472 #if defined(CONFIG_USER_ONLY)
473 #define op_ldst(name) gen_op_##name##_raw()
474 #define OP_LD_TABLE(width)
475 #define OP_ST_TABLE(width)
477 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
478 #define OP_LD_TABLE(width) \
479 static GenOpFunc *gen_op_l##width[] = { \
480 &gen_op_l##width##_user, \
481 &gen_op_l##width##_kernel, \
483 #define OP_ST_TABLE(width) \
484 static GenOpFunc *gen_op_s##width[] = { \
485 &gen_op_s##width##_user, \
486 &gen_op_s##width##_kernel, \
521 static void gen_ldst (DisasContext
*ctx
, uint16_t opc
, int rt
,
522 int base
, int16_t offset
)
524 const unsigned char *opn
= "unk";
527 GEN_LOAD_IMM_TN(T0
, offset
);
528 } else if (offset
== 0) {
529 gen_op_load_gpr_T0(base
);
531 gen_op_load_gpr_T0(base
);
532 gen_op_set_T1(offset
);
535 /* Don't do NOP if destination is zero: we must perform the actual
539 #if defined(TARGET_MIPS64)
541 #if defined (MIPS_HAS_UNALIGNED_LS)
545 GEN_STORE_TN_REG(rt
, T0
);
549 #if defined (MIPS_HAS_UNALIGNED_LS)
552 GEN_LOAD_REG_TN(T1
, rt
);
558 GEN_STORE_TN_REG(rt
, T0
);
562 GEN_LOAD_REG_TN(T1
, rt
);
568 GEN_STORE_TN_REG(rt
, T0
);
572 GEN_LOAD_REG_TN(T1
, rt
);
578 #if defined (MIPS_HAS_UNALIGNED_LS)
582 GEN_STORE_TN_REG(rt
, T0
);
587 GEN_STORE_TN_REG(rt
, T0
);
591 #if defined (MIPS_HAS_UNALIGNED_LS)
594 GEN_LOAD_REG_TN(T1
, rt
);
599 #if defined (MIPS_HAS_UNALIGNED_LS)
603 GEN_STORE_TN_REG(rt
, T0
);
607 #if defined (MIPS_HAS_UNALIGNED_LS)
610 GEN_LOAD_REG_TN(T1
, rt
);
615 #if defined (MIPS_HAS_UNALIGNED_LS)
619 GEN_STORE_TN_REG(rt
, T0
);
624 GEN_STORE_TN_REG(rt
, T0
);
628 GEN_LOAD_REG_TN(T1
, rt
);
634 GEN_STORE_TN_REG(rt
, T0
);
638 GEN_LOAD_REG_TN(T1
, rt
);
640 GEN_STORE_TN_REG(rt
, T0
);
644 GEN_LOAD_REG_TN(T1
, rt
);
649 GEN_LOAD_REG_TN(T1
, rt
);
651 GEN_STORE_TN_REG(rt
, T0
);
655 GEN_LOAD_REG_TN(T1
, rt
);
661 GEN_STORE_TN_REG(rt
, T0
);
665 GEN_LOAD_REG_TN(T1
, rt
);
667 GEN_STORE_TN_REG(rt
, T0
);
671 MIPS_INVAL("load/store");
672 generate_exception(ctx
, EXCP_RI
);
675 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
681 static void gen_flt_ldst (DisasContext
*ctx
, uint16_t opc
, int ft
,
682 int base
, int16_t offset
)
684 const unsigned char *opn
= "unk";
687 GEN_LOAD_IMM_TN(T0
, offset
);
688 } else if (offset
== 0) {
689 gen_op_load_gpr_T0(base
);
691 gen_op_load_gpr_T0(base
);
692 gen_op_set_T1(offset
);
695 /* Don't do NOP if destination is zero: we must perform the actual
701 GEN_STORE_FTN_FREG(ft
, WT0
);
705 GEN_LOAD_FREG_FTN(WT0
, ft
);
711 GEN_STORE_FTN_FREG(ft
, DT0
);
715 GEN_LOAD_FREG_FTN(DT0
, ft
);
720 MIPS_INVAL("float load/store");
721 generate_exception(ctx
, EXCP_CpU
);
724 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
728 /* Arithmetic with immediate operand */
729 static void gen_arith_imm (DisasContext
*ctx
, uint16_t opc
, int rt
,
733 const unsigned char *opn
= "unk";
735 if (rt
== 0 && opc
!= OPC_ADDI
) {
736 /* if no destination, treat it as a NOP
737 * For addi, we must generate the overflow exception when needed.
742 if (opc
== OPC_ADDI
|| opc
== OPC_ADDIU
||
743 opc
== OPC_SLTI
|| opc
== OPC_SLTIU
)
744 uimm
= (int32_t)imm
; /* Sign extent to 32 bits */
746 uimm
= (uint16_t)imm
;
747 if (opc
!= OPC_LUI
) {
748 GEN_LOAD_REG_TN(T0
, rs
);
749 GEN_LOAD_IMM_TN(T1
, uimm
);
752 GEN_LOAD_IMM_TN(T0
, uimm
);
756 save_cpu_state(ctx
, 1);
800 MIPS_INVAL("imm arith");
801 generate_exception(ctx
, EXCP_RI
);
804 GEN_STORE_TN_REG(rt
, T0
);
805 MIPS_DEBUG("%s %s, %s, %x", opn
, regnames
[rt
], regnames
[rs
], uimm
);
809 static void gen_arith (DisasContext
*ctx
, uint16_t opc
,
810 int rd
, int rs
, int rt
)
812 const unsigned char *opn
= "unk";
814 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
) {
815 /* if no destination, treat it as a NOP
816 * For add & sub, we must generate the overflow exception when needed.
821 GEN_LOAD_REG_TN(T0
, rs
);
822 GEN_LOAD_REG_TN(T1
, rt
);
825 save_cpu_state(ctx
, 1);
834 save_cpu_state(ctx
, 1);
892 generate_exception(ctx
, EXCP_RI
);
895 GEN_STORE_TN_REG(rd
, T0
);
897 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
900 /* Arithmetic on HI/LO registers */
901 static void gen_HILO (DisasContext
*ctx
, uint16_t opc
, int reg
)
903 const unsigned char *opn
= "unk";
905 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
913 GEN_STORE_TN_REG(reg
, T0
);
918 GEN_STORE_TN_REG(reg
, T0
);
922 GEN_LOAD_REG_TN(T0
, reg
);
927 GEN_LOAD_REG_TN(T0
, reg
);
933 generate_exception(ctx
, EXCP_RI
);
936 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
939 static void gen_muldiv (DisasContext
*ctx
, uint16_t opc
,
942 const unsigned char *opn
= "unk";
944 GEN_LOAD_REG_TN(T0
, rs
);
945 GEN_LOAD_REG_TN(T1
, rt
);
980 MIPS_INVAL("mul/div");
981 generate_exception(ctx
, EXCP_RI
);
984 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
987 static void gen_cl (DisasContext
*ctx
, uint16_t opc
,
990 const unsigned char *opn
= "unk";
996 GEN_LOAD_REG_TN(T0
, rs
);
1010 generate_exception(ctx
, EXCP_RI
);
1013 gen_op_store_T0_gpr(rd
);
1014 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1018 static void gen_trap (DisasContext
*ctx
, uint16_t opc
,
1019 int rs
, int rt
, int16_t imm
)
1024 /* Load needed operands */
1032 /* Compare two registers */
1034 GEN_LOAD_REG_TN(T0
, rs
);
1035 GEN_LOAD_REG_TN(T1
, rt
);
1044 /* Compare register to immediate */
1045 if (rs
!= 0 || imm
!= 0) {
1046 GEN_LOAD_REG_TN(T0
, rs
);
1047 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1054 case OPC_TEQ
: /* rs == rs */
1055 case OPC_TEQI
: /* r0 == 0 */
1056 case OPC_TGE
: /* rs >= rs */
1057 case OPC_TGEI
: /* r0 >= 0 */
1058 case OPC_TGEU
: /* rs >= rs unsigned */
1059 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1063 case OPC_TLT
: /* rs < rs */
1064 case OPC_TLTI
: /* r0 < 0 */
1065 case OPC_TLTU
: /* rs < rs unsigned */
1066 case OPC_TLTIU
: /* r0 < 0 unsigned */
1067 case OPC_TNE
: /* rs != rs */
1068 case OPC_TNEI
: /* r0 != 0 */
1069 /* Never trap: treat as NOP */
1073 generate_exception(ctx
, EXCP_RI
);
1104 generate_exception(ctx
, EXCP_RI
);
1108 save_cpu_state(ctx
, 1);
1110 ctx
->bstate
= BS_STOP
;
1113 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1115 TranslationBlock
*tb
;
1117 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1119 gen_op_goto_tb0(TBPARAM(tb
));
1121 gen_op_goto_tb1(TBPARAM(tb
));
1122 gen_op_save_pc(dest
);
1123 gen_op_set_T0((long)tb
+ n
);
1126 gen_op_save_pc(dest
);
1132 /* Branches (before delay slot) */
1133 static void gen_compute_branch (DisasContext
*ctx
, uint16_t opc
,
1134 int rs
, int rt
, int32_t offset
)
1136 target_ulong btarget
;
1142 /* Load needed operands */
1148 /* Compare two registers */
1150 GEN_LOAD_REG_TN(T0
, rs
);
1151 GEN_LOAD_REG_TN(T1
, rt
);
1154 btarget
= ctx
->pc
+ 4 + offset
;
1168 /* Compare to zero */
1170 gen_op_load_gpr_T0(rs
);
1173 btarget
= ctx
->pc
+ 4 + offset
;
1177 /* Jump to immediate */
1178 btarget
= ((ctx
->pc
+ 4) & 0xF0000000) | offset
;
1182 /* Jump to register */
1184 /* Only hint = 0 is valid */
1185 generate_exception(ctx
, EXCP_RI
);
1188 GEN_LOAD_REG_TN(T2
, rs
);
1191 MIPS_INVAL("branch/jump");
1192 generate_exception(ctx
, EXCP_RI
);
1196 /* No condition to be computed */
1198 case OPC_BEQ
: /* rx == rx */
1199 case OPC_BEQL
: /* rx == rx likely */
1200 case OPC_BGEZ
: /* 0 >= 0 */
1201 case OPC_BGEZL
: /* 0 >= 0 likely */
1202 case OPC_BLEZ
: /* 0 <= 0 */
1203 case OPC_BLEZL
: /* 0 <= 0 likely */
1205 ctx
->hflags
|= MIPS_HFLAG_B
;
1206 MIPS_DEBUG("balways");
1208 case OPC_BGEZAL
: /* 0 >= 0 */
1209 case OPC_BGEZALL
: /* 0 >= 0 likely */
1210 /* Always take and link */
1212 ctx
->hflags
|= MIPS_HFLAG_B
;
1213 MIPS_DEBUG("balways and link");
1215 case OPC_BNE
: /* rx != rx */
1216 case OPC_BGTZ
: /* 0 > 0 */
1217 case OPC_BLTZ
: /* 0 < 0 */
1218 /* Treated as NOP */
1219 MIPS_DEBUG("bnever (NOP)");
1221 case OPC_BLTZAL
: /* 0 < 0 */
1222 gen_op_set_T0(ctx
->pc
+ 8);
1223 gen_op_store_T0_gpr(31);
1225 case OPC_BLTZALL
: /* 0 < 0 likely */
1226 gen_op_set_T0(ctx
->pc
+ 8);
1227 gen_op_store_T0_gpr(31);
1228 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1230 case OPC_BNEL
: /* rx != rx likely */
1231 case OPC_BGTZL
: /* 0 > 0 likely */
1232 case OPC_BLTZL
: /* 0 < 0 likely */
1233 /* Skip the instruction in the delay slot */
1234 MIPS_DEBUG("bnever and skip");
1235 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1238 ctx
->hflags
|= MIPS_HFLAG_B
;
1239 MIPS_DEBUG("j %08x", btarget
);
1243 ctx
->hflags
|= MIPS_HFLAG_B
;
1244 MIPS_DEBUG("jal %08x", btarget
);
1247 ctx
->hflags
|= MIPS_HFLAG_BR
;
1248 MIPS_DEBUG("jr %s", regnames
[rs
]);
1252 ctx
->hflags
|= MIPS_HFLAG_BR
;
1253 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1256 MIPS_INVAL("branch/jump");
1257 generate_exception(ctx
, EXCP_RI
);
1264 MIPS_DEBUG("beq %s, %s, %08x",
1265 regnames
[rs
], regnames
[rt
], btarget
);
1269 MIPS_DEBUG("beql %s, %s, %08x",
1270 regnames
[rs
], regnames
[rt
], btarget
);
1274 MIPS_DEBUG("bne %s, %s, %08x",
1275 regnames
[rs
], regnames
[rt
], btarget
);
1279 MIPS_DEBUG("bnel %s, %s, %08x",
1280 regnames
[rs
], regnames
[rt
], btarget
);
1284 MIPS_DEBUG("bgez %s, %08x", regnames
[rs
], btarget
);
1288 MIPS_DEBUG("bgezl %s, %08x", regnames
[rs
], btarget
);
1292 MIPS_DEBUG("bgezal %s, %08x", regnames
[rs
], btarget
);
1298 MIPS_DEBUG("bgezall %s, %08x", regnames
[rs
], btarget
);
1302 MIPS_DEBUG("bgtz %s, %08x", regnames
[rs
], btarget
);
1306 MIPS_DEBUG("bgtzl %s, %08x", regnames
[rs
], btarget
);
1310 MIPS_DEBUG("blez %s, %08x", regnames
[rs
], btarget
);
1314 MIPS_DEBUG("blezl %s, %08x", regnames
[rs
], btarget
);
1318 MIPS_DEBUG("bltz %s, %08x", regnames
[rs
], btarget
);
1322 MIPS_DEBUG("bltzl %s, %08x", regnames
[rs
], btarget
);
1327 MIPS_DEBUG("bltzal %s, %08x", regnames
[rs
], btarget
);
1329 ctx
->hflags
|= MIPS_HFLAG_BC
;
1334 MIPS_DEBUG("bltzall %s, %08x", regnames
[rs
], btarget
);
1336 ctx
->hflags
|= MIPS_HFLAG_BL
;
1341 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1342 blink
, ctx
->hflags
, btarget
);
1343 ctx
->btarget
= btarget
;
1345 gen_op_set_T0(ctx
->pc
+ 8);
1346 gen_op_store_T0_gpr(blink
);
1351 /* CP0 (MMU and control) */
1352 static void gen_cp0 (DisasContext
*ctx
, uint16_t opc
, int rt
, int rd
)
1354 const unsigned char *opn
= "unk";
1356 if (!(ctx
->CP0_Status
& (1 << CP0St_CU0
)) &&
1357 (ctx
->hflags
& MIPS_HFLAG_UM
) &&
1358 !(ctx
->hflags
& MIPS_HFLAG_ERL
) &&
1359 !(ctx
->hflags
& MIPS_HFLAG_EXL
)) {
1360 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1361 fprintf(logfile
, "CP0 is not usable\n");
1363 generate_exception_err (ctx
, EXCP_CpU
, 0);
1373 gen_op_mfc0(rd
, ctx
->opcode
& 0x7);
1374 gen_op_store_T0_gpr(rt
);
1378 /* If we get an exception, we want to restart at next instruction */
1380 save_cpu_state(ctx
, 1);
1382 GEN_LOAD_REG_TN(T0
, rt
);
1383 gen_op_mtc0(rd
, ctx
->opcode
& 0x7);
1384 /* Stop translation as we may have switched the execution mode */
1385 ctx
->bstate
= BS_STOP
;
1388 #if defined(MIPS_USES_R4K_TLB)
1408 save_cpu_state(ctx
, 0);
1410 ctx
->bstate
= BS_EXCP
;
1414 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
1415 generate_exception(ctx
, EXCP_RI
);
1417 save_cpu_state(ctx
, 0);
1419 ctx
->bstate
= BS_EXCP
;
1424 /* If we get an exception, we want to restart at next instruction */
1426 save_cpu_state(ctx
, 1);
1429 ctx
->bstate
= BS_EXCP
;
1432 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1433 fprintf(logfile
, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
1434 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
1435 ((ctx
->opcode
>> 16) & 0x1F));
1437 generate_exception(ctx
, EXCP_RI
);
1440 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
1443 #ifdef MIPS_USES_FPU
1444 /* CP1 Branches (before delay slot) */
1445 static void gen_compute_branch1 (DisasContext
*ctx
, uint16_t cond
,
1448 target_ulong btarget
;
1450 btarget
= ctx
->pc
+ 4 + offset
;
1453 case 0x0000: /* bc1f */
1455 MIPS_DEBUG("bc1f %08x", btarget
);
1457 case 0x0002: /* bc1fl */
1459 MIPS_DEBUG("bc1fl %08x", btarget
);
1461 case 0x0001: /* bc1t */
1463 MIPS_DEBUG("bc1t %08x", btarget
);
1465 ctx
->hflags
|= MIPS_HFLAG_BC
;
1467 case 0x0003: /* bc1tl */
1469 MIPS_DEBUG("bc1tl %08x", btarget
);
1471 ctx
->hflags
|= MIPS_HFLAG_BL
;
1474 MIPS_INVAL("cp1 branch/jump");
1475 generate_exception(ctx
, EXCP_RI
);
1480 MIPS_DEBUG("enter ds: cond %02x target %08x",
1481 ctx
->hflags
, btarget
);
1482 ctx
->btarget
= btarget
;
1487 /* Coprocessor 1 (FPU) */
1488 static void gen_cp1 (DisasContext
*ctx
, uint16_t opc
, int rt
, int fs
)
1490 const unsigned char *opn
= "unk";
1494 GEN_LOAD_FREG_FTN(WT0
, fs
);
1496 GEN_STORE_TN_REG(rt
, T0
);
1500 GEN_LOAD_REG_TN(T0
, rt
);
1502 GEN_STORE_FTN_FREG(fs
, WT0
);
1506 if (fs
!= 0 && fs
!= 31) {
1507 MIPS_INVAL("cfc1 freg");
1508 generate_exception(ctx
, EXCP_RI
);
1511 GEN_LOAD_IMM_TN(T1
, fs
);
1513 GEN_STORE_TN_REG(rt
, T0
);
1517 if (fs
!= 0 && fs
!= 31) {
1518 MIPS_INVAL("ctc1 freg");
1519 generate_exception(ctx
, EXCP_RI
);
1522 GEN_LOAD_IMM_TN(T1
, fs
);
1523 GEN_LOAD_REG_TN(T0
, rt
);
1528 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1529 fprintf(logfile
, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
1530 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
1531 ((ctx
->opcode
>> 16) & 0x1F));
1533 generate_exception(ctx
, EXCP_RI
);
1536 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
1539 /* verify if floating point register is valid; an operation is not defined
1540 * if bit 0 of any register specification is set and the FR bit in the
1541 * Status register equals zero, since the register numbers specify an
1542 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1543 * in the Status register equals one, both even and odd register numbers
1546 * Multiple float registers can be checked by calling
1547 * CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
1549 #define CHECK_FR(ctx, freg) do { \
1550 if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
1551 generate_exception(ctx, EXCP_RI); \
1556 #define FOP(func, fmt) (((fmt) << 21) | (func))
1558 static void gen_farith (DisasContext
*ctx
, int fmt
, int ft
, int fs
, int fd
, int func
)
1560 const unsigned char *opn
= "unk";
1561 const char *condnames
[] = {
1581 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
1583 CHECK_FR(ctx
, fs
| ft
| fd
);
1584 GEN_LOAD_FREG_FTN(DT0
, fs
);
1585 GEN_LOAD_FREG_FTN(DT1
, ft
);
1586 gen_op_float_add_d();
1587 GEN_STORE_FTN_FREG(fd
, DT2
);
1592 CHECK_FR(ctx
, fs
| ft
| fd
);
1593 GEN_LOAD_FREG_FTN(DT0
, fs
);
1594 GEN_LOAD_FREG_FTN(DT1
, ft
);
1595 gen_op_float_sub_d();
1596 GEN_STORE_FTN_FREG(fd
, DT2
);
1601 CHECK_FR(ctx
, fs
| ft
| fd
);
1602 GEN_LOAD_FREG_FTN(DT0
, fs
);
1603 GEN_LOAD_FREG_FTN(DT1
, ft
);
1604 gen_op_float_mul_d();
1605 GEN_STORE_FTN_FREG(fd
, DT2
);
1610 CHECK_FR(ctx
, fs
| ft
| fd
);
1611 GEN_LOAD_FREG_FTN(DT0
, fs
);
1612 GEN_LOAD_FREG_FTN(DT1
, ft
);
1613 gen_op_float_div_d();
1614 GEN_STORE_FTN_FREG(fd
, DT2
);
1619 CHECK_FR(ctx
, fs
| fd
);
1620 GEN_LOAD_FREG_FTN(DT0
, fs
);
1621 gen_op_float_sqrt_d();
1622 GEN_STORE_FTN_FREG(fd
, DT2
);
1626 CHECK_FR(ctx
, fs
| fd
);
1627 GEN_LOAD_FREG_FTN(DT0
, fs
);
1628 gen_op_float_abs_d();
1629 GEN_STORE_FTN_FREG(fd
, DT2
);
1633 CHECK_FR(ctx
, fs
| fd
);
1634 GEN_LOAD_FREG_FTN(DT0
, fs
);
1635 gen_op_float_mov_d();
1636 GEN_STORE_FTN_FREG(fd
, DT2
);
1640 CHECK_FR(ctx
, fs
| fd
);
1641 GEN_LOAD_FREG_FTN(DT0
, fs
);
1642 gen_op_float_chs_d();
1643 GEN_STORE_FTN_FREG(fd
, DT2
);
1651 CHECK_FR(ctx
, fs
| fd
);
1652 GEN_LOAD_FREG_FTN(DT0
, fs
);
1653 gen_op_float_roundw_d();
1654 GEN_STORE_FTN_FREG(fd
, WT2
);
1658 CHECK_FR(ctx
, fs
| fd
);
1659 GEN_LOAD_FREG_FTN(DT0
, fs
);
1660 gen_op_float_truncw_d();
1661 GEN_STORE_FTN_FREG(fd
, WT2
);
1665 CHECK_FR(ctx
, fs
| fd
);
1666 GEN_LOAD_FREG_FTN(DT0
, fs
);
1667 gen_op_float_ceilw_d();
1668 GEN_STORE_FTN_FREG(fd
, WT2
);
1672 CHECK_FR(ctx
, fs
| fd
);
1673 GEN_LOAD_FREG_FTN(DT0
, fs
);
1674 gen_op_float_floorw_d();
1675 GEN_STORE_FTN_FREG(fd
, WT2
);
1678 case FOP(33, 20): /* cvt.d.w */
1679 CHECK_FR(ctx
, fs
| fd
);
1680 GEN_LOAD_FREG_FTN(WT0
, fs
);
1681 gen_op_float_cvtd_w();
1682 GEN_STORE_FTN_FREG(fd
, DT2
);
1701 CHECK_FR(ctx
, fs
| ft
);
1702 GEN_LOAD_FREG_FTN(DT0
, fs
);
1703 GEN_LOAD_FREG_FTN(DT1
, ft
);
1705 opn
= condnames
[func
-48];
1708 CHECK_FR(ctx
, fs
| ft
| fd
);
1709 GEN_LOAD_FREG_FTN(WT0
, fs
);
1710 GEN_LOAD_FREG_FTN(WT1
, ft
);
1711 gen_op_float_add_s();
1712 GEN_STORE_FTN_FREG(fd
, WT2
);
1717 CHECK_FR(ctx
, fs
| ft
| fd
);
1718 GEN_LOAD_FREG_FTN(WT0
, fs
);
1719 GEN_LOAD_FREG_FTN(WT1
, ft
);
1720 gen_op_float_sub_s();
1721 GEN_STORE_FTN_FREG(fd
, WT2
);
1726 CHECK_FR(ctx
, fs
| ft
| fd
);
1727 GEN_LOAD_FREG_FTN(WT0
, fs
);
1728 GEN_LOAD_FREG_FTN(WT1
, ft
);
1729 gen_op_float_mul_s();
1730 GEN_STORE_FTN_FREG(fd
, WT2
);
1735 CHECK_FR(ctx
, fs
| ft
| fd
);
1736 GEN_LOAD_FREG_FTN(WT0
, fs
);
1737 GEN_LOAD_FREG_FTN(WT1
, ft
);
1738 gen_op_float_div_s();
1739 GEN_STORE_FTN_FREG(fd
, WT2
);
1744 CHECK_FR(ctx
, fs
| fd
);
1745 GEN_LOAD_FREG_FTN(WT0
, fs
);
1746 gen_op_float_sqrt_s();
1747 GEN_STORE_FTN_FREG(fd
, WT2
);
1751 CHECK_FR(ctx
, fs
| fd
);
1752 GEN_LOAD_FREG_FTN(WT0
, fs
);
1753 gen_op_float_abs_s();
1754 GEN_STORE_FTN_FREG(fd
, WT2
);
1758 CHECK_FR(ctx
, fs
| fd
);
1759 GEN_LOAD_FREG_FTN(WT0
, fs
);
1760 gen_op_float_mov_s();
1761 GEN_STORE_FTN_FREG(fd
, WT2
);
1765 CHECK_FR(ctx
, fs
| fd
);
1766 GEN_LOAD_FREG_FTN(WT0
, fs
);
1767 gen_op_float_chs_s();
1768 GEN_STORE_FTN_FREG(fd
, WT2
);
1772 CHECK_FR(ctx
, fs
| fd
);
1773 GEN_LOAD_FREG_FTN(WT0
, fs
);
1774 gen_op_float_roundw_s();
1775 GEN_STORE_FTN_FREG(fd
, WT2
);
1779 CHECK_FR(ctx
, fs
| fd
);
1780 GEN_LOAD_FREG_FTN(WT0
, fs
);
1781 gen_op_float_truncw_s();
1782 GEN_STORE_FTN_FREG(fd
, WT2
);
1785 case FOP(32, 20): /* cvt.s.w */
1786 CHECK_FR(ctx
, fs
| fd
);
1787 GEN_LOAD_FREG_FTN(WT0
, fs
);
1788 gen_op_float_cvts_w();
1789 GEN_STORE_FTN_FREG(fd
, WT2
);
1792 case FOP(36, 16): /* cvt.w.s */
1793 CHECK_FR(ctx
, fs
| fd
);
1794 GEN_LOAD_FREG_FTN(WT0
, fs
);
1795 gen_op_float_cvtw_s();
1796 GEN_STORE_FTN_FREG(fd
, WT2
);
1799 case FOP(36, 17): /* cvt.w.d */
1800 CHECK_FR(ctx
, fs
| fd
);
1801 GEN_LOAD_FREG_FTN(WT0
, fs
);
1802 gen_op_float_cvtw_d();
1803 GEN_STORE_FTN_FREG(fd
, WT2
);
1822 CHECK_FR(ctx
, fs
| ft
);
1823 GEN_LOAD_FREG_FTN(WT0
, fs
);
1824 GEN_LOAD_FREG_FTN(WT1
, ft
);
1826 opn
= condnames
[func
-48];
1829 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1830 fprintf(logfile
, "Invalid arith function: %08x %03x %03x %03x\n",
1831 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
1832 ((ctx
->opcode
>> 16) & 0x1F));
1834 generate_exception(ctx
, EXCP_RI
);
1838 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
1840 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
1844 /* ISA extensions */
1845 /* MIPS16 extension to MIPS32 */
1846 /* SmartMIPS extension to MIPS32 */
1848 #ifdef TARGET_MIPS64
1849 static void gen_arith64 (DisasContext
*ctx
, uint16_t opc
)
1851 if (func
== 0x02 && rd
== 0) {
1855 if (rs
== 0 || rt
== 0) {
1859 gen_op_load_gpr_T0(rs
);
1860 gen_op_load_gpr_T1(rt
);
1873 /* Coprocessor 3 (FPU) */
1875 /* MDMX extension to MIPS64 */
1876 /* MIPS-3D extension to MIPS64 */
1880 static void gen_blikely(DisasContext
*ctx
)
1883 l1
= gen_new_label();
1885 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
1886 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
1890 static void decode_opc (DisasContext
*ctx
)
1897 /* make sure instructions are on a word boundary */
1898 if (ctx
->pc
& 0x3) {
1899 generate_exception(ctx
, EXCP_AdEL
);
1903 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
1904 /* Handle blikely not taken case */
1905 MIPS_DEBUG("blikely condition (%08x)", ctx
->pc
+ 4);
1908 op
= ctx
->opcode
>> 26;
1909 rs
= ((ctx
->opcode
>> 21) & 0x1F);
1910 rt
= ((ctx
->opcode
>> 16) & 0x1F);
1911 rd
= ((ctx
->opcode
>> 11) & 0x1F);
1912 sa
= ((ctx
->opcode
>> 6) & 0x1F);
1913 imm
= (int16_t)ctx
->opcode
;
1915 case 0x00: /* Special opcode */
1916 op1
= ctx
->opcode
& 0x3F;
1918 case 0x00: /* Arithmetic with immediate */
1920 gen_arith_imm(ctx
, op1
| EXT_SPECIAL
, rd
, rt
, sa
);
1922 case 0x04: /* Arithmetic */
1927 gen_arith(ctx
, op1
| EXT_SPECIAL
, rd
, rs
, rt
);
1929 case 0x18 ... 0x1B: /* MULT / DIV */
1930 gen_muldiv(ctx
, op1
| EXT_SPECIAL
, rs
, rt
);
1932 case 0x08 ... 0x09: /* Jumps */
1933 gen_compute_branch(ctx
, op1
| EXT_SPECIAL
, rs
, rd
, sa
);
1935 case 0x30 ... 0x34: /* Traps */
1937 gen_trap(ctx
, op1
| EXT_SPECIAL
, rs
, rt
, -1);
1939 case 0x10: /* Move from HI/LO */
1941 gen_HILO(ctx
, op1
| EXT_SPECIAL
, rd
);
1944 case 0x13: /* Move to HI/LO */
1945 gen_HILO(ctx
, op1
| EXT_SPECIAL
, rs
);
1947 case 0x0C: /* SYSCALL */
1948 generate_exception(ctx
, EXCP_SYSCALL
);
1950 case 0x0D: /* BREAK */
1951 generate_exception(ctx
, EXCP_BREAK
);
1953 case 0x0F: /* SYNC */
1954 /* Treat as a noop */
1956 case 0x05: /* Pmon entry point */
1957 gen_op_pmon((ctx
->opcode
>> 6) & 0x1F);
1960 case 0x01: /* MOVCI */
1961 #if defined (MIPS_HAS_MOVCI)
1964 /* Not implemented */
1965 generate_exception_err (ctx
, EXCP_CpU
, 1);
1969 #if defined (TARGET_MIPS64)
1970 case 0x14: /* MIPS64 specific opcodes */
1979 default: /* Invalid */
1980 MIPS_INVAL("special");
1981 generate_exception(ctx
, EXCP_RI
);
1985 case 0x1C: /* Special2 opcode */
1986 op1
= ctx
->opcode
& 0x3F;
1988 #if defined (MIPS_USES_R4K_EXT)
1989 /* Those instructions are not part of MIPS32 core */
1990 case 0x00 ... 0x01: /* Multiply and add/sub */
1992 gen_muldiv(ctx
, op1
| EXT_SPECIAL2
, rs
, rt
);
1994 case 0x02: /* MUL */
1995 gen_arith(ctx
, op1
| EXT_SPECIAL2
, rd
, rs
, rt
);
1997 case 0x20 ... 0x21: /* CLO / CLZ */
1998 gen_cl(ctx
, op1
| EXT_SPECIAL2
, rd
, rs
);
2001 case 0x3F: /* SDBBP */
2002 /* XXX: not clear which exception should be raised
2003 * when in debug mode...
2005 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
2006 generate_exception(ctx
, EXCP_DBp
);
2008 generate_exception(ctx
, EXCP_DBp
);
2010 /* Treat as a noop */
2012 default: /* Invalid */
2013 MIPS_INVAL("special2");
2014 generate_exception(ctx
, EXCP_RI
);
2018 case 0x01: /* B REGIMM opcode */
2019 op1
= ((ctx
->opcode
>> 16) & 0x1F);
2021 case 0x00 ... 0x03: /* REGIMM branches */
2023 gen_compute_branch(ctx
, op1
| EXT_REGIMM
, rs
, -1, imm
<< 2);
2025 case 0x08 ... 0x0C: /* Traps */
2027 gen_trap(ctx
, op1
| EXT_REGIMM
, rs
, -1, imm
);
2029 default: /* Invalid */
2030 MIPS_INVAL("REGIMM");
2031 generate_exception(ctx
, EXCP_RI
);
2035 case 0x10: /* CP0 opcode */
2036 op1
= ((ctx
->opcode
>> 21) & 0x1F);
2040 gen_cp0(ctx
, op1
| EXT_CP0
, rt
, rd
);
2043 gen_cp0(ctx
, (ctx
->opcode
& 0x3F) | EXT_CP0
, rt
, rd
);
2047 case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
2048 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
2050 case 0x02 ... 0x03: /* Jump */
2051 offset
= (int32_t)(ctx
->opcode
& 0x03FFFFFF) << 2;
2052 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
2054 case 0x04 ... 0x07: /* Branch */
2056 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
2058 case 0x20 ... 0x2E: /* Load and stores */
2061 gen_ldst(ctx
, op
, rt
, rs
, imm
);
2063 case 0x2F: /* Cache operation */
2064 /* Treat as a noop */
2066 case 0x33: /* Prefetch */
2067 /* Treat as a noop */
2069 case 0x3F: /* HACK */
2072 /* Floating point. */
2073 case 0x31: /* LWC1 */
2074 case 0x35: /* LDC1 */
2075 case 0x39: /* SWC1 */
2076 case 0x3D: /* SDC1 */
2077 #if defined(MIPS_USES_FPU)
2078 gen_op_cp1_enabled();
2079 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
2081 generate_exception_err(ctx
, EXCP_CpU
, 1);
2085 case 0x11: /* CP1 opcode */
2086 #if defined(MIPS_USES_FPU)
2087 gen_op_cp1_enabled();
2088 op1
= ((ctx
->opcode
>> 21) & 0x1F);
2090 case 0x00: /* mfc1 */
2091 case 0x02: /* cfc1 */
2092 case 0x04: /* mtc1 */
2093 case 0x06: /* ctc1 */
2094 gen_cp1(ctx
, op1
| EXT_CP1
, rt
, rd
);
2097 gen_compute_branch1(ctx
, rt
, imm
<< 2);
2099 case 0x10: /* 16: fmt=single fp */
2100 case 0x11: /* 17: fmt=double fp */
2101 case 0x14: /* 20: fmt=32bit fixed */
2102 case 0x15: /* 21: fmt=64bit fixed */
2103 gen_farith(ctx
, op1
, rt
, rd
, sa
, ctx
->opcode
& 0x3f);
2106 generate_exception_err(ctx
, EXCP_RI
, 1);
2111 generate_exception_err(ctx
, EXCP_CpU
, 1);
2116 case 0x32: /* LWC2 */
2117 case 0x36: /* LDC2 */
2118 case 0x3A: /* SWC2 */
2119 case 0x3E: /* SDC2 */
2120 case 0x12: /* CP2 opcode */
2121 /* Not implemented */
2122 generate_exception_err(ctx
, EXCP_CpU
, 2);
2125 case 0x13: /* CP3 opcode */
2126 /* Not implemented */
2127 generate_exception_err(ctx
, EXCP_CpU
, 3);
2130 #if defined (TARGET_MIPS64)
2135 /* MIPS64 opcodes */
2137 #if defined (MIPS_HAS_JALX)
2139 /* JALX: not implemented */
2143 default: /* Invalid */
2145 generate_exception(ctx
, EXCP_RI
);
2148 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2149 int hflags
= ctx
->hflags
;
2150 /* Branches completion */
2151 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
2152 ctx
->bstate
= BS_BRANCH
;
2153 save_cpu_state(ctx
, 0);
2154 switch (hflags
& MIPS_HFLAG_BMASK
) {
2156 /* unconditional branch */
2157 MIPS_DEBUG("unconditional branch");
2158 gen_goto_tb(ctx
, 0, ctx
->btarget
);
2161 /* blikely taken case */
2162 MIPS_DEBUG("blikely branch taken");
2163 gen_goto_tb(ctx
, 0, ctx
->btarget
);
2166 /* Conditional branch */
2167 MIPS_DEBUG("conditional branch");
2170 l1
= gen_new_label();
2172 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
2174 gen_goto_tb(ctx
, 0, ctx
->btarget
);
2178 /* unconditional branch to register */
2179 MIPS_DEBUG("branch to register");
2183 MIPS_DEBUG("unknown branch");
2189 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
2192 DisasContext ctx
, *ctxp
= &ctx
;
2193 target_ulong pc_start
;
2194 uint16_t *gen_opc_end
;
2197 if (search_pc
&& loglevel
)
2198 fprintf (logfile
, "search pc %d\n", search_pc
);
2201 gen_opc_ptr
= gen_opc_buf
;
2202 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2203 gen_opparam_ptr
= gen_opparam_buf
;
2208 ctx
.bstate
= BS_NONE
;
2209 /* Restore delay slot state from the tb context. */
2210 ctx
.hflags
= tb
->flags
;
2211 ctx
.saved_hflags
= ctx
.hflags
;
2212 if (ctx
.hflags
& MIPS_HFLAG_BR
) {
2213 gen_op_restore_breg_target();
2214 } else if (ctx
.hflags
& MIPS_HFLAG_B
) {
2215 ctx
.btarget
= env
->btarget
;
2216 } else if (ctx
.hflags
& MIPS_HFLAG_BMASK
) {
2217 /* If we are in the delay slot of a conditional branch,
2218 * restore the branch condition from env->bcond to T2
2220 ctx
.btarget
= env
->btarget
;
2221 gen_op_restore_bcond();
2223 #if defined(CONFIG_USER_ONLY)
2226 ctx
.mem_idx
= !((ctx
.hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
);
2228 ctx
.CP0_Status
= env
->CP0_Status
;
2230 if (loglevel
& CPU_LOG_TB_CPU
) {
2231 fprintf(logfile
, "------------------------------------------------\n");
2232 /* FIXME: This may print out stale hflags from env... */
2233 cpu_dump_state(env
, logfile
, fprintf
, 0);
2236 #if defined MIPS_DEBUG_DISAS
2237 if (loglevel
& CPU_LOG_TB_IN_ASM
)
2238 fprintf(logfile
, "\ntb %p super %d cond %04x\n",
2239 tb
, ctx
.mem_idx
, ctx
.hflags
);
2241 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
2242 if (env
->nb_breakpoints
> 0) {
2243 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2244 if (env
->breakpoints
[j
] == ctx
.pc
) {
2245 save_cpu_state(ctxp
, 1);
2246 ctx
.bstate
= BS_BRANCH
;
2248 goto done_generating
;
2254 j
= gen_opc_ptr
- gen_opc_buf
;
2258 gen_opc_instr_start
[lj
++] = 0;
2260 gen_opc_pc
[lj
] = ctx
.pc
;
2261 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
2262 gen_opc_instr_start
[lj
] = 1;
2264 ctx
.opcode
= ldl_code(ctx
.pc
);
2268 if (env
->singlestep_enabled
)
2271 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
2274 #if defined (MIPS_SINGLE_STEP)
2278 if (env
->singlestep_enabled
) {
2279 save_cpu_state(ctxp
, ctx
.bstate
== BS_NONE
);
2281 goto done_generating
;
2283 else if (ctx
.bstate
!= BS_BRANCH
&& ctx
.bstate
!= BS_EXCP
) {
2284 save_cpu_state(ctxp
, 0);
2285 gen_goto_tb(&ctx
, 0, ctx
.pc
);
2288 /* Generate the return instruction */
2291 *gen_opc_ptr
= INDEX_op_end
;
2293 j
= gen_opc_ptr
- gen_opc_buf
;
2296 gen_opc_instr_start
[lj
++] = 0;
2299 tb
->size
= ctx
.pc
- pc_start
;
2302 #if defined MIPS_DEBUG_DISAS
2303 if (loglevel
& CPU_LOG_TB_IN_ASM
)
2304 fprintf(logfile
, "\n");
2306 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2307 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2308 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
2309 fprintf(logfile
, "\n");
2311 if (loglevel
& CPU_LOG_TB_OP
) {
2312 fprintf(logfile
, "OP:\n");
2313 dump_ops(gen_opc_buf
, gen_opparam_buf
);
2314 fprintf(logfile
, "\n");
2316 if (loglevel
& CPU_LOG_TB_CPU
) {
2317 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
2324 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2326 return gen_intermediate_code_internal(env
, tb
, 0);
2329 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2331 return gen_intermediate_code_internal(env
, tb
, 1);
2334 #ifdef MIPS_USES_FPU
2335 void fpu_dump_state(CPUState
*env
, FILE *f
,
2336 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
2341 # define printfpr(fp) do { \
2342 fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \
2343 (fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \
2346 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n",
2347 env
->fcr0
, env
->fcr31
,
2348 (env
->CP0_Status
& (1<<CP0St_FR
)) != 0);
2349 fpu_fprintf(f
, "FT0: "); printfpr(&env
->ft0
);
2350 fpu_fprintf(f
, "FT1: "); printfpr(&env
->ft1
);
2351 fpu_fprintf(f
, "FT2: "); printfpr(&env
->ft2
);
2352 for(i
=0; i
< 32; i
+=2) {
2353 fpu_fprintf(f
, "f%02d: ", i
);
2354 printfpr(FPR(env
, i
));
2360 void dump_fpu(CPUState
*env
)
2363 fprintf(logfile
, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
2364 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
2365 fpu_dump_state(env
, logfile
, fprintf
, 0);
2368 #endif /* MIPS_USES_FPU */
2370 void cpu_dump_state (CPUState
*env
, FILE *f
,
2371 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
2377 cpu_fprintf(f
, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
2378 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
2379 for (i
= 0; i
< 32; i
++) {
2381 cpu_fprintf(f
, "GPR%02d:", i
);
2382 cpu_fprintf(f
, " %s %08x", regnames
[i
], env
->gpr
[i
]);
2384 cpu_fprintf(f
, "\n");
2387 c0_status
= env
->CP0_Status
;
2388 if (env
->hflags
& MIPS_HFLAG_UM
)
2389 c0_status
|= (1 << CP0St_UM
);
2390 if (env
->hflags
& MIPS_HFLAG_ERL
)
2391 c0_status
|= (1 << CP0St_ERL
);
2392 if (env
->hflags
& MIPS_HFLAG_EXL
)
2393 c0_status
|= (1 << CP0St_EXL
);
2395 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
2396 c0_status
, env
->CP0_Cause
, env
->CP0_EPC
);
2397 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
2398 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
2399 #ifdef MIPS_USES_FPU
2400 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
2404 CPUMIPSState
*cpu_mips_init (void)
2408 env
= qemu_mallocz(sizeof(CPUMIPSState
));
2414 env
->PC
= 0xBFC00000;
2415 #if defined (MIPS_USES_R4K_TLB)
2416 env
->CP0_random
= MIPS_TLB_NB
- 1;
2419 env
->CP0_Config0
= MIPS_CONFIG0
;
2420 #if defined (MIPS_CONFIG1)
2421 env
->CP0_Config1
= MIPS_CONFIG1
;
2423 #if defined (MIPS_CONFIG2)
2424 env
->CP0_Config2
= MIPS_CONFIG2
;
2426 #if defined (MIPS_CONFIG3)
2427 env
->CP0_Config3
= MIPS_CONFIG3
;
2429 env
->CP0_Status
= (1 << CP0St_CU0
) | (1 << CP0St_BEV
);
2430 env
->CP0_WatchLo
= 0;
2431 env
->hflags
= MIPS_HFLAG_ERL
;
2432 /* Count register increments in debug mode, EJTAG version 1 */
2433 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
2434 env
->CP0_PRid
= MIPS_CPU
;
2435 env
->exception_index
= EXCP_NONE
;
2436 #if defined(CONFIG_USER_ONLY)
2437 env
->hflags
|= MIPS_HFLAG_UM
;
2439 #ifdef MIPS_USES_FPU
2440 env
->fcr0
= MIPS_FCR0
;