2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define KERNEL_LOAD_ADDR 0x00004000
27 #define CMDLINE_ADDR 0x007ff000
28 #define INITRD_LOAD_ADDR 0x00800000
29 #define PROM_SIZE_MAX (256 * 1024)
30 #define PROM_ADDR 0xffd00000
31 #define PROM_FILENAME "openbios-sparc32"
32 #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
33 #define PHYS_JJ_IDPROM_OFF 0x1FD8
34 #define PHYS_JJ_EEPROM_SIZE 0x2000
35 // IRQs are not PIL ones, but master interrupt controller register
37 #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
38 #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
39 #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
40 #define PHYS_JJ_DMA 0x78400000 /* DMA controller */
41 #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
42 #define PHYS_JJ_ESP_IRQ 18
43 #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
44 #define PHYS_JJ_LE_IRQ 16
45 #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
46 #define PHYS_JJ_CLOCK_IRQ 7
47 #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
48 #define PHYS_JJ_CLOCK1_IRQ 19
49 #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
50 #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
51 #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
52 #define PHYS_JJ_MS_KBD_IRQ 14
53 #define PHYS_JJ_SER 0x71100000 /* Serial */
54 #define PHYS_JJ_SER_IRQ 15
55 #define PHYS_JJ_FDC 0x71400000 /* Floppy */
56 #define PHYS_JJ_FLOPPY_IRQ 22
57 #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
58 #define PHYS_JJ_CS 0x6c000000 /* Crystal CS4231 */
59 #define PHYS_JJ_CS_IRQ 5
65 uint64_t cpu_get_tsc()
67 return qemu_get_clock(vm_clock
);
70 int DMA_get_channel_mode (int nchan
)
74 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
78 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
82 void DMA_hold_DREQ (int nchan
) {}
83 void DMA_release_DREQ (int nchan
) {}
84 void DMA_schedule(int nchan
) {}
85 void DMA_run (void) {}
86 void DMA_init (int high_page_enable
) {}
87 void DMA_register_channel (int nchan
,
88 DMA_transfer_handler transfer_handler
,
93 static void nvram_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
)
95 m48t59_write(nvram
, addr
++, (value
>> 8) & 0xff);
96 m48t59_write(nvram
, addr
++, value
& 0xff);
99 static void nvram_set_lword (m48t59_t
*nvram
, uint32_t addr
, uint32_t value
)
101 m48t59_write(nvram
, addr
++, value
>> 24);
102 m48t59_write(nvram
, addr
++, (value
>> 16) & 0xff);
103 m48t59_write(nvram
, addr
++, (value
>> 8) & 0xff);
104 m48t59_write(nvram
, addr
++, value
& 0xff);
107 static void nvram_set_string (m48t59_t
*nvram
, uint32_t addr
,
108 const unsigned char *str
, uint32_t max
)
112 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
113 m48t59_write(nvram
, addr
+ i
, str
[i
]);
115 m48t59_write(nvram
, addr
+ max
- 1, '\0');
118 static m48t59_t
*nvram
;
120 extern int nographic
;
122 static void nvram_init(m48t59_t
*nvram
, uint8_t *macaddr
, const char *cmdline
,
123 int boot_device
, uint32_t RAM_size
,
124 uint32_t kernel_size
,
125 int width
, int height
, int depth
)
127 unsigned char tmp
= 0;
130 // Try to match PPC NVRAM
131 nvram_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
132 nvram_set_lword(nvram
, 0x10, 0x00000001); /* structure v1 */
133 // NVRAM_size, arch not applicable
134 m48t59_write(nvram
, 0x2D, smp_cpus
& 0xff);
135 m48t59_write(nvram
, 0x2E, 0);
136 m48t59_write(nvram
, 0x2F, nographic
& 0xff);
137 nvram_set_lword(nvram
, 0x30, RAM_size
);
138 m48t59_write(nvram
, 0x34, boot_device
& 0xff);
139 nvram_set_lword(nvram
, 0x38, KERNEL_LOAD_ADDR
);
140 nvram_set_lword(nvram
, 0x3C, kernel_size
);
142 strcpy(phys_ram_base
+ CMDLINE_ADDR
, cmdline
);
143 nvram_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
144 nvram_set_lword(nvram
, 0x44, strlen(cmdline
));
146 // initrd_image, initrd_size passed differently
147 nvram_set_word(nvram
, 0x54, width
);
148 nvram_set_word(nvram
, 0x56, height
);
149 nvram_set_word(nvram
, 0x58, depth
);
151 // Sun4m specific use
153 m48t59_write(nvram
, i
++, 0x01);
154 m48t59_write(nvram
, i
++, 0x80); /* Sun4m OBP */
156 m48t59_write(nvram
, i
++, macaddr
[j
++]);
157 m48t59_write(nvram
, i
++, macaddr
[j
++]);
158 m48t59_write(nvram
, i
++, macaddr
[j
++]);
159 m48t59_write(nvram
, i
++, macaddr
[j
++]);
160 m48t59_write(nvram
, i
++, macaddr
[j
++]);
161 m48t59_write(nvram
, i
, macaddr
[j
]);
163 /* Calculate checksum */
164 for (i
= 0x1fd8; i
< 0x1fe7; i
++) {
165 tmp
^= m48t59_read(nvram
, i
);
167 m48t59_write(nvram
, 0x1fe7, tmp
);
170 static void *slavio_intctl
;
174 slavio_pic_info(slavio_intctl
);
179 slavio_irq_info(slavio_intctl
);
182 void pic_set_irq(int irq
, int level
)
184 slavio_pic_set_irq(slavio_intctl
, irq
, level
);
187 void pic_set_irq_new(void *opaque
, int irq
, int level
)
189 pic_set_irq(irq
, level
);
192 void pic_set_irq_cpu(int irq
, int level
, unsigned int cpu
)
194 slavio_pic_set_irq_cpu(slavio_intctl
, irq
, level
, cpu
);
197 static void *slavio_misc
;
199 void qemu_system_powerdown(void)
201 slavio_set_power_fail(slavio_misc
, 1);
204 static void main_cpu_reset(void *opaque
)
206 CPUState
*env
= opaque
;
210 /* Sun4m hardware initialisation */
211 static void sun4m_init(int ram_size
, int vga_ram_size
, int boot_device
,
212 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
213 const char *kernel_filename
, const char *kernel_cmdline
,
214 const char *initrd_filename
, const char *cpu_model
)
216 CPUState
*env
, *envs
[MAX_CPUS
];
220 long vram_size
= 0x100000, prom_offset
, initrd_size
, kernel_size
;
221 void *iommu
, *dma
, *main_esp
, *main_lance
= NULL
;
223 linux_boot
= (kernel_filename
!= NULL
);
226 for(i
= 0; i
< smp_cpus
; i
++) {
231 register_savevm("cpu", i
, 3, cpu_save
, cpu_load
, env
);
232 qemu_register_reset(main_cpu_reset
, env
);
235 cpu_register_physical_memory(0, ram_size
, 0);
237 iommu
= iommu_init(PHYS_JJ_IOMMU
);
238 slavio_intctl
= slavio_intctl_init(PHYS_JJ_INTR0
, PHYS_JJ_INTR_G
);
239 for(i
= 0; i
< smp_cpus
; i
++) {
240 slavio_intctl_set_cpu(slavio_intctl
, i
, envs
[i
]);
242 dma
= sparc32_dma_init(PHYS_JJ_DMA
, PHYS_JJ_ESP_IRQ
, PHYS_JJ_LE_IRQ
, iommu
, slavio_intctl
);
244 tcx_init(ds
, PHYS_JJ_TCX_FB
, phys_ram_base
+ ram_size
, ram_size
, vram_size
, graphic_width
, graphic_height
);
245 if (nd_table
[0].vlan
) {
246 if (nd_table
[0].model
== NULL
247 || strcmp(nd_table
[0].model
, "lance") == 0) {
248 main_lance
= lance_init(&nd_table
[0], PHYS_JJ_LE
, dma
);
250 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd_table
[0].model
);
254 nvram
= m48t59_init(0, PHYS_JJ_EEPROM
, 0, PHYS_JJ_EEPROM_SIZE
, 8);
255 for (i
= 0; i
< MAX_CPUS
; i
++) {
256 slavio_timer_init(PHYS_JJ_CLOCK
+ i
* TARGET_PAGE_SIZE
, PHYS_JJ_CLOCK_IRQ
, 0, i
);
258 slavio_timer_init(PHYS_JJ_CLOCK1
, PHYS_JJ_CLOCK1_IRQ
, 2, (unsigned int)-1);
259 slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD
, PHYS_JJ_MS_KBD_IRQ
);
260 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
261 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
262 slavio_serial_init(PHYS_JJ_SER
, PHYS_JJ_SER_IRQ
, serial_hds
[1], serial_hds
[0]);
263 fdctrl_init(PHYS_JJ_FLOPPY_IRQ
, 0, 1, PHYS_JJ_FDC
, fd_table
);
264 main_esp
= esp_init(bs_table
, PHYS_JJ_ESP
, dma
);
266 for (i
= 0; i
< MAX_DISKS
; i
++) {
268 esp_scsi_attach(main_esp
, bs_table
[i
], i
);
272 slavio_misc
= slavio_misc_init(PHYS_JJ_SLAVIO
, PHYS_JJ_ME_IRQ
);
273 cs_init(PHYS_JJ_CS
, PHYS_JJ_CS_IRQ
, slavio_intctl
);
274 sparc32_dma_set_reset_data(dma
, main_esp
, main_lance
);
276 prom_offset
= ram_size
+ vram_size
;
277 cpu_register_physical_memory(PROM_ADDR
,
278 (PROM_SIZE_MAX
+ TARGET_PAGE_SIZE
- 1) & TARGET_PAGE_MASK
,
279 prom_offset
| IO_MEM_ROM
);
281 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, PROM_FILENAME
);
282 ret
= load_elf(buf
, 0, NULL
);
284 fprintf(stderr
, "qemu: could not load prom '%s'\n",
291 kernel_size
= load_elf(kernel_filename
, -0xf0000000, NULL
);
293 kernel_size
= load_aout(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
295 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
296 if (kernel_size
< 0) {
297 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
304 if (initrd_filename
) {
305 initrd_size
= load_image(initrd_filename
, phys_ram_base
+ INITRD_LOAD_ADDR
);
306 if (initrd_size
< 0) {
307 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
312 if (initrd_size
> 0) {
313 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
314 if (ldl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
)
315 == 0x48647253) { // HdrS
316 stl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
317 stl_raw(phys_ram_base
+ KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
323 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
, boot_device
, ram_size
, kernel_size
, graphic_width
, graphic_height
, graphic_depth
);
326 QEMUMachine sun4m_machine
= {