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PowerPC improvments:
[qemu/mini2440.git] / cpu-exec.c
blob634f1ba875450eeb2b02da7a09f2b4d002bc67b1
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
181 #else
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
195 cs_base = 0;
196 pc = env->PC;
197 #elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
201 #elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
205 #else
206 #error unsupported CPU
207 #endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
220 }
221 return tb;
222 }
223
224
225 /* main execution loop */
226
227 int cpu_exec(CPUState *env1)
228 {
229 #define DECLARE_HOST_REGS 1
230 #include "hostregs_helper.h"
231 #if defined(TARGET_SPARC)
232 #if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
234 #endif
235 #endif
236 #if defined(__sparc__) && !defined(HOST_SOLARIS)
237 int saved_i7;
238 target_ulong tmp_T0;
239 #endif
240 int ret, interrupt_request;
241 void (*gen_func)(void);
242 TranslationBlock *tb;
243 uint8_t *tc_ptr;
244
245 #if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
252 } else {
253 return EXCP_HALTED;
254 }
255 }
256 #elif defined(TARGET_PPC)
257 if (env1->halted) {
258 if (env1->msr[MSR_EE] &&
259 (env1->interrupt_request &
260 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
261 env1->halted = 0;
262 } else {
263 return EXCP_HALTED;
264 }
265 }
266 #elif defined(TARGET_SPARC)
267 if (env1->halted) {
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->psret != 0)) {
270 env1->halted = 0;
271 } else {
272 return EXCP_HALTED;
273 }
274 }
275 #elif defined(TARGET_ARM)
276 if (env1->halted) {
277 /* An interrupt wakes the CPU even if the I and F CPSR bits are
278 set. */
279 if (env1->interrupt_request
280 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
281 env1->halted = 0;
282 } else {
283 return EXCP_HALTED;
284 }
285 }
286 #elif defined(TARGET_MIPS)
287 if (env1->halted) {
288 if (env1->interrupt_request &
289 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
290 env1->halted = 0;
291 } else {
292 return EXCP_HALTED;
293 }
294 }
295 #endif
296
297 cpu_single_env = env1;
298
299 /* first we save global registers */
300 #define SAVE_HOST_REGS 1
301 #include "hostregs_helper.h"
302 env = env1;
303 #if defined(__sparc__) && !defined(HOST_SOLARIS)
304 /* we also save i7 because longjmp may not restore it */
305 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
306 #endif
307
308 #if defined(TARGET_I386)
309 env_to_regs();
310 /* put eflags in CPU temporary format */
311 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
312 DF = 1 - (2 * ((env->eflags >> 10) & 1));
313 CC_OP = CC_OP_EFLAGS;
314 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
315 #elif defined(TARGET_ARM)
316 #elif defined(TARGET_SPARC)
317 #if defined(reg_REGWPTR)
318 saved_regwptr = REGWPTR;
319 #endif
320 #elif defined(TARGET_PPC)
321 #elif defined(TARGET_M68K)
322 env->cc_op = CC_OP_FLAGS;
323 env->cc_dest = env->sr & 0xf;
324 env->cc_x = (env->sr >> 4) & 1;
325 #elif defined(TARGET_MIPS)
326 #elif defined(TARGET_SH4)
327 /* XXXXX */
328 #else
329 #error unsupported target CPU
330 #endif
331 env->exception_index = -1;
332
333 /* prepare setjmp context for exception handling */
334 for(;;) {
335 if (setjmp(env->jmp_env) == 0) {
336 env->current_tb = NULL;
337 /* if an exception is pending, we execute it here */
338 if (env->exception_index >= 0) {
339 if (env->exception_index >= EXCP_INTERRUPT) {
340 /* exit request from the cpu execution loop */
341 ret = env->exception_index;
342 break;
343 } else if (env->user_mode_only) {
344 /* if user mode only, we simulate a fake exception
345 which will be handled outside the cpu execution
346 loop */
347 #if defined(TARGET_I386)
348 do_interrupt_user(env->exception_index,
349 env->exception_is_int,
350 env->error_code,
351 env->exception_next_eip);
352 #endif
353 ret = env->exception_index;
354 break;
355 } else {
356 #if defined(TARGET_I386)
357 /* simulate a real cpu exception. On i386, it can
358 trigger new exceptions, but we do not handle
359 double or triple faults yet. */
360 do_interrupt(env->exception_index,
361 env->exception_is_int,
362 env->error_code,
363 env->exception_next_eip, 0);
364 #elif defined(TARGET_PPC)
365 do_interrupt(env);
366 #elif defined(TARGET_MIPS)
367 do_interrupt(env);
368 #elif defined(TARGET_SPARC)
369 do_interrupt(env->exception_index);
370 #elif defined(TARGET_ARM)
371 do_interrupt(env);
372 #elif defined(TARGET_SH4)
373 do_interrupt(env);
374 #endif
375 }
376 env->exception_index = -1;
377 }
378 #ifdef USE_KQEMU
379 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
380 int ret;
381 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
382 ret = kqemu_cpu_exec(env);
383 /* put eflags in CPU temporary format */
384 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
385 DF = 1 - (2 * ((env->eflags >> 10) & 1));
386 CC_OP = CC_OP_EFLAGS;
387 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
388 if (ret == 1) {
389 /* exception */
390 longjmp(env->jmp_env, 1);
391 } else if (ret == 2) {
392 /* softmmu execution needed */
393 } else {
394 if (env->interrupt_request != 0) {
395 /* hardware interrupt will be executed just after */
396 } else {
397 /* otherwise, we restart */
398 longjmp(env->jmp_env, 1);
399 }
400 }
401 }
402 #endif
403
404 T0 = 0; /* force lookup of first TB */
405 for(;;) {
406 #if defined(__sparc__) && !defined(HOST_SOLARIS)
407 /* g1 can be modified by some libc? functions */
408 tmp_T0 = T0;
409 #endif
410 interrupt_request = env->interrupt_request;
411 if (__builtin_expect(interrupt_request, 0)) {
412 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
413 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
414 env->exception_index = EXCP_DEBUG;
415 cpu_loop_exit();
416 }
417 #if defined(TARGET_I386)
418 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
419 !(env->hflags & HF_SMM_MASK)) {
420 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
421 do_smm_enter();
422 #if defined(__sparc__) && !defined(HOST_SOLARIS)
423 tmp_T0 = 0;
424 #else
425 T0 = 0;
426 #endif
427 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
428 (env->eflags & IF_MASK) &&
429 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
430 int intno;
431 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
432 intno = cpu_get_pic_interrupt(env);
433 if (loglevel & CPU_LOG_TB_IN_ASM) {
434 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
435 }
436 do_interrupt(intno, 0, 0, 0, 1);
437 /* ensure that no TB jump will be modified as
438 the program flow was changed */
439 #if defined(__sparc__) && !defined(HOST_SOLARIS)
440 tmp_T0 = 0;
441 #else
442 T0 = 0;
443 #endif
444 }
445 #elif defined(TARGET_PPC)
446 #if 0
447 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
448 cpu_ppc_reset(env);
449 }
450 #endif
451 if (msr_ee != 0) {
452 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
453 /* Raise it */
454 env->exception_index = EXCP_EXTERNAL;
455 env->error_code = 0;
456 do_interrupt(env);
457 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
458 #if defined(__sparc__) && !defined(HOST_SOLARIS)
459 tmp_T0 = 0;
460 #else
461 T0 = 0;
462 #endif
463 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
464 /* Raise it */
465 env->exception_index = EXCP_DECR;
466 env->error_code = 0;
467 do_interrupt(env);
468 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
469 #if defined(__sparc__) && !defined(HOST_SOLARIS)
470 tmp_T0 = 0;
471 #else
472 T0 = 0;
473 #endif
474 }
475 }
476 #elif defined(TARGET_MIPS)
477 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
478 (env->CP0_Status & (1 << CP0St_IE)) &&
479 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
480 !(env->hflags & MIPS_HFLAG_EXL) &&
481 !(env->hflags & MIPS_HFLAG_ERL) &&
482 !(env->hflags & MIPS_HFLAG_DM)) {
483 /* Raise it */
484 env->exception_index = EXCP_EXT_INTERRUPT;
485 env->error_code = 0;
486 do_interrupt(env);
487 #if defined(__sparc__) && !defined(HOST_SOLARIS)
488 tmp_T0 = 0;
489 #else
490 T0 = 0;
491 #endif
492 }
493 #elif defined(TARGET_SPARC)
494 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
495 (env->psret != 0)) {
496 int pil = env->interrupt_index & 15;
497 int type = env->interrupt_index & 0xf0;
498
499 if (((type == TT_EXTINT) &&
500 (pil == 15 || pil > env->psrpil)) ||
501 type != TT_EXTINT) {
502 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
503 do_interrupt(env->interrupt_index);
504 env->interrupt_index = 0;
505 #if defined(__sparc__) && !defined(HOST_SOLARIS)
506 tmp_T0 = 0;
507 #else
508 T0 = 0;
509 #endif
510 }
511 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
512 //do_interrupt(0, 0, 0, 0, 0);
513 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
514 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
515 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
516 env->halted = 1;
517 env->exception_index = EXCP_HLT;
518 cpu_loop_exit();
519 }
520 #elif defined(TARGET_ARM)
521 if (interrupt_request & CPU_INTERRUPT_FIQ
522 && !(env->uncached_cpsr & CPSR_F)) {
523 env->exception_index = EXCP_FIQ;
524 do_interrupt(env);
525 }
526 if (interrupt_request & CPU_INTERRUPT_HARD
527 && !(env->uncached_cpsr & CPSR_I)) {
528 env->exception_index = EXCP_IRQ;
529 do_interrupt(env);
530 }
531 #elif defined(TARGET_SH4)
532 /* XXXXX */
533 #endif
534 /* Don't use the cached interupt_request value,
535 do_interrupt may have updated the EXITTB flag. */
536 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
537 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
538 /* ensure that no TB jump will be modified as
539 the program flow was changed */
540 #if defined(__sparc__) && !defined(HOST_SOLARIS)
541 tmp_T0 = 0;
542 #else
543 T0 = 0;
544 #endif
545 }
546 if (interrupt_request & CPU_INTERRUPT_EXIT) {
547 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
548 env->exception_index = EXCP_INTERRUPT;
549 cpu_loop_exit();
550 }
551 }
552 #ifdef DEBUG_EXEC
553 if ((loglevel & CPU_LOG_TB_CPU)) {
554 #if defined(TARGET_I386)
555 /* restore flags in standard format */
556 #ifdef reg_EAX
557 env->regs[R_EAX] = EAX;
558 #endif
559 #ifdef reg_EBX
560 env->regs[R_EBX] = EBX;
561 #endif
562 #ifdef reg_ECX
563 env->regs[R_ECX] = ECX;
564 #endif
565 #ifdef reg_EDX
566 env->regs[R_EDX] = EDX;
567 #endif
568 #ifdef reg_ESI
569 env->regs[R_ESI] = ESI;
570 #endif
571 #ifdef reg_EDI
572 env->regs[R_EDI] = EDI;
573 #endif
574 #ifdef reg_EBP
575 env->regs[R_EBP] = EBP;
576 #endif
577 #ifdef reg_ESP
578 env->regs[R_ESP] = ESP;
579 #endif
580 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
581 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
582 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
583 #elif defined(TARGET_ARM)
584 cpu_dump_state(env, logfile, fprintf, 0);
585 #elif defined(TARGET_SPARC)
586 REGWPTR = env->regbase + (env->cwp * 16);
587 env->regwptr = REGWPTR;
588 cpu_dump_state(env, logfile, fprintf, 0);
589 #elif defined(TARGET_PPC)
590 cpu_dump_state(env, logfile, fprintf, 0);
591 #elif defined(TARGET_M68K)
592 cpu_m68k_flush_flags(env, env->cc_op);
593 env->cc_op = CC_OP_FLAGS;
594 env->sr = (env->sr & 0xffe0)
595 | env->cc_dest | (env->cc_x << 4);
596 cpu_dump_state(env, logfile, fprintf, 0);
597 #elif defined(TARGET_MIPS)
598 cpu_dump_state(env, logfile, fprintf, 0);
599 #elif defined(TARGET_SH4)
600 cpu_dump_state(env, logfile, fprintf, 0);
601 #else
602 #error unsupported target CPU
603 #endif
604 }
605 #endif
606 tb = tb_find_fast();
607 #ifdef DEBUG_EXEC
608 if ((loglevel & CPU_LOG_EXEC)) {
609 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
610 (long)tb->tc_ptr, tb->pc,
611 lookup_symbol(tb->pc));
612 }
613 #endif
614 #if defined(__sparc__) && !defined(HOST_SOLARIS)
615 T0 = tmp_T0;
616 #endif
617 /* see if we can patch the calling TB. When the TB
618 spans two pages, we cannot safely do a direct
619 jump. */
620 {
621 if (T0 != 0 &&
622 #if USE_KQEMU
623 (env->kqemu_enabled != 2) &&
624 #endif
625 tb->page_addr[1] == -1
626 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
627 && (tb->cflags & CF_CODE_COPY) ==
628 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
629 #endif
630 ) {
631 spin_lock(&tb_lock);
632 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
633 #if defined(USE_CODE_COPY)
634 /* propagates the FP use info */
635 ((TranslationBlock *)(T0 & ~3))->cflags |=
636 (tb->cflags & CF_FP_USED);
637 #endif
638 spin_unlock(&tb_lock);
639 }
640 }
641 tc_ptr = tb->tc_ptr;
642 env->current_tb = tb;
643 /* execute the generated code */
644 gen_func = (void *)tc_ptr;
645 #if defined(__sparc__)
646 __asm__ __volatile__("call %0\n\t"
647 "mov %%o7,%%i0"
648 : /* no outputs */
649 : "r" (gen_func)
650 : "i0", "i1", "i2", "i3", "i4", "i5",
651 "o0", "o1", "o2", "o3", "o4", "o5",
652 "l0", "l1", "l2", "l3", "l4", "l5",
653 "l6", "l7");
654 #elif defined(__arm__)
655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
657 "exec_loop:\n\t"
658 : /* no outputs */
659 : "r" (gen_func)
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
661 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
662 {
663 if (!(tb->cflags & CF_CODE_COPY)) {
664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
666 }
667 gen_func();
668 } else {
669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
671 }
672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
676 "\n"
677 "debug1:\n"
678 " pushl %%ebp\n"
679 " fs movl %10, %9\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
683 " pushl %%eax\n"
684 " popf\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
694 " fs jmp *%9\n"
695 "exec_loop:\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
705 " pushf\n"
706 " popl %%eax\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
709 " shrl $9, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
712 " movl $1, %%eax\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
716 " popl %%ebp\n"
717 :
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
728 "a" (gen_func),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
731 : "%ecx", "%edx"
732 );
733 }
734 }
735 #elif defined(__ia64)
736 struct fptr {
737 void *ip;
738 void *gp;
739 } fp;
740
741 fp.ip = tc_ptr;
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
744 #else
745 gen_func();
746 #endif
747 env->current_tb = NULL;
748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
753 /* do not allow linking to another block */
754 T0 = 0;
755 }
756 #endif
757 #if defined(USE_KQEMU)
758 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
759 if (kqemu_is_ok(env) &&
760 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
761 cpu_loop_exit();
762 }
763 #endif
764 }
765 } else {
766 env_to_regs();
767 }
768 } /* for(;;) */
769
770
771 #if defined(TARGET_I386)
772 #if defined(USE_CODE_COPY)
773 if (env->native_fp_regs) {
774 save_native_fp_state(env);
775 }
776 #endif
777 /* restore flags in standard format */
778 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
779 #elif defined(TARGET_ARM)
780 /* XXX: Save/restore host fpu exception state?. */
781 #elif defined(TARGET_SPARC)
782 #if defined(reg_REGWPTR)
783 REGWPTR = saved_regwptr;
784 #endif
785 #elif defined(TARGET_PPC)
786 #elif defined(TARGET_M68K)
787 cpu_m68k_flush_flags(env, env->cc_op);
788 env->cc_op = CC_OP_FLAGS;
789 env->sr = (env->sr & 0xffe0)
790 | env->cc_dest | (env->cc_x << 4);
791 #elif defined(TARGET_MIPS)
792 #elif defined(TARGET_SH4)
793 /* XXXXX */
794 #else
795 #error unsupported target CPU
796 #endif
797
798 /* restore global registers */
799 #if defined(__sparc__) && !defined(HOST_SOLARIS)
800 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
801 #endif
802 #include "hostregs_helper.h"
803
804 /* fail safe : never use cpu_single_env outside cpu_exec() */
805 cpu_single_env = NULL;
806 return ret;
807 }
808
809 /* must only be called from the generated code as an exception can be
810 generated */
811 void tb_invalidate_page_range(target_ulong start, target_ulong end)
812 {
813 /* XXX: cannot enable it yet because it yields to MMU exception
814 where NIP != read address on PowerPC */
815 #if 0
816 target_ulong phys_addr;
817 phys_addr = get_phys_addr_code(env, start);
818 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
819 #endif
820 }
821
822 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
823
824 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
825 {
826 CPUX86State *saved_env;
827
828 saved_env = env;
829 env = s;
830 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
831 selector &= 0xffff;
832 cpu_x86_load_seg_cache(env, seg_reg, selector,
833 (selector << 4), 0xffff, 0);
834 } else {
835 load_seg(seg_reg, selector);
836 }
837 env = saved_env;
838 }
839
840 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
841 {
842 CPUX86State *saved_env;
843
844 saved_env = env;
845 env = s;
846
847 helper_fsave((target_ulong)ptr, data32);
848
849 env = saved_env;
850 }
851
852 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
853 {
854 CPUX86State *saved_env;
855
856 saved_env = env;
857 env = s;
858
859 helper_frstor((target_ulong)ptr, data32);
860
861 env = saved_env;
862 }
863
864 #endif /* TARGET_I386 */
865
866 #if !defined(CONFIG_SOFTMMU)
867
868 #if defined(TARGET_I386)
869
870 /* 'pc' is the host PC at which the exception was raised. 'address' is
871 the effective address of the memory exception. 'is_write' is 1 if a
872 write caused the exception and otherwise 0'. 'old_set' is the
873 signal set which should be restored */
874 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
875 int is_write, sigset_t *old_set,
876 void *puc)
877 {
878 TranslationBlock *tb;
879 int ret;
880
881 if (cpu_single_env)
882 env = cpu_single_env; /* XXX: find a correct solution for multithread */
883 #if defined(DEBUG_SIGNAL)
884 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
885 pc, address, is_write, *(unsigned long *)old_set);
886 #endif
887 /* XXX: locking issue */
888 if (is_write && page_unprotect(h2g(address), pc, puc)) {
889 return 1;
890 }
891
892 /* see if it is an MMU fault */
893 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
894 ((env->hflags & HF_CPL_MASK) == 3), 0);
895 if (ret < 0)
896 return 0; /* not an MMU fault */
897 if (ret == 0)
898 return 1; /* the MMU fault was handled without causing real CPU fault */
899 /* now we have a real cpu fault */
900 tb = tb_find_pc(pc);
901 if (tb) {
902 /* the PC is inside the translated code. It means that we have
903 a virtual CPU fault */
904 cpu_restore_state(tb, env, pc, puc);
905 }
906 if (ret == 1) {
907 #if 0
908 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
909 env->eip, env->cr[2], env->error_code);
910 #endif
911 /* we restore the process signal mask as the sigreturn should
912 do it (XXX: use sigsetjmp) */
913 sigprocmask(SIG_SETMASK, old_set, NULL);
914 raise_exception_err(env->exception_index, env->error_code);
915 } else {
916 /* activate soft MMU for this block */
917 env->hflags |= HF_SOFTMMU_MASK;
918 cpu_resume_from_signal(env, puc);
919 }
920 /* never comes here */
921 return 1;
922 }
923
924 #elif defined(TARGET_ARM)
925 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
926 int is_write, sigset_t *old_set,
927 void *puc)
928 {
929 TranslationBlock *tb;
930 int ret;
931
932 if (cpu_single_env)
933 env = cpu_single_env; /* XXX: find a correct solution for multithread */
934 #if defined(DEBUG_SIGNAL)
935 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
936 pc, address, is_write, *(unsigned long *)old_set);
937 #endif
938 /* XXX: locking issue */
939 if (is_write && page_unprotect(h2g(address), pc, puc)) {
940 return 1;
941 }
942 /* see if it is an MMU fault */
943 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
944 if (ret < 0)
945 return 0; /* not an MMU fault */
946 if (ret == 0)
947 return 1; /* the MMU fault was handled without causing real CPU fault */
948 /* now we have a real cpu fault */
949 tb = tb_find_pc(pc);
950 if (tb) {
951 /* the PC is inside the translated code. It means that we have
952 a virtual CPU fault */
953 cpu_restore_state(tb, env, pc, puc);
954 }
955 /* we restore the process signal mask as the sigreturn should
956 do it (XXX: use sigsetjmp) */
957 sigprocmask(SIG_SETMASK, old_set, NULL);
958 cpu_loop_exit();
959 }
960 #elif defined(TARGET_SPARC)
961 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
962 int is_write, sigset_t *old_set,
963 void *puc)
964 {
965 TranslationBlock *tb;
966 int ret;
967
968 if (cpu_single_env)
969 env = cpu_single_env; /* XXX: find a correct solution for multithread */
970 #if defined(DEBUG_SIGNAL)
971 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
972 pc, address, is_write, *(unsigned long *)old_set);
973 #endif
974 /* XXX: locking issue */
975 if (is_write && page_unprotect(h2g(address), pc, puc)) {
976 return 1;
977 }
978 /* see if it is an MMU fault */
979 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
980 if (ret < 0)
981 return 0; /* not an MMU fault */
982 if (ret == 0)
983 return 1; /* the MMU fault was handled without causing real CPU fault */
984 /* now we have a real cpu fault */
985 tb = tb_find_pc(pc);
986 if (tb) {
987 /* the PC is inside the translated code. It means that we have
988 a virtual CPU fault */
989 cpu_restore_state(tb, env, pc, puc);
990 }
991 /* we restore the process signal mask as the sigreturn should
992 do it (XXX: use sigsetjmp) */
993 sigprocmask(SIG_SETMASK, old_set, NULL);
994 cpu_loop_exit();
995 }
996 #elif defined (TARGET_PPC)
997 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
998 int is_write, sigset_t *old_set,
999 void *puc)
1000 {
1001 TranslationBlock *tb;
1002 int ret;
1003
1004 if (cpu_single_env)
1005 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1006 #if defined(DEBUG_SIGNAL)
1007 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1008 pc, address, is_write, *(unsigned long *)old_set);
1009 #endif
1010 /* XXX: locking issue */
1011 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1012 return 1;
1013 }
1014
1015 /* see if it is an MMU fault */
1016 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1017 if (ret < 0)
1018 return 0; /* not an MMU fault */
1019 if (ret == 0)
1020 return 1; /* the MMU fault was handled without causing real CPU fault */
1021
1022 /* now we have a real cpu fault */
1023 tb = tb_find_pc(pc);
1024 if (tb) {
1025 /* the PC is inside the translated code. It means that we have
1026 a virtual CPU fault */
1027 cpu_restore_state(tb, env, pc, puc);
1028 }
1029 if (ret == 1) {
1030 #if 0
1031 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1032 env->nip, env->error_code, tb);
1033 #endif
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
1036 sigprocmask(SIG_SETMASK, old_set, NULL);
1037 do_raise_exception_err(env->exception_index, env->error_code);
1038 } else {
1039 /* activate soft MMU for this block */
1040 cpu_resume_from_signal(env, puc);
1041 }
1042 /* never comes here */
1043 return 1;
1044 }
1045
1046 #elif defined(TARGET_M68K)
1047 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1048 int is_write, sigset_t *old_set,
1049 void *puc)
1050 {
1051 TranslationBlock *tb;
1052 int ret;
1053
1054 if (cpu_single_env)
1055 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1056 #if defined(DEBUG_SIGNAL)
1057 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1058 pc, address, is_write, *(unsigned long *)old_set);
1059 #endif
1060 /* XXX: locking issue */
1061 if (is_write && page_unprotect(address, pc, puc)) {
1062 return 1;
1063 }
1064 /* see if it is an MMU fault */
1065 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1066 if (ret < 0)
1067 return 0; /* not an MMU fault */
1068 if (ret == 0)
1069 return 1; /* the MMU fault was handled without causing real CPU fault */
1070 /* now we have a real cpu fault */
1071 tb = tb_find_pc(pc);
1072 if (tb) {
1073 /* the PC is inside the translated code. It means that we have
1074 a virtual CPU fault */
1075 cpu_restore_state(tb, env, pc, puc);
1076 }
1077 /* we restore the process signal mask as the sigreturn should
1078 do it (XXX: use sigsetjmp) */
1079 sigprocmask(SIG_SETMASK, old_set, NULL);
1080 cpu_loop_exit();
1081 /* never comes here */
1082 return 1;
1083 }
1084
1085 #elif defined (TARGET_MIPS)
1086 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1087 int is_write, sigset_t *old_set,
1088 void *puc)
1089 {
1090 TranslationBlock *tb;
1091 int ret;
1092
1093 if (cpu_single_env)
1094 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1095 #if defined(DEBUG_SIGNAL)
1096 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1097 pc, address, is_write, *(unsigned long *)old_set);
1098 #endif
1099 /* XXX: locking issue */
1100 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1101 return 1;
1102 }
1103
1104 /* see if it is an MMU fault */
1105 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1106 if (ret < 0)
1107 return 0; /* not an MMU fault */
1108 if (ret == 0)
1109 return 1; /* the MMU fault was handled without causing real CPU fault */
1110
1111 /* now we have a real cpu fault */
1112 tb = tb_find_pc(pc);
1113 if (tb) {
1114 /* the PC is inside the translated code. It means that we have
1115 a virtual CPU fault */
1116 cpu_restore_state(tb, env, pc, puc);
1117 }
1118 if (ret == 1) {
1119 #if 0
1120 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1121 env->nip, env->error_code, tb);
1122 #endif
1123 /* we restore the process signal mask as the sigreturn should
1124 do it (XXX: use sigsetjmp) */
1125 sigprocmask(SIG_SETMASK, old_set, NULL);
1126 do_raise_exception_err(env->exception_index, env->error_code);
1127 } else {
1128 /* activate soft MMU for this block */
1129 cpu_resume_from_signal(env, puc);
1130 }
1131 /* never comes here */
1132 return 1;
1133 }
1134
1135 #elif defined (TARGET_SH4)
1136 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1137 int is_write, sigset_t *old_set,
1138 void *puc)
1139 {
1140 TranslationBlock *tb;
1141 int ret;
1142
1143 if (cpu_single_env)
1144 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1145 #if defined(DEBUG_SIGNAL)
1146 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1147 pc, address, is_write, *(unsigned long *)old_set);
1148 #endif
1149 /* XXX: locking issue */
1150 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1151 return 1;
1152 }
1153
1154 /* see if it is an MMU fault */
1155 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1156 if (ret < 0)
1157 return 0; /* not an MMU fault */
1158 if (ret == 0)
1159 return 1; /* the MMU fault was handled without causing real CPU fault */
1160
1161 /* now we have a real cpu fault */
1162 tb = tb_find_pc(pc);
1163 if (tb) {
1164 /* the PC is inside the translated code. It means that we have
1165 a virtual CPU fault */
1166 cpu_restore_state(tb, env, pc, puc);
1167 }
1168 #if 0
1169 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1170 env->nip, env->error_code, tb);
1171 #endif
1172 /* we restore the process signal mask as the sigreturn should
1173 do it (XXX: use sigsetjmp) */
1174 sigprocmask(SIG_SETMASK, old_set, NULL);
1175 cpu_loop_exit();
1176 /* never comes here */
1177 return 1;
1178 }
1179 #else
1180 #error unsupported target CPU
1181 #endif
1182
1183 #if defined(__i386__)
1184
1185 #if defined(__APPLE__)
1186 # include <sys/ucontext.h>
1187
1188 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1189 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1190 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1191 #else
1192 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1193 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1194 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1195 #endif
1196
1197 #if defined(USE_CODE_COPY)
1198 static void cpu_send_trap(unsigned long pc, int trap,
1199 struct ucontext *uc)
1200 {
1201 TranslationBlock *tb;
1202
1203 if (cpu_single_env)
1204 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1205 /* now we have a real cpu fault */
1206 tb = tb_find_pc(pc);
1207 if (tb) {
1208 /* the PC is inside the translated code. It means that we have
1209 a virtual CPU fault */
1210 cpu_restore_state(tb, env, pc, uc);
1211 }
1212 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1213 raise_exception_err(trap, env->error_code);
1214 }
1215 #endif
1216
1217 int cpu_signal_handler(int host_signum, void *pinfo,
1218 void *puc)
1219 {
1220 siginfo_t *info = pinfo;
1221 struct ucontext *uc = puc;
1222 unsigned long pc;
1223 int trapno;
1224
1225 #ifndef REG_EIP
1226 /* for glibc 2.1 */
1227 #define REG_EIP EIP
1228 #define REG_ERR ERR
1229 #define REG_TRAPNO TRAPNO
1230 #endif
1231 pc = EIP_sig(uc);
1232 trapno = TRAP_sig(uc);
1233 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1234 if (trapno == 0x00 || trapno == 0x05) {
1235 /* send division by zero or bound exception */
1236 cpu_send_trap(pc, trapno, uc);
1237 return 1;
1238 } else
1239 #endif
1240 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1241 trapno == 0xe ?
1242 (ERROR_sig(uc) >> 1) & 1 : 0,
1243 &uc->uc_sigmask, puc);
1244 }
1245
1246 #elif defined(__x86_64__)
1247
1248 int cpu_signal_handler(int host_signum, void *pinfo,
1249 void *puc)
1250 {
1251 siginfo_t *info = pinfo;
1252 struct ucontext *uc = puc;
1253 unsigned long pc;
1254
1255 pc = uc->uc_mcontext.gregs[REG_RIP];
1256 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1257 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1258 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1259 &uc->uc_sigmask, puc);
1260 }
1261
1262 #elif defined(__powerpc__)
1263
1264 /***********************************************************************
1265 * signal context platform-specific definitions
1266 * From Wine
1267 */
1268 #ifdef linux
1269 /* All Registers access - only for local access */
1270 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1271 /* Gpr Registers access */
1272 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1273 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1274 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1275 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1276 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1277 # define LR_sig(context) REG_sig(link, context) /* Link register */
1278 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1279 /* Float Registers access */
1280 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1281 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1282 /* Exception Registers access */
1283 # define DAR_sig(context) REG_sig(dar, context)
1284 # define DSISR_sig(context) REG_sig(dsisr, context)
1285 # define TRAP_sig(context) REG_sig(trap, context)
1286 #endif /* linux */
1287
1288 #ifdef __APPLE__
1289 # include <sys/ucontext.h>
1290 typedef struct ucontext SIGCONTEXT;
1291 /* All Registers access - only for local access */
1292 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1293 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1294 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1295 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1296 /* Gpr Registers access */
1297 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1298 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1299 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1300 # define CTR_sig(context) REG_sig(ctr, context)
1301 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1302 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1303 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1304 /* Float Registers access */
1305 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1306 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1307 /* Exception Registers access */
1308 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1309 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1310 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1311 #endif /* __APPLE__ */
1312
1313 int cpu_signal_handler(int host_signum, void *pinfo,
1314 void *puc)
1315 {
1316 siginfo_t *info = pinfo;
1317 struct ucontext *uc = puc;
1318 unsigned long pc;
1319 int is_write;
1320
1321 pc = IAR_sig(uc);
1322 is_write = 0;
1323 #if 0
1324 /* ppc 4xx case */
1325 if (DSISR_sig(uc) & 0x00800000)
1326 is_write = 1;
1327 #else
1328 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1329 is_write = 1;
1330 #endif
1331 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1332 is_write, &uc->uc_sigmask, puc);
1333 }
1334
1335 #elif defined(__alpha__)
1336
1337 int cpu_signal_handler(int host_signum, void *pinfo,
1338 void *puc)
1339 {
1340 siginfo_t *info = pinfo;
1341 struct ucontext *uc = puc;
1342 uint32_t *pc = uc->uc_mcontext.sc_pc;
1343 uint32_t insn = *pc;
1344 int is_write = 0;
1345
1346 /* XXX: need kernel patch to get write flag faster */
1347 switch (insn >> 26) {
1348 case 0x0d: // stw
1349 case 0x0e: // stb
1350 case 0x0f: // stq_u
1351 case 0x24: // stf
1352 case 0x25: // stg
1353 case 0x26: // sts
1354 case 0x27: // stt
1355 case 0x2c: // stl
1356 case 0x2d: // stq
1357 case 0x2e: // stl_c
1358 case 0x2f: // stq_c
1359 is_write = 1;
1360 }
1361
1362 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1363 is_write, &uc->uc_sigmask, puc);
1364 }
1365 #elif defined(__sparc__)
1366
1367 int cpu_signal_handler(int host_signum, void *pinfo,
1368 void *puc)
1369 {
1370 siginfo_t *info = pinfo;
1371 uint32_t *regs = (uint32_t *)(info + 1);
1372 void *sigmask = (regs + 20);
1373 unsigned long pc;
1374 int is_write;
1375 uint32_t insn;
1376
1377 /* XXX: is there a standard glibc define ? */
1378 pc = regs[1];
1379 /* XXX: need kernel patch to get write flag faster */
1380 is_write = 0;
1381 insn = *(uint32_t *)pc;
1382 if ((insn >> 30) == 3) {
1383 switch((insn >> 19) & 0x3f) {
1384 case 0x05: // stb
1385 case 0x06: // sth
1386 case 0x04: // st
1387 case 0x07: // std
1388 case 0x24: // stf
1389 case 0x27: // stdf
1390 case 0x25: // stfsr
1391 is_write = 1;
1392 break;
1393 }
1394 }
1395 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1396 is_write, sigmask, NULL);
1397 }
1398
1399 #elif defined(__arm__)
1400
1401 int cpu_signal_handler(int host_signum, void *pinfo,
1402 void *puc)
1403 {
1404 siginfo_t *info = pinfo;
1405 struct ucontext *uc = puc;
1406 unsigned long pc;
1407 int is_write;
1408
1409 pc = uc->uc_mcontext.gregs[R15];
1410 /* XXX: compute is_write */
1411 is_write = 0;
1412 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1413 is_write,
1414 &uc->uc_sigmask, puc);
1415 }
1416
1417 #elif defined(__mc68000)
1418
1419 int cpu_signal_handler(int host_signum, void *pinfo,
1420 void *puc)
1421 {
1422 siginfo_t *info = pinfo;
1423 struct ucontext *uc = puc;
1424 unsigned long pc;
1425 int is_write;
1426
1427 pc = uc->uc_mcontext.gregs[16];
1428 /* XXX: compute is_write */
1429 is_write = 0;
1430 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1431 is_write,
1432 &uc->uc_sigmask, puc);
1433 }
1434
1435 #elif defined(__ia64)
1436
1437 #ifndef __ISR_VALID
1438 /* This ought to be in <bits/siginfo.h>... */
1439 # define __ISR_VALID 1
1440 #endif
1441
1442 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1443 {
1444 siginfo_t *info = pinfo;
1445 struct ucontext *uc = puc;
1446 unsigned long ip;
1447 int is_write = 0;
1448
1449 ip = uc->uc_mcontext.sc_ip;
1450 switch (host_signum) {
1451 case SIGILL:
1452 case SIGFPE:
1453 case SIGSEGV:
1454 case SIGBUS:
1455 case SIGTRAP:
1456 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1457 /* ISR.W (write-access) is bit 33: */
1458 is_write = (info->si_isr >> 33) & 1;
1459 break;
1460
1461 default:
1462 break;
1463 }
1464 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1465 is_write,
1466 &uc->uc_sigmask, puc);
1467 }
1468
1469 #elif defined(__s390__)
1470
1471 int cpu_signal_handler(int host_signum, void *pinfo,
1472 void *puc)
1473 {
1474 siginfo_t *info = pinfo;
1475 struct ucontext *uc = puc;
1476 unsigned long pc;
1477 int is_write;
1478
1479 pc = uc->uc_mcontext.psw.addr;
1480 /* XXX: compute is_write */
1481 is_write = 0;
1482 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1483 is_write,
1484 &uc->uc_sigmask, puc);
1485 }
1486
1487 #else
1488
1489 #error host CPU specific signal handler needed
1490
1491 #endif
1492
1493 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board