hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include "vl.h"
  14
  15 //#define DEBUG_LSI
  16 //#define DEBUG_LSI_REG
  17
  18 #ifdef DEBUG_LSI
  19 #define DPRINTF(fmt, args...) \
  20 do { printf("lsi_scsi: " fmt , ##args); } while (0)
  21 #define BADF(fmt, args...) \
  22 do { fprintf(stderr, "lsi_scsi: " fmt , ##args); exit(1);} while (0)
  23 #else
  24 #define DPRINTF(fmt, args...) do {} while(0)
  25 #define BADF(fmt, args...) \
  26 do { fprintf(stderr, "lsi_scsi: " fmt , ##args); } while (0)
  27 #endif
  28
  29 #define LSI_SCNTL0_TRG    0x01
  30 #define LSI_SCNTL0_AAP    0x02
  31 #define LSI_SCNTL0_EPC    0x08
  32 #define LSI_SCNTL0_WATN   0x10
  33 #define LSI_SCNTL0_START  0x20
  34
  35 #define LSI_SCNTL1_SST    0x01
  36 #define LSI_SCNTL1_IARB   0x02
  37 #define LSI_SCNTL1_AESP   0x04
  38 #define LSI_SCNTL1_RST    0x08
  39 #define LSI_SCNTL1_CON    0x10
  40 #define LSI_SCNTL1_DHP    0x20
  41 #define LSI_SCNTL1_ADB    0x40
  42 #define LSI_SCNTL1_EXC    0x80
  43
  44 #define LSI_SCNTL2_WSR    0x01
  45 #define LSI_SCNTL2_VUE0   0x02
  46 #define LSI_SCNTL2_VUE1   0x04
  47 #define LSI_SCNTL2_WSS    0x08
  48 #define LSI_SCNTL2_SLPHBEN 0x10
  49 #define LSI_SCNTL2_SLPMD  0x20
  50 #define LSI_SCNTL2_CHM    0x40
  51 #define LSI_SCNTL2_SDU    0x80
  52
  53 #define LSI_ISTAT0_DIP    0x01
  54 #define LSI_ISTAT0_SIP    0x02
  55 #define LSI_ISTAT0_INTF   0x04
  56 #define LSI_ISTAT0_CON    0x08
  57 #define LSI_ISTAT0_SEM    0x10
  58 #define LSI_ISTAT0_SIGP   0x20
  59 #define LSI_ISTAT0_SRST   0x40
  60 #define LSI_ISTAT0_ABRT   0x80
  61
  62 #define LSI_ISTAT1_SI     0x01
  63 #define LSI_ISTAT1_SRUN   0x02
  64 #define LSI_ISTAT1_FLSH   0x04
  65
  66 #define LSI_SSTAT0_SDP0   0x01
  67 #define LSI_SSTAT0_RST    0x02
  68 #define LSI_SSTAT0_WOA    0x04
  69 #define LSI_SSTAT0_LOA    0x08
  70 #define LSI_SSTAT0_AIP    0x10
  71 #define LSI_SSTAT0_OLF    0x20
  72 #define LSI_SSTAT0_ORF    0x40
  73 #define LSI_SSTAT0_ILF    0x80
  74
  75 #define LSI_SIST0_PAR     0x01
  76 #define LSI_SIST0_RST     0x02
  77 #define LSI_SIST0_UDC     0x04
  78 #define LSI_SIST0_SGE     0x08
  79 #define LSI_SIST0_RSL     0x10
  80 #define LSI_SIST0_SEL     0x20
  81 #define LSI_SIST0_CMP     0x40
  82 #define LSI_SIST0_MA      0x80
  83
  84 #define LSI_SIST1_HTH     0x01
  85 #define LSI_SIST1_GEN     0x02
  86 #define LSI_SIST1_STO     0x04
  87 #define LSI_SIST1_SBMC    0x10
  88
  89 #define LSI_SOCL_IO       0x01
  90 #define LSI_SOCL_CD       0x02
  91 #define LSI_SOCL_MSG      0x04
  92 #define LSI_SOCL_ATN      0x08
  93 #define LSI_SOCL_SEL      0x10
  94 #define LSI_SOCL_BSY      0x20
  95 #define LSI_SOCL_ACK      0x40
  96 #define LSI_SOCL_REQ      0x80
  97
  98 #define LSI_DSTAT_IID     0x01
  99 #define LSI_DSTAT_SIR     0x04
 100 #define LSI_DSTAT_SSI     0x08
 101 #define LSI_DSTAT_ABRT    0x10
 102 #define LSI_DSTAT_BF      0x20
 103 #define LSI_DSTAT_MDPE    0x40
 104 #define LSI_DSTAT_DFE     0x80
 105
 106 #define LSI_DCNTL_COM     0x01
 107 #define LSI_DCNTL_IRQD    0x02
 108 #define LSI_DCNTL_STD     0x04
 109 #define LSI_DCNTL_IRQM    0x08
 110 #define LSI_DCNTL_SSM     0x10
 111 #define LSI_DCNTL_PFEN    0x20
 112 #define LSI_DCNTL_PFF     0x40
 113 #define LSI_DCNTL_CLSE    0x80
 114
 115 #define LSI_DMODE_MAN     0x01
 116 #define LSI_DMODE_BOF     0x02
 117 #define LSI_DMODE_ERMP    0x04
 118 #define LSI_DMODE_ERL     0x08
 119 #define LSI_DMODE_DIOM    0x10
 120 #define LSI_DMODE_SIOM    0x20
 121
 122 #define LSI_CTEST2_DACK   0x01
 123 #define LSI_CTEST2_DREQ   0x02
 124 #define LSI_CTEST2_TEOP   0x04
 125 #define LSI_CTEST2_PCICIE 0x08
 126 #define LSI_CTEST2_CM     0x10
 127 #define LSI_CTEST2_CIO    0x20
 128 #define LSI_CTEST2_SIGP   0x40
 129 #define LSI_CTEST2_DDIR   0x80
 130
 131 #define LSI_CTEST5_BL2    0x04
 132 #define LSI_CTEST5_DDIR   0x08
 133 #define LSI_CTEST5_MASR   0x10
 134 #define LSI_CTEST5_DFSN   0x20
 135 #define LSI_CTEST5_BBCK   0x40
 136 #define LSI_CTEST5_ADCK   0x80
 137
 138 #define LSI_CCNTL0_DILS   0x01
 139 #define LSI_CCNTL0_DISFC  0x10
 140 #define LSI_CCNTL0_ENNDJ  0x20
 141 #define LSI_CCNTL0_PMJCTL 0x40
 142 #define LSI_CCNTL0_ENPMJ  0x80
 143
 144 #define PHASE_DO          0
 145 #define PHASE_DI          1
 146 #define PHASE_CMD         2
 147 #define PHASE_ST          3
 148 #define PHASE_MO          6
 149 #define PHASE_MI          7
 150 #define PHASE_MASK        7
 151
 152 /* The HBA is ID 7, so for simplicitly limit to 7 devices.  */
 153 #define LSI_MAX_DEVS      7
 154
 155 /* Size of internal DMA buffer for async IO requests.  */
 156 #define LSI_DMA_BLOCK_SIZE 0x10000
 157
 158 typedef struct {
 159     PCIDevice pci_dev;
 160     int mmio_io_addr;
 161     int ram_io_addr;
 162     uint32_t script_ram_base;
 163     uint32_t data_len;
 164
 165     int carry; /* ??? Should this be an a visible register somewhere?  */
 166     int sense;
 167     uint8_t msg;
 168     /* 0 if SCRIPTS are running or stopped.
 169      * 1 if a Wait Reselect instruction has been issued.
 170      * 2 if a DMA operation is in progress.  */
 171     int waiting;
 172     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 173     SCSIDevice *current_dev;
 174     int current_lun;
 175
 176     uint32_t dsa;
 177     uint32_t temp;
 178     uint32_t dnad;
 179     uint32_t dbc;
 180     uint8_t istat0;
 181     uint8_t istat1;
 182     uint8_t dcmd;
 183     uint8_t dstat;
 184     uint8_t dien;
 185     uint8_t sist0;
 186     uint8_t sist1;
 187     uint8_t sien0;
 188     uint8_t sien1;
 189     uint8_t mbox0;
 190     uint8_t mbox1;
 191     uint8_t dfifo;
 192     uint8_t ctest3;
 193     uint8_t ctest4;
 194     uint8_t ctest5;
 195     uint8_t ccntl0;
 196     uint8_t ccntl1;
 197     uint32_t dsp;
 198     uint32_t dsps;
 199     uint8_t dmode;
 200     uint8_t dcntl;
 201     uint8_t scntl0;
 202     uint8_t scntl1;
 203     uint8_t scntl2;
 204     uint8_t scntl3;
 205     uint8_t sstat0;
 206     uint8_t sstat1;
 207     uint8_t scid;
 208     uint8_t sxfer;
 209     uint8_t socl;
 210     uint8_t sdid;
 211     uint8_t sfbr;
 212     uint8_t stest1;
 213     uint8_t stest2;
 214     uint8_t stest3;
 215     uint8_t stime0;
 216     uint8_t respid0;
 217     uint8_t respid1;
 218     uint32_t mmrs;
 219     uint32_t mmws;
 220     uint32_t sfs;
 221     uint32_t drs;
 222     uint32_t sbms;
 223     uint32_t dmbs;
 224     uint32_t dnad64;
 225     uint32_t pmjad1;
 226     uint32_t pmjad2;
 227     uint32_t rbc;
 228     uint32_t ua;
 229     uint32_t ia;
 230     uint32_t sbc;
 231     uint32_t csbc;
 232     uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
 233
 234     uint8_t dma_buf[LSI_DMA_BLOCK_SIZE];
 235     /* Script ram is stored as 32-bit words in host byteorder.  */
 236     uint32_t script_ram[2048];
 237 } LSIState;
 238
 239 static void lsi_soft_reset(LSIState *s)
 240 {
 241     DPRINTF("Reset\n");
 242     s->carry = 0;
 243
 244     s->waiting = 0;
 245     s->dsa = 0;
 246     s->dnad = 0;
 247     s->dbc = 0;
 248     s->temp = 0;
 249     memset(s->scratch, 0, sizeof(s->scratch));
 250     s->istat0 = 0;
 251     s->istat1 = 0;
 252     s->dcmd = 0;
 253     s->dstat = 0;
 254     s->dien = 0;
 255     s->sist0 = 0;
 256     s->sist1 = 0;
 257     s->sien0 = 0;
 258     s->sien1 = 0;
 259     s->mbox0 = 0;
 260     s->mbox1 = 0;
 261     s->dfifo = 0;
 262     s->ctest3 = 0;
 263     s->ctest4 = 0;
 264     s->ctest5 = 0;
 265     s->ccntl0 = 0;
 266     s->ccntl1 = 0;
 267     s->dsp = 0;
 268     s->dsps = 0;
 269     s->dmode = 0;
 270     s->dcntl = 0;
 271     s->scntl0 = 0xc0;
 272     s->scntl1 = 0;
 273     s->scntl2 = 0;
 274     s->scntl3 = 0;
 275     s->sstat0 = 0;
 276     s->sstat1 = 0;
 277     s->scid = 7;
 278     s->sxfer = 0;
 279     s->socl = 0;
 280     s->stest1 = 0;
 281     s->stest2 = 0;
 282     s->stest3 = 0;
 283     s->stime0 = 0;
 284     s->respid0 = 0x80;
 285     s->respid1 = 0;
 286     s->mmrs = 0;
 287     s->mmws = 0;
 288     s->sfs = 0;
 289     s->drs = 0;
 290     s->sbms = 0;
 291     s->dmbs = 0;
 292     s->dnad64 = 0;
 293     s->pmjad1 = 0;
 294     s->pmjad2 = 0;
 295     s->rbc = 0;
 296     s->ua = 0;
 297     s->ia = 0;
 298     s->sbc = 0;
 299     s->csbc = 0;
 300 }
 301
 302 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 303 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 304 static void lsi_execute_script(LSIState *s);
 305
 306 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 307 {
 308     uint32_t buf;
 309
 310     /* Optimize reading from SCRIPTS RAM.  */
 311     if ((addr & 0xffffe000) == s->script_ram_base) {
 312         return s->script_ram[(addr & 0x1fff) >> 2];
 313     }
 314     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 315     return cpu_to_le32(buf);
 316 }
 317
 318 static void lsi_stop_script(LSIState *s)
 319 {
 320     s->istat1 &= ~LSI_ISTAT1_SRUN;
 321 }
 322
 323 static void lsi_update_irq(LSIState *s)
 324 {
 325     int level;
 326     static int last_level;
 327
 328     /* It's unclear whether the DIP/SIP bits should be cleared when the
 329        Interrupt Status Registers are cleared or when istat0 is read.
 330        We currently do the formwer, which seems to work.  */
 331     level = 0;
 332     if (s->dstat) {
 333         if (s->dstat & s->dien)
 334             level = 1;
 335         s->istat0 |= LSI_ISTAT0_DIP;
 336     } else {
 337         s->istat0 &= ~LSI_ISTAT0_DIP;
 338     }
 339
 340     if (s->sist0 || s->sist1) {
 341         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 342             level = 1;
 343         s->istat0 |= LSI_ISTAT0_SIP;
 344     } else {
 345         s->istat0 &= ~LSI_ISTAT0_SIP;
 346     }
 347     if (s->istat0 & LSI_ISTAT0_INTF)
 348         level = 1;
 349
 350     if (level != last_level) {
 351         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 352                 level, s->dstat, s->sist1, s->sist0);
 353         last_level = level;
 354     }
 355     pci_set_irq(&s->pci_dev, 0, level);
 356 }
 357
 358 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 359 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 360 {
 361     uint32_t mask0;
 362     uint32_t mask1;
 363
 364     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 365             stat1, stat0, s->sist1, s->sist0);
 366     s->sist0 |= stat0;
 367     s->sist1 |= stat1;
 368     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 369        we don't stop processing when raising STO.  Instead continue
 370        execution and stop at the next insn that accesses the SCSI bus.  */
 371     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 372     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 373     mask1 &= ~LSI_SIST1_STO;
 374     if (s->sist0 & mask0 || s->sist1 & mask1) {
 375         lsi_stop_script(s);
 376     }
 377     lsi_update_irq(s);
 378 }
 379
 380 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 381 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 382 {
 383     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 384     s->dstat |= stat;
 385     lsi_update_irq(s);
 386     lsi_stop_script(s);
 387 }
 388
 389 static inline void lsi_set_phase(LSIState *s, int phase)
 390 {
 391     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 392 }
 393
 394 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 395 {
 396     /* Trigger a phase mismatch.  */
 397     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 398         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 399             s->dsp = s->pmjad1;
 400         } else {
 401             s->dsp = s->pmjad2;
 402         }
 403         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 404     } else {
 405         DPRINTF("Phase mismatch interrupt\n");
 406         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 407         lsi_stop_script(s);
 408     }
 409     lsi_set_phase(s, new_phase);
 410 }
 411
 412 /* Initiate a SCSI layer data transfer.  */
 413 static void lsi_do_dma(LSIState *s, int out)
 414 {
 415     uint32_t count;
 416
 417     count = s->dbc;
 418     if (count > LSI_DMA_BLOCK_SIZE)
 419         count = LSI_DMA_BLOCK_SIZE;
 420     DPRINTF("DMA addr=0x%08x len=%d avail=%d\n",
 421             addr, count, s->data_len);
 422     /* ??? Too long transfers are truncated. Don't know if this is the
 423        correct behavior.  */
 424     if (count > s->data_len) {
 425         /* If the DMA length is greater than the device data length then
 426            a phase mismatch will occur.  */
 427         count = s->data_len;
 428         s->dbc = count;
 429         lsi_bad_phase(s, out, PHASE_ST);
 430     }
 431
 432     s->csbc += count;
 433
 434     /* ??? Set SFBR to first data byte.  */
 435     if ((s->sstat1 & PHASE_MASK) == PHASE_DO) {
 436         cpu_physical_memory_read(s->dnad, s->dma_buf, count);
 437         scsi_write_data(s->current_dev, s->dma_buf, count);
 438     } else {
 439         scsi_read_data(s->current_dev, s->dma_buf, count);
 440     }
 441     /* If the DMA did not complete then suspend execution.  */
 442     if (s->dbc)
 443         s->waiting = 2;
 444 }
 445
 446 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 447 static void lsi_command_complete(void *opaque, uint32_t reason, int sense)
 448 {
 449     LSIState *s = (LSIState *)opaque;
 450     uint32_t count;
 451     int out;
 452
 453     out = ((s->sstat1 & PHASE_MASK) == PHASE_DO);
 454     count = s->dbc;
 455     if (count > LSI_DMA_BLOCK_SIZE)
 456         count = LSI_DMA_BLOCK_SIZE;
 457     if (!out)
 458         cpu_physical_memory_write(s->dnad, s->dma_buf, count);
 459     s->dnad += count;
 460     s->dbc -= count;
 461
 462     if (reason == SCSI_REASON_DONE) {
 463         DPRINTF("Command complete sense=%d\n", sense);
 464         s->sense = sense;
 465         lsi_set_phase(s, PHASE_ST);
 466     }
 467
 468     if (s->dbc) {
 469         lsi_do_dma(s, out);
 470     } else if (s->waiting == 2) {
 471         /* Restart SCRIPTS execution.  */
 472         s->waiting = 0;
 473         lsi_execute_script(s);
 474     }
 475 }
 476
 477 static void lsi_do_command(LSIState *s)
 478 {
 479     uint8_t buf[16];
 480     int n;
 481
 482     DPRINTF("Send command len=%d\n", s->dbc);
 483     if (s->dbc > 16)
 484         s->dbc = 16;
 485     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 486     s->sfbr = buf[0];
 487     n = scsi_send_command(s->current_dev, 0, buf, s->current_lun);
 488     if (n > 0) {
 489         s->data_len = n;
 490         lsi_set_phase(s, PHASE_DI);
 491     } else if (n < 0) {
 492         s->data_len = -n;
 493         lsi_set_phase(s, PHASE_DO);
 494     }
 495 }
 496
 497 static void lsi_do_status(LSIState *s)
 498 {
 499     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 500     if (s->dbc != 1)
 501         BADF("Bad Status move\n");
 502     s->dbc = 1;
 503     s->msg = s->sense;
 504     cpu_physical_memory_write(s->dnad, &s->msg, 1);
 505     s->sfbr = s->msg;
 506     lsi_set_phase(s, PHASE_MI);
 507     s->msg = 0; /* COMMAND COMPLETE */
 508 }
 509
 510 static void lsi_disconnect(LSIState *s)
 511 {
 512     s->scntl1 &= ~LSI_SCNTL1_CON;
 513     s->sstat1 &= ~PHASE_MASK;
 514 }
 515
 516 static void lsi_do_msgin(LSIState *s)
 517 {
 518     DPRINTF("Message in len=%d\n", s->dbc);
 519     s->dbc = 1;
 520     s->sfbr = s->msg;
 521     cpu_physical_memory_write(s->dnad, &s->msg, 1);
 522     if (s->msg == 0) {
 523         lsi_disconnect(s);
 524     } else {
 525         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 526            switch to PHASE_MO.  */
 527         lsi_set_phase(s, PHASE_CMD);
 528     }
 529 }
 530
 531 static void lsi_do_msgout(LSIState *s)
 532 {
 533     uint8_t msg;
 534
 535     DPRINTF("MSG out len=%d\n", s->dbc);
 536     if (s->dbc != 1) {
 537         /* Multibyte messages not implemented.  */
 538         s->msg = 7; /* MESSAGE REJECT */
 539         //s->dbc = 1;
 540         //lsi_bad_phase(s, 1, PHASE_MI);
 541         lsi_set_phase(s, PHASE_MI);
 542         return;
 543     }
 544     cpu_physical_memory_read(s->dnad, &msg, 1);
 545     s->sfbr = msg;
 546     s->dnad++;
 547
 548     switch (msg) {
 549     case 0x00:
 550         DPRINTF("Got Disconnect\n");
 551         lsi_disconnect(s);
 552         return;
 553     case 0x08:
 554         DPRINTF("Got No Operation\n");
 555         lsi_set_phase(s, PHASE_CMD);
 556         return;
 557     }
 558     if ((msg & 0x80) == 0) {
 559         DPRINTF("Unimplemented message 0x%d\n", msg);
 560         s->msg = 7; /* MESSAGE REJECT */
 561         lsi_bad_phase(s, 1, PHASE_MI);
 562         return;
 563     }
 564     s->current_lun = msg & 7;
 565     DPRINTF("Select LUN %d\n", s->current_lun);
 566     lsi_set_phase(s, PHASE_CMD);
 567 }
 568
 569 /* Sign extend a 24-bit value.  */
 570 static inline int32_t sxt24(int32_t n)
 571 {
 572     return (n << 8) >> 8;
 573 }
 574
 575 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 576 {
 577     int n;
 578     uint8_t buf[TARGET_PAGE_SIZE];
 579
 580     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 581     while (count) {
 582         n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
 583         cpu_physical_memory_read(src, buf, n);
 584         cpu_physical_memory_write(dest, buf, n);
 585         src += n;
 586         dest += n;
 587         count -= n;
 588     }
 589 }
 590
 591 static void lsi_execute_script(LSIState *s)
 592 {
 593     uint32_t insn;
 594     uint32_t addr;
 595     int opcode;
 596
 597     s->istat1 |= LSI_ISTAT1_SRUN;
 598 again:
 599     insn = read_dword(s, s->dsp);
 600     addr = read_dword(s, s->dsp + 4);
 601     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 602     s->dsps = addr;
 603     s->dcmd = insn >> 24;
 604     s->dsp += 8;
 605     switch (insn >> 30) {
 606     case 0: /* Block move.  */
 607         if (s->sist1 & LSI_SIST1_STO) {
 608             DPRINTF("Delayed select timeout\n");
 609             lsi_stop_script(s);
 610             break;
 611         }
 612         s->dbc = insn & 0xffffff;
 613         s->rbc = s->dbc;
 614         if (insn & (1 << 29)) {
 615             /* Indirect addressing.  */
 616             addr = read_dword(s, addr);
 617         } else if (insn & (1 << 28)) {
 618             uint32_t buf[2];
 619             int32_t offset;
 620             /* Table indirect addressing.  */
 621             offset = sxt24(addr);
 622             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 623             s->dbc = cpu_to_le32(buf[0]);
 624             addr = cpu_to_le32(buf[1]);
 625         }
 626         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 627             DPRINTF("Wrong phase got %d expected %d\n",
 628                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 629             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 630             break;
 631         }
 632         s->dnad = addr;
 633         switch (s->sstat1 & 0x7) {
 634         case PHASE_DO:
 635             lsi_do_dma(s, 1);
 636             break;
 637         case PHASE_DI:
 638             lsi_do_dma(s, 0);
 639             break;
 640         case PHASE_CMD:
 641             lsi_do_command(s);
 642             break;
 643         case PHASE_ST:
 644             lsi_do_status(s);
 645             break;
 646         case PHASE_MO:
 647             lsi_do_msgout(s);
 648             break;
 649         case PHASE_MI:
 650             lsi_do_msgin(s);
 651             break;
 652         default:
 653             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
 654             exit(1);
 655         }
 656         s->dfifo = s->dbc & 0xff;
 657         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
 658         s->sbc = s->dbc;
 659         s->rbc -= s->dbc;
 660         s->ua = addr + s->dbc;
 661         /* ??? Set ESA.  */
 662         s->ia = s->dsp - 8;
 663         break;
 664
 665     case 1: /* IO or Read/Write instruction.  */
 666         opcode = (insn >> 27) & 7;
 667         if (opcode < 5) {
 668             uint32_t id;
 669
 670             if (insn & (1 << 25)) {
 671                 id = read_dword(s, s->dsa + sxt24(insn));
 672             } else {
 673                 id = addr;
 674             }
 675             id = (id >> 16) & 0xf;
 676             if (insn & (1 << 26)) {
 677                 addr = s->dsp + sxt24(addr);
 678             }
 679             s->dnad = addr;
 680             switch (opcode) {
 681             case 0: /* Select */
 682                 s->sstat0 |= LSI_SSTAT0_WOA;
 683                 s->scntl1 &= ~LSI_SCNTL1_IARB;
 684                 s->sdid = id;
 685                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
 686                     DPRINTF("Selected absent target %d\n", id);
 687                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
 688                     lsi_disconnect(s);
 689                     break;
 690                 }
 691                 DPRINTF("Selected target %d%s\n",
 692                         id, insn & (1 << 3) ? " ATN" : "");
 693                 /* ??? Linux drivers compain when this is set.  Maybe
 694                    it only applies in low-level mode (unimplemented).
 695                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
 696                 s->current_dev = s->scsi_dev[id];
 697                 s->scntl1 |= LSI_SCNTL1_CON;
 698                 if (insn & (1 << 3)) {
 699                     s->socl |= LSI_SOCL_ATN;
 700                 }
 701                 lsi_set_phase(s, PHASE_MO);
 702                 break;
 703             case 1: /* Disconnect */
 704                 DPRINTF("Wait Disconect\n");
 705                 s->scntl1 &= ~LSI_SCNTL1_CON;
 706                 break;
 707             case 2: /* Wait Reselect */
 708                 DPRINTF("Wait Reselect\n");
 709                 s->waiting = 1;
 710                 break;
 711             case 3: /* Set */
 712                 DPRINTF("Set%s%s%s%s\n",
 713                         insn & (1 << 3) ? " ATN" : "",
 714                         insn & (1 << 6) ? " ACK" : "",
 715                         insn & (1 << 9) ? " TM" : "",
 716                         insn & (1 << 10) ? " CC" : "");
 717                 if (insn & (1 << 3)) {
 718                     s->socl |= LSI_SOCL_ATN;
 719                     lsi_set_phase(s, PHASE_MO);
 720                 }
 721                 if (insn & (1 << 9)) {
 722                     BADF("Target mode not implemented\n");
 723                     exit(1);
 724                 }
 725                 if (insn & (1 << 10))
 726                     s->carry = 1;
 727                 break;
 728             case 4: /* Clear */
 729                 DPRINTF("Clear%s%s%s%s\n",
 730                         insn & (1 << 3) ? " ATN" : "",
 731                         insn & (1 << 6) ? " ACK" : "",
 732                         insn & (1 << 9) ? " TM" : "",
 733                         insn & (1 << 10) ? " CC" : "");
 734                 if (insn & (1 << 3)) {
 735                     s->socl &= ~LSI_SOCL_ATN;
 736                 }
 737                 if (insn & (1 << 10))
 738                     s->carry = 0;
 739                 break;
 740             }
 741         } else {
 742             uint8_t op0;
 743             uint8_t op1;
 744             uint8_t data8;
 745             int reg;
 746             int operator;
 747 #ifdef DEBUG_LSI
 748             static const char *opcode_names[3] =
 749                 {"Write", "Read", "Read-Modify-Write"};
 750             static const char *operator_names[8] =
 751                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
 752 #endif
 753
 754             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
 755             data8 = (insn >> 8) & 0xff;
 756             opcode = (insn >> 27) & 7;
 757             operator = (insn >> 24) & 7;
 758             DPRINTF("%s reg 0x%x %s data8 %d%s\n",
 759                     opcode_names[opcode - 5], reg,
 760                     operator_names[operator], data8,
 761                     (insn & (1 << 23)) ? " SFBR" : "");
 762             op0 = op1 = 0;
 763             switch (opcode) {
 764             case 5: /* From SFBR */
 765                 op0 = s->sfbr;
 766                 op1 = data8;
 767                 break;
 768             case 6: /* To SFBR */
 769                 if (operator)
 770                     op0 = lsi_reg_readb(s, reg);
 771                 op1 = data8;
 772                 break;
 773             case 7: /* Read-modify-write */
 774                 if (operator)
 775                     op0 = lsi_reg_readb(s, reg);
 776                 if (insn & (1 << 23)) {
 777                     op1 = s->sfbr;
 778                 } else {
 779                     op1 = data8;
 780                 }
 781                 break;
 782             }
 783
 784             switch (operator) {
 785             case 0: /* move */
 786                 op0 = op1;
 787                 break;
 788             case 1: /* Shift left */
 789                 op1 = op0 >> 7;
 790                 op0 = (op0 << 1) | s->carry;
 791                 s->carry = op1;
 792                 break;
 793             case 2: /* OR */
 794                 op0 |= op1;
 795                 break;
 796             case 3: /* XOR */
 797                 op0 |= op1;
 798                 break;
 799             case 4: /* AND */
 800                 op0 &= op1;
 801                 break;
 802             case 5: /* SHR */
 803                 op1 = op0 & 1;
 804                 op0 = (op0 >> 1) | (s->carry << 7);
 805                 break;
 806             case 6: /* ADD */
 807                 op0 += op1;
 808                 s->carry = op0 < op1;
 809                 break;
 810             case 7: /* ADC */
 811                 op0 += op1 + s->carry;
 812                 if (s->carry)
 813                     s->carry = op0 <= op1;
 814                 else
 815                     s->carry = op0 < op1;
 816                 break;
 817             }
 818
 819             switch (opcode) {
 820             case 5: /* From SFBR */
 821             case 7: /* Read-modify-write */
 822                 lsi_reg_writeb(s, reg, op0);
 823                 break;
 824             case 6: /* To SFBR */
 825                 s->sfbr = op0;
 826                 break;
 827             }
 828         }
 829         break;
 830
 831     case 2: /* Transfer Control.  */
 832         {
 833             int cond;
 834             int jmp;
 835
 836             if ((insn & 0x002e0000) == 0) {
 837                 DPRINTF("NOP\n");
 838                 break;
 839             }
 840             if (s->sist1 & LSI_SIST1_STO) {
 841                 DPRINTF("Delayed select timeout\n");
 842                 lsi_stop_script(s);
 843                 break;
 844             }
 845             cond = jmp = (insn & (1 << 19)) != 0;
 846             if (cond == jmp && (insn & (1 << 21))) {
 847                 DPRINTF("Compare carry %d\n", s->carry == jmp);
 848                 cond = s->carry != 0;
 849             }
 850             if (cond == jmp && (insn & (1 << 17))) {
 851                 DPRINTF("Compare phase %d %c= %d\n",
 852                         (s->sstat1 & PHASE_MASK),
 853                         jmp ? '=' : '!',
 854                         ((insn >> 24) & 7));
 855                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
 856             }
 857             if (cond == jmp && (insn & (1 << 18))) {
 858                 uint8_t mask;
 859
 860                 mask = (~insn >> 8) & 0xff;
 861                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
 862                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
 863                 cond = (s->sfbr & mask) == (insn & mask);
 864             }
 865             if (cond == jmp) {
 866                 if (insn & (1 << 23)) {
 867                     /* Relative address.  */
 868                     addr = s->dsp + sxt24(addr);
 869                 }
 870                 switch ((insn >> 27) & 7) {
 871                 case 0: /* Jump */
 872                     DPRINTF("Jump to 0x%08x\n", addr);
 873                     s->dsp = addr;
 874                     break;
 875                 case 1: /* Call */
 876                     DPRINTF("Call 0x%08x\n", addr);
 877                     s->temp = s->dsp;
 878                     s->dsp = addr;
 879                     break;
 880                 case 2: /* Return */
 881                     DPRINTF("Return to 0x%08x\n", s->temp);
 882                     s->dsp = s->temp;
 883                     break;
 884                 case 3: /* Interrupt */
 885                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
 886                     if ((insn & (1 << 20)) != 0) {
 887                         s->istat0 |= LSI_ISTAT0_INTF;
 888                         lsi_update_irq(s);
 889                     } else {
 890                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
 891                     }
 892                     break;
 893                 default:
 894                     DPRINTF("Illegal transfer control\n");
 895                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
 896                     break;
 897                 }
 898             } else {
 899                 DPRINTF("Control condition failed\n");
 900             }
 901         }
 902         break;
 903
 904     case 3:
 905         if ((insn & (1 << 29)) == 0) {
 906             /* Memory move.  */
 907             uint32_t dest;
 908             /* ??? The docs imply the destination address is loaded into
 909                the TEMP register.  However the Linux drivers rely on
 910                the value being presrved.  */
 911             dest = read_dword(s, s->dsp);
 912             s->dsp += 4;
 913             lsi_memcpy(s, dest, addr, insn & 0xffffff);
 914         } else {
 915             uint8_t data[7];
 916             int reg;
 917             int n;
 918             int i;
 919
 920             if (insn & (1 << 28)) {
 921                 addr = s->dsa + sxt24(addr);
 922             }
 923             n = (insn & 7);
 924             reg = (insn >> 16) & 0xff;
 925             if (insn & (1 << 24)) {
 926                 DPRINTF("Load reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
 927                 cpu_physical_memory_read(addr, data, n);
 928                 for (i = 0; i < n; i++) {
 929                     lsi_reg_writeb(s, reg + i, data[i]);
 930                 }
 931             } else {
 932                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
 933                 for (i = 0; i < n; i++) {
 934                     data[i] = lsi_reg_readb(s, reg + i);
 935                 }
 936                 cpu_physical_memory_write(addr, data, n);
 937             }
 938         }
 939     }
 940     /* ??? Need to avoid infinite loops.  */
 941     if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
 942         if (s->dcntl & LSI_DCNTL_SSM) {
 943             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
 944         } else {
 945             goto again;
 946         }
 947     }
 948     DPRINTF("SCRIPTS execution stopped\n");
 949 }
 950
 951 static uint8_t lsi_reg_readb(LSIState *s, int offset)
 952 {
 953     uint8_t tmp;
 954 #define CASE_GET_REG32(name, addr) \
 955     case addr: return s->name & 0xff; \
 956     case addr + 1: return (s->name >> 8) & 0xff; \
 957     case addr + 2: return (s->name >> 16) & 0xff; \
 958     case addr + 3: return (s->name >> 24) & 0xff;
 959
 960 #ifdef DEBUG_LSI_REG
 961     DPRINTF("Read reg %x\n", offset);
 962 #endif
 963     switch (offset) {
 964     case 0x00: /* SCNTL0 */
 965         return s->scntl0;
 966     case 0x01: /* SCNTL1 */
 967         return s->scntl1;
 968     case 0x02: /* SCNTL2 */
 969         return s->scntl2;
 970     case 0x03: /* SCNTL3 */
 971         return s->scntl3;
 972     case 0x04: /* SCID */
 973         return s->scid;
 974     case 0x05: /* SXFER */
 975         return s->sxfer;
 976     case 0x06: /* SDID */
 977         return s->sdid;
 978     case 0x07: /* GPREG0 */
 979         return 0x7f;
 980     case 0xb: /* SBCL */
 981         /* ??? This is not correct. However it's (hopefully) only
 982            used for diagnostics, so should be ok.  */
 983         return 0;
 984     case 0xc: /* DSTAT */
 985         tmp = s->dstat | 0x80;
 986         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
 987             s->dstat = 0;
 988         lsi_update_irq(s);
 989         return tmp;
 990     case 0x0d: /* SSTAT0 */
 991         return s->sstat0;
 992     case 0x0e: /* SSTAT1 */
 993         return s->sstat1;
 994     case 0x0f: /* SSTAT2 */
 995         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
 996     CASE_GET_REG32(dsa, 0x10)
 997     case 0x14: /* ISTAT0 */
 998         return s->istat0;
 999     case 0x16: /* MBOX0 */
1000         return s->mbox0;
1001     case 0x17: /* MBOX1 */
1002         return s->mbox1;
1003     case 0x18: /* CTEST0 */
1004         return 0xff;
1005     case 0x19: /* CTEST1 */
1006         return 0;
1007     case 0x1a: /* CTEST2 */
1008         tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1009         if (s->istat0 & LSI_ISTAT0_SIGP) {
1010             s->istat0 &= ~LSI_ISTAT0_SIGP;
1011             tmp |= LSI_CTEST2_SIGP;
1012         }
1013         return tmp;
1014     case 0x1b: /* CTEST3 */
1015         return s->ctest3;
1016     CASE_GET_REG32(temp, 0x1c)
1017     case 0x20: /* DFIFO */
1018         return 0;
1019     case 0x21: /* CTEST4 */
1020         return s->ctest4;
1021     case 0x22: /* CTEST5 */
1022         return s->ctest5;
1023     case 0x24: /* DBC[0:7] */
1024         return s->dbc & 0xff;
1025     case 0x25: /* DBC[8:15] */
1026         return (s->dbc >> 8) & 0xff;
1027     case 0x26: /* DBC[16->23] */
1028         return (s->dbc >> 16) & 0xff;
1029     case 0x27: /* DCMD */
1030         return s->dcmd;
1031     CASE_GET_REG32(dsp, 0x2c)
1032     CASE_GET_REG32(dsps, 0x30)
1033     CASE_GET_REG32(scratch[0], 0x34)
1034     case 0x38: /* DMODE */
1035         return s->dmode;
1036     case 0x39: /* DIEN */
1037         return s->dien;
1038     case 0x3b: /* DCNTL */
1039         return s->dcntl;
1040     case 0x40: /* SIEN0 */
1041         return s->sien0;
1042     case 0x41: /* SIEN1 */
1043         return s->sien1;
1044     case 0x42: /* SIST0 */
1045         tmp = s->sist0;
1046         s->sist0 = 0;
1047         lsi_update_irq(s);
1048         return tmp;
1049     case 0x43: /* SIST1 */
1050         tmp = s->sist1;
1051         s->sist1 = 0;
1052         lsi_update_irq(s);
1053         return tmp;
1054     case 0x47: /* GPCNTL0 */
1055         return 0x0f;
1056     case 0x48: /* STIME0 */
1057         return s->stime0;
1058     case 0x4a: /* RESPID0 */
1059         return s->respid0;
1060     case 0x4b: /* RESPID1 */
1061         return s->respid1;
1062     case 0x4d: /* STEST1 */
1063         return s->stest1;
1064     case 0x4e: /* STEST2 */
1065         return s->stest2;
1066     case 0x4f: /* STEST3 */
1067         return s->stest3;
1068     case 0x52: /* STEST4 */
1069         return 0xe0;
1070     case 0x56: /* CCNTL0 */
1071         return s->ccntl0;
1072     case 0x57: /* CCNTL1 */
1073         return s->ccntl1;
1074     case 0x58: case 0x59: /* SBDL */
1075         return 0;
1076     CASE_GET_REG32(mmrs, 0xa0)
1077     CASE_GET_REG32(mmws, 0xa4)
1078     CASE_GET_REG32(sfs, 0xa8)
1079     CASE_GET_REG32(drs, 0xac)
1080     CASE_GET_REG32(sbms, 0xb0)
1081     CASE_GET_REG32(dmbs, 0xb4)
1082     CASE_GET_REG32(dnad64, 0xb8)
1083     CASE_GET_REG32(pmjad1, 0xc0)
1084     CASE_GET_REG32(pmjad2, 0xc4)
1085     CASE_GET_REG32(rbc, 0xc8)
1086     CASE_GET_REG32(ua, 0xcc)
1087     CASE_GET_REG32(ia, 0xd4)
1088     CASE_GET_REG32(sbc, 0xd8)
1089     CASE_GET_REG32(csbc, 0xdc)
1090     }
1091     if (offset >= 0x5c && offset < 0xa0) {
1092         int n;
1093         int shift;
1094         n = (offset - 0x58) >> 2;
1095         shift = (offset & 3) * 8;
1096         return (s->scratch[n] >> shift) & 0xff;
1097     }
1098     BADF("readb 0x%x\n", offset);
1099     exit(1);
1100 #undef CASE_GET_REG32
1101 }
1102
1103 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1104 {
1105 #define CASE_SET_REG32(name, addr) \
1106     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1107     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1108     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1109     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1110
1111 #ifdef DEBUG_LSI_REG
1112     DPRINTF("Write reg %x = %02x\n", offset, val);
1113 #endif
1114     switch (offset) {
1115     case 0x00: /* SCNTL0 */
1116         s->scntl0 = val;
1117         if (val & LSI_SCNTL0_START) {
1118             BADF("Start sequence not implemented\n");
1119         }
1120         break;
1121     case 0x01: /* SCNTL1 */
1122         s->scntl1 = val & ~LSI_SCNTL1_SST;
1123         if (val & LSI_SCNTL1_IARB) {
1124             BADF("Immediate Arbritration not implemented\n");
1125         }
1126         if (val & LSI_SCNTL1_RST) {
1127             s->sstat0 |= LSI_SSTAT0_RST;
1128             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1129         } else {
1130             s->sstat0 &= ~LSI_SSTAT0_RST;
1131         }
1132         break;
1133     case 0x02: /* SCNTL2 */
1134         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1135         s->scntl3 = val;
1136         break;
1137     case 0x03: /* SCNTL3 */
1138         s->scntl3 = val;
1139         break;
1140     case 0x04: /* SCID */
1141         s->scid = val;
1142         break;
1143     case 0x05: /* SXFER */
1144         s->sxfer = val;
1145         break;
1146     case 0x07: /* GPREG0 */
1147         break;
1148     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1149         /* Linux writes to these readonly registers on startup.  */
1150         return;
1151     CASE_SET_REG32(dsa, 0x10)
1152     case 0x14: /* ISTAT0 */
1153         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1154         if (val & LSI_ISTAT0_ABRT) {
1155             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1156         }
1157         if (val & LSI_ISTAT0_INTF) {
1158             s->istat0 &= ~LSI_ISTAT0_INTF;
1159             lsi_update_irq(s);
1160         }
1161         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1162             DPRINTF("Woken by SIGP\n");
1163             s->waiting = 0;
1164             s->dsp = s->dnad;
1165             lsi_execute_script(s);
1166         }
1167         if (val & LSI_ISTAT0_SRST) {
1168             lsi_soft_reset(s);
1169         }
1170     case 0x16: /* MBOX0 */
1171         s->mbox0 = val;
1172     case 0x17: /* MBOX1 */
1173         s->mbox1 = val;
1174     case 0x1b: /* CTEST3 */
1175         s->ctest3 = val & 0x0f;
1176         break;
1177     CASE_SET_REG32(temp, 0x1c)
1178     case 0x21: /* CTEST4 */
1179         if (val & 7) {
1180            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1181         }
1182         s->ctest4 = val;
1183         break;
1184     case 0x22: /* CTEST5 */
1185         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1186             BADF("CTEST5 DMA increment not implemented\n");
1187         }
1188         s->ctest5 = val;
1189         break;
1190     case 0x2c: /* DSPS[0:7] */
1191         s->dsp &= 0xffffff00;
1192         s->dsp |= val;
1193         break;
1194     case 0x2d: /* DSPS[8:15] */
1195         s->dsp &= 0xffff00ff;
1196         s->dsp |= val << 8;
1197         break;
1198     case 0x2e: /* DSPS[16:23] */
1199         s->dsp &= 0xff00ffff;
1200         s->dsp |= val << 16;
1201         break;
1202     case 0x2f: /* DSPS[14:31] */
1203         s->dsp &= 0x00ffffff;
1204         s->dsp |= val << 24;
1205         if ((s->dmode & LSI_DMODE_MAN) == 0
1206             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1207             lsi_execute_script(s);
1208         break;
1209     CASE_SET_REG32(dsps, 0x30)
1210     CASE_SET_REG32(scratch[0], 0x34)
1211     case 0x38: /* DMODE */
1212         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1213             BADF("IO mappings not implemented\n");
1214         }
1215         s->dmode = val;
1216         break;
1217     case 0x39: /* DIEN */
1218         s->dien = val;
1219         lsi_update_irq(s);
1220         break;
1221     case 0x3b: /* DCNTL */
1222         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1223         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1224             lsi_execute_script(s);
1225         break;
1226     case 0x40: /* SIEN0 */
1227         s->sien0 = val;
1228         lsi_update_irq(s);
1229         break;
1230     case 0x41: /* SIEN1 */
1231         s->sien1 = val;
1232         lsi_update_irq(s);
1233         break;
1234     case 0x47: /* GPCNTL0 */
1235         break;
1236     case 0x48: /* STIME0 */
1237         s->stime0 = val;
1238         break;
1239     case 0x49: /* STIME1 */
1240         if (val & 0xf) {
1241             DPRINTF("General purpose timer not implemented\n");
1242             /* ??? Raising the interrupt immediately seems to be sufficient
1243                to keep the FreeBSD driver happy.  */
1244             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1245         }
1246         break;
1247     case 0x4a: /* RESPID0 */
1248         s->respid0 = val;
1249         break;
1250     case 0x4b: /* RESPID1 */
1251         s->respid1 = val;
1252         break;
1253     case 0x4d: /* STEST1 */
1254         s->stest1 = val;
1255         break;
1256     case 0x4e: /* STEST2 */
1257         if (val & 1) {
1258             BADF("Low level mode not implemented\n");
1259         }
1260         s->stest2 = val;
1261         break;
1262     case 0x4f: /* STEST3 */
1263         if (val & 0x41) {
1264             BADF("SCSI FIFO test mode not implemented\n");
1265         }
1266         s->stest3 = val;
1267         break;
1268     case 0x56: /* CCNTL0 */
1269         s->ccntl0 = val;
1270         break;
1271     case 0x57: /* CCNTL1 */
1272         s->ccntl1 = val;
1273         break;
1274     CASE_SET_REG32(mmrs, 0xa0)
1275     CASE_SET_REG32(mmws, 0xa4)
1276     CASE_SET_REG32(sfs, 0xa8)
1277     CASE_SET_REG32(drs, 0xac)
1278     CASE_SET_REG32(sbms, 0xb0)
1279     CASE_SET_REG32(dmbs, 0xb4)
1280     CASE_SET_REG32(dnad64, 0xb8)
1281     CASE_SET_REG32(pmjad1, 0xc0)
1282     CASE_SET_REG32(pmjad2, 0xc4)
1283     CASE_SET_REG32(rbc, 0xc8)
1284     CASE_SET_REG32(ua, 0xcc)
1285     CASE_SET_REG32(ia, 0xd4)
1286     CASE_SET_REG32(sbc, 0xd8)
1287     CASE_SET_REG32(csbc, 0xdc)
1288     default:
1289         if (offset >= 0x5c && offset < 0xa0) {
1290             int n;
1291             int shift;
1292             n = (offset - 0x58) >> 2;
1293             shift = (offset & 3) * 8;
1294             s->scratch[n] &= ~(0xff << shift);
1295             s->scratch[n] |= (val & 0xff) << shift;
1296         } else {
1297             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1298         }
1299     }
1300 #undef CASE_SET_REG32
1301 }
1302
1303 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1304 {
1305     LSIState *s = (LSIState *)opaque;
1306
1307     lsi_reg_writeb(s, addr & 0xff, val);
1308 }
1309
1310 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1311 {
1312     LSIState *s = (LSIState *)opaque;
1313
1314     addr &= 0xff;
1315     lsi_reg_writeb(s, addr, val & 0xff);
1316     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1317 }
1318
1319 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1320 {
1321     LSIState *s = (LSIState *)opaque;
1322
1323     addr &= 0xff;
1324     lsi_reg_writeb(s, addr, val & 0xff);
1325     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1326     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1327     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1328 }
1329
1330 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1331 {
1332     LSIState *s = (LSIState *)opaque;
1333
1334     return lsi_reg_readb(s, addr & 0xff);
1335 }
1336
1337 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1338 {
1339     LSIState *s = (LSIState *)opaque;
1340     uint32_t val;
1341
1342     addr &= 0xff;
1343     val = lsi_reg_readb(s, addr);
1344     val |= lsi_reg_readb(s, addr + 1) << 8;
1345     return val;
1346 }
1347
1348 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1349 {
1350     LSIState *s = (LSIState *)opaque;
1351     uint32_t val;
1352     addr &= 0xff;
1353     val = lsi_reg_readb(s, addr);
1354     val |= lsi_reg_readb(s, addr + 1) << 8;
1355     val |= lsi_reg_readb(s, addr + 2) << 16;
1356     val |= lsi_reg_readb(s, addr + 3) << 24;
1357     return val;
1358 }
1359
1360 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1361     lsi_mmio_readb,
1362     lsi_mmio_readw,
1363     lsi_mmio_readl,
1364 };
1365
1366 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1367     lsi_mmio_writeb,
1368     lsi_mmio_writew,
1369     lsi_mmio_writel,
1370 };
1371
1372 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1373 {
1374     LSIState *s = (LSIState *)opaque;
1375     uint32_t newval;
1376     int shift;
1377
1378     addr &= 0x1fff;
1379     newval = s->script_ram[addr >> 2];
1380     shift = (addr & 3) * 8;
1381     newval &= ~(0xff << shift);
1382     newval |= val << shift;
1383     s->script_ram[addr >> 2] = newval;
1384 }
1385
1386 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1387 {
1388     LSIState *s = (LSIState *)opaque;
1389     uint32_t newval;
1390
1391     addr &= 0x1fff;
1392     newval = s->script_ram[addr >> 2];
1393     if (addr & 2) {
1394         newval = (newval & 0xffff) | (val << 16);
1395     } else {
1396         newval = (newval & 0xffff0000) | val;
1397     }
1398     s->script_ram[addr >> 2] = newval;
1399 }
1400
1401
1402 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1403 {
1404     LSIState *s = (LSIState *)opaque;
1405
1406     addr &= 0x1fff;
1407     s->script_ram[addr >> 2] = val;
1408 }
1409
1410 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1411 {
1412     LSIState *s = (LSIState *)opaque;
1413     uint32_t val;
1414
1415     addr &= 0x1fff;
1416     val = s->script_ram[addr >> 2];
1417     val >>= (addr & 3) * 8;
1418     return val & 0xff;
1419 }
1420
1421 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1422 {
1423     LSIState *s = (LSIState *)opaque;
1424     uint32_t val;
1425
1426     addr &= 0x1fff;
1427     val = s->script_ram[addr >> 2];
1428     if (addr & 2)
1429         val >>= 16;
1430     return le16_to_cpu(val);
1431 }
1432
1433 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1434 {
1435     LSIState *s = (LSIState *)opaque;
1436
1437     addr &= 0x1fff;
1438     return le32_to_cpu(s->script_ram[addr >> 2]);
1439 }
1440
1441 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1442     lsi_ram_readb,
1443     lsi_ram_readw,
1444     lsi_ram_readl,
1445 };
1446
1447 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1448     lsi_ram_writeb,
1449     lsi_ram_writew,
1450     lsi_ram_writel,
1451 };
1452
1453 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1454 {
1455     LSIState *s = (LSIState *)opaque;
1456     return lsi_reg_readb(s, addr & 0xff);
1457 }
1458
1459 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1460 {
1461     LSIState *s = (LSIState *)opaque;
1462     uint32_t val;
1463     addr &= 0xff;
1464     val = lsi_reg_readb(s, addr);
1465     val |= lsi_reg_readb(s, addr + 1) << 8;
1466     return val;
1467 }
1468
1469 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1470 {
1471     LSIState *s = (LSIState *)opaque;
1472     uint32_t val;
1473     addr &= 0xff;
1474     val = lsi_reg_readb(s, addr);
1475     val |= lsi_reg_readb(s, addr + 1) << 8;
1476     val |= lsi_reg_readb(s, addr + 2) << 16;
1477     val |= lsi_reg_readb(s, addr + 3) << 24;
1478     return val;
1479 }
1480
1481 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1482 {
1483     LSIState *s = (LSIState *)opaque;
1484     lsi_reg_writeb(s, addr & 0xff, val);
1485 }
1486
1487 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1488 {
1489     LSIState *s = (LSIState *)opaque;
1490     addr &= 0xff;
1491     lsi_reg_writeb(s, addr, val & 0xff);
1492     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1493 }
1494
1495 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1496 {
1497     LSIState *s = (LSIState *)opaque;
1498     addr &= 0xff;
1499     lsi_reg_writeb(s, addr, val & 0xff);
1500     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1501     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1502     lsi_reg_writeb(s, addr + 2, (val >> 24) & 0xff);
1503 }
1504
1505 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1506                            uint32_t addr, uint32_t size, int type)
1507 {
1508     LSIState *s = (LSIState *)pci_dev;
1509
1510     DPRINTF("Mapping IO at %08x\n", addr);
1511
1512     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1513     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1514     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1515     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1516     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1517     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1518 }
1519
1520 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1521                             uint32_t addr, uint32_t size, int type)
1522 {
1523     LSIState *s = (LSIState *)pci_dev;
1524
1525     DPRINTF("Mapping ram at %08x\n", addr);
1526     s->script_ram_base = addr;
1527     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1528 }
1529
1530 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1531                              uint32_t addr, uint32_t size, int type)
1532 {
1533     LSIState *s = (LSIState *)pci_dev;
1534
1535     DPRINTF("Mapping registers at %08x\n", addr);
1536     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1537 }
1538
1539 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1540 {
1541     LSIState *s = (LSIState *)opaque;
1542
1543     if (id < 0) {
1544         for (id = 0; id < LSI_MAX_DEVS; id++) {
1545             if (s->scsi_dev[id] == NULL)
1546                 break;
1547         }
1548     }
1549     if (id >= LSI_MAX_DEVS) {
1550         BADF("Bad Device ID %d\n", id);
1551         return;
1552     }
1553     if (s->scsi_dev[id]) {
1554         DPRINTF("Destroying device %d\n", id);
1555         scsi_disk_destroy(s->scsi_dev[id]);
1556     }
1557     DPRINTF("Attaching block device %d\n", id);
1558     s->scsi_dev[id] = scsi_disk_init(bd, lsi_command_complete, s);
1559 }
1560
1561 void *lsi_scsi_init(PCIBus *bus, int devfn)
1562 {
1563     LSIState *s;
1564
1565     s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1566                                         sizeof(*s), devfn, NULL, NULL);
1567     if (s == NULL) {
1568         fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1569         return NULL;
1570     }
1571
1572     s->pci_dev.config[0x00] = 0x00;
1573     s->pci_dev.config[0x01] = 0x10;
1574     s->pci_dev.config[0x02] = 0x12;
1575     s->pci_dev.config[0x03] = 0x00;
1576     s->pci_dev.config[0x0b] = 0x01;
1577     s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1578
1579     s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1580                                              lsi_mmio_writefn, s);
1581     s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1582                                             lsi_ram_writefn, s);
1583
1584     pci_register_io_region((struct PCIDevice *)s, 0, 256,
1585                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1586     pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1587                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1588     pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1589                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1590
1591     lsi_soft_reset(s);
1592
1593     return s;
1594 }
1595