2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext
*uc
= puc
;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 longjmp(env
->jmp_env
, 1);
77 static TranslationBlock
*tb_find_slow(target_ulong pc
,
81 TranslationBlock
*tb
, **ptb1
;
84 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
89 tb_invalidated_flag
= 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc
= get_phys_addr_code(env
, pc
);
95 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
97 h
= tb_phys_hash_func(phys_pc
);
98 ptb1
= &tb_phys_hash
[h
];
104 tb
->page_addr
[0] == phys_page1
&&
105 tb
->cs_base
== cs_base
&&
106 tb
->flags
== flags
) {
107 /* check next page if needed */
108 if (tb
->page_addr
[1] != -1) {
109 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
111 phys_page2
= get_phys_addr_code(env
, virt_page2
);
112 if (tb
->page_addr
[1] == phys_page2
)
118 ptb1
= &tb
->phys_hash_next
;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag
= 1;
131 tc_ptr
= code_gen_ptr
;
133 tb
->cs_base
= cs_base
;
135 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
136 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
138 /* check next page if needed */
139 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
141 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
142 phys_page2
= get_phys_addr_code(env
, virt_page2
);
144 tb_link_phys(tb
, phys_pc
, phys_page2
);
147 /* we add the TB in the virtual pc hash table */
148 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
149 spin_unlock(&tb_lock
);
153 static inline TranslationBlock
*tb_find_fast(void)
155 TranslationBlock
*tb
;
156 target_ulong cs_base
, pc
;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
165 cs_base
= env
->segs
[R_CS
].base
;
166 pc
= cs_base
+ env
->eip
;
167 #elif defined(TARGET_ARM)
168 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
169 | (env
->vfp
.vec_stride
<< 4);
170 if ((env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
)
172 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 flags
= (env
->pstate
<< 2) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
180 flags
= env
->psrs
| ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1);
184 #elif defined(TARGET_PPC)
185 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
186 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
189 #elif defined(TARGET_MIPS)
190 flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
);
193 #elif defined(TARGET_SH4)
194 flags
= env
->sr
& (SR_MD
| SR_RB
);
195 cs_base
= 0; /* XXXXX */
198 #error unsupported CPU
200 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
201 if (__builtin_expect(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
202 tb
->flags
!= flags
, 0)) {
203 tb
= tb_find_slow(pc
, cs_base
, flags
);
204 /* Note: we do it here to avoid a gcc bug on Mac OS X when
205 doing it in tb_find_slow */
206 if (tb_invalidated_flag
) {
207 /* as some TB could have been invalidated because
208 of memory exceptions while generating the code, we
209 must recompute the hash index here */
217 /* main execution loop */
219 int cpu_exec(CPUState
*env1
)
221 int saved_T0
, saved_T1
;
226 #if defined(TARGET_I386)
251 #elif defined(TARGET_SPARC)
252 #if defined(reg_REGWPTR)
253 uint32_t *saved_regwptr
;
256 #if defined(__sparc__) && !defined(HOST_SOLARIS)
257 int saved_i7
, tmp_T0
;
259 int ret
, interrupt_request
;
260 void (*gen_func
)(void);
261 TranslationBlock
*tb
;
264 #if defined(TARGET_I386)
265 /* handle exit of HALTED state */
266 if (env1
->hflags
& HF_HALTED_MASK
) {
267 /* disable halt condition */
268 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
269 (env1
->eflags
& IF_MASK
)) {
270 env1
->hflags
&= ~HF_HALTED_MASK
;
275 #elif defined(TARGET_PPC)
277 if (env1
->msr
[MSR_EE
] &&
278 (env1
->interrupt_request
&
279 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
))) {
285 #elif defined(TARGET_SPARC)
287 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
288 (env1
->psret
!= 0)) {
294 #elif defined(TARGET_ARM)
296 /* An interrupt wakes the CPU even if the I and F CPSR bits are
298 if (env1
->interrupt_request
299 & (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
)) {
305 #elif defined(TARGET_MIPS)
307 if (env1
->interrupt_request
&
308 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
316 cpu_single_env
= env1
;
318 /* first we save global registers */
326 #if defined(__sparc__) && !defined(HOST_SOLARIS)
327 /* we also save i7 because longjmp may not restore it */
328 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
331 #if defined(TARGET_I386)
358 /* put eflags in CPU temporary format */
359 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
360 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
361 CC_OP
= CC_OP_EFLAGS
;
362 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
363 #elif defined(TARGET_ARM)
364 #elif defined(TARGET_SPARC)
365 #if defined(reg_REGWPTR)
366 saved_regwptr
= REGWPTR
;
368 #elif defined(TARGET_PPC)
369 #elif defined(TARGET_MIPS)
370 #elif defined(TARGET_SH4)
373 #error unsupported target CPU
375 env
->exception_index
= -1;
377 /* prepare setjmp context for exception handling */
379 if (setjmp(env
->jmp_env
) == 0) {
380 env
->current_tb
= NULL
;
381 /* if an exception is pending, we execute it here */
382 if (env
->exception_index
>= 0) {
383 if (env
->exception_index
>= EXCP_INTERRUPT
) {
384 /* exit request from the cpu execution loop */
385 ret
= env
->exception_index
;
387 } else if (env
->user_mode_only
) {
388 /* if user mode only, we simulate a fake exception
389 which will be hanlded outside the cpu execution
391 #if defined(TARGET_I386)
392 do_interrupt_user(env
->exception_index
,
393 env
->exception_is_int
,
395 env
->exception_next_eip
);
397 ret
= env
->exception_index
;
400 #if defined(TARGET_I386)
401 /* simulate a real cpu exception. On i386, it can
402 trigger new exceptions, but we do not handle
403 double or triple faults yet. */
404 do_interrupt(env
->exception_index
,
405 env
->exception_is_int
,
407 env
->exception_next_eip
, 0);
408 #elif defined(TARGET_PPC)
410 #elif defined(TARGET_MIPS)
412 #elif defined(TARGET_SPARC)
413 do_interrupt(env
->exception_index
);
414 #elif defined(TARGET_ARM)
416 #elif defined(TARGET_SH4)
420 env
->exception_index
= -1;
423 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
425 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
426 ret
= kqemu_cpu_exec(env
);
427 /* put eflags in CPU temporary format */
428 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
429 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
430 CC_OP
= CC_OP_EFLAGS
;
431 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
434 longjmp(env
->jmp_env
, 1);
435 } else if (ret
== 2) {
436 /* softmmu execution needed */
438 if (env
->interrupt_request
!= 0) {
439 /* hardware interrupt will be executed just after */
441 /* otherwise, we restart */
442 longjmp(env
->jmp_env
, 1);
448 T0
= 0; /* force lookup of first TB */
450 #if defined(__sparc__) && !defined(HOST_SOLARIS)
451 /* g1 can be modified by some libc? functions */
454 interrupt_request
= env
->interrupt_request
;
455 if (__builtin_expect(interrupt_request
, 0)) {
456 #if defined(TARGET_I386)
457 /* if hardware interrupt pending, we execute it */
458 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
459 (env
->eflags
& IF_MASK
) &&
460 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
462 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
463 intno
= cpu_get_pic_interrupt(env
);
464 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
465 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
467 do_interrupt(intno
, 0, 0, 0, 1);
468 /* ensure that no TB jump will be modified as
469 the program flow was changed */
470 #if defined(__sparc__) && !defined(HOST_SOLARIS)
476 #elif defined(TARGET_PPC)
478 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
483 if ((interrupt_request
& CPU_INTERRUPT_HARD
)) {
485 env
->exception_index
= EXCP_EXTERNAL
;
488 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
489 #if defined(__sparc__) && !defined(HOST_SOLARIS)
494 } else if ((interrupt_request
& CPU_INTERRUPT_TIMER
)) {
496 env
->exception_index
= EXCP_DECR
;
499 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
500 #if defined(__sparc__) && !defined(HOST_SOLARIS)
507 #elif defined(TARGET_MIPS)
508 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
509 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
510 (env
->CP0_Status
& env
->CP0_Cause
& 0x0000FF00) &&
511 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
512 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
513 !(env
->hflags
& MIPS_HFLAG_DM
)) {
515 env
->exception_index
= EXCP_EXT_INTERRUPT
;
518 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
519 #if defined(__sparc__) && !defined(HOST_SOLARIS)
525 #elif defined(TARGET_SPARC)
526 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
528 int pil
= env
->interrupt_index
& 15;
529 int type
= env
->interrupt_index
& 0xf0;
531 if (((type
== TT_EXTINT
) &&
532 (pil
== 15 || pil
> env
->psrpil
)) ||
534 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
535 do_interrupt(env
->interrupt_index
);
536 env
->interrupt_index
= 0;
537 #if defined(__sparc__) && !defined(HOST_SOLARIS)
543 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
544 //do_interrupt(0, 0, 0, 0, 0);
545 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
546 } else if (interrupt_request
& CPU_INTERRUPT_HALT
) {
550 #elif defined(TARGET_ARM)
551 if (interrupt_request
& CPU_INTERRUPT_FIQ
552 && !(env
->uncached_cpsr
& CPSR_F
)) {
553 env
->exception_index
= EXCP_FIQ
;
556 if (interrupt_request
& CPU_INTERRUPT_HARD
557 && !(env
->uncached_cpsr
& CPSR_I
)) {
558 env
->exception_index
= EXCP_IRQ
;
561 #elif defined(TARGET_SH4)
564 /* Don't use the cached interupt_request value,
565 do_interrupt may have updated the EXITTB flag. */
566 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
567 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
568 /* ensure that no TB jump will be modified as
569 the program flow was changed */
570 #if defined(__sparc__) && !defined(HOST_SOLARIS)
576 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
577 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
578 env
->exception_index
= EXCP_INTERRUPT
;
583 if ((loglevel
& CPU_LOG_TB_CPU
)) {
584 #if defined(TARGET_I386)
585 /* restore flags in standard format */
587 env
->regs
[R_EAX
] = EAX
;
590 env
->regs
[R_EBX
] = EBX
;
593 env
->regs
[R_ECX
] = ECX
;
596 env
->regs
[R_EDX
] = EDX
;
599 env
->regs
[R_ESI
] = ESI
;
602 env
->regs
[R_EDI
] = EDI
;
605 env
->regs
[R_EBP
] = EBP
;
608 env
->regs
[R_ESP
] = ESP
;
610 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
611 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
612 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
613 #elif defined(TARGET_ARM)
614 cpu_dump_state(env
, logfile
, fprintf
, 0);
615 #elif defined(TARGET_SPARC)
616 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
617 env
->regwptr
= REGWPTR
;
618 cpu_dump_state(env
, logfile
, fprintf
, 0);
619 #elif defined(TARGET_PPC)
620 cpu_dump_state(env
, logfile
, fprintf
, 0);
621 #elif defined(TARGET_MIPS)
622 cpu_dump_state(env
, logfile
, fprintf
, 0);
623 #elif defined(TARGET_SH4)
624 cpu_dump_state(env
, logfile
, fprintf
, 0);
626 #error unsupported target CPU
632 if ((loglevel
& CPU_LOG_EXEC
)) {
633 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
634 (long)tb
->tc_ptr
, tb
->pc
,
635 lookup_symbol(tb
->pc
));
638 #if defined(__sparc__) && !defined(HOST_SOLARIS)
641 /* see if we can patch the calling TB. When the TB
642 spans two pages, we cannot safely do a direct
647 (env
->kqemu_enabled
!= 2) &&
649 tb
->page_addr
[1] == -1
650 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
651 && (tb
->cflags
& CF_CODE_COPY
) ==
652 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
656 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
657 #if defined(USE_CODE_COPY)
658 /* propagates the FP use info */
659 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
660 (tb
->cflags
& CF_FP_USED
);
662 spin_unlock(&tb_lock
);
666 env
->current_tb
= tb
;
667 /* execute the generated code */
668 gen_func
= (void *)tc_ptr
;
669 #if defined(__sparc__)
670 __asm__
__volatile__("call %0\n\t"
674 : "i0", "i1", "i2", "i3", "i4", "i5",
675 "l0", "l1", "l2", "l3", "l4", "l5",
677 #elif defined(__arm__)
678 asm volatile ("mov pc, %0\n\t"
679 ".global exec_loop\n\t"
683 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
684 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
686 if (!(tb
->cflags
& CF_CODE_COPY
)) {
687 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
688 save_native_fp_state(env
);
692 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
693 restore_native_fp_state(env
);
695 /* we work with native eflags */
696 CC_SRC
= cc_table
[CC_OP
].compute_all();
697 CC_OP
= CC_OP_EFLAGS
;
698 asm(".globl exec_loop\n"
703 " fs movl %11, %%eax\n"
704 " andl $0x400, %%eax\n"
705 " fs orl %8, %%eax\n"
708 " fs movl %%esp, %12\n"
709 " fs movl %0, %%eax\n"
710 " fs movl %1, %%ecx\n"
711 " fs movl %2, %%edx\n"
712 " fs movl %3, %%ebx\n"
713 " fs movl %4, %%esp\n"
714 " fs movl %5, %%ebp\n"
715 " fs movl %6, %%esi\n"
716 " fs movl %7, %%edi\n"
719 " fs movl %%esp, %4\n"
720 " fs movl %12, %%esp\n"
721 " fs movl %%eax, %0\n"
722 " fs movl %%ecx, %1\n"
723 " fs movl %%edx, %2\n"
724 " fs movl %%ebx, %3\n"
725 " fs movl %%ebp, %5\n"
726 " fs movl %%esi, %6\n"
727 " fs movl %%edi, %7\n"
730 " movl %%eax, %%ecx\n"
731 " andl $0x400, %%ecx\n"
733 " andl $0x8d5, %%eax\n"
734 " fs movl %%eax, %8\n"
736 " subl %%ecx, %%eax\n"
737 " fs movl %%eax, %11\n"
738 " fs movl %9, %%ebx\n" /* get T0 value */
741 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
742 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
743 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
744 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
745 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
746 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
747 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
748 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
749 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
750 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
752 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
753 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
758 #elif defined(__ia64)
765 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
766 (*(void (*)(void)) &fp
)();
770 env
->current_tb
= NULL
;
771 /* reset soft MMU for next block (it can currently
772 only be set by a memory fault) */
773 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
774 if (env
->hflags
& HF_SOFTMMU_MASK
) {
775 env
->hflags
&= ~HF_SOFTMMU_MASK
;
776 /* do not allow linking to another block */
780 #if defined(USE_KQEMU)
781 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
782 if (kqemu_is_ok(env
) &&
783 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
794 #if defined(TARGET_I386)
795 #if defined(USE_CODE_COPY)
796 if (env
->native_fp_regs
) {
797 save_native_fp_state(env
);
800 /* restore flags in standard format */
801 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
803 /* restore global registers */
828 #elif defined(TARGET_ARM)
829 /* XXX: Save/restore host fpu exception state?. */
830 #elif defined(TARGET_SPARC)
831 #if defined(reg_REGWPTR)
832 REGWPTR
= saved_regwptr
;
834 #elif defined(TARGET_PPC)
835 #elif defined(TARGET_MIPS)
836 #elif defined(TARGET_SH4)
839 #error unsupported target CPU
841 #if defined(__sparc__) && !defined(HOST_SOLARIS)
842 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
850 /* fail safe : never use cpu_single_env outside cpu_exec() */
851 cpu_single_env
= NULL
;
855 /* must only be called from the generated code as an exception can be
857 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
859 /* XXX: cannot enable it yet because it yields to MMU exception
860 where NIP != read address on PowerPC */
862 target_ulong phys_addr
;
863 phys_addr
= get_phys_addr_code(env
, start
);
864 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
868 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
870 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
872 CPUX86State
*saved_env
;
876 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
878 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
879 (selector
<< 4), 0xffff, 0);
881 load_seg(seg_reg
, selector
);
886 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
888 CPUX86State
*saved_env
;
893 helper_fsave((target_ulong
)ptr
, data32
);
898 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
900 CPUX86State
*saved_env
;
905 helper_frstor((target_ulong
)ptr
, data32
);
910 #endif /* TARGET_I386 */
912 #if !defined(CONFIG_SOFTMMU)
914 #if defined(TARGET_I386)
916 /* 'pc' is the host PC at which the exception was raised. 'address' is
917 the effective address of the memory exception. 'is_write' is 1 if a
918 write caused the exception and otherwise 0'. 'old_set' is the
919 signal set which should be restored */
920 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
921 int is_write
, sigset_t
*old_set
,
924 TranslationBlock
*tb
;
928 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
929 #if defined(DEBUG_SIGNAL)
930 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
931 pc
, address
, is_write
, *(unsigned long *)old_set
);
933 /* XXX: locking issue */
934 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
938 /* see if it is an MMU fault */
939 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
940 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
942 return 0; /* not an MMU fault */
944 return 1; /* the MMU fault was handled without causing real CPU fault */
945 /* now we have a real cpu fault */
948 /* the PC is inside the translated code. It means that we have
949 a virtual CPU fault */
950 cpu_restore_state(tb
, env
, pc
, puc
);
954 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
955 env
->eip
, env
->cr
[2], env
->error_code
);
957 /* we restore the process signal mask as the sigreturn should
958 do it (XXX: use sigsetjmp) */
959 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
960 raise_exception_err(env
->exception_index
, env
->error_code
);
962 /* activate soft MMU for this block */
963 env
->hflags
|= HF_SOFTMMU_MASK
;
964 cpu_resume_from_signal(env
, puc
);
966 /* never comes here */
970 #elif defined(TARGET_ARM)
971 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
972 int is_write
, sigset_t
*old_set
,
975 TranslationBlock
*tb
;
979 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
980 #if defined(DEBUG_SIGNAL)
981 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
982 pc
, address
, is_write
, *(unsigned long *)old_set
);
984 /* XXX: locking issue */
985 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
988 /* see if it is an MMU fault */
989 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
991 return 0; /* not an MMU fault */
993 return 1; /* the MMU fault was handled without causing real CPU fault */
994 /* now we have a real cpu fault */
997 /* the PC is inside the translated code. It means that we have
998 a virtual CPU fault */
999 cpu_restore_state(tb
, env
, pc
, puc
);
1001 /* we restore the process signal mask as the sigreturn should
1002 do it (XXX: use sigsetjmp) */
1003 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1006 #elif defined(TARGET_SPARC)
1007 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1008 int is_write
, sigset_t
*old_set
,
1011 TranslationBlock
*tb
;
1015 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1016 #if defined(DEBUG_SIGNAL)
1017 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1018 pc
, address
, is_write
, *(unsigned long *)old_set
);
1020 /* XXX: locking issue */
1021 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1024 /* see if it is an MMU fault */
1025 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1027 return 0; /* not an MMU fault */
1029 return 1; /* the MMU fault was handled without causing real CPU fault */
1030 /* now we have a real cpu fault */
1031 tb
= tb_find_pc(pc
);
1033 /* the PC is inside the translated code. It means that we have
1034 a virtual CPU fault */
1035 cpu_restore_state(tb
, env
, pc
, puc
);
1037 /* we restore the process signal mask as the sigreturn should
1038 do it (XXX: use sigsetjmp) */
1039 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1042 #elif defined (TARGET_PPC)
1043 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1044 int is_write
, sigset_t
*old_set
,
1047 TranslationBlock
*tb
;
1051 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1052 #if defined(DEBUG_SIGNAL)
1053 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1054 pc
, address
, is_write
, *(unsigned long *)old_set
);
1056 /* XXX: locking issue */
1057 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1061 /* see if it is an MMU fault */
1062 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
1064 return 0; /* not an MMU fault */
1066 return 1; /* the MMU fault was handled without causing real CPU fault */
1068 /* now we have a real cpu fault */
1069 tb
= tb_find_pc(pc
);
1071 /* the PC is inside the translated code. It means that we have
1072 a virtual CPU fault */
1073 cpu_restore_state(tb
, env
, pc
, puc
);
1077 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1078 env
->nip
, env
->error_code
, tb
);
1080 /* we restore the process signal mask as the sigreturn should
1081 do it (XXX: use sigsetjmp) */
1082 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1083 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1085 /* activate soft MMU for this block */
1086 cpu_resume_from_signal(env
, puc
);
1088 /* never comes here */
1092 #elif defined (TARGET_MIPS)
1093 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1094 int is_write
, sigset_t
*old_set
,
1097 TranslationBlock
*tb
;
1101 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1102 #if defined(DEBUG_SIGNAL)
1103 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1104 pc
, address
, is_write
, *(unsigned long *)old_set
);
1106 /* XXX: locking issue */
1107 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1111 /* see if it is an MMU fault */
1112 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1114 return 0; /* not an MMU fault */
1116 return 1; /* the MMU fault was handled without causing real CPU fault */
1118 /* now we have a real cpu fault */
1119 tb
= tb_find_pc(pc
);
1121 /* the PC is inside the translated code. It means that we have
1122 a virtual CPU fault */
1123 cpu_restore_state(tb
, env
, pc
, puc
);
1127 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1128 env
->nip
, env
->error_code
, tb
);
1130 /* we restore the process signal mask as the sigreturn should
1131 do it (XXX: use sigsetjmp) */
1132 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1133 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1135 /* activate soft MMU for this block */
1136 cpu_resume_from_signal(env
, puc
);
1138 /* never comes here */
1142 #elif defined (TARGET_SH4)
1143 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1144 int is_write
, sigset_t
*old_set
,
1147 TranslationBlock
*tb
;
1151 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1152 #if defined(DEBUG_SIGNAL)
1153 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1154 pc
, address
, is_write
, *(unsigned long *)old_set
);
1156 /* XXX: locking issue */
1157 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1161 /* see if it is an MMU fault */
1162 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1164 return 0; /* not an MMU fault */
1166 return 1; /* the MMU fault was handled without causing real CPU fault */
1168 /* now we have a real cpu fault */
1169 tb
= tb_find_pc(pc
);
1171 /* the PC is inside the translated code. It means that we have
1172 a virtual CPU fault */
1173 cpu_restore_state(tb
, env
, pc
, puc
);
1176 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1177 env
->nip
, env
->error_code
, tb
);
1179 /* we restore the process signal mask as the sigreturn should
1180 do it (XXX: use sigsetjmp) */
1181 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1183 /* never comes here */
1187 #error unsupported target CPU
1190 #if defined(__i386__)
1192 #if defined(USE_CODE_COPY)
1193 static void cpu_send_trap(unsigned long pc
, int trap
,
1194 struct ucontext
*uc
)
1196 TranslationBlock
*tb
;
1199 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1200 /* now we have a real cpu fault */
1201 tb
= tb_find_pc(pc
);
1203 /* the PC is inside the translated code. It means that we have
1204 a virtual CPU fault */
1205 cpu_restore_state(tb
, env
, pc
, uc
);
1207 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1208 raise_exception_err(trap
, env
->error_code
);
1212 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1215 struct ucontext
*uc
= puc
;
1223 #define REG_TRAPNO TRAPNO
1225 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
1226 trapno
= uc
->uc_mcontext
.gregs
[REG_TRAPNO
];
1227 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1228 if (trapno
== 0x00 || trapno
== 0x05) {
1229 /* send division by zero or bound exception */
1230 cpu_send_trap(pc
, trapno
, uc
);
1234 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1236 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1237 &uc
->uc_sigmask
, puc
);
1240 #elif defined(__x86_64__)
1242 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1245 struct ucontext
*uc
= puc
;
1248 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1249 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1250 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1251 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1252 &uc
->uc_sigmask
, puc
);
1255 #elif defined(__powerpc__)
1257 /***********************************************************************
1258 * signal context platform-specific definitions
1262 /* All Registers access - only for local access */
1263 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1264 /* Gpr Registers access */
1265 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1266 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1267 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1268 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1269 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1270 # define LR_sig(context) REG_sig(link, context) /* Link register */
1271 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1272 /* Float Registers access */
1273 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1274 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1275 /* Exception Registers access */
1276 # define DAR_sig(context) REG_sig(dar, context)
1277 # define DSISR_sig(context) REG_sig(dsisr, context)
1278 # define TRAP_sig(context) REG_sig(trap, context)
1282 # include <sys/ucontext.h>
1283 typedef struct ucontext SIGCONTEXT
;
1284 /* All Registers access - only for local access */
1285 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1286 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1287 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1288 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1289 /* Gpr Registers access */
1290 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1291 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1292 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1293 # define CTR_sig(context) REG_sig(ctr, context)
1294 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1295 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1296 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1297 /* Float Registers access */
1298 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1299 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1300 /* Exception Registers access */
1301 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1302 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1303 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1304 #endif /* __APPLE__ */
1306 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1309 struct ucontext
*uc
= puc
;
1317 if (DSISR_sig(uc
) & 0x00800000)
1320 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1323 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1324 is_write
, &uc
->uc_sigmask
, puc
);
1327 #elif defined(__alpha__)
1329 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1332 struct ucontext
*uc
= puc
;
1333 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1334 uint32_t insn
= *pc
;
1337 /* XXX: need kernel patch to get write flag faster */
1338 switch (insn
>> 26) {
1353 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1354 is_write
, &uc
->uc_sigmask
, puc
);
1356 #elif defined(__sparc__)
1358 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1361 uint32_t *regs
= (uint32_t *)(info
+ 1);
1362 void *sigmask
= (regs
+ 20);
1367 /* XXX: is there a standard glibc define ? */
1369 /* XXX: need kernel patch to get write flag faster */
1371 insn
= *(uint32_t *)pc
;
1372 if ((insn
>> 30) == 3) {
1373 switch((insn
>> 19) & 0x3f) {
1385 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1386 is_write
, sigmask
, NULL
);
1389 #elif defined(__arm__)
1391 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1394 struct ucontext
*uc
= puc
;
1398 pc
= uc
->uc_mcontext
.gregs
[R15
];
1399 /* XXX: compute is_write */
1401 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1406 #elif defined(__mc68000)
1408 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1411 struct ucontext
*uc
= puc
;
1415 pc
= uc
->uc_mcontext
.gregs
[16];
1416 /* XXX: compute is_write */
1418 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1420 &uc
->uc_sigmask
, puc
);
1423 #elif defined(__ia64)
1426 /* This ought to be in <bits/siginfo.h>... */
1427 # define __ISR_VALID 1
1430 int cpu_signal_handler(int host_signum
, struct siginfo
*info
, void *puc
)
1432 struct ucontext
*uc
= puc
;
1436 ip
= uc
->uc_mcontext
.sc_ip
;
1437 switch (host_signum
) {
1443 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1444 /* ISR.W (write-access) is bit 33: */
1445 is_write
= (info
->si_isr
>> 33) & 1;
1451 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1453 &uc
->uc_sigmask
, puc
);
1456 #elif defined(__s390__)
1458 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1461 struct ucontext
*uc
= puc
;
1465 pc
= uc
->uc_mcontext
.psw
.addr
;
1466 /* XXX: compute is_write */
1468 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1470 &uc
->uc_sigmask
, puc
);
1475 #error host CPU specific signal handler needed
1479 #endif /* !defined(CONFIG_SOFTMMU) */