hw/ppc.c

   1 /*
   2  * QEMU generic PPC hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "m48t59.h"
  26
  27 extern FILE *logfile;
  28 extern int loglevel;
  29
  30 /*****************************************************************************/
  31 /* PowerPC internal fake IRQ controller
  32  * used to manage multiple sources hardware events
  33  */
  34 /* XXX: should be protected */
  35 void ppc_set_irq (void *opaque, int n_IRQ, int level)
  36 {
  37     CPUState *env;
  38
  39     env = opaque;
  40     if (level) {
  41         env->pending_interrupts |= 1 << n_IRQ;
  42         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  43     } else {
  44         env->pending_interrupts &= ~(1 << n_IRQ);
  45         if (env->pending_interrupts == 0)
  46             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  47     }
  48 #if 0
  49     printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
  50            env, n_IRQ, level, env->pending_interrupts, env->interrupt_request);
  51 #endif
  52 }
  53
  54 /* External IRQ callback from OpenPIC IRQ controller */
  55 void ppc_openpic_irq (void *opaque, int n_IRQ, int level)
  56 {
  57     switch (n_IRQ) {
  58     case OPENPIC_EVT_INT:
  59         n_IRQ = PPC_INTERRUPT_EXT;
  60         break;
  61     case OPENPIC_EVT_CINT:
  62         /* On PowerPC BookE, critical input use vector 0 */
  63         n_IRQ = PPC_INTERRUPT_RESET;
  64         break;
  65     case OPENPIC_EVT_MCK:
  66         n_IRQ = PPC_INTERRUPT_MCK;
  67         break;
  68     case OPENPIC_EVT_DEBUG:
  69         n_IRQ = PPC_INTERRUPT_DEBUG;
  70         break;
  71     case OPENPIC_EVT_RESET:
  72         qemu_system_reset_request();
  73         return;
  74     }
  75     ppc_set_irq(opaque, n_IRQ, level);
  76 }
  77
  78 /*****************************************************************************/
  79 /* PPC time base and decrementer emulation */
  80 //#define DEBUG_TB
  81
  82 struct ppc_tb_t {
  83     /* Time base management */
  84     int64_t  tb_offset;    /* Compensation               */
  85     uint32_t tb_freq;      /* TB frequency               */
  86     /* Decrementer management */
  87     uint64_t decr_next;    /* Tick for next decr interrupt  */
  88     struct QEMUTimer *decr_timer;
  89     void *opaque;
  90 };
  91
  92 static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
  93 {
  94     /* TB time in tb periods */
  95     return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
  96                     tb_env->tb_freq, ticks_per_sec);
  97 }
  98
  99 uint32_t cpu_ppc_load_tbl (CPUState *env)
 100 {
 101     ppc_tb_t *tb_env = env->tb_env;
 102     uint64_t tb;
 103
 104     tb = cpu_ppc_get_tb(tb_env);
 105 #ifdef DEBUG_TB
 106     {
 107         static int last_time;
 108         int now;
 109         now = time(NULL);
 110         if (last_time != now) {
 111             last_time = now;
 112             printf("%s: tb=0x%016lx %d %08lx\n",
 113                    __func__, tb, now, tb_env->tb_offset);
 114         }
 115     }
 116 #endif
 117
 118     return tb & 0xFFFFFFFF;
 119 }
 120
 121 uint32_t cpu_ppc_load_tbu (CPUState *env)
 122 {
 123     ppc_tb_t *tb_env = env->tb_env;
 124     uint64_t tb;
 125
 126     tb = cpu_ppc_get_tb(tb_env);
 127 #ifdef DEBUG_TB
 128     printf("%s: tb=0x%016lx\n", __func__, tb);
 129 #endif
 130
 131     return tb >> 32;
 132 }
 133
 134 static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
 135 {
 136     tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
 137         - qemu_get_clock(vm_clock);
 138 #ifdef DEBUG_TB
 139     printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
 140 #endif
 141 }
 142
 143 void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
 144 {
 145     ppc_tb_t *tb_env = env->tb_env;
 146
 147     cpu_ppc_store_tb(tb_env,
 148                      ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
 149 }
 150
 151 void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
 152 {
 153     ppc_tb_t *tb_env = env->tb_env;
 154
 155     cpu_ppc_store_tb(tb_env,
 156                      ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
 157 }
 158
 159 uint32_t cpu_ppc_load_decr (CPUState *env)
 160 {
 161     ppc_tb_t *tb_env = env->tb_env;
 162     uint32_t decr;
 163     int64_t diff;
 164
 165     diff = tb_env->decr_next - qemu_get_clock(vm_clock);
 166     if (diff >= 0)
 167         decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
 168     else
 169         decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
 170 #if defined(DEBUG_TB)
 171     printf("%s: 0x%08x\n", __func__, decr);
 172 #endif
 173
 174     return decr;
 175 }
 176
 177 /* When decrementer expires,
 178  * all we need to do is generate or queue a CPU exception
 179  */
 180 static inline void cpu_ppc_decr_excp (CPUState *env)
 181 {
 182     /* Raise it */
 183 #ifdef DEBUG_TB
 184     printf("raise decrementer exception\n");
 185 #endif
 186     ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
 187 }
 188
 189 static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
 190                                  uint32_t value, int is_excp)
 191 {
 192     ppc_tb_t *tb_env = env->tb_env;
 193     uint64_t now, next;
 194
 195 #ifdef DEBUG_TB
 196     printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
 197 #endif
 198     now = qemu_get_clock(vm_clock);
 199     next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
 200     if (is_excp)
 201         next += tb_env->decr_next - now;
 202     if (next == now)
 203         next++;
 204     tb_env->decr_next = next;
 205     /* Adjust timer */
 206     qemu_mod_timer(tb_env->decr_timer, next);
 207     /* If we set a negative value and the decrementer was positive,
 208      * raise an exception.
 209      */
 210     if ((value & 0x80000000) && !(decr & 0x80000000))
 211         cpu_ppc_decr_excp(env);
 212 }
 213
 214 void cpu_ppc_store_decr (CPUState *env, uint32_t value)
 215 {
 216     _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
 217 }
 218
 219 static void cpu_ppc_decr_cb (void *opaque)
 220 {
 221     _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
 222 }
 223
 224 /* Set up (once) timebase frequency (in Hz) */
 225 ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
 226 {
 227     ppc_tb_t *tb_env;
 228
 229     tb_env = qemu_mallocz(sizeof(ppc_tb_t));
 230     if (tb_env == NULL)
 231         return NULL;
 232     env->tb_env = tb_env;
 233     if (tb_env->tb_freq == 0 || 1) {
 234         tb_env->tb_freq = freq;
 235         /* Create new timer */
 236         tb_env->decr_timer =
 237             qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
 238         /* There is a bug in Linux 2.4 kernels:
 239          * if a decrementer exception is pending when it enables msr_ee,
 240          * it's not ready to handle it...
 241          */
 242         _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
 243     }
 244
 245     return tb_env;
 246 }
 247
 248 /* Specific helpers for POWER & PowerPC 601 RTC */
 249 ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
 250 {
 251     return cpu_ppc_tb_init(env, 7812500);
 252 }
 253
 254 void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
 255 __attribute__ (( alias ("cpu_ppc_store_tbu") ));
 256
 257 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
 258 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
 259
 260 void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
 261 {
 262     cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
 263 }
 264
 265 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
 266 {
 267     return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
 268 }
 269
 270 /* Embedded PowerPC timers */
 271 target_ulong load_40x_pit (CPUState *env)
 272 {
 273     /* XXX: TODO */
 274     return 0;
 275 }
 276
 277 void store_40x_pit (CPUState *env, target_ulong val)
 278 {
 279     /* XXX: TODO */
 280 }
 281
 282 void store_booke_tcr (CPUState *env, target_ulong val)
 283 {
 284     /* XXX: TODO */
 285 }
 286
 287 void store_booke_tsr (CPUState *env, target_ulong val)
 288 {
 289     /* XXX: TODO */
 290 }
 291
 292 #if 0
 293 /*****************************************************************************/
 294 /* Handle system reset (for now, just stop emulation) */
 295 void cpu_ppc_reset (CPUState *env)
 296 {
 297     printf("Reset asked... Stop emulation\n");
 298     abort();
 299 }
 300 #endif
 301
 302 /*****************************************************************************/
 303 /* Debug port */
 304 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
 305 {
 306     addr &= 0xF;
 307     switch (addr) {
 308     case 0:
 309         printf("%c", val);
 310         break;
 311     case 1:
 312         printf("\n");
 313         fflush(stdout);
 314         break;
 315     case 2:
 316         printf("Set loglevel to %04x\n", val);
 317         cpu_set_log(val | 0x100);
 318         break;
 319     }
 320 }
 321
 322 /*****************************************************************************/
 323 /* NVRAM helpers */
 324 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
 325 {
 326     m48t59_write(nvram, addr, value);
 327 }
 328
 329 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
 330 {
 331     return m48t59_read(nvram, addr);
 332 }
 333
 334 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
 335 {
 336     m48t59_write(nvram, addr, value >> 8);
 337     m48t59_write(nvram, addr + 1, value & 0xFF);
 338 }
 339
 340 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
 341 {
 342     uint16_t tmp;
 343
 344     tmp = m48t59_read(nvram, addr) << 8;
 345     tmp |= m48t59_read(nvram, addr + 1);
 346     return tmp;
 347 }
 348
 349 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
 350 {
 351     m48t59_write(nvram, addr, value >> 24);
 352     m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
 353     m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
 354     m48t59_write(nvram, addr + 3, value & 0xFF);
 355 }
 356
 357 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
 358 {
 359     uint32_t tmp;
 360
 361     tmp = m48t59_read(nvram, addr) << 24;
 362     tmp |= m48t59_read(nvram, addr + 1) << 16;
 363     tmp |= m48t59_read(nvram, addr + 2) << 8;
 364     tmp |= m48t59_read(nvram, addr + 3);
 365
 366     return tmp;
 367 }
 368
 369 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
 370                        const unsigned char *str, uint32_t max)
 371 {
 372     int i;
 373
 374     for (i = 0; i < max && str[i] != '\0'; i++) {
 375         m48t59_write(nvram, addr + i, str[i]);
 376     }
 377     m48t59_write(nvram, addr + max - 1, '\0');
 378 }
 379
 380 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
 381 {
 382     int i;
 383
 384     memset(dst, 0, max);
 385     for (i = 0; i < max; i++) {
 386         dst[i] = NVRAM_get_byte(nvram, addr + i);
 387         if (dst[i] == '\0')
 388             break;
 389     }
 390
 391     return i;
 392 }
 393
 394 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 395 {
 396     uint16_t tmp;
 397     uint16_t pd, pd1, pd2;
 398
 399     tmp = prev >> 8;
 400     pd = prev ^ value;
 401     pd1 = pd & 0x000F;
 402     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 403     tmp ^= (pd1 << 3) | (pd1 << 8);
 404     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 405
 406     return tmp;
 407 }
 408
 409 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
 410 {
 411     uint32_t i;
 412     uint16_t crc = 0xFFFF;
 413     int odd;
 414
 415     odd = count & 1;
 416     count &= ~1;
 417     for (i = 0; i != count; i++) {
 418         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 419     }
 420     if (odd) {
 421         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 422     }
 423
 424     return crc;
 425 }
 426
 427 #define CMDLINE_ADDR 0x017ff000
 428
 429 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 430                           const unsigned char *arch,
 431                           uint32_t RAM_size, int boot_device,
 432                           uint32_t kernel_image, uint32_t kernel_size,
 433                           const char *cmdline,
 434                           uint32_t initrd_image, uint32_t initrd_size,
 435                           uint32_t NVRAM_image,
 436                           int width, int height, int depth)
 437 {
 438     uint16_t crc;
 439
 440     /* Set parameters for Open Hack'Ware BIOS */
 441     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 442     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 443     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 444     NVRAM_set_string(nvram, 0x20, arch, 16);
 445     NVRAM_set_lword(nvram,  0x30, RAM_size);
 446     NVRAM_set_byte(nvram,   0x34, boot_device);
 447     NVRAM_set_lword(nvram,  0x38, kernel_image);
 448     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 449     if (cmdline) {
 450         /* XXX: put the cmdline in NVRAM too ? */
 451         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 452         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 453         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 454     } else {
 455         NVRAM_set_lword(nvram,  0x40, 0);
 456         NVRAM_set_lword(nvram,  0x44, 0);
 457     }
 458     NVRAM_set_lword(nvram,  0x48, initrd_image);
 459     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 460     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 461
 462     NVRAM_set_word(nvram,   0x54, width);
 463     NVRAM_set_word(nvram,   0x56, height);
 464     NVRAM_set_word(nvram,   0x58, depth);
 465     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 466     NVRAM_set_word(nvram,  0xFC, crc);
 467
 468     return 0;
 469 }