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Merge commit 'origin/master' into dev-mini2440-stable
[qemu/mini2440.git] / linux-user / main.c
blobfeb30361705355e6356ea41a19ec84c3de1be681
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <stdarg.h>
24 #include <string.h>
25 #include <errno.h>
26 #include <unistd.h>
27 #include <sys/mman.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cache-utils.h"
32 /* For tb_lock */
33 #include "exec-all.h"
34
35
36 #include "envlist.h"
37
38 #define DEBUG_LOGFILE "/tmp/qemu.log"
39
40 char *exec_path;
41
42 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
43 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
44
45 #if defined(__i386__) && !defined(CONFIG_STATIC)
46 /* Force usage of an ELF interpreter even if it is an ELF shared
47 object ! */
48 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2";
49 #endif
50
51 /* for recent libc, we add these dummy symbols which are not declared
52 when generating a linked object (bug in ld ?) */
53 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC)
54 asm(".globl __preinit_array_start\n"
55 ".globl __preinit_array_end\n"
56 ".globl __init_array_start\n"
57 ".globl __init_array_end\n"
58 ".globl __fini_array_start\n"
59 ".globl __fini_array_end\n"
60 ".section \".rodata\"\n"
61 "__preinit_array_start:\n"
62 "__preinit_array_end:\n"
63 "__init_array_start:\n"
64 "__init_array_end:\n"
65 "__fini_array_start:\n"
66 "__fini_array_end:\n"
67 ".long 0\n"
68 ".previous\n");
69 #endif
70
71 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
74 unsigned long x86_stack_size = 512 * 1024;
75
76 void gemu_log(const char *fmt, ...)
77 {
78 va_list ap;
79
80 va_start(ap, fmt);
81 vfprintf(stderr, fmt, ap);
82 va_end(ap);
83 }
84
85 void cpu_outb(CPUState *env, int addr, int val)
86 {
87 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
88 }
89
90 void cpu_outw(CPUState *env, int addr, int val)
91 {
92 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
93 }
94
95 void cpu_outl(CPUState *env, int addr, int val)
96 {
97 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
98 }
99
100 int cpu_inb(CPUState *env, int addr)
101 {
102 fprintf(stderr, "inb: port=0x%04x\n", addr);
103 return 0;
104 }
105
106 int cpu_inw(CPUState *env, int addr)
107 {
108 fprintf(stderr, "inw: port=0x%04x\n", addr);
109 return 0;
110 }
111
112 int cpu_inl(CPUState *env, int addr)
113 {
114 fprintf(stderr, "inl: port=0x%04x\n", addr);
115 return 0;
116 }
117
118 #if defined(TARGET_I386)
119 int cpu_get_pic_interrupt(CPUState *env)
120 {
121 return -1;
122 }
123 #endif
124
125 /* timers for rdtsc */
126
127 #if 0
128
129 static uint64_t emu_time;
130
131 int64_t cpu_get_real_ticks(void)
132 {
133 return emu_time++;
134 }
135
136 #endif
137
138 #if defined(USE_NPTL)
139 /***********************************************************/
140 /* Helper routines for implementing atomic operations. */
141
142 /* To implement exclusive operations we force all cpus to syncronise.
143 We don't require a full sync, only that no cpus are executing guest code.
144 The alternative is to map target atomic ops onto host equivalents,
145 which requires quite a lot of per host/target work. */
146 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
147 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
148 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
149 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
150 static int pending_cpus;
151
152 /* Make sure everything is in a consistent state for calling fork(). */
153 void fork_start(void)
154 {
155 mmap_fork_start();
156 pthread_mutex_lock(&tb_lock);
157 pthread_mutex_lock(&exclusive_lock);
158 }
159
160 void fork_end(int child)
161 {
162 if (child) {
163 /* Child processes created by fork() only have a single thread.
164 Discard information about the parent threads. */
165 first_cpu = thread_env;
166 thread_env->next_cpu = NULL;
167 pending_cpus = 0;
168 pthread_mutex_init(&exclusive_lock, NULL);
169 pthread_mutex_init(&cpu_list_mutex, NULL);
170 pthread_cond_init(&exclusive_cond, NULL);
171 pthread_cond_init(&exclusive_resume, NULL);
172 pthread_mutex_init(&tb_lock, NULL);
173 gdbserver_fork(thread_env);
174 } else {
175 pthread_mutex_unlock(&exclusive_lock);
176 pthread_mutex_unlock(&tb_lock);
177 }
178 mmap_fork_end(child);
179 }
180
181 /* Wait for pending exclusive operations to complete. The exclusive lock
182 must be held. */
183 static inline void exclusive_idle(void)
184 {
185 while (pending_cpus) {
186 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
187 }
188 }
189
190 /* Start an exclusive operation.
191 Must only be called from outside cpu_arm_exec. */
192 static inline void start_exclusive(void)
193 {
194 CPUState *other;
195 pthread_mutex_lock(&exclusive_lock);
196 exclusive_idle();
197
198 pending_cpus = 1;
199 /* Make all other cpus stop executing. */
200 for (other = first_cpu; other; other = other->next_cpu) {
201 if (other->running) {
202 pending_cpus++;
203 cpu_exit(other);
204 }
205 }
206 if (pending_cpus > 1) {
207 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
208 }
209 }
210
211 /* Finish an exclusive operation. */
212 static inline void end_exclusive(void)
213 {
214 pending_cpus = 0;
215 pthread_cond_broadcast(&exclusive_resume);
216 pthread_mutex_unlock(&exclusive_lock);
217 }
218
219 /* Wait for exclusive ops to finish, and begin cpu execution. */
220 static inline void cpu_exec_start(CPUState *env)
221 {
222 pthread_mutex_lock(&exclusive_lock);
223 exclusive_idle();
224 env->running = 1;
225 pthread_mutex_unlock(&exclusive_lock);
226 }
227
228 /* Mark cpu as not executing, and release pending exclusive ops. */
229 static inline void cpu_exec_end(CPUState *env)
230 {
231 pthread_mutex_lock(&exclusive_lock);
232 env->running = 0;
233 if (pending_cpus > 1) {
234 pending_cpus--;
235 if (pending_cpus == 1) {
236 pthread_cond_signal(&exclusive_cond);
237 }
238 }
239 exclusive_idle();
240 pthread_mutex_unlock(&exclusive_lock);
241 }
242
243 void cpu_list_lock(void)
244 {
245 pthread_mutex_lock(&cpu_list_mutex);
246 }
247
248 void cpu_list_unlock(void)
249 {
250 pthread_mutex_unlock(&cpu_list_mutex);
251 }
252 #else /* if !USE_NPTL */
253 /* These are no-ops because we are not threadsafe. */
254 static inline void cpu_exec_start(CPUState *env)
255 {
256 }
257
258 static inline void cpu_exec_end(CPUState *env)
259 {
260 }
261
262 static inline void start_exclusive(void)
263 {
264 }
265
266 static inline void end_exclusive(void)
267 {
268 }
269
270 void fork_start(void)
271 {
272 }
273
274 void fork_end(int child)
275 {
276 if (child) {
277 gdbserver_fork(thread_env);
278 }
279 }
280
281 void cpu_list_lock(void)
282 {
283 }
284
285 void cpu_list_unlock(void)
286 {
287 }
288 #endif
289
290
291 #ifdef TARGET_I386
292 /***********************************************************/
293 /* CPUX86 core interface */
294
295 void cpu_smm_update(CPUState *env)
296 {
297 }
298
299 uint64_t cpu_get_tsc(CPUX86State *env)
300 {
301 return cpu_get_real_ticks();
302 }
303
304 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
305 int flags)
306 {
307 unsigned int e1, e2;
308 uint32_t *p;
309 e1 = (addr << 16) | (limit & 0xffff);
310 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
311 e2 |= flags;
312 p = ptr;
313 p[0] = tswap32(e1);
314 p[1] = tswap32(e2);
315 }
316
317 static uint64_t *idt_table;
318 #ifdef TARGET_X86_64
319 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
320 uint64_t addr, unsigned int sel)
321 {
322 uint32_t *p, e1, e2;
323 e1 = (addr & 0xffff) | (sel << 16);
324 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
325 p = ptr;
326 p[0] = tswap32(e1);
327 p[1] = tswap32(e2);
328 p[2] = tswap32(addr >> 32);
329 p[3] = 0;
330 }
331 /* only dpl matters as we do only user space emulation */
332 static void set_idt(int n, unsigned int dpl)
333 {
334 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
335 }
336 #else
337 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
338 uint32_t addr, unsigned int sel)
339 {
340 uint32_t *p, e1, e2;
341 e1 = (addr & 0xffff) | (sel << 16);
342 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
343 p = ptr;
344 p[0] = tswap32(e1);
345 p[1] = tswap32(e2);
346 }
347
348 /* only dpl matters as we do only user space emulation */
349 static void set_idt(int n, unsigned int dpl)
350 {
351 set_gate(idt_table + n, 0, dpl, 0, 0);
352 }
353 #endif
354
355 void cpu_loop(CPUX86State *env)
356 {
357 int trapnr;
358 abi_ulong pc;
359 target_siginfo_t info;
360
361 for(;;) {
362 trapnr = cpu_x86_exec(env);
363 switch(trapnr) {
364 case 0x80:
365 /* linux syscall from int $0x80 */
366 env->regs[R_EAX] = do_syscall(env,
367 env->regs[R_EAX],
368 env->regs[R_EBX],
369 env->regs[R_ECX],
370 env->regs[R_EDX],
371 env->regs[R_ESI],
372 env->regs[R_EDI],
373 env->regs[R_EBP]);
374 break;
375 #ifndef TARGET_ABI32
376 case EXCP_SYSCALL:
377 /* linux syscall from syscall intruction */
378 env->regs[R_EAX] = do_syscall(env,
379 env->regs[R_EAX],
380 env->regs[R_EDI],
381 env->regs[R_ESI],
382 env->regs[R_EDX],
383 env->regs[10],
384 env->regs[8],
385 env->regs[9]);
386 env->eip = env->exception_next_eip;
387 break;
388 #endif
389 case EXCP0B_NOSEG:
390 case EXCP0C_STACK:
391 info.si_signo = SIGBUS;
392 info.si_errno = 0;
393 info.si_code = TARGET_SI_KERNEL;
394 info._sifields._sigfault._addr = 0;
395 queue_signal(env, info.si_signo, &info);
396 break;
397 case EXCP0D_GPF:
398 /* XXX: potential problem if ABI32 */
399 #ifndef TARGET_X86_64
400 if (env->eflags & VM_MASK) {
401 handle_vm86_fault(env);
402 } else
403 #endif
404 {
405 info.si_signo = SIGSEGV;
406 info.si_errno = 0;
407 info.si_code = TARGET_SI_KERNEL;
408 info._sifields._sigfault._addr = 0;
409 queue_signal(env, info.si_signo, &info);
410 }
411 break;
412 case EXCP0E_PAGE:
413 info.si_signo = SIGSEGV;
414 info.si_errno = 0;
415 if (!(env->error_code & 1))
416 info.si_code = TARGET_SEGV_MAPERR;
417 else
418 info.si_code = TARGET_SEGV_ACCERR;
419 info._sifields._sigfault._addr = env->cr[2];
420 queue_signal(env, info.si_signo, &info);
421 break;
422 case EXCP00_DIVZ:
423 #ifndef TARGET_X86_64
424 if (env->eflags & VM_MASK) {
425 handle_vm86_trap(env, trapnr);
426 } else
427 #endif
428 {
429 /* division by zero */
430 info.si_signo = SIGFPE;
431 info.si_errno = 0;
432 info.si_code = TARGET_FPE_INTDIV;
433 info._sifields._sigfault._addr = env->eip;
434 queue_signal(env, info.si_signo, &info);
435 }
436 break;
437 case EXCP01_DB:
438 case EXCP03_INT3:
439 #ifndef TARGET_X86_64
440 if (env->eflags & VM_MASK) {
441 handle_vm86_trap(env, trapnr);
442 } else
443 #endif
444 {
445 info.si_signo = SIGTRAP;
446 info.si_errno = 0;
447 if (trapnr == EXCP01_DB) {
448 info.si_code = TARGET_TRAP_BRKPT;
449 info._sifields._sigfault._addr = env->eip;
450 } else {
451 info.si_code = TARGET_SI_KERNEL;
452 info._sifields._sigfault._addr = 0;
453 }
454 queue_signal(env, info.si_signo, &info);
455 }
456 break;
457 case EXCP04_INTO:
458 case EXCP05_BOUND:
459 #ifndef TARGET_X86_64
460 if (env->eflags & VM_MASK) {
461 handle_vm86_trap(env, trapnr);
462 } else
463 #endif
464 {
465 info.si_signo = SIGSEGV;
466 info.si_errno = 0;
467 info.si_code = TARGET_SI_KERNEL;
468 info._sifields._sigfault._addr = 0;
469 queue_signal(env, info.si_signo, &info);
470 }
471 break;
472 case EXCP06_ILLOP:
473 info.si_signo = SIGILL;
474 info.si_errno = 0;
475 info.si_code = TARGET_ILL_ILLOPN;
476 info._sifields._sigfault._addr = env->eip;
477 queue_signal(env, info.si_signo, &info);
478 break;
479 case EXCP_INTERRUPT:
480 /* just indicate that signals should be handled asap */
481 break;
482 case EXCP_DEBUG:
483 {
484 int sig;
485
486 sig = gdb_handlesig (env, TARGET_SIGTRAP);
487 if (sig)
488 {
489 info.si_signo = sig;
490 info.si_errno = 0;
491 info.si_code = TARGET_TRAP_BRKPT;
492 queue_signal(env, info.si_signo, &info);
493 }
494 }
495 break;
496 default:
497 pc = env->segs[R_CS].base + env->eip;
498 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
499 (long)pc, trapnr);
500 abort();
501 }
502 process_pending_signals(env);
503 }
504 }
505 #endif
506
507 #ifdef TARGET_ARM
508
509 static void arm_cache_flush(abi_ulong start, abi_ulong last)
510 {
511 abi_ulong addr, last1;
512
513 if (last < start)
514 return;
515 addr = start;
516 for(;;) {
517 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
518 if (last1 > last)
519 last1 = last;
520 tb_invalidate_page_range(addr, last1 + 1);
521 if (last1 == last)
522 break;
523 addr = last1 + 1;
524 }
525 }
526
527 /* Handle a jump to the kernel code page. */
528 static int
529 do_kernel_trap(CPUARMState *env)
530 {
531 uint32_t addr;
532 uint32_t cpsr;
533 uint32_t val;
534
535 switch (env->regs[15]) {
536 case 0xffff0fa0: /* __kernel_memory_barrier */
537 /* ??? No-op. Will need to do better for SMP. */
538 break;
539 case 0xffff0fc0: /* __kernel_cmpxchg */
540 /* XXX: This only works between threads, not between processes.
541 It's probably possible to implement this with native host
542 operations. However things like ldrex/strex are much harder so
543 there's not much point trying. */
544 start_exclusive();
545 cpsr = cpsr_read(env);
546 addr = env->regs[2];
547 /* FIXME: This should SEGV if the access fails. */
548 if (get_user_u32(val, addr))
549 val = ~env->regs[0];
550 if (val == env->regs[0]) {
551 val = env->regs[1];
552 /* FIXME: Check for segfaults. */
553 put_user_u32(val, addr);
554 env->regs[0] = 0;
555 cpsr |= CPSR_C;
556 } else {
557 env->regs[0] = -1;
558 cpsr &= ~CPSR_C;
559 }
560 cpsr_write(env, cpsr, CPSR_C);
561 end_exclusive();
562 break;
563 case 0xffff0fe0: /* __kernel_get_tls */
564 env->regs[0] = env->cp15.c13_tls2;
565 break;
566 default:
567 return 1;
568 }
569 /* Jump back to the caller. */
570 addr = env->regs[14];
571 if (addr & 1) {
572 env->thumb = 1;
573 addr &= ~1;
574 }
575 env->regs[15] = addr;
576
577 return 0;
578 }
579
580 void cpu_loop(CPUARMState *env)
581 {
582 int trapnr;
583 unsigned int n, insn;
584 target_siginfo_t info;
585 uint32_t addr;
586
587 for(;;) {
588 cpu_exec_start(env);
589 trapnr = cpu_arm_exec(env);
590 cpu_exec_end(env);
591 switch(trapnr) {
592 case EXCP_UDEF:
593 {
594 TaskState *ts = env->opaque;
595 uint32_t opcode;
596 int rc;
597
598 /* we handle the FPU emulation here, as Linux */
599 /* we get the opcode */
600 /* FIXME - what to do if get_user() fails? */
601 get_user_u32(opcode, env->regs[15]);
602
603 rc = EmulateAll(opcode, &ts->fpa, env);
604 if (rc == 0) { /* illegal instruction */
605 info.si_signo = SIGILL;
606 info.si_errno = 0;
607 info.si_code = TARGET_ILL_ILLOPN;
608 info._sifields._sigfault._addr = env->regs[15];
609 queue_signal(env, info.si_signo, &info);
610 } else if (rc < 0) { /* FP exception */
611 int arm_fpe=0;
612
613 /* translate softfloat flags to FPSR flags */
614 if (-rc & float_flag_invalid)
615 arm_fpe |= BIT_IOC;
616 if (-rc & float_flag_divbyzero)
617 arm_fpe |= BIT_DZC;
618 if (-rc & float_flag_overflow)
619 arm_fpe |= BIT_OFC;
620 if (-rc & float_flag_underflow)
621 arm_fpe |= BIT_UFC;
622 if (-rc & float_flag_inexact)
623 arm_fpe |= BIT_IXC;
624
625 FPSR fpsr = ts->fpa.fpsr;
626 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
627
628 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
629 info.si_signo = SIGFPE;
630 info.si_errno = 0;
631
632 /* ordered by priority, least first */
633 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
634 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
635 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
636 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
637 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
638
639 info._sifields._sigfault._addr = env->regs[15];
640 queue_signal(env, info.si_signo, &info);
641 } else {
642 env->regs[15] += 4;
643 }
644
645 /* accumulate unenabled exceptions */
646 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
647 fpsr |= BIT_IXC;
648 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
649 fpsr |= BIT_UFC;
650 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
651 fpsr |= BIT_OFC;
652 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
653 fpsr |= BIT_DZC;
654 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
655 fpsr |= BIT_IOC;
656 ts->fpa.fpsr=fpsr;
657 } else { /* everything OK */
658 /* increment PC */
659 env->regs[15] += 4;
660 }
661 }
662 break;
663 case EXCP_SWI:
664 case EXCP_BKPT:
665 {
666 env->eabi = 1;
667 /* system call */
668 if (trapnr == EXCP_BKPT) {
669 if (env->thumb) {
670 /* FIXME - what to do if get_user() fails? */
671 get_user_u16(insn, env->regs[15]);
672 n = insn & 0xff;
673 env->regs[15] += 2;
674 } else {
675 /* FIXME - what to do if get_user() fails? */
676 get_user_u32(insn, env->regs[15]);
677 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
678 env->regs[15] += 4;
679 }
680 } else {
681 if (env->thumb) {
682 /* FIXME - what to do if get_user() fails? */
683 get_user_u16(insn, env->regs[15] - 2);
684 n = insn & 0xff;
685 } else {
686 /* FIXME - what to do if get_user() fails? */
687 get_user_u32(insn, env->regs[15] - 4);
688 n = insn & 0xffffff;
689 }
690 }
691
692 if (n == ARM_NR_cacheflush) {
693 arm_cache_flush(env->regs[0], env->regs[1]);
694 } else if (n == ARM_NR_semihosting
695 || n == ARM_NR_thumb_semihosting) {
696 env->regs[0] = do_arm_semihosting (env);
697 } else if (n == 0 || n >= ARM_SYSCALL_BASE
698 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
699 /* linux syscall */
700 if (env->thumb || n == 0) {
701 n = env->regs[7];
702 } else {
703 n -= ARM_SYSCALL_BASE;
704 env->eabi = 0;
705 }
706 if ( n > ARM_NR_BASE) {
707 switch (n) {
708 case ARM_NR_cacheflush:
709 arm_cache_flush(env->regs[0], env->regs[1]);
710 break;
711 case ARM_NR_set_tls:
712 cpu_set_tls(env, env->regs[0]);
713 env->regs[0] = 0;
714 break;
715 default:
716 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
717 n);
718 env->regs[0] = -TARGET_ENOSYS;
719 break;
720 }
721 } else {
722 env->regs[0] = do_syscall(env,
723 n,
724 env->regs[0],
725 env->regs[1],
726 env->regs[2],
727 env->regs[3],
728 env->regs[4],
729 env->regs[5]);
730 }
731 } else {
732 goto error;
733 }
734 }
735 break;
736 case EXCP_INTERRUPT:
737 /* just indicate that signals should be handled asap */
738 break;
739 case EXCP_PREFETCH_ABORT:
740 addr = env->cp15.c6_insn;
741 goto do_segv;
742 case EXCP_DATA_ABORT:
743 addr = env->cp15.c6_data;
744 goto do_segv;
745 do_segv:
746 {
747 info.si_signo = SIGSEGV;
748 info.si_errno = 0;
749 /* XXX: check env->error_code */
750 info.si_code = TARGET_SEGV_MAPERR;
751 info._sifields._sigfault._addr = addr;
752 queue_signal(env, info.si_signo, &info);
753 }
754 break;
755 case EXCP_DEBUG:
756 {
757 int sig;
758
759 sig = gdb_handlesig (env, TARGET_SIGTRAP);
760 if (sig)
761 {
762 info.si_signo = sig;
763 info.si_errno = 0;
764 info.si_code = TARGET_TRAP_BRKPT;
765 queue_signal(env, info.si_signo, &info);
766 }
767 }
768 break;
769 case EXCP_KERNEL_TRAP:
770 if (do_kernel_trap(env))
771 goto error;
772 break;
773 default:
774 error:
775 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
776 trapnr);
777 cpu_dump_state(env, stderr, fprintf, 0);
778 abort();
779 }
780 process_pending_signals(env);
781 }
782 }
783
784 #endif
785
786 #ifdef TARGET_SPARC
787 #define SPARC64_STACK_BIAS 2047
788
789 //#define DEBUG_WIN
790
791 /* WARNING: dealing with register windows _is_ complicated. More info
792 can be found at http://www.sics.se/~psm/sparcstack.html */
793 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
794 {
795 index = (index + cwp * 16) % (16 * env->nwindows);
796 /* wrap handling : if cwp is on the last window, then we use the
797 registers 'after' the end */
798 if (index < 8 && env->cwp == env->nwindows - 1)
799 index += 16 * env->nwindows;
800 return index;
801 }
802
803 /* save the register window 'cwp1' */
804 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
805 {
806 unsigned int i;
807 abi_ulong sp_ptr;
808
809 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
810 #ifdef TARGET_SPARC64
811 if (sp_ptr & 3)
812 sp_ptr += SPARC64_STACK_BIAS;
813 #endif
814 #if defined(DEBUG_WIN)
815 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
816 sp_ptr, cwp1);
817 #endif
818 for(i = 0; i < 16; i++) {
819 /* FIXME - what to do if put_user() fails? */
820 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
821 sp_ptr += sizeof(abi_ulong);
822 }
823 }
824
825 static void save_window(CPUSPARCState *env)
826 {
827 #ifndef TARGET_SPARC64
828 unsigned int new_wim;
829 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
830 ((1LL << env->nwindows) - 1);
831 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
832 env->wim = new_wim;
833 #else
834 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
835 env->cansave++;
836 env->canrestore--;
837 #endif
838 }
839
840 static void restore_window(CPUSPARCState *env)
841 {
842 #ifndef TARGET_SPARC64
843 unsigned int new_wim;
844 #endif
845 unsigned int i, cwp1;
846 abi_ulong sp_ptr;
847
848 #ifndef TARGET_SPARC64
849 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
850 ((1LL << env->nwindows) - 1);
851 #endif
852
853 /* restore the invalid window */
854 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
855 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
856 #ifdef TARGET_SPARC64
857 if (sp_ptr & 3)
858 sp_ptr += SPARC64_STACK_BIAS;
859 #endif
860 #if defined(DEBUG_WIN)
861 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
862 sp_ptr, cwp1);
863 #endif
864 for(i = 0; i < 16; i++) {
865 /* FIXME - what to do if get_user() fails? */
866 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
867 sp_ptr += sizeof(abi_ulong);
868 }
869 #ifdef TARGET_SPARC64
870 env->canrestore++;
871 if (env->cleanwin < env->nwindows - 1)
872 env->cleanwin++;
873 env->cansave--;
874 #else
875 env->wim = new_wim;
876 #endif
877 }
878
879 static void flush_windows(CPUSPARCState *env)
880 {
881 int offset, cwp1;
882
883 offset = 1;
884 for(;;) {
885 /* if restore would invoke restore_window(), then we can stop */
886 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
887 #ifndef TARGET_SPARC64
888 if (env->wim & (1 << cwp1))
889 break;
890 #else
891 if (env->canrestore == 0)
892 break;
893 env->cansave++;
894 env->canrestore--;
895 #endif
896 save_window_offset(env, cwp1);
897 offset++;
898 }
899 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
900 #ifndef TARGET_SPARC64
901 /* set wim so that restore will reload the registers */
902 env->wim = 1 << cwp1;
903 #endif
904 #if defined(DEBUG_WIN)
905 printf("flush_windows: nb=%d\n", offset - 1);
906 #endif
907 }
908
909 void cpu_loop (CPUSPARCState *env)
910 {
911 int trapnr, ret;
912 target_siginfo_t info;
913
914 while (1) {
915 trapnr = cpu_sparc_exec (env);
916
917 switch (trapnr) {
918 #ifndef TARGET_SPARC64
919 case 0x88:
920 case 0x90:
921 #else
922 case 0x110:
923 case 0x16d:
924 #endif
925 ret = do_syscall (env, env->gregs[1],
926 env->regwptr[0], env->regwptr[1],
927 env->regwptr[2], env->regwptr[3],
928 env->regwptr[4], env->regwptr[5]);
929 if ((unsigned int)ret >= (unsigned int)(-515)) {
930 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
931 env->xcc |= PSR_CARRY;
932 #else
933 env->psr |= PSR_CARRY;
934 #endif
935 ret = -ret;
936 } else {
937 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
938 env->xcc &= ~PSR_CARRY;
939 #else
940 env->psr &= ~PSR_CARRY;
941 #endif
942 }
943 env->regwptr[0] = ret;
944 /* next instruction */
945 env->pc = env->npc;
946 env->npc = env->npc + 4;
947 break;
948 case 0x83: /* flush windows */
949 #ifdef TARGET_ABI32
950 case 0x103:
951 #endif
952 flush_windows(env);
953 /* next instruction */
954 env->pc = env->npc;
955 env->npc = env->npc + 4;
956 break;
957 #ifndef TARGET_SPARC64
958 case TT_WIN_OVF: /* window overflow */
959 save_window(env);
960 break;
961 case TT_WIN_UNF: /* window underflow */
962 restore_window(env);
963 break;
964 case TT_TFAULT:
965 case TT_DFAULT:
966 {
967 info.si_signo = SIGSEGV;
968 info.si_errno = 0;
969 /* XXX: check env->error_code */
970 info.si_code = TARGET_SEGV_MAPERR;
971 info._sifields._sigfault._addr = env->mmuregs[4];
972 queue_signal(env, info.si_signo, &info);
973 }
974 break;
975 #else
976 case TT_SPILL: /* window overflow */
977 save_window(env);
978 break;
979 case TT_FILL: /* window underflow */
980 restore_window(env);
981 break;
982 case TT_TFAULT:
983 case TT_DFAULT:
984 {
985 info.si_signo = SIGSEGV;
986 info.si_errno = 0;
987 /* XXX: check env->error_code */
988 info.si_code = TARGET_SEGV_MAPERR;
989 if (trapnr == TT_DFAULT)
990 info._sifields._sigfault._addr = env->dmmuregs[4];
991 else
992 info._sifields._sigfault._addr = env->tsptr->tpc;
993 queue_signal(env, info.si_signo, &info);
994 }
995 break;
996 #ifndef TARGET_ABI32
997 case 0x16e:
998 flush_windows(env);
999 sparc64_get_context(env);
1000 break;
1001 case 0x16f:
1002 flush_windows(env);
1003 sparc64_set_context(env);
1004 break;
1005 #endif
1006 #endif
1007 case EXCP_INTERRUPT:
1008 /* just indicate that signals should be handled asap */
1009 break;
1010 case EXCP_DEBUG:
1011 {
1012 int sig;
1013
1014 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1015 if (sig)
1016 {
1017 info.si_signo = sig;
1018 info.si_errno = 0;
1019 info.si_code = TARGET_TRAP_BRKPT;
1020 queue_signal(env, info.si_signo, &info);
1021 }
1022 }
1023 break;
1024 default:
1025 printf ("Unhandled trap: 0x%x\n", trapnr);
1026 cpu_dump_state(env, stderr, fprintf, 0);
1027 exit (1);
1028 }
1029 process_pending_signals (env);
1030 }
1031 }
1032
1033 #endif
1034
1035 #ifdef TARGET_PPC
1036 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1037 {
1038 /* TO FIX */
1039 return 0;
1040 }
1041
1042 uint32_t cpu_ppc_load_tbl (CPUState *env)
1043 {
1044 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1045 }
1046
1047 uint32_t cpu_ppc_load_tbu (CPUState *env)
1048 {
1049 return cpu_ppc_get_tb(env) >> 32;
1050 }
1051
1052 uint32_t cpu_ppc_load_atbl (CPUState *env)
1053 {
1054 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1055 }
1056
1057 uint32_t cpu_ppc_load_atbu (CPUState *env)
1058 {
1059 return cpu_ppc_get_tb(env) >> 32;
1060 }
1061
1062 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1063 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1064
1065 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1066 {
1067 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1068 }
1069
1070 /* XXX: to be fixed */
1071 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1072 {
1073 return -1;
1074 }
1075
1076 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1077 {
1078 return -1;
1079 }
1080
1081 #define EXCP_DUMP(env, fmt, args...) \
1082 do { \
1083 fprintf(stderr, fmt , ##args); \
1084 cpu_dump_state(env, stderr, fprintf, 0); \
1085 qemu_log(fmt, ##args); \
1086 log_cpu_state(env, 0); \
1087 } while (0)
1088
1089 void cpu_loop(CPUPPCState *env)
1090 {
1091 target_siginfo_t info;
1092 int trapnr;
1093 uint32_t ret;
1094
1095 for(;;) {
1096 trapnr = cpu_ppc_exec(env);
1097 switch(trapnr) {
1098 case POWERPC_EXCP_NONE:
1099 /* Just go on */
1100 break;
1101 case POWERPC_EXCP_CRITICAL: /* Critical input */
1102 cpu_abort(env, "Critical interrupt while in user mode. "
1103 "Aborting\n");
1104 break;
1105 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1106 cpu_abort(env, "Machine check exception while in user mode. "
1107 "Aborting\n");
1108 break;
1109 case POWERPC_EXCP_DSI: /* Data storage exception */
1110 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
1111 env->spr[SPR_DAR]);
1112 /* XXX: check this. Seems bugged */
1113 switch (env->error_code & 0xFF000000) {
1114 case 0x40000000:
1115 info.si_signo = TARGET_SIGSEGV;
1116 info.si_errno = 0;
1117 info.si_code = TARGET_SEGV_MAPERR;
1118 break;
1119 case 0x04000000:
1120 info.si_signo = TARGET_SIGILL;
1121 info.si_errno = 0;
1122 info.si_code = TARGET_ILL_ILLADR;
1123 break;
1124 case 0x08000000:
1125 info.si_signo = TARGET_SIGSEGV;
1126 info.si_errno = 0;
1127 info.si_code = TARGET_SEGV_ACCERR;
1128 break;
1129 default:
1130 /* Let's send a regular segfault... */
1131 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1132 env->error_code);
1133 info.si_signo = TARGET_SIGSEGV;
1134 info.si_errno = 0;
1135 info.si_code = TARGET_SEGV_MAPERR;
1136 break;
1137 }
1138 info._sifields._sigfault._addr = env->nip;
1139 queue_signal(env, info.si_signo, &info);
1140 break;
1141 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1142 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
1143 env->spr[SPR_SRR0]);
1144 /* XXX: check this */
1145 switch (env->error_code & 0xFF000000) {
1146 case 0x40000000:
1147 info.si_signo = TARGET_SIGSEGV;
1148 info.si_errno = 0;
1149 info.si_code = TARGET_SEGV_MAPERR;
1150 break;
1151 case 0x10000000:
1152 case 0x08000000:
1153 info.si_signo = TARGET_SIGSEGV;
1154 info.si_errno = 0;
1155 info.si_code = TARGET_SEGV_ACCERR;
1156 break;
1157 default:
1158 /* Let's send a regular segfault... */
1159 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1160 env->error_code);
1161 info.si_signo = TARGET_SIGSEGV;
1162 info.si_errno = 0;
1163 info.si_code = TARGET_SEGV_MAPERR;
1164 break;
1165 }
1166 info._sifields._sigfault._addr = env->nip - 4;
1167 queue_signal(env, info.si_signo, &info);
1168 break;
1169 case POWERPC_EXCP_EXTERNAL: /* External input */
1170 cpu_abort(env, "External interrupt while in user mode. "
1171 "Aborting\n");
1172 break;
1173 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1174 EXCP_DUMP(env, "Unaligned memory access\n");
1175 /* XXX: check this */
1176 info.si_signo = TARGET_SIGBUS;
1177 info.si_errno = 0;
1178 info.si_code = TARGET_BUS_ADRALN;
1179 info._sifields._sigfault._addr = env->nip - 4;
1180 queue_signal(env, info.si_signo, &info);
1181 break;
1182 case POWERPC_EXCP_PROGRAM: /* Program exception */
1183 /* XXX: check this */
1184 switch (env->error_code & ~0xF) {
1185 case POWERPC_EXCP_FP:
1186 EXCP_DUMP(env, "Floating point program exception\n");
1187 info.si_signo = TARGET_SIGFPE;
1188 info.si_errno = 0;
1189 switch (env->error_code & 0xF) {
1190 case POWERPC_EXCP_FP_OX:
1191 info.si_code = TARGET_FPE_FLTOVF;
1192 break;
1193 case POWERPC_EXCP_FP_UX:
1194 info.si_code = TARGET_FPE_FLTUND;
1195 break;
1196 case POWERPC_EXCP_FP_ZX:
1197 case POWERPC_EXCP_FP_VXZDZ:
1198 info.si_code = TARGET_FPE_FLTDIV;
1199 break;
1200 case POWERPC_EXCP_FP_XX:
1201 info.si_code = TARGET_FPE_FLTRES;
1202 break;
1203 case POWERPC_EXCP_FP_VXSOFT:
1204 info.si_code = TARGET_FPE_FLTINV;
1205 break;
1206 case POWERPC_EXCP_FP_VXSNAN:
1207 case POWERPC_EXCP_FP_VXISI:
1208 case POWERPC_EXCP_FP_VXIDI:
1209 case POWERPC_EXCP_FP_VXIMZ:
1210 case POWERPC_EXCP_FP_VXVC:
1211 case POWERPC_EXCP_FP_VXSQRT:
1212 case POWERPC_EXCP_FP_VXCVI:
1213 info.si_code = TARGET_FPE_FLTSUB;
1214 break;
1215 default:
1216 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1217 env->error_code);
1218 break;
1219 }
1220 break;
1221 case POWERPC_EXCP_INVAL:
1222 EXCP_DUMP(env, "Invalid instruction\n");
1223 info.si_signo = TARGET_SIGILL;
1224 info.si_errno = 0;
1225 switch (env->error_code & 0xF) {
1226 case POWERPC_EXCP_INVAL_INVAL:
1227 info.si_code = TARGET_ILL_ILLOPC;
1228 break;
1229 case POWERPC_EXCP_INVAL_LSWX:
1230 info.si_code = TARGET_ILL_ILLOPN;
1231 break;
1232 case POWERPC_EXCP_INVAL_SPR:
1233 info.si_code = TARGET_ILL_PRVREG;
1234 break;
1235 case POWERPC_EXCP_INVAL_FP:
1236 info.si_code = TARGET_ILL_COPROC;
1237 break;
1238 default:
1239 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1240 env->error_code & 0xF);
1241 info.si_code = TARGET_ILL_ILLADR;
1242 break;
1243 }
1244 break;
1245 case POWERPC_EXCP_PRIV:
1246 EXCP_DUMP(env, "Privilege violation\n");
1247 info.si_signo = TARGET_SIGILL;
1248 info.si_errno = 0;
1249 switch (env->error_code & 0xF) {
1250 case POWERPC_EXCP_PRIV_OPC:
1251 info.si_code = TARGET_ILL_PRVOPC;
1252 break;
1253 case POWERPC_EXCP_PRIV_REG:
1254 info.si_code = TARGET_ILL_PRVREG;
1255 break;
1256 default:
1257 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1258 env->error_code & 0xF);
1259 info.si_code = TARGET_ILL_PRVOPC;
1260 break;
1261 }
1262 break;
1263 case POWERPC_EXCP_TRAP:
1264 cpu_abort(env, "Tried to call a TRAP\n");
1265 break;
1266 default:
1267 /* Should not happen ! */
1268 cpu_abort(env, "Unknown program exception (%02x)\n",
1269 env->error_code);
1270 break;
1271 }
1272 info._sifields._sigfault._addr = env->nip - 4;
1273 queue_signal(env, info.si_signo, &info);
1274 break;
1275 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1276 EXCP_DUMP(env, "No floating point allowed\n");
1277 info.si_signo = TARGET_SIGILL;
1278 info.si_errno = 0;
1279 info.si_code = TARGET_ILL_COPROC;
1280 info._sifields._sigfault._addr = env->nip - 4;
1281 queue_signal(env, info.si_signo, &info);
1282 break;
1283 case POWERPC_EXCP_SYSCALL: /* System call exception */
1284 cpu_abort(env, "Syscall exception while in user mode. "
1285 "Aborting\n");
1286 break;
1287 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1288 EXCP_DUMP(env, "No APU instruction allowed\n");
1289 info.si_signo = TARGET_SIGILL;
1290 info.si_errno = 0;
1291 info.si_code = TARGET_ILL_COPROC;
1292 info._sifields._sigfault._addr = env->nip - 4;
1293 queue_signal(env, info.si_signo, &info);
1294 break;
1295 case POWERPC_EXCP_DECR: /* Decrementer exception */
1296 cpu_abort(env, "Decrementer interrupt while in user mode. "
1297 "Aborting\n");
1298 break;
1299 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1300 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1301 "Aborting\n");
1302 break;
1303 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1304 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1305 "Aborting\n");
1306 break;
1307 case POWERPC_EXCP_DTLB: /* Data TLB error */
1308 cpu_abort(env, "Data TLB exception while in user mode. "
1309 "Aborting\n");
1310 break;
1311 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1312 cpu_abort(env, "Instruction TLB exception while in user mode. "
1313 "Aborting\n");
1314 break;
1315 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1316 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1317 info.si_signo = TARGET_SIGILL;
1318 info.si_errno = 0;
1319 info.si_code = TARGET_ILL_COPROC;
1320 info._sifields._sigfault._addr = env->nip - 4;
1321 queue_signal(env, info.si_signo, &info);
1322 break;
1323 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1324 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1325 break;
1326 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1327 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1328 break;
1329 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1330 cpu_abort(env, "Performance monitor exception not handled\n");
1331 break;
1332 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1333 cpu_abort(env, "Doorbell interrupt while in user mode. "
1334 "Aborting\n");
1335 break;
1336 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1337 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1338 "Aborting\n");
1339 break;
1340 case POWERPC_EXCP_RESET: /* System reset exception */
1341 cpu_abort(env, "Reset interrupt while in user mode. "
1342 "Aborting\n");
1343 break;
1344 case POWERPC_EXCP_DSEG: /* Data segment exception */
1345 cpu_abort(env, "Data segment exception while in user mode. "
1346 "Aborting\n");
1347 break;
1348 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1349 cpu_abort(env, "Instruction segment exception "
1350 "while in user mode. Aborting\n");
1351 break;
1352 /* PowerPC 64 with hypervisor mode support */
1353 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1354 cpu_abort(env, "Hypervisor decrementer interrupt "
1355 "while in user mode. Aborting\n");
1356 break;
1357 case POWERPC_EXCP_TRACE: /* Trace exception */
1358 /* Nothing to do:
1359 * we use this exception to emulate step-by-step execution mode.
1360 */
1361 break;
1362 /* PowerPC 64 with hypervisor mode support */
1363 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1364 cpu_abort(env, "Hypervisor data storage exception "
1365 "while in user mode. Aborting\n");
1366 break;
1367 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1368 cpu_abort(env, "Hypervisor instruction storage exception "
1369 "while in user mode. Aborting\n");
1370 break;
1371 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1372 cpu_abort(env, "Hypervisor data segment exception "
1373 "while in user mode. Aborting\n");
1374 break;
1375 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1376 cpu_abort(env, "Hypervisor instruction segment exception "
1377 "while in user mode. Aborting\n");
1378 break;
1379 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1380 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1381 info.si_signo = TARGET_SIGILL;
1382 info.si_errno = 0;
1383 info.si_code = TARGET_ILL_COPROC;
1384 info._sifields._sigfault._addr = env->nip - 4;
1385 queue_signal(env, info.si_signo, &info);
1386 break;
1387 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1388 cpu_abort(env, "Programable interval timer interrupt "
1389 "while in user mode. Aborting\n");
1390 break;
1391 case POWERPC_EXCP_IO: /* IO error exception */
1392 cpu_abort(env, "IO error exception while in user mode. "
1393 "Aborting\n");
1394 break;
1395 case POWERPC_EXCP_RUNM: /* Run mode exception */
1396 cpu_abort(env, "Run mode exception while in user mode. "
1397 "Aborting\n");
1398 break;
1399 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1400 cpu_abort(env, "Emulation trap exception not handled\n");
1401 break;
1402 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1403 cpu_abort(env, "Instruction fetch TLB exception "
1404 "while in user-mode. Aborting");
1405 break;
1406 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1407 cpu_abort(env, "Data load TLB exception while in user-mode. "
1408 "Aborting");
1409 break;
1410 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1411 cpu_abort(env, "Data store TLB exception while in user-mode. "
1412 "Aborting");
1413 break;
1414 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1415 cpu_abort(env, "Floating-point assist exception not handled\n");
1416 break;
1417 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1418 cpu_abort(env, "Instruction address breakpoint exception "
1419 "not handled\n");
1420 break;
1421 case POWERPC_EXCP_SMI: /* System management interrupt */
1422 cpu_abort(env, "System management interrupt while in user mode. "
1423 "Aborting\n");
1424 break;
1425 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1426 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1427 "Aborting\n");
1428 break;
1429 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1430 cpu_abort(env, "Performance monitor exception not handled\n");
1431 break;
1432 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1433 cpu_abort(env, "Vector assist exception not handled\n");
1434 break;
1435 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1436 cpu_abort(env, "Soft patch exception not handled\n");
1437 break;
1438 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1439 cpu_abort(env, "Maintenance exception while in user mode. "
1440 "Aborting\n");
1441 break;
1442 case POWERPC_EXCP_STOP: /* stop translation */
1443 /* We did invalidate the instruction cache. Go on */
1444 break;
1445 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1446 /* We just stopped because of a branch. Go on */
1447 break;
1448 case POWERPC_EXCP_SYSCALL_USER:
1449 /* system call in user-mode emulation */
1450 /* WARNING:
1451 * PPC ABI uses overflow flag in cr0 to signal an error
1452 * in syscalls.
1453 */
1454 #if 0
1455 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1456 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1457 #endif
1458 env->crf[0] &= ~0x1;
1459 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1460 env->gpr[5], env->gpr[6], env->gpr[7],
1461 env->gpr[8]);
1462 if (ret > (uint32_t)(-515)) {
1463 env->crf[0] |= 0x1;
1464 ret = -ret;
1465 }
1466 env->gpr[3] = ret;
1467 #if 0
1468 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1469 #endif
1470 break;
1471 case EXCP_DEBUG:
1472 {
1473 int sig;
1474
1475 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1476 if (sig) {
1477 info.si_signo = sig;
1478 info.si_errno = 0;
1479 info.si_code = TARGET_TRAP_BRKPT;
1480 queue_signal(env, info.si_signo, &info);
1481 }
1482 }
1483 break;
1484 case EXCP_INTERRUPT:
1485 /* just indicate that signals should be handled asap */
1486 break;
1487 default:
1488 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1489 break;
1490 }
1491 process_pending_signals(env);
1492 }
1493 }
1494 #endif
1495
1496 #ifdef TARGET_MIPS
1497
1498 #define MIPS_SYS(name, args) args,
1499
1500 static const uint8_t mips_syscall_args[] = {
1501 MIPS_SYS(sys_syscall , 0) /* 4000 */
1502 MIPS_SYS(sys_exit , 1)
1503 MIPS_SYS(sys_fork , 0)
1504 MIPS_SYS(sys_read , 3)
1505 MIPS_SYS(sys_write , 3)
1506 MIPS_SYS(sys_open , 3) /* 4005 */
1507 MIPS_SYS(sys_close , 1)
1508 MIPS_SYS(sys_waitpid , 3)
1509 MIPS_SYS(sys_creat , 2)
1510 MIPS_SYS(sys_link , 2)
1511 MIPS_SYS(sys_unlink , 1) /* 4010 */
1512 MIPS_SYS(sys_execve , 0)
1513 MIPS_SYS(sys_chdir , 1)
1514 MIPS_SYS(sys_time , 1)
1515 MIPS_SYS(sys_mknod , 3)
1516 MIPS_SYS(sys_chmod , 2) /* 4015 */
1517 MIPS_SYS(sys_lchown , 3)
1518 MIPS_SYS(sys_ni_syscall , 0)
1519 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1520 MIPS_SYS(sys_lseek , 3)
1521 MIPS_SYS(sys_getpid , 0) /* 4020 */
1522 MIPS_SYS(sys_mount , 5)
1523 MIPS_SYS(sys_oldumount , 1)
1524 MIPS_SYS(sys_setuid , 1)
1525 MIPS_SYS(sys_getuid , 0)
1526 MIPS_SYS(sys_stime , 1) /* 4025 */
1527 MIPS_SYS(sys_ptrace , 4)
1528 MIPS_SYS(sys_alarm , 1)
1529 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1530 MIPS_SYS(sys_pause , 0)
1531 MIPS_SYS(sys_utime , 2) /* 4030 */
1532 MIPS_SYS(sys_ni_syscall , 0)
1533 MIPS_SYS(sys_ni_syscall , 0)
1534 MIPS_SYS(sys_access , 2)
1535 MIPS_SYS(sys_nice , 1)
1536 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1537 MIPS_SYS(sys_sync , 0)
1538 MIPS_SYS(sys_kill , 2)
1539 MIPS_SYS(sys_rename , 2)
1540 MIPS_SYS(sys_mkdir , 2)
1541 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1542 MIPS_SYS(sys_dup , 1)
1543 MIPS_SYS(sys_pipe , 0)
1544 MIPS_SYS(sys_times , 1)
1545 MIPS_SYS(sys_ni_syscall , 0)
1546 MIPS_SYS(sys_brk , 1) /* 4045 */
1547 MIPS_SYS(sys_setgid , 1)
1548 MIPS_SYS(sys_getgid , 0)
1549 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1550 MIPS_SYS(sys_geteuid , 0)
1551 MIPS_SYS(sys_getegid , 0) /* 4050 */
1552 MIPS_SYS(sys_acct , 0)
1553 MIPS_SYS(sys_umount , 2)
1554 MIPS_SYS(sys_ni_syscall , 0)
1555 MIPS_SYS(sys_ioctl , 3)
1556 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1557 MIPS_SYS(sys_ni_syscall , 2)
1558 MIPS_SYS(sys_setpgid , 2)
1559 MIPS_SYS(sys_ni_syscall , 0)
1560 MIPS_SYS(sys_olduname , 1)
1561 MIPS_SYS(sys_umask , 1) /* 4060 */
1562 MIPS_SYS(sys_chroot , 1)
1563 MIPS_SYS(sys_ustat , 2)
1564 MIPS_SYS(sys_dup2 , 2)
1565 MIPS_SYS(sys_getppid , 0)
1566 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1567 MIPS_SYS(sys_setsid , 0)
1568 MIPS_SYS(sys_sigaction , 3)
1569 MIPS_SYS(sys_sgetmask , 0)
1570 MIPS_SYS(sys_ssetmask , 1)
1571 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1572 MIPS_SYS(sys_setregid , 2)
1573 MIPS_SYS(sys_sigsuspend , 0)
1574 MIPS_SYS(sys_sigpending , 1)
1575 MIPS_SYS(sys_sethostname , 2)
1576 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1577 MIPS_SYS(sys_getrlimit , 2)
1578 MIPS_SYS(sys_getrusage , 2)
1579 MIPS_SYS(sys_gettimeofday, 2)
1580 MIPS_SYS(sys_settimeofday, 2)
1581 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1582 MIPS_SYS(sys_setgroups , 2)
1583 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1584 MIPS_SYS(sys_symlink , 2)
1585 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1586 MIPS_SYS(sys_readlink , 3) /* 4085 */
1587 MIPS_SYS(sys_uselib , 1)
1588 MIPS_SYS(sys_swapon , 2)
1589 MIPS_SYS(sys_reboot , 3)
1590 MIPS_SYS(old_readdir , 3)
1591 MIPS_SYS(old_mmap , 6) /* 4090 */
1592 MIPS_SYS(sys_munmap , 2)
1593 MIPS_SYS(sys_truncate , 2)
1594 MIPS_SYS(sys_ftruncate , 2)
1595 MIPS_SYS(sys_fchmod , 2)
1596 MIPS_SYS(sys_fchown , 3) /* 4095 */
1597 MIPS_SYS(sys_getpriority , 2)
1598 MIPS_SYS(sys_setpriority , 3)
1599 MIPS_SYS(sys_ni_syscall , 0)
1600 MIPS_SYS(sys_statfs , 2)
1601 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1602 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1603 MIPS_SYS(sys_socketcall , 2)
1604 MIPS_SYS(sys_syslog , 3)
1605 MIPS_SYS(sys_setitimer , 3)
1606 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1607 MIPS_SYS(sys_newstat , 2)
1608 MIPS_SYS(sys_newlstat , 2)
1609 MIPS_SYS(sys_newfstat , 2)
1610 MIPS_SYS(sys_uname , 1)
1611 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1612 MIPS_SYS(sys_vhangup , 0)
1613 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1614 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1615 MIPS_SYS(sys_wait4 , 4)
1616 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1617 MIPS_SYS(sys_sysinfo , 1)
1618 MIPS_SYS(sys_ipc , 6)
1619 MIPS_SYS(sys_fsync , 1)
1620 MIPS_SYS(sys_sigreturn , 0)
1621 MIPS_SYS(sys_clone , 0) /* 4120 */
1622 MIPS_SYS(sys_setdomainname, 2)
1623 MIPS_SYS(sys_newuname , 1)
1624 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1625 MIPS_SYS(sys_adjtimex , 1)
1626 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1627 MIPS_SYS(sys_sigprocmask , 3)
1628 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1629 MIPS_SYS(sys_init_module , 5)
1630 MIPS_SYS(sys_delete_module, 1)
1631 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1632 MIPS_SYS(sys_quotactl , 0)
1633 MIPS_SYS(sys_getpgid , 1)
1634 MIPS_SYS(sys_fchdir , 1)
1635 MIPS_SYS(sys_bdflush , 2)
1636 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1637 MIPS_SYS(sys_personality , 1)
1638 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1639 MIPS_SYS(sys_setfsuid , 1)
1640 MIPS_SYS(sys_setfsgid , 1)
1641 MIPS_SYS(sys_llseek , 5) /* 4140 */
1642 MIPS_SYS(sys_getdents , 3)
1643 MIPS_SYS(sys_select , 5)
1644 MIPS_SYS(sys_flock , 2)
1645 MIPS_SYS(sys_msync , 3)
1646 MIPS_SYS(sys_readv , 3) /* 4145 */
1647 MIPS_SYS(sys_writev , 3)
1648 MIPS_SYS(sys_cacheflush , 3)
1649 MIPS_SYS(sys_cachectl , 3)
1650 MIPS_SYS(sys_sysmips , 4)
1651 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1652 MIPS_SYS(sys_getsid , 1)
1653 MIPS_SYS(sys_fdatasync , 0)
1654 MIPS_SYS(sys_sysctl , 1)
1655 MIPS_SYS(sys_mlock , 2)
1656 MIPS_SYS(sys_munlock , 2) /* 4155 */
1657 MIPS_SYS(sys_mlockall , 1)
1658 MIPS_SYS(sys_munlockall , 0)
1659 MIPS_SYS(sys_sched_setparam, 2)
1660 MIPS_SYS(sys_sched_getparam, 2)
1661 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1662 MIPS_SYS(sys_sched_getscheduler, 1)
1663 MIPS_SYS(sys_sched_yield , 0)
1664 MIPS_SYS(sys_sched_get_priority_max, 1)
1665 MIPS_SYS(sys_sched_get_priority_min, 1)
1666 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1667 MIPS_SYS(sys_nanosleep, 2)
1668 MIPS_SYS(sys_mremap , 4)
1669 MIPS_SYS(sys_accept , 3)
1670 MIPS_SYS(sys_bind , 3)
1671 MIPS_SYS(sys_connect , 3) /* 4170 */
1672 MIPS_SYS(sys_getpeername , 3)
1673 MIPS_SYS(sys_getsockname , 3)
1674 MIPS_SYS(sys_getsockopt , 5)
1675 MIPS_SYS(sys_listen , 2)
1676 MIPS_SYS(sys_recv , 4) /* 4175 */
1677 MIPS_SYS(sys_recvfrom , 6)
1678 MIPS_SYS(sys_recvmsg , 3)
1679 MIPS_SYS(sys_send , 4)
1680 MIPS_SYS(sys_sendmsg , 3)
1681 MIPS_SYS(sys_sendto , 6) /* 4180 */
1682 MIPS_SYS(sys_setsockopt , 5)
1683 MIPS_SYS(sys_shutdown , 2)
1684 MIPS_SYS(sys_socket , 3)
1685 MIPS_SYS(sys_socketpair , 4)
1686 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1687 MIPS_SYS(sys_getresuid , 3)
1688 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1689 MIPS_SYS(sys_poll , 3)
1690 MIPS_SYS(sys_nfsservctl , 3)
1691 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1692 MIPS_SYS(sys_getresgid , 3)
1693 MIPS_SYS(sys_prctl , 5)
1694 MIPS_SYS(sys_rt_sigreturn, 0)
1695 MIPS_SYS(sys_rt_sigaction, 4)
1696 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1697 MIPS_SYS(sys_rt_sigpending, 2)
1698 MIPS_SYS(sys_rt_sigtimedwait, 4)
1699 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1700 MIPS_SYS(sys_rt_sigsuspend, 0)
1701 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1702 MIPS_SYS(sys_pwrite64 , 6)
1703 MIPS_SYS(sys_chown , 3)
1704 MIPS_SYS(sys_getcwd , 2)
1705 MIPS_SYS(sys_capget , 2)
1706 MIPS_SYS(sys_capset , 2) /* 4205 */
1707 MIPS_SYS(sys_sigaltstack , 0)
1708 MIPS_SYS(sys_sendfile , 4)
1709 MIPS_SYS(sys_ni_syscall , 0)
1710 MIPS_SYS(sys_ni_syscall , 0)
1711 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1712 MIPS_SYS(sys_truncate64 , 4)
1713 MIPS_SYS(sys_ftruncate64 , 4)
1714 MIPS_SYS(sys_stat64 , 2)
1715 MIPS_SYS(sys_lstat64 , 2)
1716 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1717 MIPS_SYS(sys_pivot_root , 2)
1718 MIPS_SYS(sys_mincore , 3)
1719 MIPS_SYS(sys_madvise , 3)
1720 MIPS_SYS(sys_getdents64 , 3)
1721 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1722 MIPS_SYS(sys_ni_syscall , 0)
1723 MIPS_SYS(sys_gettid , 0)
1724 MIPS_SYS(sys_readahead , 5)
1725 MIPS_SYS(sys_setxattr , 5)
1726 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1727 MIPS_SYS(sys_fsetxattr , 5)
1728 MIPS_SYS(sys_getxattr , 4)
1729 MIPS_SYS(sys_lgetxattr , 4)
1730 MIPS_SYS(sys_fgetxattr , 4)
1731 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1732 MIPS_SYS(sys_llistxattr , 3)
1733 MIPS_SYS(sys_flistxattr , 3)
1734 MIPS_SYS(sys_removexattr , 2)
1735 MIPS_SYS(sys_lremovexattr, 2)
1736 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1737 MIPS_SYS(sys_tkill , 2)
1738 MIPS_SYS(sys_sendfile64 , 5)
1739 MIPS_SYS(sys_futex , 2)
1740 MIPS_SYS(sys_sched_setaffinity, 3)
1741 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1742 MIPS_SYS(sys_io_setup , 2)
1743 MIPS_SYS(sys_io_destroy , 1)
1744 MIPS_SYS(sys_io_getevents, 5)
1745 MIPS_SYS(sys_io_submit , 3)
1746 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1747 MIPS_SYS(sys_exit_group , 1)
1748 MIPS_SYS(sys_lookup_dcookie, 3)
1749 MIPS_SYS(sys_epoll_create, 1)
1750 MIPS_SYS(sys_epoll_ctl , 4)
1751 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1752 MIPS_SYS(sys_remap_file_pages, 5)
1753 MIPS_SYS(sys_set_tid_address, 1)
1754 MIPS_SYS(sys_restart_syscall, 0)
1755 MIPS_SYS(sys_fadvise64_64, 7)
1756 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1757 MIPS_SYS(sys_fstatfs64 , 2)
1758 MIPS_SYS(sys_timer_create, 3)
1759 MIPS_SYS(sys_timer_settime, 4)
1760 MIPS_SYS(sys_timer_gettime, 2)
1761 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1762 MIPS_SYS(sys_timer_delete, 1)
1763 MIPS_SYS(sys_clock_settime, 2)
1764 MIPS_SYS(sys_clock_gettime, 2)
1765 MIPS_SYS(sys_clock_getres, 2)
1766 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1767 MIPS_SYS(sys_tgkill , 3)
1768 MIPS_SYS(sys_utimes , 2)
1769 MIPS_SYS(sys_mbind , 4)
1770 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1771 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1772 MIPS_SYS(sys_mq_open , 4)
1773 MIPS_SYS(sys_mq_unlink , 1)
1774 MIPS_SYS(sys_mq_timedsend, 5)
1775 MIPS_SYS(sys_mq_timedreceive, 5)
1776 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1777 MIPS_SYS(sys_mq_getsetattr, 3)
1778 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1779 MIPS_SYS(sys_waitid , 4)
1780 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1781 MIPS_SYS(sys_add_key , 5)
1782 MIPS_SYS(sys_request_key, 4)
1783 MIPS_SYS(sys_keyctl , 5)
1784 MIPS_SYS(sys_set_thread_area, 1)
1785 MIPS_SYS(sys_inotify_init, 0)
1786 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1787 MIPS_SYS(sys_inotify_rm_watch, 2)
1788 MIPS_SYS(sys_migrate_pages, 4)
1789 MIPS_SYS(sys_openat, 4)
1790 MIPS_SYS(sys_mkdirat, 3)
1791 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1792 MIPS_SYS(sys_fchownat, 5)
1793 MIPS_SYS(sys_futimesat, 3)
1794 MIPS_SYS(sys_fstatat64, 4)
1795 MIPS_SYS(sys_unlinkat, 3)
1796 MIPS_SYS(sys_renameat, 4) /* 4295 */
1797 MIPS_SYS(sys_linkat, 5)
1798 MIPS_SYS(sys_symlinkat, 3)
1799 MIPS_SYS(sys_readlinkat, 4)
1800 MIPS_SYS(sys_fchmodat, 3)
1801 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1802 MIPS_SYS(sys_pselect6, 6)
1803 MIPS_SYS(sys_ppoll, 5)
1804 MIPS_SYS(sys_unshare, 1)
1805 MIPS_SYS(sys_splice, 4)
1806 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1807 MIPS_SYS(sys_tee, 4)
1808 MIPS_SYS(sys_vmsplice, 4)
1809 MIPS_SYS(sys_move_pages, 6)
1810 MIPS_SYS(sys_set_robust_list, 2)
1811 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1812 MIPS_SYS(sys_kexec_load, 4)
1813 MIPS_SYS(sys_getcpu, 3)
1814 MIPS_SYS(sys_epoll_pwait, 6)
1815 MIPS_SYS(sys_ioprio_set, 3)
1816 MIPS_SYS(sys_ioprio_get, 2)
1817 };
1818
1819 #undef MIPS_SYS
1820
1821 void cpu_loop(CPUMIPSState *env)
1822 {
1823 target_siginfo_t info;
1824 int trapnr, ret;
1825 unsigned int syscall_num;
1826
1827 for(;;) {
1828 trapnr = cpu_mips_exec(env);
1829 switch(trapnr) {
1830 case EXCP_SYSCALL:
1831 syscall_num = env->active_tc.gpr[2] - 4000;
1832 env->active_tc.PC += 4;
1833 if (syscall_num >= sizeof(mips_syscall_args)) {
1834 ret = -ENOSYS;
1835 } else {
1836 int nb_args;
1837 abi_ulong sp_reg;
1838 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1839
1840 nb_args = mips_syscall_args[syscall_num];
1841 sp_reg = env->active_tc.gpr[29];
1842 switch (nb_args) {
1843 /* these arguments are taken from the stack */
1844 /* FIXME - what to do if get_user() fails? */
1845 case 8: get_user_ual(arg8, sp_reg + 28);
1846 case 7: get_user_ual(arg7, sp_reg + 24);
1847 case 6: get_user_ual(arg6, sp_reg + 20);
1848 case 5: get_user_ual(arg5, sp_reg + 16);
1849 default:
1850 break;
1851 }
1852 ret = do_syscall(env, env->active_tc.gpr[2],
1853 env->active_tc.gpr[4],
1854 env->active_tc.gpr[5],
1855 env->active_tc.gpr[6],
1856 env->active_tc.gpr[7],
1857 arg5, arg6/*, arg7, arg8*/);
1858 }
1859 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1860 env->active_tc.gpr[7] = 1; /* error flag */
1861 ret = -ret;
1862 } else {
1863 env->active_tc.gpr[7] = 0; /* error flag */
1864 }
1865 env->active_tc.gpr[2] = ret;
1866 break;
1867 case EXCP_TLBL:
1868 case EXCP_TLBS:
1869 case EXCP_CpU:
1870 case EXCP_RI:
1871 info.si_signo = TARGET_SIGILL;
1872 info.si_errno = 0;
1873 info.si_code = 0;
1874 queue_signal(env, info.si_signo, &info);
1875 break;
1876 case EXCP_INTERRUPT:
1877 /* just indicate that signals should be handled asap */
1878 break;
1879 case EXCP_DEBUG:
1880 {
1881 int sig;
1882
1883 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1884 if (sig)
1885 {
1886 info.si_signo = sig;
1887 info.si_errno = 0;
1888 info.si_code = TARGET_TRAP_BRKPT;
1889 queue_signal(env, info.si_signo, &info);
1890 }
1891 }
1892 break;
1893 default:
1894 // error:
1895 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1896 trapnr);
1897 cpu_dump_state(env, stderr, fprintf, 0);
1898 abort();
1899 }
1900 process_pending_signals(env);
1901 }
1902 }
1903 #endif
1904
1905 #ifdef TARGET_SH4
1906 void cpu_loop (CPUState *env)
1907 {
1908 int trapnr, ret;
1909 target_siginfo_t info;
1910
1911 while (1) {
1912 trapnr = cpu_sh4_exec (env);
1913
1914 switch (trapnr) {
1915 case 0x160:
1916 env->pc += 2;
1917 ret = do_syscall(env,
1918 env->gregs[3],
1919 env->gregs[4],
1920 env->gregs[5],
1921 env->gregs[6],
1922 env->gregs[7],
1923 env->gregs[0],
1924 env->gregs[1]);
1925 env->gregs[0] = ret;
1926 break;
1927 case EXCP_INTERRUPT:
1928 /* just indicate that signals should be handled asap */
1929 break;
1930 case EXCP_DEBUG:
1931 {
1932 int sig;
1933
1934 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1935 if (sig)
1936 {
1937 info.si_signo = sig;
1938 info.si_errno = 0;
1939 info.si_code = TARGET_TRAP_BRKPT;
1940 queue_signal(env, info.si_signo, &info);
1941 }
1942 }
1943 break;
1944 case 0xa0:
1945 case 0xc0:
1946 info.si_signo = SIGSEGV;
1947 info.si_errno = 0;
1948 info.si_code = TARGET_SEGV_MAPERR;
1949 info._sifields._sigfault._addr = env->tea;
1950 queue_signal(env, info.si_signo, &info);
1951 break;
1952
1953 default:
1954 printf ("Unhandled trap: 0x%x\n", trapnr);
1955 cpu_dump_state(env, stderr, fprintf, 0);
1956 exit (1);
1957 }
1958 process_pending_signals (env);
1959 }
1960 }
1961 #endif
1962
1963 #ifdef TARGET_CRIS
1964 void cpu_loop (CPUState *env)
1965 {
1966 int trapnr, ret;
1967 target_siginfo_t info;
1968
1969 while (1) {
1970 trapnr = cpu_cris_exec (env);
1971 switch (trapnr) {
1972 case 0xaa:
1973 {
1974 info.si_signo = SIGSEGV;
1975 info.si_errno = 0;
1976 /* XXX: check env->error_code */
1977 info.si_code = TARGET_SEGV_MAPERR;
1978 info._sifields._sigfault._addr = env->pregs[PR_EDA];
1979 queue_signal(env, info.si_signo, &info);
1980 }
1981 break;
1982 case EXCP_INTERRUPT:
1983 /* just indicate that signals should be handled asap */
1984 break;
1985 case EXCP_BREAK:
1986 ret = do_syscall(env,
1987 env->regs[9],
1988 env->regs[10],
1989 env->regs[11],
1990 env->regs[12],
1991 env->regs[13],
1992 env->pregs[7],
1993 env->pregs[11]);
1994 env->regs[10] = ret;
1995 break;
1996 case EXCP_DEBUG:
1997 {
1998 int sig;
1999
2000 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2001 if (sig)
2002 {
2003 info.si_signo = sig;
2004 info.si_errno = 0;
2005 info.si_code = TARGET_TRAP_BRKPT;
2006 queue_signal(env, info.si_signo, &info);
2007 }
2008 }
2009 break;
2010 default:
2011 printf ("Unhandled trap: 0x%x\n", trapnr);
2012 cpu_dump_state(env, stderr, fprintf, 0);
2013 exit (1);
2014 }
2015 process_pending_signals (env);
2016 }
2017 }
2018 #endif
2019
2020 #ifdef TARGET_M68K
2021
2022 void cpu_loop(CPUM68KState *env)
2023 {
2024 int trapnr;
2025 unsigned int n;
2026 target_siginfo_t info;
2027 TaskState *ts = env->opaque;
2028
2029 for(;;) {
2030 trapnr = cpu_m68k_exec(env);
2031 switch(trapnr) {
2032 case EXCP_ILLEGAL:
2033 {
2034 if (ts->sim_syscalls) {
2035 uint16_t nr;
2036 nr = lduw(env->pc + 2);
2037 env->pc += 4;
2038 do_m68k_simcall(env, nr);
2039 } else {
2040 goto do_sigill;
2041 }
2042 }
2043 break;
2044 case EXCP_HALT_INSN:
2045 /* Semihosing syscall. */
2046 env->pc += 4;
2047 do_m68k_semihosting(env, env->dregs[0]);
2048 break;
2049 case EXCP_LINEA:
2050 case EXCP_LINEF:
2051 case EXCP_UNSUPPORTED:
2052 do_sigill:
2053 info.si_signo = SIGILL;
2054 info.si_errno = 0;
2055 info.si_code = TARGET_ILL_ILLOPN;
2056 info._sifields._sigfault._addr = env->pc;
2057 queue_signal(env, info.si_signo, &info);
2058 break;
2059 case EXCP_TRAP0:
2060 {
2061 ts->sim_syscalls = 0;
2062 n = env->dregs[0];
2063 env->pc += 2;
2064 env->dregs[0] = do_syscall(env,
2065 n,
2066 env->dregs[1],
2067 env->dregs[2],
2068 env->dregs[3],
2069 env->dregs[4],
2070 env->dregs[5],
2071 env->aregs[0]);
2072 }
2073 break;
2074 case EXCP_INTERRUPT:
2075 /* just indicate that signals should be handled asap */
2076 break;
2077 case EXCP_ACCESS:
2078 {
2079 info.si_signo = SIGSEGV;
2080 info.si_errno = 0;
2081 /* XXX: check env->error_code */
2082 info.si_code = TARGET_SEGV_MAPERR;
2083 info._sifields._sigfault._addr = env->mmu.ar;
2084 queue_signal(env, info.si_signo, &info);
2085 }
2086 break;
2087 case EXCP_DEBUG:
2088 {
2089 int sig;
2090
2091 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2092 if (sig)
2093 {
2094 info.si_signo = sig;
2095 info.si_errno = 0;
2096 info.si_code = TARGET_TRAP_BRKPT;
2097 queue_signal(env, info.si_signo, &info);
2098 }
2099 }
2100 break;
2101 default:
2102 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2103 trapnr);
2104 cpu_dump_state(env, stderr, fprintf, 0);
2105 abort();
2106 }
2107 process_pending_signals(env);
2108 }
2109 }
2110 #endif /* TARGET_M68K */
2111
2112 #ifdef TARGET_ALPHA
2113 void cpu_loop (CPUState *env)
2114 {
2115 int trapnr;
2116 target_siginfo_t info;
2117
2118 while (1) {
2119 trapnr = cpu_alpha_exec (env);
2120
2121 switch (trapnr) {
2122 case EXCP_RESET:
2123 fprintf(stderr, "Reset requested. Exit\n");
2124 exit(1);
2125 break;
2126 case EXCP_MCHK:
2127 fprintf(stderr, "Machine check exception. Exit\n");
2128 exit(1);
2129 break;
2130 case EXCP_ARITH:
2131 fprintf(stderr, "Arithmetic trap.\n");
2132 exit(1);
2133 break;
2134 case EXCP_HW_INTERRUPT:
2135 fprintf(stderr, "External interrupt. Exit\n");
2136 exit(1);
2137 break;
2138 case EXCP_DFAULT:
2139 fprintf(stderr, "MMU data fault\n");
2140 exit(1);
2141 break;
2142 case EXCP_DTB_MISS_PAL:
2143 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2144 exit(1);
2145 break;
2146 case EXCP_ITB_MISS:
2147 fprintf(stderr, "MMU instruction TLB miss\n");
2148 exit(1);
2149 break;
2150 case EXCP_ITB_ACV:
2151 fprintf(stderr, "MMU instruction access violation\n");
2152 exit(1);
2153 break;
2154 case EXCP_DTB_MISS_NATIVE:
2155 fprintf(stderr, "MMU data TLB miss\n");
2156 exit(1);
2157 break;
2158 case EXCP_UNALIGN:
2159 fprintf(stderr, "Unaligned access\n");
2160 exit(1);
2161 break;
2162 case EXCP_OPCDEC:
2163 fprintf(stderr, "Invalid instruction\n");
2164 exit(1);
2165 break;
2166 case EXCP_FEN:
2167 fprintf(stderr, "Floating-point not allowed\n");
2168 exit(1);
2169 break;
2170 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2171 call_pal(env, (trapnr >> 6) | 0x80);
2172 break;
2173 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2174 fprintf(stderr, "Privileged call to PALcode\n");
2175 exit(1);
2176 break;
2177 case EXCP_DEBUG:
2178 {
2179 int sig;
2180
2181 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2182 if (sig)
2183 {
2184 info.si_signo = sig;
2185 info.si_errno = 0;
2186 info.si_code = TARGET_TRAP_BRKPT;
2187 queue_signal(env, info.si_signo, &info);
2188 }
2189 }
2190 break;
2191 default:
2192 printf ("Unhandled trap: 0x%x\n", trapnr);
2193 cpu_dump_state(env, stderr, fprintf, 0);
2194 exit (1);
2195 }
2196 process_pending_signals (env);
2197 }
2198 }
2199 #endif /* TARGET_ALPHA */
2200
2201 static void usage(void)
2202 {
2203 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2204 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2205 "Linux CPU emulator (compiled for %s emulation)\n"
2206 "\n"
2207 "Standard options:\n"
2208 "-h print this help\n"
2209 "-g port wait gdb connection to port\n"
2210 "-L path set the elf interpreter prefix (default=%s)\n"
2211 "-s size set the stack size in bytes (default=%ld)\n"
2212 "-cpu model select CPU (-cpu ? for list)\n"
2213 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2214 "-E var=value sets/modifies targets environment variable(s)\n"
2215 "-U var unsets targets environment variable(s)\n"
2216 "\n"
2217 "Debug options:\n"
2218 "-d options activate log (logfile=%s)\n"
2219 "-p pagesize set the host page size to 'pagesize'\n"
2220 "-strace log system calls\n"
2221 "\n"
2222 "Environment variables:\n"
2223 "QEMU_STRACE Print system calls and arguments similar to the\n"
2224 " 'strace' program. Enable by setting to any value.\n"
2225 "You can use -E and -U options to set/unset environment variables\n"
2226 "for target process. It is possible to provide several variables\n"
2227 "by repeating the option. For example:\n"
2228 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2229 "Note that if you provide several changes to single variable\n"
2230 "last change will stay in effect.\n"
2231 ,
2232 TARGET_ARCH,
2233 interp_prefix,
2234 x86_stack_size,
2235 DEBUG_LOGFILE);
2236 exit(1);
2237 }
2238
2239 THREAD CPUState *thread_env;
2240
2241 /* Assumes contents are already zeroed. */
2242 void init_task_state(TaskState *ts)
2243 {
2244 int i;
2245
2246 ts->used = 1;
2247 ts->first_free = ts->sigqueue_table;
2248 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2249 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2250 }
2251 ts->sigqueue_table[i].next = NULL;
2252 }
2253
2254 int main(int argc, char **argv, char **envp)
2255 {
2256 const char *filename;
2257 const char *cpu_model;
2258 struct target_pt_regs regs1, *regs = &regs1;
2259 struct image_info info1, *info = &info1;
2260 TaskState ts1, *ts = &ts1;
2261 CPUState *env;
2262 int optind;
2263 const char *r;
2264 int gdbstub_port = 0;
2265 char **target_environ, **wrk;
2266 envlist_t *envlist = NULL;
2267
2268 if (argc <= 1)
2269 usage();
2270
2271 qemu_cache_utils_init(envp);
2272
2273 /* init debug */
2274 cpu_set_log_filename(DEBUG_LOGFILE);
2275
2276 if ((envlist = envlist_create()) == NULL) {
2277 (void) fprintf(stderr, "Unable to allocate envlist\n");
2278 exit(1);
2279 }
2280
2281 /* add current environment into the list */
2282 for (wrk = environ; *wrk != NULL; wrk++) {
2283 (void) envlist_setenv(envlist, *wrk);
2284 }
2285
2286 cpu_model = NULL;
2287 optind = 1;
2288 for(;;) {
2289 if (optind >= argc)
2290 break;
2291 r = argv[optind];
2292 if (r[0] != '-')
2293 break;
2294 optind++;
2295 r++;
2296 if (!strcmp(r, "-")) {
2297 break;
2298 } else if (!strcmp(r, "d")) {
2299 int mask;
2300 const CPULogItem *item;
2301
2302 if (optind >= argc)
2303 break;
2304
2305 r = argv[optind++];
2306 mask = cpu_str_to_log_mask(r);
2307 if (!mask) {
2308 printf("Log items (comma separated):\n");
2309 for(item = cpu_log_items; item->mask != 0; item++) {
2310 printf("%-10s %s\n", item->name, item->help);
2311 }
2312 exit(1);
2313 }
2314 cpu_set_log(mask);
2315 } else if (!strcmp(r, "E")) {
2316 r = argv[optind++];
2317 if (envlist_setenv(envlist, r) != 0)
2318 usage();
2319 } else if (!strcmp(r, "U")) {
2320 r = argv[optind++];
2321 if (envlist_unsetenv(envlist, r) != 0)
2322 usage();
2323 } else if (!strcmp(r, "s")) {
2324 if (optind >= argc)
2325 break;
2326 r = argv[optind++];
2327 x86_stack_size = strtol(r, (char **)&r, 0);
2328 if (x86_stack_size <= 0)
2329 usage();
2330 if (*r == 'M')
2331 x86_stack_size *= 1024 * 1024;
2332 else if (*r == 'k' || *r == 'K')
2333 x86_stack_size *= 1024;
2334 } else if (!strcmp(r, "L")) {
2335 interp_prefix = argv[optind++];
2336 } else if (!strcmp(r, "p")) {
2337 if (optind >= argc)
2338 break;
2339 qemu_host_page_size = atoi(argv[optind++]);
2340 if (qemu_host_page_size == 0 ||
2341 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2342 fprintf(stderr, "page size must be a power of two\n");
2343 exit(1);
2344 }
2345 } else if (!strcmp(r, "g")) {
2346 if (optind >= argc)
2347 break;
2348 gdbstub_port = atoi(argv[optind++]);
2349 } else if (!strcmp(r, "r")) {
2350 qemu_uname_release = argv[optind++];
2351 } else if (!strcmp(r, "cpu")) {
2352 cpu_model = argv[optind++];
2353 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2354 /* XXX: implement xxx_cpu_list for targets that still miss it */
2355 #if defined(cpu_list)
2356 cpu_list(stdout, &fprintf);
2357 #endif
2358 exit(1);
2359 }
2360 } else if (!strcmp(r, "drop-ld-preload")) {
2361 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2362 } else if (!strcmp(r, "strace")) {
2363 do_strace = 1;
2364 } else
2365 {
2366 usage();
2367 }
2368 }
2369 if (optind >= argc)
2370 usage();
2371 filename = argv[optind];
2372 exec_path = argv[optind];
2373
2374 /* Zero out regs */
2375 memset(regs, 0, sizeof(struct target_pt_regs));
2376
2377 /* Zero out image_info */
2378 memset(info, 0, sizeof(struct image_info));
2379
2380 /* Scan interp_prefix dir for replacement files. */
2381 init_paths(interp_prefix);
2382
2383 if (cpu_model == NULL) {
2384 #if defined(TARGET_I386)
2385 #ifdef TARGET_X86_64
2386 cpu_model = "qemu64";
2387 #else
2388 cpu_model = "qemu32";
2389 #endif
2390 #elif defined(TARGET_ARM)
2391 cpu_model = "arm926";
2392 #elif defined(TARGET_M68K)
2393 cpu_model = "any";
2394 #elif defined(TARGET_SPARC)
2395 #ifdef TARGET_SPARC64
2396 cpu_model = "TI UltraSparc II";
2397 #else
2398 cpu_model = "Fujitsu MB86904";
2399 #endif
2400 #elif defined(TARGET_MIPS)
2401 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2402 cpu_model = "20Kc";
2403 #else
2404 cpu_model = "24Kf";
2405 #endif
2406 #elif defined(TARGET_PPC)
2407 #ifdef TARGET_PPC64
2408 cpu_model = "970";
2409 #else
2410 cpu_model = "750";
2411 #endif
2412 #else
2413 cpu_model = "any";
2414 #endif
2415 }
2416 cpu_exec_init_all(0);
2417 /* NOTE: we need to init the CPU at this stage to get
2418 qemu_host_page_size */
2419 env = cpu_init(cpu_model);
2420 if (!env) {
2421 fprintf(stderr, "Unable to find CPU definition\n");
2422 exit(1);
2423 }
2424 thread_env = env;
2425
2426 if (getenv("QEMU_STRACE")) {
2427 do_strace = 1;
2428 }
2429
2430 target_environ = envlist_to_environ(envlist, NULL);
2431 envlist_free(envlist);
2432
2433 if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) {
2434 printf("Error loading %s\n", filename);
2435 _exit(1);
2436 }
2437
2438 for (wrk = target_environ; *wrk; wrk++) {
2439 free(*wrk);
2440 }
2441
2442 free(target_environ);
2443
2444 if (qemu_log_enabled()) {
2445 log_page_dump();
2446
2447 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2448 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2449 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2450 info->start_code);
2451 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2452 info->start_data);
2453 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2454 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2455 info->start_stack);
2456 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2457 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2458 }
2459
2460 target_set_brk(info->brk);
2461 syscall_init();
2462 signal_init();
2463
2464 /* build Task State */
2465 memset(ts, 0, sizeof(TaskState));
2466 init_task_state(ts);
2467 ts->info = info;
2468 env->opaque = ts;
2469
2470 #if defined(TARGET_I386)
2471 cpu_x86_set_cpl(env, 3);
2472
2473 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2474 env->hflags |= HF_PE_MASK;
2475 if (env->cpuid_features & CPUID_SSE) {
2476 env->cr[4] |= CR4_OSFXSR_MASK;
2477 env->hflags |= HF_OSFXSR_MASK;
2478 }
2479 #ifndef TARGET_ABI32
2480 /* enable 64 bit mode if possible */
2481 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2482 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2483 exit(1);
2484 }
2485 env->cr[4] |= CR4_PAE_MASK;
2486 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2487 env->hflags |= HF_LMA_MASK;
2488 #endif
2489
2490 /* flags setup : we activate the IRQs by default as in user mode */
2491 env->eflags |= IF_MASK;
2492
2493 /* linux register setup */
2494 #ifndef TARGET_ABI32
2495 env->regs[R_EAX] = regs->rax;
2496 env->regs[R_EBX] = regs->rbx;
2497 env->regs[R_ECX] = regs->rcx;
2498 env->regs[R_EDX] = regs->rdx;
2499 env->regs[R_ESI] = regs->rsi;
2500 env->regs[R_EDI] = regs->rdi;
2501 env->regs[R_EBP] = regs->rbp;
2502 env->regs[R_ESP] = regs->rsp;
2503 env->eip = regs->rip;
2504 #else
2505 env->regs[R_EAX] = regs->eax;
2506 env->regs[R_EBX] = regs->ebx;
2507 env->regs[R_ECX] = regs->ecx;
2508 env->regs[R_EDX] = regs->edx;
2509 env->regs[R_ESI] = regs->esi;
2510 env->regs[R_EDI] = regs->edi;
2511 env->regs[R_EBP] = regs->ebp;
2512 env->regs[R_ESP] = regs->esp;
2513 env->eip = regs->eip;
2514 #endif
2515
2516 /* linux interrupt setup */
2517 #ifndef TARGET_ABI32
2518 env->idt.limit = 511;
2519 #else
2520 env->idt.limit = 255;
2521 #endif
2522 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2523 PROT_READ|PROT_WRITE,
2524 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2525 idt_table = g2h(env->idt.base);
2526 set_idt(0, 0);
2527 set_idt(1, 0);
2528 set_idt(2, 0);
2529 set_idt(3, 3);
2530 set_idt(4, 3);
2531 set_idt(5, 0);
2532 set_idt(6, 0);
2533 set_idt(7, 0);
2534 set_idt(8, 0);
2535 set_idt(9, 0);
2536 set_idt(10, 0);
2537 set_idt(11, 0);
2538 set_idt(12, 0);
2539 set_idt(13, 0);
2540 set_idt(14, 0);
2541 set_idt(15, 0);
2542 set_idt(16, 0);
2543 set_idt(17, 0);
2544 set_idt(18, 0);
2545 set_idt(19, 0);
2546 set_idt(0x80, 3);
2547
2548 /* linux segment setup */
2549 {
2550 uint64_t *gdt_table;
2551 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2552 PROT_READ|PROT_WRITE,
2553 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2554 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2555 gdt_table = g2h(env->gdt.base);
2556 #ifdef TARGET_ABI32
2557 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2558 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2559 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2560 #else
2561 /* 64 bit code segment */
2562 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2563 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2564 DESC_L_MASK |
2565 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2566 #endif
2567 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2568 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2569 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2570 }
2571 cpu_x86_load_seg(env, R_CS, __USER_CS);
2572 cpu_x86_load_seg(env, R_SS, __USER_DS);
2573 #ifdef TARGET_ABI32
2574 cpu_x86_load_seg(env, R_DS, __USER_DS);
2575 cpu_x86_load_seg(env, R_ES, __USER_DS);
2576 cpu_x86_load_seg(env, R_FS, __USER_DS);
2577 cpu_x86_load_seg(env, R_GS, __USER_DS);
2578 /* This hack makes Wine work... */
2579 env->segs[R_FS].selector = 0;
2580 #else
2581 cpu_x86_load_seg(env, R_DS, 0);
2582 cpu_x86_load_seg(env, R_ES, 0);
2583 cpu_x86_load_seg(env, R_FS, 0);
2584 cpu_x86_load_seg(env, R_GS, 0);
2585 #endif
2586 #elif defined(TARGET_ARM)
2587 {
2588 int i;
2589 cpsr_write(env, regs->uregs[16], 0xffffffff);
2590 for(i = 0; i < 16; i++) {
2591 env->regs[i] = regs->uregs[i];
2592 }
2593 }
2594 #elif defined(TARGET_SPARC)
2595 {
2596 int i;
2597 env->pc = regs->pc;
2598 env->npc = regs->npc;
2599 env->y = regs->y;
2600 for(i = 0; i < 8; i++)
2601 env->gregs[i] = regs->u_regs[i];
2602 for(i = 0; i < 8; i++)
2603 env->regwptr[i] = regs->u_regs[i + 8];
2604 }
2605 #elif defined(TARGET_PPC)
2606 {
2607 int i;
2608
2609 #if defined(TARGET_PPC64)
2610 #if defined(TARGET_ABI32)
2611 env->msr &= ~((target_ulong)1 << MSR_SF);
2612 #else
2613 env->msr |= (target_ulong)1 << MSR_SF;
2614 #endif
2615 #endif
2616 env->nip = regs->nip;
2617 for(i = 0; i < 32; i++) {
2618 env->gpr[i] = regs->gpr[i];
2619 }
2620 }
2621 #elif defined(TARGET_M68K)
2622 {
2623 env->pc = regs->pc;
2624 env->dregs[0] = regs->d0;
2625 env->dregs[1] = regs->d1;
2626 env->dregs[2] = regs->d2;
2627 env->dregs[3] = regs->d3;
2628 env->dregs[4] = regs->d4;
2629 env->dregs[5] = regs->d5;
2630 env->dregs[6] = regs->d6;
2631 env->dregs[7] = regs->d7;
2632 env->aregs[0] = regs->a0;
2633 env->aregs[1] = regs->a1;
2634 env->aregs[2] = regs->a2;
2635 env->aregs[3] = regs->a3;
2636 env->aregs[4] = regs->a4;
2637 env->aregs[5] = regs->a5;
2638 env->aregs[6] = regs->a6;
2639 env->aregs[7] = regs->usp;
2640 env->sr = regs->sr;
2641 ts->sim_syscalls = 1;
2642 }
2643 #elif defined(TARGET_MIPS)
2644 {
2645 int i;
2646
2647 for(i = 0; i < 32; i++) {
2648 env->active_tc.gpr[i] = regs->regs[i];
2649 }
2650 env->active_tc.PC = regs->cp0_epc;
2651 }
2652 #elif defined(TARGET_SH4)
2653 {
2654 int i;
2655
2656 for(i = 0; i < 16; i++) {
2657 env->gregs[i] = regs->regs[i];
2658 }
2659 env->pc = regs->pc;
2660 }
2661 #elif defined(TARGET_ALPHA)
2662 {
2663 int i;
2664
2665 for(i = 0; i < 28; i++) {
2666 env->ir[i] = ((abi_ulong *)regs)[i];
2667 }
2668 env->ipr[IPR_USP] = regs->usp;
2669 env->ir[30] = regs->usp;
2670 env->pc = regs->pc;
2671 env->unique = regs->unique;
2672 }
2673 #elif defined(TARGET_CRIS)
2674 {
2675 env->regs[0] = regs->r0;
2676 env->regs[1] = regs->r1;
2677 env->regs[2] = regs->r2;
2678 env->regs[3] = regs->r3;
2679 env->regs[4] = regs->r4;
2680 env->regs[5] = regs->r5;
2681 env->regs[6] = regs->r6;
2682 env->regs[7] = regs->r7;
2683 env->regs[8] = regs->r8;
2684 env->regs[9] = regs->r9;
2685 env->regs[10] = regs->r10;
2686 env->regs[11] = regs->r11;
2687 env->regs[12] = regs->r12;
2688 env->regs[13] = regs->r13;
2689 env->regs[14] = info->start_stack;
2690 env->regs[15] = regs->acr;
2691 env->pc = regs->erp;
2692 }
2693 #else
2694 #error unsupported target CPU
2695 #endif
2696
2697 #if defined(TARGET_ARM) || defined(TARGET_M68K)
2698 ts->stack_base = info->start_stack;
2699 ts->heap_base = info->brk;
2700 /* This will be filled in on the first SYS_HEAPINFO call. */
2701 ts->heap_limit = 0;
2702 #endif
2703
2704 if (gdbstub_port) {
2705 gdbserver_start (gdbstub_port);
2706 gdb_handlesig(env, 0);
2707 }
2708 cpu_loop(env);
2709 /* never exits */
2710 return 0;
2711 }
Samsung s3c2440 and arm920t support for the mini2440 dev board