hw/pxa2xx_gpio.c

   1 /*
   2  * Intel XScale PXA255/270 GPIO controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "vl.h"
  11
  12 #define PXA2XX_GPIO_BANKS       4
  13
  14 struct pxa2xx_gpio_info_s {
  15     target_phys_addr_t base;
  16     qemu_irq *pic;
  17     int lines;
  18     CPUState *cpu_env;
  19
  20     /* XXX: GNU C vectors are more suitable */
  21     uint32_t ilevel[PXA2XX_GPIO_BANKS];
  22     uint32_t olevel[PXA2XX_GPIO_BANKS];
  23     uint32_t dir[PXA2XX_GPIO_BANKS];
  24     uint32_t rising[PXA2XX_GPIO_BANKS];
  25     uint32_t falling[PXA2XX_GPIO_BANKS];
  26     uint32_t status[PXA2XX_GPIO_BANKS];
  27     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  28
  29     uint32_t prev_level[PXA2XX_GPIO_BANKS];
  30     struct {
  31         gpio_handler_t fn;
  32         void *opaque;
  33     } handler[PXA2XX_GPIO_BANKS * 32];
  34
  35     void (*read_notify)(void *opaque);
  36     void *opaque;
  37 };
  38
  39 static struct {
  40     enum {
  41         GPIO_NONE,
  42         GPLR,
  43         GPSR,
  44         GPCR,
  45         GPDR,
  46         GRER,
  47         GFER,
  48         GEDR,
  49         GAFR_L,
  50         GAFR_U,
  51     } reg;
  52     int bank;
  53 } pxa2xx_gpio_regs[0x200] = {
  54     [0 ... 0x1ff] = { GPIO_NONE, 0 },
  55 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  56     [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  57
  58     PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  59     PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  60     PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  61     PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  62     PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  63     PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  64     PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  65     PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  66     PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  67 };
  68
  69 static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
  70 {
  71     if (s->status[0] & (1 << 0))
  72         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
  73     else
  74         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
  75
  76     if (s->status[0] & (1 << 1))
  77         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
  78     else
  79         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
  80
  81     if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  82         qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
  83     else
  84         qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
  85 }
  86
  87 /* Bitmap of pins used as standby and sleep wake-up sources.  */
  88 const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  89     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  90 };
  91
  92 void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level)
  93 {
  94     int bank;
  95     uint32_t mask;
  96
  97     if (line >= s->lines) {
  98         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
  99         return;
 100     }
 101
 102     bank = line >> 5;
 103     mask = 1 << (line & 31);
 104
 105     if (level) {
 106         s->status[bank] |= s->rising[bank] & mask &
 107                 ~s->ilevel[bank] & ~s->dir[bank];
 108         s->ilevel[bank] |= mask;
 109     } else {
 110         s->status[bank] |= s->falling[bank] & mask &
 111                 s->ilevel[bank] & ~s->dir[bank];
 112         s->ilevel[bank] &= ~mask;
 113     }
 114
 115     if (s->status[bank] & mask)
 116         pxa2xx_gpio_irq_update(s);
 117
 118     /* Wake-up GPIOs */
 119     if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
 120         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
 121 }
 122
 123 static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
 124     uint32_t level, diff;
 125     int i, bit, line;
 126     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 127         level = s->olevel[i] & s->dir[i];
 128
 129         for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
 130             bit = ffs(diff) - 1;
 131             line = bit + 32 * i;
 132             if (s->handler[line].fn)
 133                 s->handler[line].fn(line, (level >> bit) & 1,
 134                                 s->handler[line].opaque);
 135         }
 136
 137         s->prev_level[i] = level;
 138     }
 139 }
 140
 141 static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
 142 {
 143     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 144     uint32_t ret;
 145     int bank;
 146     offset -= s->base;
 147     if (offset >= 0x200)
 148         return 0;
 149
 150     bank = pxa2xx_gpio_regs[offset].bank;
 151     switch (pxa2xx_gpio_regs[offset].reg) {
 152     case GPDR:          /* GPIO Pin-Direction registers */
 153         return s->dir[bank];
 154
 155     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 156         return s->rising[bank];
 157
 158     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 159         return s->falling[bank];
 160
 161     case GAFR_L:        /* GPIO Alternate Function registers */
 162         return s->gafr[bank * 2];
 163
 164     case GAFR_U:        /* GPIO Alternate Function registers */
 165         return s->gafr[bank * 2 + 1];
 166
 167     case GPLR:          /* GPIO Pin-Level registers */
 168         ret = (s->olevel[bank] & s->dir[bank]) |
 169                 (s->ilevel[bank] & ~s->dir[bank]);
 170         if (s->read_notify)
 171             s->read_notify(s->opaque);
 172         return ret;
 173
 174     case GEDR:          /* GPIO Edge Detect Status registers */
 175         return s->status[bank];
 176
 177     default:
 178         cpu_abort(cpu_single_env,
 179                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 180     }
 181
 182     return 0;
 183 }
 184
 185 static void pxa2xx_gpio_write(void *opaque,
 186                 target_phys_addr_t offset, uint32_t value)
 187 {
 188     struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
 189     int bank;
 190     offset -= s->base;
 191     if (offset >= 0x200)
 192         return;
 193
 194     bank = pxa2xx_gpio_regs[offset].bank;
 195     switch (pxa2xx_gpio_regs[offset].reg) {
 196     case GPDR:          /* GPIO Pin-Direction registers */
 197         s->dir[bank] = value;
 198         pxa2xx_gpio_handler_update(s);
 199         break;
 200
 201     case GPSR:          /* GPIO Pin-Output Set registers */
 202         s->olevel[bank] |= value;
 203         pxa2xx_gpio_handler_update(s);
 204         break;
 205
 206     case GPCR:          /* GPIO Pin-Output Clear registers */
 207         s->olevel[bank] &= ~value;
 208         pxa2xx_gpio_handler_update(s);
 209         break;
 210
 211     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 212         s->rising[bank] = value;
 213         break;
 214
 215     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 216         s->falling[bank] = value;
 217         break;
 218
 219     case GAFR_L:        /* GPIO Alternate Function registers */
 220         s->gafr[bank * 2] = value;
 221         break;
 222
 223     case GAFR_U:        /* GPIO Alternate Function registers */
 224         s->gafr[bank * 2 + 1] = value;
 225         break;
 226
 227     case GEDR:          /* GPIO Edge Detect Status registers */
 228         s->status[bank] &= ~value;
 229         pxa2xx_gpio_irq_update(s);
 230         break;
 231
 232     default:
 233         cpu_abort(cpu_single_env,
 234                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 235     }
 236 }
 237
 238 static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
 239     pxa2xx_gpio_read,
 240     pxa2xx_gpio_read,
 241     pxa2xx_gpio_read
 242 };
 243
 244 static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
 245     pxa2xx_gpio_write,
 246     pxa2xx_gpio_write,
 247     pxa2xx_gpio_write
 248 };
 249
 250 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
 251                 CPUState *env, qemu_irq *pic, int lines)
 252 {
 253     int iomemtype;
 254     struct pxa2xx_gpio_info_s *s;
 255
 256     s = (struct pxa2xx_gpio_info_s *)
 257             qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
 258     memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
 259     s->base = base;
 260     s->pic = pic;
 261     s->lines = lines;
 262     s->cpu_env = env;
 263
 264     iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
 265                     pxa2xx_gpio_writefn, s);
 266     cpu_register_physical_memory(base, 0x00000fff, iomemtype);
 267
 268     return s;
 269 }
 270
 271 void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
 272                 gpio_handler_t handler, void *opaque) {
 273     if (line >= s->lines) {
 274         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
 275         return;
 276     }
 277
 278     s->handler[line].fn = handler;
 279     s->handler[line].opaque = opaque;
 280 }
 281
 282 /*
 283  * Registers a callback to notify on GPLR reads.  This normally
 284  * shouldn't be needed but it is used for the hack on Spitz machines.
 285  */
 286 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
 287                 void (*handler)(void *opaque), void *opaque) {
 288     s->read_notify = handler;
 289     s->opaque = opaque;
 290 }