4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* XXX: implement all timer modes */
29 //#define DEBUG_CUDA_PACKET
31 /* Bits in B data register: all active low */
32 #define TREQ 0x08 /* Transfer request (input) */
33 #define TACK 0x10 /* Transfer acknowledge (output) */
34 #define TIP 0x20 /* Transfer in progress (output) */
37 #define SR_CTRL 0x1c /* Shift register control bits */
38 #define SR_EXT 0x0c /* Shift on external clock */
39 #define SR_OUT 0x10 /* Shift out if 1 */
41 /* Bits in IFR and IER */
42 #define IER_SET 0x80 /* set bits in IER */
43 #define IER_CLR 0 /* clear bits in IER */
44 #define SR_INT 0x04 /* Shift register full/empty */
45 #define T1_INT 0x40 /* Timer 1 interrupt */
46 #define T2_INT 0x20 /* Timer 2 interrupt */
49 #define T1MODE 0xc0 /* Timer 1 mode */
50 #define T1MODE_CONT 0x40 /* continuous interrupts */
52 /* commands (1st byte) */
55 #define ERROR_PACKET 2
56 #define TIMER_PACKET 3
57 #define POWER_PACKET 4
58 #define MACIIC_PACKET 5
62 /* CUDA commands (2nd byte) */
63 #define CUDA_WARM_START 0x0
64 #define CUDA_AUTOPOLL 0x1
65 #define CUDA_GET_6805_ADDR 0x2
66 #define CUDA_GET_TIME 0x3
67 #define CUDA_GET_PRAM 0x7
68 #define CUDA_SET_6805_ADDR 0x8
69 #define CUDA_SET_TIME 0x9
70 #define CUDA_POWERDOWN 0xa
71 #define CUDA_POWERUP_TIME 0xb
72 #define CUDA_SET_PRAM 0xc
73 #define CUDA_MS_RESET 0xd
74 #define CUDA_SEND_DFAC 0xe
75 #define CUDA_BATTERY_SWAP_SENSE 0x10
76 #define CUDA_RESET_SYSTEM 0x11
77 #define CUDA_SET_IPL 0x12
78 #define CUDA_FILE_SERVER_FLAG 0x13
79 #define CUDA_SET_AUTO_RATE 0x14
80 #define CUDA_GET_AUTO_RATE 0x16
81 #define CUDA_SET_DEVICE_LIST 0x19
82 #define CUDA_GET_DEVICE_LIST 0x1a
83 #define CUDA_SET_ONE_SECOND_MODE 0x1b
84 #define CUDA_SET_POWER_MESSAGES 0x21
85 #define CUDA_GET_SET_IIC 0x22
86 #define CUDA_WAKEUP 0x23
87 #define CUDA_TIMER_TICKLE 0x24
88 #define CUDA_COMBINED_FORMAT_IIC 0x25
90 #define CUDA_TIMER_FREQ (4700000 / 6)
91 #define CUDA_ADB_POLL_FREQ 50
93 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
94 #define RTC_OFFSET 2082844800
96 typedef struct CUDATimer
{
99 uint16_t counter_value
; /* counter value at load time */
101 int64_t next_irq_time
;
105 typedef struct CUDAState
{
107 uint8_t b
; /* B-side data */
108 uint8_t a
; /* A-side data */
109 uint8_t dirb
; /* B-side direction (1=output) */
110 uint8_t dira
; /* A-side direction (1=output) */
111 uint8_t sr
; /* Shift register */
112 uint8_t acr
; /* Auxiliary control register */
113 uint8_t pcr
; /* Peripheral control register */
114 uint8_t ifr
; /* Interrupt flag register */
115 uint8_t ier
; /* Interrupt enable register */
116 uint8_t anh
; /* A-side data, no handshake */
120 uint8_t last_b
; /* last value of B register */
121 uint8_t last_acr
; /* last value of B register */
129 uint8_t data_in
[128];
130 uint8_t data_out
[16];
131 QEMUTimer
*adb_poll_timer
;
134 static CUDAState cuda_state
;
137 static void cuda_update(CUDAState
*s
);
138 static void cuda_receive_packet_from_host(CUDAState
*s
,
139 const uint8_t *data
, int len
);
140 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
141 int64_t current_time
);
143 static void cuda_update_irq(CUDAState
*s
)
145 if (s
->ifr
& s
->ier
& (SR_INT
| T1_INT
)) {
146 qemu_irq_raise(s
->irq
);
148 qemu_irq_lower(s
->irq
);
152 static unsigned int get_counter(CUDATimer
*s
)
155 unsigned int counter
;
157 d
= muldiv64(qemu_get_clock(vm_clock
) - s
->load_time
,
158 CUDA_TIMER_FREQ
, ticks_per_sec
);
160 /* the timer goes down from latch to -1 (period of latch + 2) */
161 if (d
<= (s
->counter_value
+ 1)) {
162 counter
= (s
->counter_value
- d
) & 0xffff;
164 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
165 counter
= (s
->latch
- counter
) & 0xffff;
168 counter
= (s
->counter_value
- d
) & 0xffff;
173 static void set_counter(CUDAState
*s
, CUDATimer
*ti
, unsigned int val
)
176 printf("cuda: T%d.counter=%d\n",
177 1 + (ti
->timer
== NULL
), val
);
179 ti
->load_time
= qemu_get_clock(vm_clock
);
180 ti
->counter_value
= val
;
181 cuda_timer_update(s
, ti
, ti
->load_time
);
184 static int64_t get_next_irq_time(CUDATimer
*s
, int64_t current_time
)
186 int64_t d
, next_time
;
187 unsigned int counter
;
189 /* current counter value */
190 d
= muldiv64(current_time
- s
->load_time
,
191 CUDA_TIMER_FREQ
, ticks_per_sec
);
192 /* the timer goes down from latch to -1 (period of latch + 2) */
193 if (d
<= (s
->counter_value
+ 1)) {
194 counter
= (s
->counter_value
- d
) & 0xffff;
196 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
197 counter
= (s
->latch
- counter
) & 0xffff;
200 /* Note: we consider the irq is raised on 0 */
201 if (counter
== 0xffff) {
202 next_time
= d
+ s
->latch
+ 1;
203 } else if (counter
== 0) {
204 next_time
= d
+ s
->latch
+ 2;
206 next_time
= d
+ counter
;
210 printf("latch=%d counter=%" PRId64
" delta_next=%" PRId64
"\n",
211 s
->latch
, d
, next_time
- d
);
214 next_time
= muldiv64(next_time
, ticks_per_sec
, CUDA_TIMER_FREQ
) +
216 if (next_time
<= current_time
)
217 next_time
= current_time
+ 1;
221 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
222 int64_t current_time
)
226 if ((s
->acr
& T1MODE
) != T1MODE_CONT
) {
227 qemu_del_timer(ti
->timer
);
229 ti
->next_irq_time
= get_next_irq_time(ti
, current_time
);
230 qemu_mod_timer(ti
->timer
, ti
->next_irq_time
);
234 static void cuda_timer1(void *opaque
)
236 CUDAState
*s
= opaque
;
237 CUDATimer
*ti
= &s
->timers
[0];
239 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
244 static uint32_t cuda_readb(void *opaque
, target_phys_addr_t addr
)
246 CUDAState
*s
= opaque
;
249 addr
= (addr
>> 9) & 0xf;
264 val
= get_counter(&s
->timers
[0]) & 0xff;
269 val
= get_counter(&s
->timers
[0]) >> 8;
273 val
= s
->timers
[0].latch
& 0xff;
276 /* XXX: check this */
277 val
= (s
->timers
[0].latch
>> 8) & 0xff;
280 val
= get_counter(&s
->timers
[1]) & 0xff;
284 val
= get_counter(&s
->timers
[1]) >> 8;
311 if (addr
!= 13 || val
!= 0)
312 printf("cuda: read: reg=0x%x val=%02x\n", addr
, val
);
317 static void cuda_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
319 CUDAState
*s
= opaque
;
321 addr
= (addr
>> 9) & 0xf;
323 printf("cuda: write: reg=0x%x val=%02x\n", addr
, val
);
341 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
342 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
345 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
347 set_counter(s
, &s
->timers
[0], s
->timers
[0].latch
);
350 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
351 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
354 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
356 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
359 s
->timers
[1].latch
= val
;
360 set_counter(s
, &s
->timers
[1], val
);
363 set_counter(s
, &s
->timers
[1], (val
<< 8) | s
->timers
[1].latch
);
370 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
384 s
->ier
|= val
& 0x7f;
398 /* NOTE: TIP and TREQ are negated */
399 static void cuda_update(CUDAState
*s
)
401 int packet_received
, len
;
405 /* transfer requested from host */
407 if (s
->acr
& SR_OUT
) {
409 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
410 if (s
->data_out_index
< sizeof(s
->data_out
)) {
412 printf("cuda: send: %02x\n", s
->sr
);
414 s
->data_out
[s
->data_out_index
++] = s
->sr
;
420 if (s
->data_in_index
< s
->data_in_size
) {
422 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
423 s
->sr
= s
->data_in
[s
->data_in_index
++];
425 printf("cuda: recv: %02x\n", s
->sr
);
427 /* indicate end of transfer */
428 if (s
->data_in_index
>= s
->data_in_size
) {
429 s
->b
= (s
->b
| TREQ
);
437 /* no transfer requested: handle sync case */
438 if ((s
->last_b
& TIP
) && (s
->b
& TACK
) != (s
->last_b
& TACK
)) {
439 /* update TREQ state each time TACK change state */
441 s
->b
= (s
->b
| TREQ
);
443 s
->b
= (s
->b
& ~TREQ
);
447 if (!(s
->last_b
& TIP
)) {
448 /* handle end of host to cuda transfert */
449 packet_received
= (s
->data_out_index
> 0);
450 /* always an IRQ at the end of transfert */
454 /* signal if there is data to read */
455 if (s
->data_in_index
< s
->data_in_size
) {
456 s
->b
= (s
->b
& ~TREQ
);
461 s
->last_acr
= s
->acr
;
464 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
466 if (packet_received
) {
467 len
= s
->data_out_index
;
468 s
->data_out_index
= 0;
469 cuda_receive_packet_from_host(s
, s
->data_out
, len
);
473 static void cuda_send_packet_to_host(CUDAState
*s
,
474 const uint8_t *data
, int len
)
476 #ifdef DEBUG_CUDA_PACKET
479 printf("cuda_send_packet_to_host:\n");
480 for(i
= 0; i
< len
; i
++)
481 printf(" %02x", data
[i
]);
485 memcpy(s
->data_in
, data
, len
);
486 s
->data_in_size
= len
;
487 s
->data_in_index
= 0;
493 static void cuda_adb_poll(void *opaque
)
495 CUDAState
*s
= opaque
;
496 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
499 olen
= adb_poll(&adb_bus
, obuf
+ 2);
501 obuf
[0] = ADB_PACKET
;
502 obuf
[1] = 0x40; /* polled data */
503 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
505 qemu_mod_timer(s
->adb_poll_timer
,
506 qemu_get_clock(vm_clock
) +
507 (ticks_per_sec
/ CUDA_ADB_POLL_FREQ
));
510 static void cuda_receive_packet(CUDAState
*s
,
511 const uint8_t *data
, int len
)
518 autopoll
= (data
[1] != 0);
519 if (autopoll
!= s
->autopoll
) {
520 s
->autopoll
= autopoll
;
522 qemu_mod_timer(s
->adb_poll_timer
,
523 qemu_get_clock(vm_clock
) +
524 (ticks_per_sec
/ CUDA_ADB_POLL_FREQ
));
526 qemu_del_timer(s
->adb_poll_timer
);
529 obuf
[0] = CUDA_PACKET
;
531 cuda_send_packet_to_host(s
, obuf
, 2);
535 /* XXX: add time support ? */
536 ti
= time(NULL
) + RTC_OFFSET
;
537 obuf
[0] = CUDA_PACKET
;
544 cuda_send_packet_to_host(s
, obuf
, 7);
546 case CUDA_FILE_SERVER_FLAG
:
547 case CUDA_SET_DEVICE_LIST
:
548 case CUDA_SET_AUTO_RATE
:
549 case CUDA_SET_POWER_MESSAGES
:
550 obuf
[0] = CUDA_PACKET
;
552 cuda_send_packet_to_host(s
, obuf
, 2);
555 obuf
[0] = CUDA_PACKET
;
557 cuda_send_packet_to_host(s
, obuf
, 2);
558 qemu_system_shutdown_request();
565 static void cuda_receive_packet_from_host(CUDAState
*s
,
566 const uint8_t *data
, int len
)
568 #ifdef DEBUG_CUDA_PACKET
571 printf("cuda_receive_packet_from_host:\n");
572 for(i
= 0; i
< len
; i
++)
573 printf(" %02x", data
[i
]);
580 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
582 olen
= adb_request(&adb_bus
, obuf
+ 2, data
+ 1, len
- 1);
584 obuf
[0] = ADB_PACKET
;
588 obuf
[0] = ADB_PACKET
;
592 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
596 cuda_receive_packet(s
, data
+ 1, len
- 1);
601 static void cuda_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
605 static void cuda_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
609 static uint32_t cuda_readw (void *opaque
, target_phys_addr_t addr
)
614 static uint32_t cuda_readl (void *opaque
, target_phys_addr_t addr
)
619 static CPUWriteMemoryFunc
*cuda_write
[] = {
625 static CPUReadMemoryFunc
*cuda_read
[] = {
631 int cuda_init(qemu_irq irq
)
633 CUDAState
*s
= &cuda_state
;
638 s
->timers
[0].index
= 0;
639 s
->timers
[0].timer
= qemu_new_timer(vm_clock
, cuda_timer1
, s
);
640 s
->timers
[0].latch
= 0xffff;
641 set_counter(s
, &s
->timers
[0], 0xffff);
643 s
->timers
[1].index
= 1;
644 s
->timers
[1].latch
= 0;
645 // s->ier = T1_INT | SR_INT;
647 set_counter(s
, &s
->timers
[1], 0xffff);
649 s
->adb_poll_timer
= qemu_new_timer(vm_clock
, cuda_adb_poll
, s
);
650 cuda_mem_index
= cpu_register_io_memory(0, cuda_read
, cuda_write
, s
);
651 return cuda_mem_index
;