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Add Arm926 core support.
[qemu/mini2440.git] / target-i386 / helper.c
blob46cbe8b8d7954352ddcc71dd95b589b05d4b6bef
1 /*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21
22 //#define DEBUG_PCALL
23
24 #if 0
25 #define raise_exception_err(a, b)\
26 do {\
27 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
28 (raise_exception_err)(a, b);\
29 } while (0)
30 #endif
31
32 const uint8_t parity_table[256] = {
33 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
34 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
46 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
62 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
65 };
66
67 /* modulo 17 table */
68 const uint8_t rclw_table[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 9,10,11,12,13,14,15,
71 16, 0, 1, 2, 3, 4, 5, 6,
72 7, 8, 9,10,11,12,13,14,
73 };
74
75 /* modulo 9 table */
76 const uint8_t rclb_table[32] = {
77 0, 1, 2, 3, 4, 5, 6, 7,
78 8, 0, 1, 2, 3, 4, 5, 6,
79 7, 8, 0, 1, 2, 3, 4, 5,
80 6, 7, 8, 0, 1, 2, 3, 4,
81 };
82
83 const CPU86_LDouble f15rk[7] =
84 {
85 0.00000000000000000000L,
86 1.00000000000000000000L,
87 3.14159265358979323851L, /*pi*/
88 0.30102999566398119523L, /*lg2*/
89 0.69314718055994530943L, /*ln2*/
90 1.44269504088896340739L, /*l2e*/
91 3.32192809488736234781L, /*l2t*/
92 };
93
94 /* thread support */
95
96 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
97
98 void cpu_lock(void)
99 {
100 spin_lock(&global_cpu_lock);
101 }
102
103 void cpu_unlock(void)
104 {
105 spin_unlock(&global_cpu_lock);
106 }
107
108 void cpu_loop_exit(void)
109 {
110 /* NOTE: the register at this point must be saved by hand because
111 longjmp restore them */
112 regs_to_env();
113 longjmp(env->jmp_env, 1);
114 }
115
116 /* return non zero if error */
117 static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
118 int selector)
119 {
120 SegmentCache *dt;
121 int index;
122 target_ulong ptr;
123
124 if (selector & 0x4)
125 dt = &env->ldt;
126 else
127 dt = &env->gdt;
128 index = selector & ~7;
129 if ((index + 7) > dt->limit)
130 return -1;
131 ptr = dt->base + index;
132 *e1_ptr = ldl_kernel(ptr);
133 *e2_ptr = ldl_kernel(ptr + 4);
134 return 0;
135 }
136
137 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
138 {
139 unsigned int limit;
140 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
141 if (e2 & DESC_G_MASK)
142 limit = (limit << 12) | 0xfff;
143 return limit;
144 }
145
146 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
147 {
148 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
149 }
150
151 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
152 {
153 sc->base = get_seg_base(e1, e2);
154 sc->limit = get_seg_limit(e1, e2);
155 sc->flags = e2;
156 }
157
158 /* init the segment cache in vm86 mode. */
159 static inline void load_seg_vm(int seg, int selector)
160 {
161 selector &= 0xffff;
162 cpu_x86_load_seg_cache(env, seg, selector,
163 (selector << 4), 0xffff, 0);
164 }
165
166 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
167 uint32_t *esp_ptr, int dpl)
168 {
169 int type, index, shift;
170
171 #if 0
172 {
173 int i;
174 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
175 for(i=0;i<env->tr.limit;i++) {
176 printf("%02x ", env->tr.base[i]);
177 if ((i & 7) == 7) printf("\n");
178 }
179 printf("\n");
180 }
181 #endif
182
183 if (!(env->tr.flags & DESC_P_MASK))
184 cpu_abort(env, "invalid tss");
185 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
186 if ((type & 7) != 1)
187 cpu_abort(env, "invalid tss type");
188 shift = type >> 3;
189 index = (dpl * 4 + 2) << shift;
190 if (index + (4 << shift) - 1 > env->tr.limit)
191 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
192 if (shift == 0) {
193 *esp_ptr = lduw_kernel(env->tr.base + index);
194 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
195 } else {
196 *esp_ptr = ldl_kernel(env->tr.base + index);
197 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
198 }
199 }
200
201 /* XXX: merge with load_seg() */
202 static void tss_load_seg(int seg_reg, int selector)
203 {
204 uint32_t e1, e2;
205 int rpl, dpl, cpl;
206
207 if ((selector & 0xfffc) != 0) {
208 if (load_segment(&e1, &e2, selector) != 0)
209 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
210 if (!(e2 & DESC_S_MASK))
211 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
212 rpl = selector & 3;
213 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
214 cpl = env->hflags & HF_CPL_MASK;
215 if (seg_reg == R_CS) {
216 if (!(e2 & DESC_CS_MASK))
217 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
218 if (dpl != rpl)
219 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
220 if ((e2 & DESC_C_MASK) && dpl > rpl)
221 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222
223 } else if (seg_reg == R_SS) {
224 /* SS must be writable data */
225 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
226 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
227 if (dpl != cpl || dpl != rpl)
228 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
229 } else {
230 /* not readable code */
231 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
232 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233 /* if data or non conforming code, checks the rights */
234 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
235 if (dpl < cpl || dpl < rpl)
236 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237 }
238 }
239 if (!(e2 & DESC_P_MASK))
240 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
241 cpu_x86_load_seg_cache(env, seg_reg, selector,
242 get_seg_base(e1, e2),
243 get_seg_limit(e1, e2),
244 e2);
245 } else {
246 if (seg_reg == R_SS || seg_reg == R_CS)
247 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
248 }
249 }
250
251 #define SWITCH_TSS_JMP 0
252 #define SWITCH_TSS_IRET 1
253 #define SWITCH_TSS_CALL 2
254
255 /* XXX: restore CPU state in registers (PowerPC case) */
256 static void switch_tss(int tss_selector,
257 uint32_t e1, uint32_t e2, int source,
258 uint32_t next_eip)
259 {
260 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
261 target_ulong tss_base;
262 uint32_t new_regs[8], new_segs[6];
263 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
264 uint32_t old_eflags, eflags_mask;
265 SegmentCache *dt;
266 int index;
267 target_ulong ptr;
268
269 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
270 #ifdef DEBUG_PCALL
271 if (loglevel & CPU_LOG_PCALL)
272 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
273 #endif
274
275 /* if task gate, we read the TSS segment and we load it */
276 if (type == 5) {
277 if (!(e2 & DESC_P_MASK))
278 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
279 tss_selector = e1 >> 16;
280 if (tss_selector & 4)
281 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
282 if (load_segment(&e1, &e2, tss_selector) != 0)
283 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
284 if (e2 & DESC_S_MASK)
285 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
286 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
287 if ((type & 7) != 1)
288 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
289 }
290
291 if (!(e2 & DESC_P_MASK))
292 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
293
294 if (type & 8)
295 tss_limit_max = 103;
296 else
297 tss_limit_max = 43;
298 tss_limit = get_seg_limit(e1, e2);
299 tss_base = get_seg_base(e1, e2);
300 if ((tss_selector & 4) != 0 ||
301 tss_limit < tss_limit_max)
302 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
303 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
304 if (old_type & 8)
305 old_tss_limit_max = 103;
306 else
307 old_tss_limit_max = 43;
308
309 /* read all the registers from the new TSS */
310 if (type & 8) {
311 /* 32 bit */
312 new_cr3 = ldl_kernel(tss_base + 0x1c);
313 new_eip = ldl_kernel(tss_base + 0x20);
314 new_eflags = ldl_kernel(tss_base + 0x24);
315 for(i = 0; i < 8; i++)
316 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
317 for(i = 0; i < 6; i++)
318 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
319 new_ldt = lduw_kernel(tss_base + 0x60);
320 new_trap = ldl_kernel(tss_base + 0x64);
321 } else {
322 /* 16 bit */
323 new_cr3 = 0;
324 new_eip = lduw_kernel(tss_base + 0x0e);
325 new_eflags = lduw_kernel(tss_base + 0x10);
326 for(i = 0; i < 8; i++)
327 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
328 for(i = 0; i < 4; i++)
329 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
330 new_ldt = lduw_kernel(tss_base + 0x2a);
331 new_segs[R_FS] = 0;
332 new_segs[R_GS] = 0;
333 new_trap = 0;
334 }
335
336 /* NOTE: we must avoid memory exceptions during the task switch,
337 so we make dummy accesses before */
338 /* XXX: it can still fail in some cases, so a bigger hack is
339 necessary to valid the TLB after having done the accesses */
340
341 v1 = ldub_kernel(env->tr.base);
342 v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
343 stb_kernel(env->tr.base, v1);
344 stb_kernel(env->tr.base + old_tss_limit_max, v2);
345
346 /* clear busy bit (it is restartable) */
347 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
348 target_ulong ptr;
349 uint32_t e2;
350 ptr = env->gdt.base + (env->tr.selector & ~7);
351 e2 = ldl_kernel(ptr + 4);
352 e2 &= ~DESC_TSS_BUSY_MASK;
353 stl_kernel(ptr + 4, e2);
354 }
355 old_eflags = compute_eflags();
356 if (source == SWITCH_TSS_IRET)
357 old_eflags &= ~NT_MASK;
358
359 /* save the current state in the old TSS */
360 if (type & 8) {
361 /* 32 bit */
362 stl_kernel(env->tr.base + 0x20, next_eip);
363 stl_kernel(env->tr.base + 0x24, old_eflags);
364 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
365 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
366 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
367 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
368 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
369 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
370 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
371 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
372 for(i = 0; i < 6; i++)
373 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
374 } else {
375 /* 16 bit */
376 stw_kernel(env->tr.base + 0x0e, next_eip);
377 stw_kernel(env->tr.base + 0x10, old_eflags);
378 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
379 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
380 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
381 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
382 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
383 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
384 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
385 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
386 for(i = 0; i < 4; i++)
387 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
388 }
389
390 /* now if an exception occurs, it will occurs in the next task
391 context */
392
393 if (source == SWITCH_TSS_CALL) {
394 stw_kernel(tss_base, env->tr.selector);
395 new_eflags |= NT_MASK;
396 }
397
398 /* set busy bit */
399 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
400 target_ulong ptr;
401 uint32_t e2;
402 ptr = env->gdt.base + (tss_selector & ~7);
403 e2 = ldl_kernel(ptr + 4);
404 e2 |= DESC_TSS_BUSY_MASK;
405 stl_kernel(ptr + 4, e2);
406 }
407
408 /* set the new CPU state */
409 /* from this point, any exception which occurs can give problems */
410 env->cr[0] |= CR0_TS_MASK;
411 env->hflags |= HF_TS_MASK;
412 env->tr.selector = tss_selector;
413 env->tr.base = tss_base;
414 env->tr.limit = tss_limit;
415 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
416
417 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
418 cpu_x86_update_cr3(env, new_cr3);
419 }
420
421 /* load all registers without an exception, then reload them with
422 possible exception */
423 env->eip = new_eip;
424 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
425 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
426 if (!(type & 8))
427 eflags_mask &= 0xffff;
428 load_eflags(new_eflags, eflags_mask);
429 /* XXX: what to do in 16 bit case ? */
430 EAX = new_regs[0];
431 ECX = new_regs[1];
432 EDX = new_regs[2];
433 EBX = new_regs[3];
434 ESP = new_regs[4];
435 EBP = new_regs[5];
436 ESI = new_regs[6];
437 EDI = new_regs[7];
438 if (new_eflags & VM_MASK) {
439 for(i = 0; i < 6; i++)
440 load_seg_vm(i, new_segs[i]);
441 /* in vm86, CPL is always 3 */
442 cpu_x86_set_cpl(env, 3);
443 } else {
444 /* CPL is set the RPL of CS */
445 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
446 /* first just selectors as the rest may trigger exceptions */
447 for(i = 0; i < 6; i++)
448 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
449 }
450
451 env->ldt.selector = new_ldt & ~4;
452 env->ldt.base = 0;
453 env->ldt.limit = 0;
454 env->ldt.flags = 0;
455
456 /* load the LDT */
457 if (new_ldt & 4)
458 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
459
460 if ((new_ldt & 0xfffc) != 0) {
461 dt = &env->gdt;
462 index = new_ldt & ~7;
463 if ((index + 7) > dt->limit)
464 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
465 ptr = dt->base + index;
466 e1 = ldl_kernel(ptr);
467 e2 = ldl_kernel(ptr + 4);
468 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
469 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
470 if (!(e2 & DESC_P_MASK))
471 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
472 load_seg_cache_raw_dt(&env->ldt, e1, e2);
473 }
474
475 /* load the segments */
476 if (!(new_eflags & VM_MASK)) {
477 tss_load_seg(R_CS, new_segs[R_CS]);
478 tss_load_seg(R_SS, new_segs[R_SS]);
479 tss_load_seg(R_ES, new_segs[R_ES]);
480 tss_load_seg(R_DS, new_segs[R_DS]);
481 tss_load_seg(R_FS, new_segs[R_FS]);
482 tss_load_seg(R_GS, new_segs[R_GS]);
483 }
484
485 /* check that EIP is in the CS segment limits */
486 if (new_eip > env->segs[R_CS].limit) {
487 /* XXX: different exception if CALL ? */
488 raise_exception_err(EXCP0D_GPF, 0);
489 }
490 }
491
492 /* check if Port I/O is allowed in TSS */
493 static inline void check_io(int addr, int size)
494 {
495 int io_offset, val, mask;
496
497 /* TSS must be a valid 32 bit one */
498 if (!(env->tr.flags & DESC_P_MASK) ||
499 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
500 env->tr.limit < 103)
501 goto fail;
502 io_offset = lduw_kernel(env->tr.base + 0x66);
503 io_offset += (addr >> 3);
504 /* Note: the check needs two bytes */
505 if ((io_offset + 1) > env->tr.limit)
506 goto fail;
507 val = lduw_kernel(env->tr.base + io_offset);
508 val >>= (addr & 7);
509 mask = (1 << size) - 1;
510 /* all bits must be zero to allow the I/O */
511 if ((val & mask) != 0) {
512 fail:
513 raise_exception_err(EXCP0D_GPF, 0);
514 }
515 }
516
517 void check_iob_T0(void)
518 {
519 check_io(T0, 1);
520 }
521
522 void check_iow_T0(void)
523 {
524 check_io(T0, 2);
525 }
526
527 void check_iol_T0(void)
528 {
529 check_io(T0, 4);
530 }
531
532 void check_iob_DX(void)
533 {
534 check_io(EDX & 0xffff, 1);
535 }
536
537 void check_iow_DX(void)
538 {
539 check_io(EDX & 0xffff, 2);
540 }
541
542 void check_iol_DX(void)
543 {
544 check_io(EDX & 0xffff, 4);
545 }
546
547 static inline unsigned int get_sp_mask(unsigned int e2)
548 {
549 if (e2 & DESC_B_MASK)
550 return 0xffffffff;
551 else
552 return 0xffff;
553 }
554
555 /* XXX: add a is_user flag to have proper security support */
556 #define PUSHW(ssp, sp, sp_mask, val)\
557 {\
558 sp -= 2;\
559 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
560 }
561
562 #define PUSHL(ssp, sp, sp_mask, val)\
563 {\
564 sp -= 4;\
565 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
566 }
567
568 #define POPW(ssp, sp, sp_mask, val)\
569 {\
570 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
571 sp += 2;\
572 }
573
574 #define POPL(ssp, sp, sp_mask, val)\
575 {\
576 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
577 sp += 4;\
578 }
579
580 /* protected mode interrupt */
581 static void do_interrupt_protected(int intno, int is_int, int error_code,
582 unsigned int next_eip, int is_hw)
583 {
584 SegmentCache *dt;
585 target_ulong ptr, ssp;
586 int type, dpl, selector, ss_dpl, cpl, sp_mask;
587 int has_error_code, new_stack, shift;
588 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
589 uint32_t old_eip;
590
591 has_error_code = 0;
592 if (!is_int && !is_hw) {
593 switch(intno) {
594 case 8:
595 case 10:
596 case 11:
597 case 12:
598 case 13:
599 case 14:
600 case 17:
601 has_error_code = 1;
602 break;
603 }
604 }
605 if (is_int)
606 old_eip = next_eip;
607 else
608 old_eip = env->eip;
609
610 dt = &env->idt;
611 if (intno * 8 + 7 > dt->limit)
612 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
613 ptr = dt->base + intno * 8;
614 e1 = ldl_kernel(ptr);
615 e2 = ldl_kernel(ptr + 4);
616 /* check gate type */
617 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
618 switch(type) {
619 case 5: /* task gate */
620 /* must do that check here to return the correct error code */
621 if (!(e2 & DESC_P_MASK))
622 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
623 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
624 if (has_error_code) {
625 int mask, type;
626 /* push the error code */
627 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
628 shift = type >> 3;
629 if (env->segs[R_SS].flags & DESC_B_MASK)
630 mask = 0xffffffff;
631 else
632 mask = 0xffff;
633 esp = (ESP - (2 << shift)) & mask;
634 ssp = env->segs[R_SS].base + esp;
635 if (shift)
636 stl_kernel(ssp, error_code);
637 else
638 stw_kernel(ssp, error_code);
639 ESP = (esp & mask) | (ESP & ~mask);
640 }
641 return;
642 case 6: /* 286 interrupt gate */
643 case 7: /* 286 trap gate */
644 case 14: /* 386 interrupt gate */
645 case 15: /* 386 trap gate */
646 break;
647 default:
648 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
649 break;
650 }
651 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
652 cpl = env->hflags & HF_CPL_MASK;
653 /* check privledge if software int */
654 if (is_int && dpl < cpl)
655 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
656 /* check valid bit */
657 if (!(e2 & DESC_P_MASK))
658 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
659 selector = e1 >> 16;
660 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
661 if ((selector & 0xfffc) == 0)
662 raise_exception_err(EXCP0D_GPF, 0);
663
664 if (load_segment(&e1, &e2, selector) != 0)
665 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
666 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
667 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
668 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
669 if (dpl > cpl)
670 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
671 if (!(e2 & DESC_P_MASK))
672 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
673 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
674 /* to inner priviledge */
675 get_ss_esp_from_tss(&ss, &esp, dpl);
676 if ((ss & 0xfffc) == 0)
677 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
678 if ((ss & 3) != dpl)
679 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
680 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
681 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
682 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
683 if (ss_dpl != dpl)
684 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
685 if (!(ss_e2 & DESC_S_MASK) ||
686 (ss_e2 & DESC_CS_MASK) ||
687 !(ss_e2 & DESC_W_MASK))
688 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
689 if (!(ss_e2 & DESC_P_MASK))
690 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
691 new_stack = 1;
692 sp_mask = get_sp_mask(ss_e2);
693 ssp = get_seg_base(ss_e1, ss_e2);
694 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
695 /* to same priviledge */
696 if (env->eflags & VM_MASK)
697 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
698 new_stack = 0;
699 sp_mask = get_sp_mask(env->segs[R_SS].flags);
700 ssp = env->segs[R_SS].base;
701 esp = ESP;
702 dpl = cpl;
703 } else {
704 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
705 new_stack = 0; /* avoid warning */
706 sp_mask = 0; /* avoid warning */
707 ssp = 0; /* avoid warning */
708 esp = 0; /* avoid warning */
709 }
710
711 shift = type >> 3;
712
713 #if 0
714 /* XXX: check that enough room is available */
715 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
716 if (env->eflags & VM_MASK)
717 push_size += 8;
718 push_size <<= shift;
719 #endif
720 if (shift == 1) {
721 if (new_stack) {
722 if (env->eflags & VM_MASK) {
723 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
724 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
725 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
726 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
727 }
728 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
729 PUSHL(ssp, esp, sp_mask, ESP);
730 }
731 PUSHL(ssp, esp, sp_mask, compute_eflags());
732 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
733 PUSHL(ssp, esp, sp_mask, old_eip);
734 if (has_error_code) {
735 PUSHL(ssp, esp, sp_mask, error_code);
736 }
737 } else {
738 if (new_stack) {
739 if (env->eflags & VM_MASK) {
740 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
741 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
742 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
743 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
744 }
745 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
746 PUSHW(ssp, esp, sp_mask, ESP);
747 }
748 PUSHW(ssp, esp, sp_mask, compute_eflags());
749 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
750 PUSHW(ssp, esp, sp_mask, old_eip);
751 if (has_error_code) {
752 PUSHW(ssp, esp, sp_mask, error_code);
753 }
754 }
755
756 if (new_stack) {
757 if (env->eflags & VM_MASK) {
758 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
759 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
760 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
761 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
762 }
763 ss = (ss & ~3) | dpl;
764 cpu_x86_load_seg_cache(env, R_SS, ss,
765 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
766 }
767 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
768
769 selector = (selector & ~3) | dpl;
770 cpu_x86_load_seg_cache(env, R_CS, selector,
771 get_seg_base(e1, e2),
772 get_seg_limit(e1, e2),
773 e2);
774 cpu_x86_set_cpl(env, dpl);
775 env->eip = offset;
776
777 /* interrupt gate clear IF mask */
778 if ((type & 1) == 0) {
779 env->eflags &= ~IF_MASK;
780 }
781 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
782 }
783
784 #ifdef TARGET_X86_64
785
786 #define PUSHQ(sp, val)\
787 {\
788 sp -= 8;\
789 stq_kernel(sp, (val));\
790 }
791
792 #define POPQ(sp, val)\
793 {\
794 val = ldq_kernel(sp);\
795 sp += 8;\
796 }
797
798 static inline target_ulong get_rsp_from_tss(int level)
799 {
800 int index;
801
802 #if 0
803 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
804 env->tr.base, env->tr.limit);
805 #endif
806
807 if (!(env->tr.flags & DESC_P_MASK))
808 cpu_abort(env, "invalid tss");
809 index = 8 * level + 4;
810 if ((index + 7) > env->tr.limit)
811 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
812 return ldq_kernel(env->tr.base + index);
813 }
814
815 /* 64 bit interrupt */
816 static void do_interrupt64(int intno, int is_int, int error_code,
817 target_ulong next_eip, int is_hw)
818 {
819 SegmentCache *dt;
820 target_ulong ptr;
821 int type, dpl, selector, cpl, ist;
822 int has_error_code, new_stack;
823 uint32_t e1, e2, e3, ss;
824 target_ulong old_eip, esp, offset;
825
826 has_error_code = 0;
827 if (!is_int && !is_hw) {
828 switch(intno) {
829 case 8:
830 case 10:
831 case 11:
832 case 12:
833 case 13:
834 case 14:
835 case 17:
836 has_error_code = 1;
837 break;
838 }
839 }
840 if (is_int)
841 old_eip = next_eip;
842 else
843 old_eip = env->eip;
844
845 dt = &env->idt;
846 if (intno * 16 + 15 > dt->limit)
847 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
848 ptr = dt->base + intno * 16;
849 e1 = ldl_kernel(ptr);
850 e2 = ldl_kernel(ptr + 4);
851 e3 = ldl_kernel(ptr + 8);
852 /* check gate type */
853 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
854 switch(type) {
855 case 14: /* 386 interrupt gate */
856 case 15: /* 386 trap gate */
857 break;
858 default:
859 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
860 break;
861 }
862 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
863 cpl = env->hflags & HF_CPL_MASK;
864 /* check privledge if software int */
865 if (is_int && dpl < cpl)
866 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
867 /* check valid bit */
868 if (!(e2 & DESC_P_MASK))
869 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
870 selector = e1 >> 16;
871 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
872 ist = e2 & 7;
873 if ((selector & 0xfffc) == 0)
874 raise_exception_err(EXCP0D_GPF, 0);
875
876 if (load_segment(&e1, &e2, selector) != 0)
877 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
878 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
879 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
880 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
881 if (dpl > cpl)
882 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
883 if (!(e2 & DESC_P_MASK))
884 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
885 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
886 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
887 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
888 /* to inner priviledge */
889 if (ist != 0)
890 esp = get_rsp_from_tss(ist + 3);
891 else
892 esp = get_rsp_from_tss(dpl);
893 ss = 0;
894 new_stack = 1;
895 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
896 /* to same priviledge */
897 if (env->eflags & VM_MASK)
898 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
899 new_stack = 0;
900 esp = ESP & ~0xf; /* align stack */
901 dpl = cpl;
902 } else {
903 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
904 new_stack = 0; /* avoid warning */
905 esp = 0; /* avoid warning */
906 }
907
908 PUSHQ(esp, env->segs[R_SS].selector);
909 PUSHQ(esp, ESP);
910 PUSHQ(esp, compute_eflags());
911 PUSHQ(esp, env->segs[R_CS].selector);
912 PUSHQ(esp, old_eip);
913 if (has_error_code) {
914 PUSHQ(esp, error_code);
915 }
916
917 if (new_stack) {
918 ss = 0 | dpl;
919 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
920 }
921 ESP = esp;
922
923 selector = (selector & ~3) | dpl;
924 cpu_x86_load_seg_cache(env, R_CS, selector,
925 get_seg_base(e1, e2),
926 get_seg_limit(e1, e2),
927 e2);
928 cpu_x86_set_cpl(env, dpl);
929 env->eip = offset;
930
931 /* interrupt gate clear IF mask */
932 if ((type & 1) == 0) {
933 env->eflags &= ~IF_MASK;
934 }
935 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
936 }
937 #endif
938
939 void helper_syscall(int next_eip_addend)
940 {
941 int selector;
942
943 if (!(env->efer & MSR_EFER_SCE)) {
944 raise_exception_err(EXCP06_ILLOP, 0);
945 }
946 selector = (env->star >> 32) & 0xffff;
947 #ifdef TARGET_X86_64
948 if (env->hflags & HF_LMA_MASK) {
949 ECX = env->eip + next_eip_addend;
950 env->regs[11] = compute_eflags();
951
952 cpu_x86_set_cpl(env, 0);
953 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
954 0, 0xffffffff,
955 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
956 DESC_S_MASK |
957 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
958 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
959 0, 0xffffffff,
960 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
961 DESC_S_MASK |
962 DESC_W_MASK | DESC_A_MASK);
963 env->eflags &= ~env->fmask;
964 if (env->hflags & HF_CS64_MASK)
965 env->eip = env->lstar;
966 else
967 env->eip = env->cstar;
968 } else
969 #endif
970 {
971 ECX = (uint32_t)(env->eip + next_eip_addend);
972
973 cpu_x86_set_cpl(env, 0);
974 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
975 0, 0xffffffff,
976 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
977 DESC_S_MASK |
978 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
979 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
980 0, 0xffffffff,
981 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
982 DESC_S_MASK |
983 DESC_W_MASK | DESC_A_MASK);
984 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
985 env->eip = (uint32_t)env->star;
986 }
987 }
988
989 void helper_sysret(int dflag)
990 {
991 int cpl, selector;
992
993 if (!(env->efer & MSR_EFER_SCE)) {
994 raise_exception_err(EXCP06_ILLOP, 0);
995 }
996 cpl = env->hflags & HF_CPL_MASK;
997 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
998 raise_exception_err(EXCP0D_GPF, 0);
999 }
1000 selector = (env->star >> 48) & 0xffff;
1001 #ifdef TARGET_X86_64
1002 if (env->hflags & HF_LMA_MASK) {
1003 if (dflag == 2) {
1004 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1005 0, 0xffffffff,
1006 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1007 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1008 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1009 DESC_L_MASK);
1010 env->eip = ECX;
1011 } else {
1012 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1013 0, 0xffffffff,
1014 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1015 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1016 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1017 env->eip = (uint32_t)ECX;
1018 }
1019 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1020 0, 0xffffffff,
1021 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1022 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1023 DESC_W_MASK | DESC_A_MASK);
1024 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1025 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1026 cpu_x86_set_cpl(env, 3);
1027 } else
1028 #endif
1029 {
1030 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1031 0, 0xffffffff,
1032 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1033 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1034 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1035 env->eip = (uint32_t)ECX;
1036 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1037 0, 0xffffffff,
1038 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1039 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1040 DESC_W_MASK | DESC_A_MASK);
1041 env->eflags |= IF_MASK;
1042 cpu_x86_set_cpl(env, 3);
1043 }
1044 #ifdef USE_KQEMU
1045 if (kqemu_is_ok(env)) {
1046 if (env->hflags & HF_LMA_MASK)
1047 CC_OP = CC_OP_EFLAGS;
1048 env->exception_index = -1;
1049 cpu_loop_exit();
1050 }
1051 #endif
1052 }
1053
1054 /* real mode interrupt */
1055 static void do_interrupt_real(int intno, int is_int, int error_code,
1056 unsigned int next_eip)
1057 {
1058 SegmentCache *dt;
1059 target_ulong ptr, ssp;
1060 int selector;
1061 uint32_t offset, esp;
1062 uint32_t old_cs, old_eip;
1063
1064 /* real mode (simpler !) */
1065 dt = &env->idt;
1066 if (intno * 4 + 3 > dt->limit)
1067 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1068 ptr = dt->base + intno * 4;
1069 offset = lduw_kernel(ptr);
1070 selector = lduw_kernel(ptr + 2);
1071 esp = ESP;
1072 ssp = env->segs[R_SS].base;
1073 if (is_int)
1074 old_eip = next_eip;
1075 else
1076 old_eip = env->eip;
1077 old_cs = env->segs[R_CS].selector;
1078 /* XXX: use SS segment size ? */
1079 PUSHW(ssp, esp, 0xffff, compute_eflags());
1080 PUSHW(ssp, esp, 0xffff, old_cs);
1081 PUSHW(ssp, esp, 0xffff, old_eip);
1082
1083 /* update processor state */
1084 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1085 env->eip = offset;
1086 env->segs[R_CS].selector = selector;
1087 env->segs[R_CS].base = (selector << 4);
1088 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1089 }
1090
1091 /* fake user mode interrupt */
1092 void do_interrupt_user(int intno, int is_int, int error_code,
1093 target_ulong next_eip)
1094 {
1095 SegmentCache *dt;
1096 target_ulong ptr;
1097 int dpl, cpl;
1098 uint32_t e2;
1099
1100 dt = &env->idt;
1101 ptr = dt->base + (intno * 8);
1102 e2 = ldl_kernel(ptr + 4);
1103
1104 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1105 cpl = env->hflags & HF_CPL_MASK;
1106 /* check privledge if software int */
1107 if (is_int && dpl < cpl)
1108 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1109
1110 /* Since we emulate only user space, we cannot do more than
1111 exiting the emulation with the suitable exception and error
1112 code */
1113 if (is_int)
1114 EIP = next_eip;
1115 }
1116
1117 /*
1118 * Begin execution of an interruption. is_int is TRUE if coming from
1119 * the int instruction. next_eip is the EIP value AFTER the interrupt
1120 * instruction. It is only relevant if is_int is TRUE.
1121 */
1122 void do_interrupt(int intno, int is_int, int error_code,
1123 target_ulong next_eip, int is_hw)
1124 {
1125 if (loglevel & CPU_LOG_INT) {
1126 if ((env->cr[0] & CR0_PE_MASK)) {
1127 static int count;
1128 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1129 count, intno, error_code, is_int,
1130 env->hflags & HF_CPL_MASK,
1131 env->segs[R_CS].selector, EIP,
1132 (int)env->segs[R_CS].base + EIP,
1133 env->segs[R_SS].selector, ESP);
1134 if (intno == 0x0e) {
1135 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1136 } else {
1137 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1138 }
1139 fprintf(logfile, "\n");
1140 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1141 #if 0
1142 {
1143 int i;
1144 uint8_t *ptr;
1145 fprintf(logfile, " code=");
1146 ptr = env->segs[R_CS].base + env->eip;
1147 for(i = 0; i < 16; i++) {
1148 fprintf(logfile, " %02x", ldub(ptr + i));
1149 }
1150 fprintf(logfile, "\n");
1151 }
1152 #endif
1153 count++;
1154 }
1155 }
1156 if (env->cr[0] & CR0_PE_MASK) {
1157 #if TARGET_X86_64
1158 if (env->hflags & HF_LMA_MASK) {
1159 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1160 } else
1161 #endif
1162 {
1163 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1164 }
1165 } else {
1166 do_interrupt_real(intno, is_int, error_code, next_eip);
1167 }
1168 }
1169
1170 /*
1171 * Signal an interruption. It is executed in the main CPU loop.
1172 * is_int is TRUE if coming from the int instruction. next_eip is the
1173 * EIP value AFTER the interrupt instruction. It is only relevant if
1174 * is_int is TRUE.
1175 */
1176 void raise_interrupt(int intno, int is_int, int error_code,
1177 int next_eip_addend)
1178 {
1179 env->exception_index = intno;
1180 env->error_code = error_code;
1181 env->exception_is_int = is_int;
1182 env->exception_next_eip = env->eip + next_eip_addend;
1183 cpu_loop_exit();
1184 }
1185
1186 /* same as raise_exception_err, but do not restore global registers */
1187 static void raise_exception_err_norestore(int exception_index, int error_code)
1188 {
1189 env->exception_index = exception_index;
1190 env->error_code = error_code;
1191 env->exception_is_int = 0;
1192 env->exception_next_eip = 0;
1193 longjmp(env->jmp_env, 1);
1194 }
1195
1196 /* shortcuts to generate exceptions */
1197
1198 void (raise_exception_err)(int exception_index, int error_code)
1199 {
1200 raise_interrupt(exception_index, 0, error_code, 0);
1201 }
1202
1203 void raise_exception(int exception_index)
1204 {
1205 raise_interrupt(exception_index, 0, 0, 0);
1206 }
1207
1208 #ifdef BUGGY_GCC_DIV64
1209 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1210 call it from another function */
1211 uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1212 {
1213 *q_ptr = num / den;
1214 return num % den;
1215 }
1216
1217 int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1218 {
1219 *q_ptr = num / den;
1220 return num % den;
1221 }
1222 #endif
1223
1224 void helper_divl_EAX_T0(void)
1225 {
1226 unsigned int den, r;
1227 uint64_t num, q;
1228
1229 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1230 den = T0;
1231 if (den == 0) {
1232 raise_exception(EXCP00_DIVZ);
1233 }
1234 #ifdef BUGGY_GCC_DIV64
1235 r = div32(&q, num, den);
1236 #else
1237 q = (num / den);
1238 r = (num % den);
1239 #endif
1240 if (q > 0xffffffff)
1241 raise_exception(EXCP00_DIVZ);
1242 EAX = (uint32_t)q;
1243 EDX = (uint32_t)r;
1244 }
1245
1246 void helper_idivl_EAX_T0(void)
1247 {
1248 int den, r;
1249 int64_t num, q;
1250
1251 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1252 den = T0;
1253 if (den == 0) {
1254 raise_exception(EXCP00_DIVZ);
1255 }
1256 #ifdef BUGGY_GCC_DIV64
1257 r = idiv32(&q, num, den);
1258 #else
1259 q = (num / den);
1260 r = (num % den);
1261 #endif
1262 if (q != (int32_t)q)
1263 raise_exception(EXCP00_DIVZ);
1264 EAX = (uint32_t)q;
1265 EDX = (uint32_t)r;
1266 }
1267
1268 void helper_cmpxchg8b(void)
1269 {
1270 uint64_t d;
1271 int eflags;
1272
1273 eflags = cc_table[CC_OP].compute_all();
1274 d = ldq(A0);
1275 if (d == (((uint64_t)EDX << 32) | EAX)) {
1276 stq(A0, ((uint64_t)ECX << 32) | EBX);
1277 eflags |= CC_Z;
1278 } else {
1279 EDX = d >> 32;
1280 EAX = d;
1281 eflags &= ~CC_Z;
1282 }
1283 CC_SRC = eflags;
1284 }
1285
1286 void helper_cpuid(void)
1287 {
1288 uint32_t index;
1289 index = (uint32_t)EAX;
1290
1291 /* test if maximum index reached */
1292 if (index & 0x80000000) {
1293 if (index > env->cpuid_xlevel)
1294 index = env->cpuid_level;
1295 } else {
1296 if (index > env->cpuid_level)
1297 index = env->cpuid_level;
1298 }
1299
1300 switch(index) {
1301 case 0:
1302 EAX = env->cpuid_level;
1303 EBX = env->cpuid_vendor1;
1304 EDX = env->cpuid_vendor2;
1305 ECX = env->cpuid_vendor3;
1306 break;
1307 case 1:
1308 EAX = env->cpuid_version;
1309 EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1310 ECX = env->cpuid_ext_features;
1311 EDX = env->cpuid_features;
1312 break;
1313 case 2:
1314 /* cache info: needed for Pentium Pro compatibility */
1315 EAX = 0x410601;
1316 EBX = 0;
1317 ECX = 0;
1318 EDX = 0;
1319 break;
1320 case 0x80000000:
1321 EAX = env->cpuid_xlevel;
1322 EBX = env->cpuid_vendor1;
1323 EDX = env->cpuid_vendor2;
1324 ECX = env->cpuid_vendor3;
1325 break;
1326 case 0x80000001:
1327 EAX = env->cpuid_features;
1328 EBX = 0;
1329 ECX = 0;
1330 EDX = env->cpuid_ext2_features;
1331 break;
1332 case 0x80000002:
1333 case 0x80000003:
1334 case 0x80000004:
1335 EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1336 EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1337 ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1338 EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1339 break;
1340 case 0x80000005:
1341 /* cache info (L1 cache) */
1342 EAX = 0x01ff01ff;
1343 EBX = 0x01ff01ff;
1344 ECX = 0x40020140;
1345 EDX = 0x40020140;
1346 break;
1347 case 0x80000006:
1348 /* cache info (L2 cache) */
1349 EAX = 0;
1350 EBX = 0x42004200;
1351 ECX = 0x02008140;
1352 EDX = 0;
1353 break;
1354 case 0x80000008:
1355 /* virtual & phys address size in low 2 bytes. */
1356 EAX = 0x00003028;
1357 EBX = 0;
1358 ECX = 0;
1359 EDX = 0;
1360 break;
1361 default:
1362 /* reserved values: zero */
1363 EAX = 0;
1364 EBX = 0;
1365 ECX = 0;
1366 EDX = 0;
1367 break;
1368 }
1369 }
1370
1371 void helper_enter_level(int level, int data32)
1372 {
1373 target_ulong ssp;
1374 uint32_t esp_mask, esp, ebp;
1375
1376 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1377 ssp = env->segs[R_SS].base;
1378 ebp = EBP;
1379 esp = ESP;
1380 if (data32) {
1381 /* 32 bit */
1382 esp -= 4;
1383 while (--level) {
1384 esp -= 4;
1385 ebp -= 4;
1386 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1387 }
1388 esp -= 4;
1389 stl(ssp + (esp & esp_mask), T1);
1390 } else {
1391 /* 16 bit */
1392 esp -= 2;
1393 while (--level) {
1394 esp -= 2;
1395 ebp -= 2;
1396 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1397 }
1398 esp -= 2;
1399 stw(ssp + (esp & esp_mask), T1);
1400 }
1401 }
1402
1403 #ifdef TARGET_X86_64
1404 void helper_enter64_level(int level, int data64)
1405 {
1406 target_ulong esp, ebp;
1407 ebp = EBP;
1408 esp = ESP;
1409
1410 if (data64) {
1411 /* 64 bit */
1412 esp -= 8;
1413 while (--level) {
1414 esp -= 8;
1415 ebp -= 8;
1416 stq(esp, ldq(ebp));
1417 }
1418 esp -= 8;
1419 stq(esp, T1);
1420 } else {
1421 /* 16 bit */
1422 esp -= 2;
1423 while (--level) {
1424 esp -= 2;
1425 ebp -= 2;
1426 stw(esp, lduw(ebp));
1427 }
1428 esp -= 2;
1429 stw(esp, T1);
1430 }
1431 }
1432 #endif
1433
1434 void helper_lldt_T0(void)
1435 {
1436 int selector;
1437 SegmentCache *dt;
1438 uint32_t e1, e2;
1439 int index, entry_limit;
1440 target_ulong ptr;
1441
1442 selector = T0 & 0xffff;
1443 if ((selector & 0xfffc) == 0) {
1444 /* XXX: NULL selector case: invalid LDT */
1445 env->ldt.base = 0;
1446 env->ldt.limit = 0;
1447 } else {
1448 if (selector & 0x4)
1449 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1450 dt = &env->gdt;
1451 index = selector & ~7;
1452 #ifdef TARGET_X86_64
1453 if (env->hflags & HF_LMA_MASK)
1454 entry_limit = 15;
1455 else
1456 #endif
1457 entry_limit = 7;
1458 if ((index + entry_limit) > dt->limit)
1459 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1460 ptr = dt->base + index;
1461 e1 = ldl_kernel(ptr);
1462 e2 = ldl_kernel(ptr + 4);
1463 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1464 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1465 if (!(e2 & DESC_P_MASK))
1466 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1467 #ifdef TARGET_X86_64
1468 if (env->hflags & HF_LMA_MASK) {
1469 uint32_t e3;
1470 e3 = ldl_kernel(ptr + 8);
1471 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1472 env->ldt.base |= (target_ulong)e3 << 32;
1473 } else
1474 #endif
1475 {
1476 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1477 }
1478 }
1479 env->ldt.selector = selector;
1480 }
1481
1482 void helper_ltr_T0(void)
1483 {
1484 int selector;
1485 SegmentCache *dt;
1486 uint32_t e1, e2;
1487 int index, type, entry_limit;
1488 target_ulong ptr;
1489
1490 selector = T0 & 0xffff;
1491 if ((selector & 0xfffc) == 0) {
1492 /* NULL selector case: invalid TR */
1493 env->tr.base = 0;
1494 env->tr.limit = 0;
1495 env->tr.flags = 0;
1496 } else {
1497 if (selector & 0x4)
1498 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1499 dt = &env->gdt;
1500 index = selector & ~7;
1501 #ifdef TARGET_X86_64
1502 if (env->hflags & HF_LMA_MASK)
1503 entry_limit = 15;
1504 else
1505 #endif
1506 entry_limit = 7;
1507 if ((index + entry_limit) > dt->limit)
1508 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1509 ptr = dt->base + index;
1510 e1 = ldl_kernel(ptr);
1511 e2 = ldl_kernel(ptr + 4);
1512 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1513 if ((e2 & DESC_S_MASK) ||
1514 (type != 1 && type != 9))
1515 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1516 if (!(e2 & DESC_P_MASK))
1517 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1518 #ifdef TARGET_X86_64
1519 if (env->hflags & HF_LMA_MASK) {
1520 uint32_t e3;
1521 e3 = ldl_kernel(ptr + 8);
1522 load_seg_cache_raw_dt(&env->tr, e1, e2);
1523 env->tr.base |= (target_ulong)e3 << 32;
1524 } else
1525 #endif
1526 {
1527 load_seg_cache_raw_dt(&env->tr, e1, e2);
1528 }
1529 e2 |= DESC_TSS_BUSY_MASK;
1530 stl_kernel(ptr + 4, e2);
1531 }
1532 env->tr.selector = selector;
1533 }
1534
1535 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1536 void load_seg(int seg_reg, int selector)
1537 {
1538 uint32_t e1, e2;
1539 int cpl, dpl, rpl;
1540 SegmentCache *dt;
1541 int index;
1542 target_ulong ptr;
1543
1544 selector &= 0xffff;
1545 cpl = env->hflags & HF_CPL_MASK;
1546 if ((selector & 0xfffc) == 0) {
1547 /* null selector case */
1548 if (seg_reg == R_SS
1549 #ifdef TARGET_X86_64
1550 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1551 #endif
1552 )
1553 raise_exception_err(EXCP0D_GPF, 0);
1554 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1555 } else {
1556
1557 if (selector & 0x4)
1558 dt = &env->ldt;
1559 else
1560 dt = &env->gdt;
1561 index = selector & ~7;
1562 if ((index + 7) > dt->limit)
1563 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1564 ptr = dt->base + index;
1565 e1 = ldl_kernel(ptr);
1566 e2 = ldl_kernel(ptr + 4);
1567
1568 if (!(e2 & DESC_S_MASK))
1569 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1570 rpl = selector & 3;
1571 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1572 if (seg_reg == R_SS) {
1573 /* must be writable segment */
1574 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1575 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1576 if (rpl != cpl || dpl != cpl)
1577 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1578 } else {
1579 /* must be readable segment */
1580 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1581 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1582
1583 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1584 /* if not conforming code, test rights */
1585 if (dpl < cpl || dpl < rpl)
1586 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1587 }
1588 }
1589
1590 if (!(e2 & DESC_P_MASK)) {
1591 if (seg_reg == R_SS)
1592 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1593 else
1594 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1595 }
1596
1597 /* set the access bit if not already set */
1598 if (!(e2 & DESC_A_MASK)) {
1599 e2 |= DESC_A_MASK;
1600 stl_kernel(ptr + 4, e2);
1601 }
1602
1603 cpu_x86_load_seg_cache(env, seg_reg, selector,
1604 get_seg_base(e1, e2),
1605 get_seg_limit(e1, e2),
1606 e2);
1607 #if 0
1608 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1609 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1610 #endif
1611 }
1612 }
1613
1614 /* protected mode jump */
1615 void helper_ljmp_protected_T0_T1(int next_eip_addend)
1616 {
1617 int new_cs, gate_cs, type;
1618 uint32_t e1, e2, cpl, dpl, rpl, limit;
1619 target_ulong new_eip, next_eip;
1620
1621 new_cs = T0;
1622 new_eip = T1;
1623 if ((new_cs & 0xfffc) == 0)
1624 raise_exception_err(EXCP0D_GPF, 0);
1625 if (load_segment(&e1, &e2, new_cs) != 0)
1626 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1627 cpl = env->hflags & HF_CPL_MASK;
1628 if (e2 & DESC_S_MASK) {
1629 if (!(e2 & DESC_CS_MASK))
1630 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1631 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1632 if (e2 & DESC_C_MASK) {
1633 /* conforming code segment */
1634 if (dpl > cpl)
1635 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1636 } else {
1637 /* non conforming code segment */
1638 rpl = new_cs & 3;
1639 if (rpl > cpl)
1640 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1641 if (dpl != cpl)
1642 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1643 }
1644 if (!(e2 & DESC_P_MASK))
1645 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1646 limit = get_seg_limit(e1, e2);
1647 if (new_eip > limit &&
1648 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1649 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1650 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1651 get_seg_base(e1, e2), limit, e2);
1652 EIP = new_eip;
1653 } else {
1654 /* jump to call or task gate */
1655 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1656 rpl = new_cs & 3;
1657 cpl = env->hflags & HF_CPL_MASK;
1658 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1659 switch(type) {
1660 case 1: /* 286 TSS */
1661 case 9: /* 386 TSS */
1662 case 5: /* task gate */
1663 if (dpl < cpl || dpl < rpl)
1664 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1665 next_eip = env->eip + next_eip_addend;
1666 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1667 break;
1668 case 4: /* 286 call gate */
1669 case 12: /* 386 call gate */
1670 if ((dpl < cpl) || (dpl < rpl))
1671 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1672 if (!(e2 & DESC_P_MASK))
1673 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1674 gate_cs = e1 >> 16;
1675 new_eip = (e1 & 0xffff);
1676 if (type == 12)
1677 new_eip |= (e2 & 0xffff0000);
1678 if (load_segment(&e1, &e2, gate_cs) != 0)
1679 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1680 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1681 /* must be code segment */
1682 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1683 (DESC_S_MASK | DESC_CS_MASK)))
1684 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1685 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1686 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1687 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1688 if (!(e2 & DESC_P_MASK))
1689 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1690 limit = get_seg_limit(e1, e2);
1691 if (new_eip > limit)
1692 raise_exception_err(EXCP0D_GPF, 0);
1693 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1694 get_seg_base(e1, e2), limit, e2);
1695 EIP = new_eip;
1696 break;
1697 default:
1698 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1699 break;
1700 }
1701 }
1702 }
1703
1704 /* real mode call */
1705 void helper_lcall_real_T0_T1(int shift, int next_eip)
1706 {
1707 int new_cs, new_eip;
1708 uint32_t esp, esp_mask;
1709 target_ulong ssp;
1710
1711 new_cs = T0;
1712 new_eip = T1;
1713 esp = ESP;
1714 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1715 ssp = env->segs[R_SS].base;
1716 if (shift) {
1717 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1718 PUSHL(ssp, esp, esp_mask, next_eip);
1719 } else {
1720 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1721 PUSHW(ssp, esp, esp_mask, next_eip);
1722 }
1723
1724 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
1725 env->eip = new_eip;
1726 env->segs[R_CS].selector = new_cs;
1727 env->segs[R_CS].base = (new_cs << 4);
1728 }
1729
1730 /* protected mode call */
1731 void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
1732 {
1733 int new_cs, new_stack, i;
1734 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1735 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
1736 uint32_t val, limit, old_sp_mask;
1737 target_ulong ssp, old_ssp, next_eip, new_eip;
1738
1739 new_cs = T0;
1740 new_eip = T1;
1741 next_eip = env->eip + next_eip_addend;
1742 #ifdef DEBUG_PCALL
1743 if (loglevel & CPU_LOG_PCALL) {
1744 fprintf(logfile, "lcall %04x:%08x s=%d\n",
1745 new_cs, (uint32_t)new_eip, shift);
1746 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1747 }
1748 #endif
1749 if ((new_cs & 0xfffc) == 0)
1750 raise_exception_err(EXCP0D_GPF, 0);
1751 if (load_segment(&e1, &e2, new_cs) != 0)
1752 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1753 cpl = env->hflags & HF_CPL_MASK;
1754 #ifdef DEBUG_PCALL
1755 if (loglevel & CPU_LOG_PCALL) {
1756 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
1757 }
1758 #endif
1759 if (e2 & DESC_S_MASK) {
1760 if (!(e2 & DESC_CS_MASK))
1761 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1762 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1763 if (e2 & DESC_C_MASK) {
1764 /* conforming code segment */
1765 if (dpl > cpl)
1766 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1767 } else {
1768 /* non conforming code segment */
1769 rpl = new_cs & 3;
1770 if (rpl > cpl)
1771 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1772 if (dpl != cpl)
1773 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1774 }
1775 if (!(e2 & DESC_P_MASK))
1776 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1777
1778 #ifdef TARGET_X86_64
1779 /* XXX: check 16/32 bit cases in long mode */
1780 if (shift == 2) {
1781 target_ulong rsp;
1782 /* 64 bit case */
1783 rsp = ESP;
1784 PUSHQ(rsp, env->segs[R_CS].selector);
1785 PUSHQ(rsp, next_eip);
1786 /* from this point, not restartable */
1787 ESP = rsp;
1788 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1789 get_seg_base(e1, e2),
1790 get_seg_limit(e1, e2), e2);
1791 EIP = new_eip;
1792 } else
1793 #endif
1794 {
1795 sp = ESP;
1796 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1797 ssp = env->segs[R_SS].base;
1798 if (shift) {
1799 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1800 PUSHL(ssp, sp, sp_mask, next_eip);
1801 } else {
1802 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1803 PUSHW(ssp, sp, sp_mask, next_eip);
1804 }
1805
1806 limit = get_seg_limit(e1, e2);
1807 if (new_eip > limit)
1808 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1809 /* from this point, not restartable */
1810 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1811 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1812 get_seg_base(e1, e2), limit, e2);
1813 EIP = new_eip;
1814 }
1815 } else {
1816 /* check gate type */
1817 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1818 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1819 rpl = new_cs & 3;
1820 switch(type) {
1821 case 1: /* available 286 TSS */
1822 case 9: /* available 386 TSS */
1823 case 5: /* task gate */
1824 if (dpl < cpl || dpl < rpl)
1825 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1826 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1827 return;
1828 case 4: /* 286 call gate */
1829 case 12: /* 386 call gate */
1830 break;
1831 default:
1832 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1833 break;
1834 }
1835 shift = type >> 3;
1836
1837 if (dpl < cpl || dpl < rpl)
1838 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1839 /* check valid bit */
1840 if (!(e2 & DESC_P_MASK))
1841 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1842 selector = e1 >> 16;
1843 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1844 param_count = e2 & 0x1f;
1845 if ((selector & 0xfffc) == 0)
1846 raise_exception_err(EXCP0D_GPF, 0);
1847
1848 if (load_segment(&e1, &e2, selector) != 0)
1849 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1850 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
1851 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1852 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1853 if (dpl > cpl)
1854 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1855 if (!(e2 & DESC_P_MASK))
1856 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1857
1858 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1859 /* to inner priviledge */
1860 get_ss_esp_from_tss(&ss, &sp, dpl);
1861 #ifdef DEBUG_PCALL
1862 if (loglevel & CPU_LOG_PCALL)
1863 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
1864 ss, sp, param_count, ESP);
1865 #endif
1866 if ((ss & 0xfffc) == 0)
1867 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1868 if ((ss & 3) != dpl)
1869 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1870 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
1871 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1872 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1873 if (ss_dpl != dpl)
1874 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1875 if (!(ss_e2 & DESC_S_MASK) ||
1876 (ss_e2 & DESC_CS_MASK) ||
1877 !(ss_e2 & DESC_W_MASK))
1878 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1879 if (!(ss_e2 & DESC_P_MASK))
1880 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1881
1882 // push_size = ((param_count * 2) + 8) << shift;
1883
1884 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1885 old_ssp = env->segs[R_SS].base;
1886
1887 sp_mask = get_sp_mask(ss_e2);
1888 ssp = get_seg_base(ss_e1, ss_e2);
1889 if (shift) {
1890 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1891 PUSHL(ssp, sp, sp_mask, ESP);
1892 for(i = param_count - 1; i >= 0; i--) {
1893 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
1894 PUSHL(ssp, sp, sp_mask, val);
1895 }
1896 } else {
1897 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1898 PUSHW(ssp, sp, sp_mask, ESP);
1899 for(i = param_count - 1; i >= 0; i--) {
1900 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
1901 PUSHW(ssp, sp, sp_mask, val);
1902 }
1903 }
1904 new_stack = 1;
1905 } else {
1906 /* to same priviledge */
1907 sp = ESP;
1908 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1909 ssp = env->segs[R_SS].base;
1910 // push_size = (4 << shift);
1911 new_stack = 0;
1912 }
1913
1914 if (shift) {
1915 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1916 PUSHL(ssp, sp, sp_mask, next_eip);
1917 } else {
1918 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1919 PUSHW(ssp, sp, sp_mask, next_eip);
1920 }
1921
1922 /* from this point, not restartable */
1923
1924 if (new_stack) {
1925 ss = (ss & ~3) | dpl;
1926 cpu_x86_load_seg_cache(env, R_SS, ss,
1927 ssp,
1928 get_seg_limit(ss_e1, ss_e2),
1929 ss_e2);
1930 }
1931
1932 selector = (selector & ~3) | dpl;
1933 cpu_x86_load_seg_cache(env, R_CS, selector,
1934 get_seg_base(e1, e2),
1935 get_seg_limit(e1, e2),
1936 e2);
1937 cpu_x86_set_cpl(env, dpl);
1938 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1939 EIP = offset;
1940 }
1941 #ifdef USE_KQEMU
1942 if (kqemu_is_ok(env)) {
1943 env->exception_index = -1;
1944 cpu_loop_exit();
1945 }
1946 #endif
1947 }
1948
1949 /* real and vm86 mode iret */
1950 void helper_iret_real(int shift)
1951 {
1952 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1953 target_ulong ssp;
1954 int eflags_mask;
1955
1956 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
1957 sp = ESP;
1958 ssp = env->segs[R_SS].base;
1959 if (shift == 1) {
1960 /* 32 bits */
1961 POPL(ssp, sp, sp_mask, new_eip);
1962 POPL(ssp, sp, sp_mask, new_cs);
1963 new_cs &= 0xffff;
1964 POPL(ssp, sp, sp_mask, new_eflags);
1965 } else {
1966 /* 16 bits */
1967 POPW(ssp, sp, sp_mask, new_eip);
1968 POPW(ssp, sp, sp_mask, new_cs);
1969 POPW(ssp, sp, sp_mask, new_eflags);
1970 }
1971 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1972 load_seg_vm(R_CS, new_cs);
1973 env->eip = new_eip;
1974 if (env->eflags & VM_MASK)
1975 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
1976 else
1977 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
1978 if (shift == 0)
1979 eflags_mask &= 0xffff;
1980 load_eflags(new_eflags, eflags_mask);
1981 }
1982
1983 static inline void validate_seg(int seg_reg, int cpl)
1984 {
1985 int dpl;
1986 uint32_t e2;
1987
1988 /* XXX: on x86_64, we do not want to nullify FS and GS because
1989 they may still contain a valid base. I would be interested to
1990 know how a real x86_64 CPU behaves */
1991 if ((seg_reg == R_FS || seg_reg == R_GS) &&
1992 (env->segs[seg_reg].selector & 0xfffc) == 0)
1993 return;
1994
1995 e2 = env->segs[seg_reg].flags;
1996 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1997 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1998 /* data or non conforming code segment */
1999 if (dpl < cpl) {
2000 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2001 }
2002 }
2003 }
2004
2005 /* protected mode iret */
2006 static inline void helper_ret_protected(int shift, int is_iret, int addend)
2007 {
2008 uint32_t new_cs, new_eflags, new_ss;
2009 uint32_t new_es, new_ds, new_fs, new_gs;
2010 uint32_t e1, e2, ss_e1, ss_e2;
2011 int cpl, dpl, rpl, eflags_mask, iopl;
2012 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2013
2014 #ifdef TARGET_X86_64
2015 if (shift == 2)
2016 sp_mask = -1;
2017 else
2018 #endif
2019 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2020 sp = ESP;
2021 ssp = env->segs[R_SS].base;
2022 new_eflags = 0; /* avoid warning */
2023 #ifdef TARGET_X86_64
2024 if (shift == 2) {
2025 POPQ(sp, new_eip);
2026 POPQ(sp, new_cs);
2027 new_cs &= 0xffff;
2028 if (is_iret) {
2029 POPQ(sp, new_eflags);
2030 }
2031 } else
2032 #endif
2033 if (shift == 1) {
2034 /* 32 bits */
2035 POPL(ssp, sp, sp_mask, new_eip);
2036 POPL(ssp, sp, sp_mask, new_cs);
2037 new_cs &= 0xffff;
2038 if (is_iret) {
2039 POPL(ssp, sp, sp_mask, new_eflags);
2040 if (new_eflags & VM_MASK)
2041 goto return_to_vm86;
2042 }
2043 } else {
2044 /* 16 bits */
2045 POPW(ssp, sp, sp_mask, new_eip);
2046 POPW(ssp, sp, sp_mask, new_cs);
2047 if (is_iret)
2048 POPW(ssp, sp, sp_mask, new_eflags);
2049 }
2050 #ifdef DEBUG_PCALL
2051 if (loglevel & CPU_LOG_PCALL) {
2052 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2053 new_cs, new_eip, shift, addend);
2054 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2055 }
2056 #endif
2057 if ((new_cs & 0xfffc) == 0)
2058 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2059 if (load_segment(&e1, &e2, new_cs) != 0)
2060 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2061 if (!(e2 & DESC_S_MASK) ||
2062 !(e2 & DESC_CS_MASK))
2063 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2064 cpl = env->hflags & HF_CPL_MASK;
2065 rpl = new_cs & 3;
2066 if (rpl < cpl)
2067 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2068 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2069 if (e2 & DESC_C_MASK) {
2070 if (dpl > rpl)
2071 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2072 } else {
2073 if (dpl != rpl)
2074 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2075 }
2076 if (!(e2 & DESC_P_MASK))
2077 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2078
2079 sp += addend;
2080 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2081 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2082 /* return to same priledge level */
2083 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2084 get_seg_base(e1, e2),
2085 get_seg_limit(e1, e2),
2086 e2);
2087 } else {
2088 /* return to different priviledge level */
2089 #ifdef TARGET_X86_64
2090 if (shift == 2) {
2091 POPQ(sp, new_esp);
2092 POPQ(sp, new_ss);
2093 new_ss &= 0xffff;
2094 } else
2095 #endif
2096 if (shift == 1) {
2097 /* 32 bits */
2098 POPL(ssp, sp, sp_mask, new_esp);
2099 POPL(ssp, sp, sp_mask, new_ss);
2100 new_ss &= 0xffff;
2101 } else {
2102 /* 16 bits */
2103 POPW(ssp, sp, sp_mask, new_esp);
2104 POPW(ssp, sp, sp_mask, new_ss);
2105 }
2106 #ifdef DEBUG_PCALL
2107 if (loglevel & CPU_LOG_PCALL) {
2108 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2109 new_ss, new_esp);
2110 }
2111 #endif
2112 if ((new_ss & 0xfffc) == 0) {
2113 #ifdef TARGET_X86_64
2114 /* NULL ss is allowed in long mode if cpl != 3*/
2115 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2116 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2117 0, 0xffffffff,
2118 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2119 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2120 DESC_W_MASK | DESC_A_MASK);
2121 } else
2122 #endif
2123 {
2124 raise_exception_err(EXCP0D_GPF, 0);
2125 }
2126 } else {
2127 if ((new_ss & 3) != rpl)
2128 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2129 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2130 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2131 if (!(ss_e2 & DESC_S_MASK) ||
2132 (ss_e2 & DESC_CS_MASK) ||
2133 !(ss_e2 & DESC_W_MASK))
2134 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2135 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2136 if (dpl != rpl)
2137 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2138 if (!(ss_e2 & DESC_P_MASK))
2139 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2140 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2141 get_seg_base(ss_e1, ss_e2),
2142 get_seg_limit(ss_e1, ss_e2),
2143 ss_e2);
2144 }
2145
2146 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2147 get_seg_base(e1, e2),
2148 get_seg_limit(e1, e2),
2149 e2);
2150 cpu_x86_set_cpl(env, rpl);
2151 sp = new_esp;
2152 #ifdef TARGET_X86_64
2153 if (env->hflags & HF_CS64_MASK)
2154 sp_mask = -1;
2155 else
2156 #endif
2157 sp_mask = get_sp_mask(ss_e2);
2158
2159 /* validate data segments */
2160 validate_seg(R_ES, rpl);
2161 validate_seg(R_DS, rpl);
2162 validate_seg(R_FS, rpl);
2163 validate_seg(R_GS, rpl);
2164
2165 sp += addend;
2166 }
2167 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2168 env->eip = new_eip;
2169 if (is_iret) {
2170 /* NOTE: 'cpl' is the _old_ CPL */
2171 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2172 if (cpl == 0)
2173 eflags_mask |= IOPL_MASK;
2174 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2175 if (cpl <= iopl)
2176 eflags_mask |= IF_MASK;
2177 if (shift == 0)
2178 eflags_mask &= 0xffff;
2179 load_eflags(new_eflags, eflags_mask);
2180 }
2181 return;
2182
2183 return_to_vm86:
2184 POPL(ssp, sp, sp_mask, new_esp);
2185 POPL(ssp, sp, sp_mask, new_ss);
2186 POPL(ssp, sp, sp_mask, new_es);
2187 POPL(ssp, sp, sp_mask, new_ds);
2188 POPL(ssp, sp, sp_mask, new_fs);
2189 POPL(ssp, sp, sp_mask, new_gs);
2190
2191 /* modify processor state */
2192 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2193 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2194 load_seg_vm(R_CS, new_cs & 0xffff);
2195 cpu_x86_set_cpl(env, 3);
2196 load_seg_vm(R_SS, new_ss & 0xffff);
2197 load_seg_vm(R_ES, new_es & 0xffff);
2198 load_seg_vm(R_DS, new_ds & 0xffff);
2199 load_seg_vm(R_FS, new_fs & 0xffff);
2200 load_seg_vm(R_GS, new_gs & 0xffff);
2201
2202 env->eip = new_eip & 0xffff;
2203 ESP = new_esp;
2204 }
2205
2206 void helper_iret_protected(int shift, int next_eip)
2207 {
2208 int tss_selector, type;
2209 uint32_t e1, e2;
2210
2211 /* specific case for TSS */
2212 if (env->eflags & NT_MASK) {
2213 #ifdef TARGET_X86_64
2214 if (env->hflags & HF_LMA_MASK)
2215 raise_exception_err(EXCP0D_GPF, 0);
2216 #endif
2217 tss_selector = lduw_kernel(env->tr.base + 0);
2218 if (tss_selector & 4)
2219 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2220 if (load_segment(&e1, &e2, tss_selector) != 0)
2221 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2222 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2223 /* NOTE: we check both segment and busy TSS */
2224 if (type != 3)
2225 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2226 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2227 } else {
2228 helper_ret_protected(shift, 1, 0);
2229 }
2230 #ifdef USE_KQEMU
2231 if (kqemu_is_ok(env)) {
2232 CC_OP = CC_OP_EFLAGS;
2233 env->exception_index = -1;
2234 cpu_loop_exit();
2235 }
2236 #endif
2237 }
2238
2239 void helper_lret_protected(int shift, int addend)
2240 {
2241 helper_ret_protected(shift, 0, addend);
2242 #ifdef USE_KQEMU
2243 if (kqemu_is_ok(env)) {
2244 env->exception_index = -1;
2245 cpu_loop_exit();
2246 }
2247 #endif
2248 }
2249
2250 void helper_sysenter(void)
2251 {
2252 if (env->sysenter_cs == 0) {
2253 raise_exception_err(EXCP0D_GPF, 0);
2254 }
2255 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2256 cpu_x86_set_cpl(env, 0);
2257 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2258 0, 0xffffffff,
2259 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2260 DESC_S_MASK |
2261 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2262 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2263 0, 0xffffffff,
2264 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2265 DESC_S_MASK |
2266 DESC_W_MASK | DESC_A_MASK);
2267 ESP = env->sysenter_esp;
2268 EIP = env->sysenter_eip;
2269 }
2270
2271 void helper_sysexit(void)
2272 {
2273 int cpl;
2274
2275 cpl = env->hflags & HF_CPL_MASK;
2276 if (env->sysenter_cs == 0 || cpl != 0) {
2277 raise_exception_err(EXCP0D_GPF, 0);
2278 }
2279 cpu_x86_set_cpl(env, 3);
2280 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2281 0, 0xffffffff,
2282 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2283 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2284 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2285 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2286 0, 0xffffffff,
2287 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2288 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2289 DESC_W_MASK | DESC_A_MASK);
2290 ESP = ECX;
2291 EIP = EDX;
2292 #ifdef USE_KQEMU
2293 if (kqemu_is_ok(env)) {
2294 env->exception_index = -1;
2295 cpu_loop_exit();
2296 }
2297 #endif
2298 }
2299
2300 void helper_movl_crN_T0(int reg)
2301 {
2302 #if !defined(CONFIG_USER_ONLY)
2303 switch(reg) {
2304 case 0:
2305 cpu_x86_update_cr0(env, T0);
2306 break;
2307 case 3:
2308 cpu_x86_update_cr3(env, T0);
2309 break;
2310 case 4:
2311 cpu_x86_update_cr4(env, T0);
2312 break;
2313 case 8:
2314 cpu_set_apic_tpr(env, T0);
2315 break;
2316 default:
2317 env->cr[reg] = T0;
2318 break;
2319 }
2320 #endif
2321 }
2322
2323 /* XXX: do more */
2324 void helper_movl_drN_T0(int reg)
2325 {
2326 env->dr[reg] = T0;
2327 }
2328
2329 void helper_invlpg(target_ulong addr)
2330 {
2331 cpu_x86_flush_tlb(env, addr);
2332 }
2333
2334 void helper_rdtsc(void)
2335 {
2336 uint64_t val;
2337
2338 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2339 raise_exception(EXCP0D_GPF);
2340 }
2341 val = cpu_get_tsc(env);
2342 EAX = (uint32_t)(val);
2343 EDX = (uint32_t)(val >> 32);
2344 }
2345
2346 #if defined(CONFIG_USER_ONLY)
2347 void helper_wrmsr(void)
2348 {
2349 }
2350
2351 void helper_rdmsr(void)
2352 {
2353 }
2354 #else
2355 void helper_wrmsr(void)
2356 {
2357 uint64_t val;
2358
2359 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2360
2361 switch((uint32_t)ECX) {
2362 case MSR_IA32_SYSENTER_CS:
2363 env->sysenter_cs = val & 0xffff;
2364 break;
2365 case MSR_IA32_SYSENTER_ESP:
2366 env->sysenter_esp = val;
2367 break;
2368 case MSR_IA32_SYSENTER_EIP:
2369 env->sysenter_eip = val;
2370 break;
2371 case MSR_IA32_APICBASE:
2372 cpu_set_apic_base(env, val);
2373 break;
2374 case MSR_EFER:
2375 {
2376 uint64_t update_mask;
2377 update_mask = 0;
2378 if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
2379 update_mask |= MSR_EFER_SCE;
2380 if (env->cpuid_ext2_features & CPUID_EXT2_LM)
2381 update_mask |= MSR_EFER_LME;
2382 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
2383 update_mask |= MSR_EFER_FFXSR;
2384 if (env->cpuid_ext2_features & CPUID_EXT2_NX)
2385 update_mask |= MSR_EFER_NXE;
2386 env->efer = (env->efer & ~update_mask) |
2387 (val & update_mask);
2388 }
2389 break;
2390 case MSR_STAR:
2391 env->star = val;
2392 break;
2393 case MSR_PAT:
2394 env->pat = val;
2395 break;
2396 #ifdef TARGET_X86_64
2397 case MSR_LSTAR:
2398 env->lstar = val;
2399 break;
2400 case MSR_CSTAR:
2401 env->cstar = val;
2402 break;
2403 case MSR_FMASK:
2404 env->fmask = val;
2405 break;
2406 case MSR_FSBASE:
2407 env->segs[R_FS].base = val;
2408 break;
2409 case MSR_GSBASE:
2410 env->segs[R_GS].base = val;
2411 break;
2412 case MSR_KERNELGSBASE:
2413 env->kernelgsbase = val;
2414 break;
2415 #endif
2416 default:
2417 /* XXX: exception ? */
2418 break;
2419 }
2420 }
2421
2422 void helper_rdmsr(void)
2423 {
2424 uint64_t val;
2425 switch((uint32_t)ECX) {
2426 case MSR_IA32_SYSENTER_CS:
2427 val = env->sysenter_cs;
2428 break;
2429 case MSR_IA32_SYSENTER_ESP:
2430 val = env->sysenter_esp;
2431 break;
2432 case MSR_IA32_SYSENTER_EIP:
2433 val = env->sysenter_eip;
2434 break;
2435 case MSR_IA32_APICBASE:
2436 val = cpu_get_apic_base(env);
2437 break;
2438 case MSR_EFER:
2439 val = env->efer;
2440 break;
2441 case MSR_STAR:
2442 val = env->star;
2443 break;
2444 case MSR_PAT:
2445 val = env->pat;
2446 break;
2447 #ifdef TARGET_X86_64
2448 case MSR_LSTAR:
2449 val = env->lstar;
2450 break;
2451 case MSR_CSTAR:
2452 val = env->cstar;
2453 break;
2454 case MSR_FMASK:
2455 val = env->fmask;
2456 break;
2457 case MSR_FSBASE:
2458 val = env->segs[R_FS].base;
2459 break;
2460 case MSR_GSBASE:
2461 val = env->segs[R_GS].base;
2462 break;
2463 case MSR_KERNELGSBASE:
2464 val = env->kernelgsbase;
2465 break;
2466 #endif
2467 default:
2468 /* XXX: exception ? */
2469 val = 0;
2470 break;
2471 }
2472 EAX = (uint32_t)(val);
2473 EDX = (uint32_t)(val >> 32);
2474 }
2475 #endif
2476
2477 void helper_lsl(void)
2478 {
2479 unsigned int selector, limit;
2480 uint32_t e1, e2, eflags;
2481 int rpl, dpl, cpl, type;
2482
2483 eflags = cc_table[CC_OP].compute_all();
2484 selector = T0 & 0xffff;
2485 if (load_segment(&e1, &e2, selector) != 0)
2486 goto fail;
2487 rpl = selector & 3;
2488 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2489 cpl = env->hflags & HF_CPL_MASK;
2490 if (e2 & DESC_S_MASK) {
2491 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2492 /* conforming */
2493 } else {
2494 if (dpl < cpl || dpl < rpl)
2495 goto fail;
2496 }
2497 } else {
2498 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2499 switch(type) {
2500 case 1:
2501 case 2:
2502 case 3:
2503 case 9:
2504 case 11:
2505 break;
2506 default:
2507 goto fail;
2508 }
2509 if (dpl < cpl || dpl < rpl) {
2510 fail:
2511 CC_SRC = eflags & ~CC_Z;
2512 return;
2513 }
2514 }
2515 limit = get_seg_limit(e1, e2);
2516 T1 = limit;
2517 CC_SRC = eflags | CC_Z;
2518 }
2519
2520 void helper_lar(void)
2521 {
2522 unsigned int selector;
2523 uint32_t e1, e2, eflags;
2524 int rpl, dpl, cpl, type;
2525
2526 eflags = cc_table[CC_OP].compute_all();
2527 selector = T0 & 0xffff;
2528 if ((selector & 0xfffc) == 0)
2529 goto fail;
2530 if (load_segment(&e1, &e2, selector) != 0)
2531 goto fail;
2532 rpl = selector & 3;
2533 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2534 cpl = env->hflags & HF_CPL_MASK;
2535 if (e2 & DESC_S_MASK) {
2536 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2537 /* conforming */
2538 } else {
2539 if (dpl < cpl || dpl < rpl)
2540 goto fail;
2541 }
2542 } else {
2543 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2544 switch(type) {
2545 case 1:
2546 case 2:
2547 case 3:
2548 case 4:
2549 case 5:
2550 case 9:
2551 case 11:
2552 case 12:
2553 break;
2554 default:
2555 goto fail;
2556 }
2557 if (dpl < cpl || dpl < rpl) {
2558 fail:
2559 CC_SRC = eflags & ~CC_Z;
2560 return;
2561 }
2562 }
2563 T1 = e2 & 0x00f0ff00;
2564 CC_SRC = eflags | CC_Z;
2565 }
2566
2567 void helper_verr(void)
2568 {
2569 unsigned int selector;
2570 uint32_t e1, e2, eflags;
2571 int rpl, dpl, cpl;
2572
2573 eflags = cc_table[CC_OP].compute_all();
2574 selector = T0 & 0xffff;
2575 if ((selector & 0xfffc) == 0)
2576 goto fail;
2577 if (load_segment(&e1, &e2, selector) != 0)
2578 goto fail;
2579 if (!(e2 & DESC_S_MASK))
2580 goto fail;
2581 rpl = selector & 3;
2582 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2583 cpl = env->hflags & HF_CPL_MASK;
2584 if (e2 & DESC_CS_MASK) {
2585 if (!(e2 & DESC_R_MASK))
2586 goto fail;
2587 if (!(e2 & DESC_C_MASK)) {
2588 if (dpl < cpl || dpl < rpl)
2589 goto fail;
2590 }
2591 } else {
2592 if (dpl < cpl || dpl < rpl) {
2593 fail:
2594 CC_SRC = eflags & ~CC_Z;
2595 return;
2596 }
2597 }
2598 CC_SRC = eflags | CC_Z;
2599 }
2600
2601 void helper_verw(void)
2602 {
2603 unsigned int selector;
2604 uint32_t e1, e2, eflags;
2605 int rpl, dpl, cpl;
2606
2607 eflags = cc_table[CC_OP].compute_all();
2608 selector = T0 & 0xffff;
2609 if ((selector & 0xfffc) == 0)
2610 goto fail;
2611 if (load_segment(&e1, &e2, selector) != 0)
2612 goto fail;
2613 if (!(e2 & DESC_S_MASK))
2614 goto fail;
2615 rpl = selector & 3;
2616 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2617 cpl = env->hflags & HF_CPL_MASK;
2618 if (e2 & DESC_CS_MASK) {
2619 goto fail;
2620 } else {
2621 if (dpl < cpl || dpl < rpl)
2622 goto fail;
2623 if (!(e2 & DESC_W_MASK)) {
2624 fail:
2625 CC_SRC = eflags & ~CC_Z;
2626 return;
2627 }
2628 }
2629 CC_SRC = eflags | CC_Z;
2630 }
2631
2632 /* FPU helpers */
2633
2634 void helper_fldt_ST0_A0(void)
2635 {
2636 int new_fpstt;
2637 new_fpstt = (env->fpstt - 1) & 7;
2638 env->fpregs[new_fpstt].d = helper_fldt(A0);
2639 env->fpstt = new_fpstt;
2640 env->fptags[new_fpstt] = 0; /* validate stack entry */
2641 }
2642
2643 void helper_fstt_ST0_A0(void)
2644 {
2645 helper_fstt(ST0, A0);
2646 }
2647
2648 void fpu_set_exception(int mask)
2649 {
2650 env->fpus |= mask;
2651 if (env->fpus & (~env->fpuc & FPUC_EM))
2652 env->fpus |= FPUS_SE | FPUS_B;
2653 }
2654
2655 CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2656 {
2657 if (b == 0.0)
2658 fpu_set_exception(FPUS_ZE);
2659 return a / b;
2660 }
2661
2662 void fpu_raise_exception(void)
2663 {
2664 if (env->cr[0] & CR0_NE_MASK) {
2665 raise_exception(EXCP10_COPR);
2666 }
2667 #if !defined(CONFIG_USER_ONLY)
2668 else {
2669 cpu_set_ferr(env);
2670 }
2671 #endif
2672 }
2673
2674 /* BCD ops */
2675
2676 void helper_fbld_ST0_A0(void)
2677 {
2678 CPU86_LDouble tmp;
2679 uint64_t val;
2680 unsigned int v;
2681 int i;
2682
2683 val = 0;
2684 for(i = 8; i >= 0; i--) {
2685 v = ldub(A0 + i);
2686 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2687 }
2688 tmp = val;
2689 if (ldub(A0 + 9) & 0x80)
2690 tmp = -tmp;
2691 fpush();
2692 ST0 = tmp;
2693 }
2694
2695 void helper_fbst_ST0_A0(void)
2696 {
2697 int v;
2698 target_ulong mem_ref, mem_end;
2699 int64_t val;
2700
2701 val = floatx_to_int64(ST0, &env->fp_status);
2702 mem_ref = A0;
2703 mem_end = mem_ref + 9;
2704 if (val < 0) {
2705 stb(mem_end, 0x80);
2706 val = -val;
2707 } else {
2708 stb(mem_end, 0x00);
2709 }
2710 while (mem_ref < mem_end) {
2711 if (val == 0)
2712 break;
2713 v = val % 100;
2714 val = val / 100;
2715 v = ((v / 10) << 4) | (v % 10);
2716 stb(mem_ref++, v);
2717 }
2718 while (mem_ref < mem_end) {
2719 stb(mem_ref++, 0);
2720 }
2721 }
2722
2723 void helper_f2xm1(void)
2724 {
2725 ST0 = pow(2.0,ST0) - 1.0;
2726 }
2727
2728 void helper_fyl2x(void)
2729 {
2730 CPU86_LDouble fptemp;
2731
2732 fptemp = ST0;
2733 if (fptemp>0.0){
2734 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
2735 ST1 *= fptemp;
2736 fpop();
2737 } else {
2738 env->fpus &= (~0x4700);
2739 env->fpus |= 0x400;
2740 }
2741 }
2742
2743 void helper_fptan(void)
2744 {
2745 CPU86_LDouble fptemp;
2746
2747 fptemp = ST0;
2748 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2749 env->fpus |= 0x400;
2750 } else {
2751 ST0 = tan(fptemp);
2752 fpush();
2753 ST0 = 1.0;
2754 env->fpus &= (~0x400); /* C2 <-- 0 */
2755 /* the above code is for |arg| < 2**52 only */
2756 }
2757 }
2758
2759 void helper_fpatan(void)
2760 {
2761 CPU86_LDouble fptemp, fpsrcop;
2762
2763 fpsrcop = ST1;
2764 fptemp = ST0;
2765 ST1 = atan2(fpsrcop,fptemp);
2766 fpop();
2767 }
2768
2769 void helper_fxtract(void)
2770 {
2771 CPU86_LDoubleU temp;
2772 unsigned int expdif;
2773
2774 temp.d = ST0;
2775 expdif = EXPD(temp) - EXPBIAS;
2776 /*DP exponent bias*/
2777 ST0 = expdif;
2778 fpush();
2779 BIASEXPONENT(temp);
2780 ST0 = temp.d;
2781 }
2782
2783 void helper_fprem1(void)
2784 {
2785 CPU86_LDouble dblq, fpsrcop, fptemp;
2786 CPU86_LDoubleU fpsrcop1, fptemp1;
2787 int expdif;
2788 int q;
2789
2790 fpsrcop = ST0;
2791 fptemp = ST1;
2792 fpsrcop1.d = fpsrcop;
2793 fptemp1.d = fptemp;
2794 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2795 if (expdif < 53) {
2796 dblq = fpsrcop / fptemp;
2797 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2798 ST0 = fpsrcop - fptemp*dblq;
2799 q = (int)dblq; /* cutting off top bits is assumed here */
2800 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2801 /* (C0,C1,C3) <-- (q2,q1,q0) */
2802 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2803 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2804 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2805 } else {
2806 env->fpus |= 0x400; /* C2 <-- 1 */
2807 fptemp = pow(2.0, expdif-50);
2808 fpsrcop = (ST0 / ST1) / fptemp;
2809 /* fpsrcop = integer obtained by rounding to the nearest */
2810 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
2811 floor(fpsrcop): ceil(fpsrcop);
2812 ST0 -= (ST1 * fpsrcop * fptemp);
2813 }
2814 }
2815
2816 void helper_fprem(void)
2817 {
2818 CPU86_LDouble dblq, fpsrcop, fptemp;
2819 CPU86_LDoubleU fpsrcop1, fptemp1;
2820 int expdif;
2821 int q;
2822
2823 fpsrcop = ST0;
2824 fptemp = ST1;
2825 fpsrcop1.d = fpsrcop;
2826 fptemp1.d = fptemp;
2827 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2828 if ( expdif < 53 ) {
2829 dblq = fpsrcop / fptemp;
2830 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2831 ST0 = fpsrcop - fptemp*dblq;
2832 q = (int)dblq; /* cutting off top bits is assumed here */
2833 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2834 /* (C0,C1,C3) <-- (q2,q1,q0) */
2835 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2836 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2837 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2838 } else {
2839 env->fpus |= 0x400; /* C2 <-- 1 */
2840 fptemp = pow(2.0, expdif-50);
2841 fpsrcop = (ST0 / ST1) / fptemp;
2842 /* fpsrcop = integer obtained by chopping */
2843 fpsrcop = (fpsrcop < 0.0)?
2844 -(floor(fabs(fpsrcop))): floor(fpsrcop);
2845 ST0 -= (ST1 * fpsrcop * fptemp);
2846 }
2847 }
2848
2849 void helper_fyl2xp1(void)
2850 {
2851 CPU86_LDouble fptemp;
2852
2853 fptemp = ST0;
2854 if ((fptemp+1.0)>0.0) {
2855 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
2856 ST1 *= fptemp;
2857 fpop();
2858 } else {
2859 env->fpus &= (~0x4700);
2860 env->fpus |= 0x400;
2861 }
2862 }
2863
2864 void helper_fsqrt(void)
2865 {
2866 CPU86_LDouble fptemp;
2867
2868 fptemp = ST0;
2869 if (fptemp<0.0) {
2870 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2871 env->fpus |= 0x400;
2872 }
2873 ST0 = sqrt(fptemp);
2874 }
2875
2876 void helper_fsincos(void)
2877 {
2878 CPU86_LDouble fptemp;
2879
2880 fptemp = ST0;
2881 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2882 env->fpus |= 0x400;
2883 } else {
2884 ST0 = sin(fptemp);
2885 fpush();
2886 ST0 = cos(fptemp);
2887 env->fpus &= (~0x400); /* C2 <-- 0 */
2888 /* the above code is for |arg| < 2**63 only */
2889 }
2890 }
2891
2892 void helper_frndint(void)
2893 {
2894 ST0 = floatx_round_to_int(ST0, &env->fp_status);
2895 }
2896
2897 void helper_fscale(void)
2898 {
2899 ST0 = ldexp (ST0, (int)(ST1));
2900 }
2901
2902 void helper_fsin(void)
2903 {
2904 CPU86_LDouble fptemp;
2905
2906 fptemp = ST0;
2907 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2908 env->fpus |= 0x400;
2909 } else {
2910 ST0 = sin(fptemp);
2911 env->fpus &= (~0x400); /* C2 <-- 0 */
2912 /* the above code is for |arg| < 2**53 only */
2913 }
2914 }
2915
2916 void helper_fcos(void)
2917 {
2918 CPU86_LDouble fptemp;
2919
2920 fptemp = ST0;
2921 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2922 env->fpus |= 0x400;
2923 } else {
2924 ST0 = cos(fptemp);
2925 env->fpus &= (~0x400); /* C2 <-- 0 */
2926 /* the above code is for |arg5 < 2**63 only */
2927 }
2928 }
2929
2930 void helper_fxam_ST0(void)
2931 {
2932 CPU86_LDoubleU temp;
2933 int expdif;
2934
2935 temp.d = ST0;
2936
2937 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2938 if (SIGND(temp))
2939 env->fpus |= 0x200; /* C1 <-- 1 */
2940
2941 expdif = EXPD(temp);
2942 if (expdif == MAXEXPD) {
2943 if (MANTD(temp) == 0)
2944 env->fpus |= 0x500 /*Infinity*/;
2945 else
2946 env->fpus |= 0x100 /*NaN*/;
2947 } else if (expdif == 0) {
2948 if (MANTD(temp) == 0)
2949 env->fpus |= 0x4000 /*Zero*/;
2950 else
2951 env->fpus |= 0x4400 /*Denormal*/;
2952 } else {
2953 env->fpus |= 0x400;
2954 }
2955 }
2956
2957 void helper_fstenv(target_ulong ptr, int data32)
2958 {
2959 int fpus, fptag, exp, i;
2960 uint64_t mant;
2961 CPU86_LDoubleU tmp;
2962
2963 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2964 fptag = 0;
2965 for (i=7; i>=0; i--) {
2966 fptag <<= 2;
2967 if (env->fptags[i]) {
2968 fptag |= 3;
2969 } else {
2970 tmp.d = env->fpregs[i].d;
2971 exp = EXPD(tmp);
2972 mant = MANTD(tmp);
2973 if (exp == 0 && mant == 0) {
2974 /* zero */
2975 fptag |= 1;
2976 } else if (exp == 0 || exp == MAXEXPD
2977 #ifdef USE_X86LDOUBLE
2978 || (mant & (1LL << 63)) == 0
2979 #endif
2980 ) {
2981 /* NaNs, infinity, denormal */
2982 fptag |= 2;
2983 }
2984 }
2985 }
2986 if (data32) {
2987 /* 32 bit */
2988 stl(ptr, env->fpuc);
2989 stl(ptr + 4, fpus);
2990 stl(ptr + 8, fptag);
2991 stl(ptr + 12, 0); /* fpip */
2992 stl(ptr + 16, 0); /* fpcs */
2993 stl(ptr + 20, 0); /* fpoo */
2994 stl(ptr + 24, 0); /* fpos */
2995 } else {
2996 /* 16 bit */
2997 stw(ptr, env->fpuc);
2998 stw(ptr + 2, fpus);
2999 stw(ptr + 4, fptag);
3000 stw(ptr + 6, 0);
3001 stw(ptr + 8, 0);
3002 stw(ptr + 10, 0);
3003 stw(ptr + 12, 0);
3004 }
3005 }
3006
3007 void helper_fldenv(target_ulong ptr, int data32)
3008 {
3009 int i, fpus, fptag;
3010
3011 if (data32) {
3012 env->fpuc = lduw(ptr);
3013 fpus = lduw(ptr + 4);
3014 fptag = lduw(ptr + 8);
3015 }
3016 else {
3017 env->fpuc = lduw(ptr);
3018 fpus = lduw(ptr + 2);
3019 fptag = lduw(ptr + 4);
3020 }
3021 env->fpstt = (fpus >> 11) & 7;
3022 env->fpus = fpus & ~0x3800;
3023 for(i = 0;i < 8; i++) {
3024 env->fptags[i] = ((fptag & 3) == 3);
3025 fptag >>= 2;
3026 }
3027 }
3028
3029 void helper_fsave(target_ulong ptr, int data32)
3030 {
3031 CPU86_LDouble tmp;
3032 int i;
3033
3034 helper_fstenv(ptr, data32);
3035
3036 ptr += (14 << data32);
3037 for(i = 0;i < 8; i++) {
3038 tmp = ST(i);
3039 helper_fstt(tmp, ptr);
3040 ptr += 10;
3041 }
3042
3043 /* fninit */
3044 env->fpus = 0;
3045 env->fpstt = 0;
3046 env->fpuc = 0x37f;
3047 env->fptags[0] = 1;
3048 env->fptags[1] = 1;
3049 env->fptags[2] = 1;
3050 env->fptags[3] = 1;
3051 env->fptags[4] = 1;
3052 env->fptags[5] = 1;
3053 env->fptags[6] = 1;
3054 env->fptags[7] = 1;
3055 }
3056
3057 void helper_frstor(target_ulong ptr, int data32)
3058 {
3059 CPU86_LDouble tmp;
3060 int i;
3061
3062 helper_fldenv(ptr, data32);
3063 ptr += (14 << data32);
3064
3065 for(i = 0;i < 8; i++) {
3066 tmp = helper_fldt(ptr);
3067 ST(i) = tmp;
3068 ptr += 10;
3069 }
3070 }
3071
3072 void helper_fxsave(target_ulong ptr, int data64)
3073 {
3074 int fpus, fptag, i, nb_xmm_regs;
3075 CPU86_LDouble tmp;
3076 target_ulong addr;
3077
3078 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3079 fptag = 0;
3080 for(i = 0; i < 8; i++) {
3081 fptag |= (env->fptags[i] << i);
3082 }
3083 stw(ptr, env->fpuc);
3084 stw(ptr + 2, fpus);
3085 stw(ptr + 4, fptag ^ 0xff);
3086
3087 addr = ptr + 0x20;
3088 for(i = 0;i < 8; i++) {
3089 tmp = ST(i);
3090 helper_fstt(tmp, addr);
3091 addr += 16;
3092 }
3093
3094 if (env->cr[4] & CR4_OSFXSR_MASK) {
3095 /* XXX: finish it */
3096 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3097 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3098 nb_xmm_regs = 8 << data64;
3099 addr = ptr + 0xa0;
3100 for(i = 0; i < nb_xmm_regs; i++) {
3101 stq(addr, env->xmm_regs[i].XMM_Q(0));
3102 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3103 addr += 16;
3104 }
3105 }
3106 }
3107
3108 void helper_fxrstor(target_ulong ptr, int data64)
3109 {
3110 int i, fpus, fptag, nb_xmm_regs;
3111 CPU86_LDouble tmp;
3112 target_ulong addr;
3113
3114 env->fpuc = lduw(ptr);
3115 fpus = lduw(ptr + 2);
3116 fptag = lduw(ptr + 4);
3117 env->fpstt = (fpus >> 11) & 7;
3118 env->fpus = fpus & ~0x3800;
3119 fptag ^= 0xff;
3120 for(i = 0;i < 8; i++) {
3121 env->fptags[i] = ((fptag >> i) & 1);
3122 }
3123
3124 addr = ptr + 0x20;
3125 for(i = 0;i < 8; i++) {
3126 tmp = helper_fldt(addr);
3127 ST(i) = tmp;
3128 addr += 16;
3129 }
3130
3131 if (env->cr[4] & CR4_OSFXSR_MASK) {
3132 /* XXX: finish it */
3133 env->mxcsr = ldl(ptr + 0x18);
3134 //ldl(ptr + 0x1c);
3135 nb_xmm_regs = 8 << data64;
3136 addr = ptr + 0xa0;
3137 for(i = 0; i < nb_xmm_regs; i++) {
3138 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3139 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3140 addr += 16;
3141 }
3142 }
3143 }
3144
3145 #ifndef USE_X86LDOUBLE
3146
3147 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3148 {
3149 CPU86_LDoubleU temp;
3150 int e;
3151
3152 temp.d = f;
3153 /* mantissa */
3154 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3155 /* exponent + sign */
3156 e = EXPD(temp) - EXPBIAS + 16383;
3157 e |= SIGND(temp) >> 16;
3158 *pexp = e;
3159 }
3160
3161 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3162 {
3163 CPU86_LDoubleU temp;
3164 int e;
3165 uint64_t ll;
3166
3167 /* XXX: handle overflow ? */
3168 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3169 e |= (upper >> 4) & 0x800; /* sign */
3170 ll = (mant >> 11) & ((1LL << 52) - 1);
3171 #ifdef __arm__
3172 temp.l.upper = (e << 20) | (ll >> 32);
3173 temp.l.lower = ll;
3174 #else
3175 temp.ll = ll | ((uint64_t)e << 52);
3176 #endif
3177 return temp.d;
3178 }
3179
3180 #else
3181
3182 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3183 {
3184 CPU86_LDoubleU temp;
3185
3186 temp.d = f;
3187 *pmant = temp.l.lower;
3188 *pexp = temp.l.upper;
3189 }
3190
3191 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3192 {
3193 CPU86_LDoubleU temp;
3194
3195 temp.l.upper = upper;
3196 temp.l.lower = mant;
3197 return temp.d;
3198 }
3199 #endif
3200
3201 #ifdef TARGET_X86_64
3202
3203 //#define DEBUG_MULDIV
3204
3205 static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3206 {
3207 *plow += a;
3208 /* carry test */
3209 if (*plow < a)
3210 (*phigh)++;
3211 *phigh += b;
3212 }
3213
3214 static void neg128(uint64_t *plow, uint64_t *phigh)
3215 {
3216 *plow = ~ *plow;
3217 *phigh = ~ *phigh;
3218 add128(plow, phigh, 1, 0);
3219 }
3220
3221 static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3222 {
3223 uint32_t a0, a1, b0, b1;
3224 uint64_t v;
3225
3226 a0 = a;
3227 a1 = a >> 32;
3228
3229 b0 = b;
3230 b1 = b >> 32;
3231
3232 v = (uint64_t)a0 * (uint64_t)b0;
3233 *plow = v;
3234 *phigh = 0;
3235
3236 v = (uint64_t)a0 * (uint64_t)b1;
3237 add128(plow, phigh, v << 32, v >> 32);
3238
3239 v = (uint64_t)a1 * (uint64_t)b0;
3240 add128(plow, phigh, v << 32, v >> 32);
3241
3242 v = (uint64_t)a1 * (uint64_t)b1;
3243 *phigh += v;
3244 #ifdef DEBUG_MULDIV
3245 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
3246 a, b, *phigh, *plow);
3247 #endif
3248 }
3249
3250 static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3251 {
3252 int sa, sb;
3253 sa = (a < 0);
3254 if (sa)
3255 a = -a;
3256 sb = (b < 0);
3257 if (sb)
3258 b = -b;
3259 mul64(plow, phigh, a, b);
3260 if (sa ^ sb) {
3261 neg128(plow, phigh);
3262 }
3263 }
3264
3265 /* return TRUE if overflow */
3266 static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3267 {
3268 uint64_t q, r, a1, a0;
3269 int i, qb, ab;
3270
3271 a0 = *plow;
3272 a1 = *phigh;
3273 if (a1 == 0) {
3274 q = a0 / b;
3275 r = a0 % b;
3276 *plow = q;
3277 *phigh = r;
3278 } else {
3279 if (a1 >= b)
3280 return 1;
3281 /* XXX: use a better algorithm */
3282 for(i = 0; i < 64; i++) {
3283 ab = a1 >> 63;
3284 a1 = (a1 << 1) | (a0 >> 63);
3285 if (ab || a1 >= b) {
3286 a1 -= b;
3287 qb = 1;
3288 } else {
3289 qb = 0;
3290 }
3291 a0 = (a0 << 1) | qb;
3292 }
3293 #if defined(DEBUG_MULDIV)
3294 printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
3295 *phigh, *plow, b, a0, a1);
3296 #endif
3297 *plow = a0;
3298 *phigh = a1;
3299 }
3300 return 0;
3301 }
3302
3303 /* return TRUE if overflow */
3304 static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
3305 {
3306 int sa, sb;
3307 sa = ((int64_t)*phigh < 0);
3308 if (sa)
3309 neg128(plow, phigh);
3310 sb = (b < 0);
3311 if (sb)
3312 b = -b;
3313 if (div64(plow, phigh, b) != 0)
3314 return 1;
3315 if (sa ^ sb) {
3316 if (*plow > (1ULL << 63))
3317 return 1;
3318 *plow = - *plow;
3319 } else {
3320 if (*plow >= (1ULL << 63))
3321 return 1;
3322 }
3323 if (sa)
3324 *phigh = - *phigh;
3325 return 0;
3326 }
3327
3328 void helper_mulq_EAX_T0(void)
3329 {
3330 uint64_t r0, r1;
3331
3332 mul64(&r0, &r1, EAX, T0);
3333 EAX = r0;
3334 EDX = r1;
3335 CC_DST = r0;
3336 CC_SRC = r1;
3337 }
3338
3339 void helper_imulq_EAX_T0(void)
3340 {
3341 uint64_t r0, r1;
3342
3343 imul64(&r0, &r1, EAX, T0);
3344 EAX = r0;
3345 EDX = r1;
3346 CC_DST = r0;
3347 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3348 }
3349
3350 void helper_imulq_T0_T1(void)
3351 {
3352 uint64_t r0, r1;
3353
3354 imul64(&r0, &r1, T0, T1);
3355 T0 = r0;
3356 CC_DST = r0;
3357 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3358 }
3359
3360 void helper_divq_EAX_T0(void)
3361 {
3362 uint64_t r0, r1;
3363 if (T0 == 0) {
3364 raise_exception(EXCP00_DIVZ);
3365 }
3366 r0 = EAX;
3367 r1 = EDX;
3368 if (div64(&r0, &r1, T0))
3369 raise_exception(EXCP00_DIVZ);
3370 EAX = r0;
3371 EDX = r1;
3372 }
3373
3374 void helper_idivq_EAX_T0(void)
3375 {
3376 uint64_t r0, r1;
3377 if (T0 == 0) {
3378 raise_exception(EXCP00_DIVZ);
3379 }
3380 r0 = EAX;
3381 r1 = EDX;
3382 if (idiv64(&r0, &r1, T0))
3383 raise_exception(EXCP00_DIVZ);
3384 EAX = r0;
3385 EDX = r1;
3386 }
3387
3388 #endif
3389
3390 float approx_rsqrt(float a)
3391 {
3392 return 1.0 / sqrt(a);
3393 }
3394
3395 float approx_rcp(float a)
3396 {
3397 return 1.0 / a;
3398 }
3399
3400 void update_fp_status(void)
3401 {
3402 int rnd_type;
3403
3404 /* set rounding mode */
3405 switch(env->fpuc & RC_MASK) {
3406 default:
3407 case RC_NEAR:
3408 rnd_type = float_round_nearest_even;
3409 break;
3410 case RC_DOWN:
3411 rnd_type = float_round_down;
3412 break;
3413 case RC_UP:
3414 rnd_type = float_round_up;
3415 break;
3416 case RC_CHOP:
3417 rnd_type = float_round_to_zero;
3418 break;
3419 }
3420 set_float_rounding_mode(rnd_type, &env->fp_status);
3421 #ifdef FLOATX80
3422 switch((env->fpuc >> 8) & 3) {
3423 case 0:
3424 rnd_type = 32;
3425 break;
3426 case 2:
3427 rnd_type = 64;
3428 break;
3429 case 3:
3430 default:
3431 rnd_type = 80;
3432 break;
3433 }
3434 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
3435 #endif
3436 }
3437
3438 #if !defined(CONFIG_USER_ONLY)
3439
3440 #define MMUSUFFIX _mmu
3441 #define GETPC() (__builtin_return_address(0))
3442
3443 #define SHIFT 0
3444 #include "softmmu_template.h"
3445
3446 #define SHIFT 1
3447 #include "softmmu_template.h"
3448
3449 #define SHIFT 2
3450 #include "softmmu_template.h"
3451
3452 #define SHIFT 3
3453 #include "softmmu_template.h"
3454
3455 #endif
3456
3457 /* try to fill the TLB and return an exception if error. If retaddr is
3458 NULL, it means that the function was called in C code (i.e. not
3459 from generated code or from helper.c) */
3460 /* XXX: fix it to restore all registers */
3461 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3462 {
3463 TranslationBlock *tb;
3464 int ret;
3465 unsigned long pc;
3466 CPUX86State *saved_env;
3467
3468 /* XXX: hack to restore env in all cases, even if not called from
3469 generated code */
3470 saved_env = env;
3471 env = cpu_single_env;
3472
3473 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3474 if (ret) {
3475 if (retaddr) {
3476 /* now we have a real cpu fault */
3477 pc = (unsigned long)retaddr;
3478 tb = tb_find_pc(pc);
3479 if (tb) {
3480 /* the PC is inside the translated code. It means that we have
3481 a virtual CPU fault */
3482 cpu_restore_state(tb, env, pc, NULL);
3483 }
3484 }
3485 if (retaddr)
3486 raise_exception_err(env->exception_index, env->error_code);
3487 else
3488 raise_exception_err_norestore(env->exception_index, env->error_code);
3489 }
3490 env = saved_env;
3491 }
Samsung s3c2440 and arm920t support for the mini2440 dev board