2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 #if !defined (__CPU_ALPHA_H__)
22 #define __CPU_ALPHA_H__
26 #define TARGET_LONG_BITS 64
28 #define CPUState struct CPUAlphaState
34 #include "softfloat.h"
36 #define TARGET_HAS_ICE 1
38 #define ELF_MACHINE EM_ALPHA
40 #define ICACHE_LINE_SIZE 32
41 #define DCACHE_LINE_SIZE 32
43 #define TARGET_PAGE_BITS 12
47 /* Alpha major type */
53 ALPHA_EV5
= 5, /* 21164 */
54 ALPHA_EV45
= 6, /* 21064A */
55 ALPHA_EV56
= 7, /* 21164A */
66 ALPHA_LCA_1
= 1, /* 21066 */
67 ALPHA_LCA_2
= 2, /* 20166 */
68 ALPHA_LCA_3
= 3, /* 21068 */
69 ALPHA_LCA_4
= 4, /* 21068 */
70 ALPHA_LCA_5
= 5, /* 21066A */
71 ALPHA_LCA_6
= 6, /* 21068A */
76 ALPHA_EV5_1
= 1, /* Rev BA, CA */
77 ALPHA_EV5_2
= 2, /* Rev DA, EA */
78 ALPHA_EV5_3
= 3, /* Pass 3 */
79 ALPHA_EV5_4
= 4, /* Pass 3.2 */
80 ALPHA_EV5_5
= 5, /* Pass 4 */
85 ALPHA_EV45_1
= 1, /* Pass 1 */
86 ALPHA_EV45_2
= 2, /* Pass 1.1 */
87 ALPHA_EV45_3
= 3, /* Pass 2 */
92 ALPHA_EV56_1
= 1, /* Pass 1 */
93 ALPHA_EV56_2
= 2, /* Pass 2 */
97 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
98 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
99 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
100 IMPLVER_21364
= 3, /* EV7 & EV79 */
104 AMASK_BWX
= 0x00000001,
105 AMASK_FIX
= 0x00000002,
106 AMASK_CIX
= 0x00000004,
107 AMASK_MVI
= 0x00000100,
108 AMASK_TRAP
= 0x00000200,
109 AMASK_PREFETCH
= 0x00001000,
113 VAX_ROUND_NORMAL
= 0,
118 IEEE_ROUND_NORMAL
= 0,
125 /* IEEE floating-point operations encoding */
137 FP_ROUND_CHOPPED
= 0x0,
138 FP_ROUND_MINUS
= 0x1,
139 FP_ROUND_NORMAL
= 0x2,
140 FP_ROUND_DYNAMIC
= 0x3,
143 /* Internal processor registers */
144 /* XXX: TOFIX: most of those registers are implementation dependant */
165 IPR_HW_INT_CLR
= 0x0E,
171 IPR_IC_FLUSH_ASM
= 0x12,
181 IPR_DTB_ALTMODE
= 0xA6,
228 typedef struct CPUAlphaState CPUAlphaState
;
230 typedef struct pal_handler_t pal_handler_t
;
231 struct pal_handler_t
{
233 void (*reset
)(CPUAlphaState
*env
);
234 /* Uncorrectable hardware error */
235 void (*machine_check
)(CPUAlphaState
*env
);
236 /* Arithmetic exception */
237 void (*arithmetic
)(CPUAlphaState
*env
);
238 /* Interrupt / correctable hardware error */
239 void (*interrupt
)(CPUAlphaState
*env
);
241 void (*dfault
)(CPUAlphaState
*env
);
243 void (*dtb_miss_pal
)(CPUAlphaState
*env
);
244 /* DTB miss native */
245 void (*dtb_miss_native
)(CPUAlphaState
*env
);
246 /* Unaligned access */
247 void (*unalign
)(CPUAlphaState
*env
);
249 void (*itb_miss
)(CPUAlphaState
*env
);
250 /* Instruction stream access violation */
251 void (*itb_acv
)(CPUAlphaState
*env
);
252 /* Reserved or privileged opcode */
253 void (*opcdec
)(CPUAlphaState
*env
);
254 /* Floating point exception */
255 void (*fen
)(CPUAlphaState
*env
);
256 /* Call pal instruction */
257 void (*call_pal
)(CPUAlphaState
*env
, uint32_t palcode
);
260 #define NB_MMU_MODES 4
262 struct CPUAlphaState
{
265 float_status fp_status
;
270 uint64_t ipr
[IPR_LAST
];
273 int saved_mode
; /* Used for HW_LD / HW_ST */
274 int intr_flag
; /* For RC and RS */
276 #if TARGET_LONG_BITS > HOST_LONG_BITS
277 /* temporary fixed-point registers
278 * used to emulate 64 bits target on 32 bits hosts
283 /* Those resources are used only in Qemu core */
293 pal_handler_t
*pal_handler
;
296 #define cpu_init cpu_alpha_init
297 #define cpu_exec cpu_alpha_exec
298 #define cpu_gen_code cpu_alpha_gen_code
299 #define cpu_signal_handler cpu_alpha_signal_handler
301 /* MMU modes definitions */
302 #define MMU_MODE0_SUFFIX _kernel
303 #define MMU_MODE1_SUFFIX _executive
304 #define MMU_MODE2_SUFFIX _supervisor
305 #define MMU_MODE3_SUFFIX _user
306 #define MMU_USER_IDX 3
307 static inline int cpu_mmu_index (CPUState
*env
)
309 return (env
->ps
>> 3) & 3;
312 #if defined(CONFIG_USER_ONLY)
313 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
317 /* FIXME: Zero syscall return value. */
322 #include "exec-all.h"
325 FEATURE_ASN
= 0x00000001,
326 FEATURE_SPS
= 0x00000002,
327 FEATURE_VIRBND
= 0x00000004,
328 FEATURE_TBCHK
= 0x00000008,
335 EXCP_HW_INTERRUPT
= 0x00E0,
336 EXCP_DFAULT
= 0x01E0,
337 EXCP_DTB_MISS_PAL
= 0x09E0,
338 EXCP_ITB_MISS
= 0x03E0,
339 EXCP_ITB_ACV
= 0x07E0,
340 EXCP_DTB_MISS_NATIVE
= 0x08E0,
341 EXCP_UNALIGN
= 0x11E0,
342 EXCP_OPCDEC
= 0x13E0,
344 EXCP_CALL_PAL
= 0x2000,
345 EXCP_CALL_PALP
= 0x3000,
346 EXCP_CALL_PALE
= 0x4000,
347 /* Pseudo exception for console */
348 EXCP_CONSOLE_DISPATCH
= 0x4001,
349 EXCP_CONSOLE_FIXUP
= 0x4002,
352 /* Arithmetic exception */
358 PALCODE_CALL
= 0x00000000,
359 PALCODE_LD
= 0x01000000,
360 PALCODE_ST
= 0x02000000,
361 PALCODE_MFPR
= 0x03000000,
362 PALCODE_MTPR
= 0x04000000,
363 PALCODE_REI
= 0x05000000,
364 PALCODE_INIT
= 0xF0000000,
404 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
);
405 int cpu_alpha_exec(CPUAlphaState
*s
);
406 /* you can call this signal handler from your SIGBUS and SIGSEGV
407 signal handlers to inform the virtual CPU of exceptions. non zero
408 is returned if the signal was handled by the virtual CPU. */
409 int cpu_alpha_signal_handler(int host_signum
, void *pinfo
,
411 int cpu_alpha_handle_mmu_fault (CPUState
*env
, uint64_t address
, int rw
,
412 int mmu_idx
, int is_softmmu
);
413 void do_interrupt (CPUState
*env
);
415 int cpu_alpha_mfpr (CPUState
*env
, int iprn
, uint64_t *valp
);
416 int cpu_alpha_mtpr (CPUState
*env
, int iprn
, uint64_t val
, uint64_t *oldvalp
);
417 void pal_init (CPUState
*env
);
418 #if !defined (CONFIG_USER_ONLY)
419 void call_pal (CPUState
*env
);
421 void call_pal (CPUState
*env
, int palcode
);
424 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)
429 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
430 target_ulong
*cs_base
, int *flags
)
437 #endif /* !defined (__CPU_ALPHA_H__) */