target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20
  21 /* A lot of PowerPC definition have been included here.
  22  * Most of them are not usable for now but have been kept
  23  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  24  */
  25
  26 #include "dis-asm.h"
  27 #include "host-utils.h"
  28
  29 //#define PPC_DUMP_CPU
  30 //#define PPC_DEBUG_SPR
  31 //#define PPC_DUMP_SPR_ACCESSES
  32 #if defined(CONFIG_USER_ONLY)
  33 #define TODO_USER_ONLY 1
  34 #endif
  35
  36 struct ppc_def_t {
  37     const char *name;
  38     uint32_t pvr;
  39     uint32_t svr;
  40     uint64_t insns_flags;
  41     uint64_t msr_mask;
  42     powerpc_mmu_t   mmu_model;
  43     powerpc_excp_t  excp_model;
  44     powerpc_input_t bus_model;
  45     uint32_t flags;
  46     int bfd_mach;
  47     void (*init_proc)(CPUPPCState *env);
  48     int  (*check_pow)(CPUPPCState *env);
  49 };
  50
  51 /* For user-mode emulation, we don't emulate any IRQ controller */
  52 #if defined(CONFIG_USER_ONLY)
  53 #define PPC_IRQ_INIT_FN(name)                                                 \
  54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  55 {                                                                             \
  56 }
  57 #else
  58 #define PPC_IRQ_INIT_FN(name)                                                 \
  59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  60 #endif
  61
  62 PPC_IRQ_INIT_FN(40x);
  63 PPC_IRQ_INIT_FN(6xx);
  64 PPC_IRQ_INIT_FN(970);
  65
  66 /* Generic callbacks:
  67  * do nothing but store/retrieve spr value
  68  */
  69 static void spr_read_generic (void *opaque, int gprn, int sprn)
  70 {
  71     gen_load_spr(cpu_gpr[gprn], sprn);
  72 #ifdef PPC_DUMP_SPR_ACCESSES
  73     {
  74         TCGv t0 = tcg_const_i32(sprn);
  75         gen_helper_load_dump_spr(t0);
  76         tcg_temp_free_i32(t0);
  77     }
  78 #endif
  79 }
  80
  81 static void spr_write_generic (void *opaque, int sprn, int gprn)
  82 {
  83     gen_store_spr(sprn, cpu_gpr[gprn]);
  84 #ifdef PPC_DUMP_SPR_ACCESSES
  85     {
  86         TCGv t0 = tcg_const_i32(sprn);
  87         gen_helper_store_dump_spr(t0);
  88         tcg_temp_free_i32(t0);
  89     }
  90 #endif
  91 }
  92
  93 #if !defined(CONFIG_USER_ONLY)
  94 static void spr_write_clear (void *opaque, int sprn, int gprn)
  95 {
  96     TCGv t0 = tcg_temp_new();
  97     TCGv t1 = tcg_temp_new();
  98     gen_load_spr(t0, sprn);
  99     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 100     tcg_gen_and_tl(t0, t0, t1);
 101     gen_store_spr(sprn, t0);
 102     tcg_temp_free(t0);
 103     tcg_temp_free(t1);
 104 }
 105 #endif
 106
 107 /* SPR common to all PowerPC */
 108 /* XER */
 109 static void spr_read_xer (void *opaque, int gprn, int sprn)
 110 {
 111     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 112 }
 113
 114 static void spr_write_xer (void *opaque, int sprn, int gprn)
 115 {
 116     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 117 }
 118
 119 /* LR */
 120 static void spr_read_lr (void *opaque, int gprn, int sprn)
 121 {
 122     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 123 }
 124
 125 static void spr_write_lr (void *opaque, int sprn, int gprn)
 126 {
 127     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 128 }
 129
 130 /* CTR */
 131 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 132 {
 133     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 134 }
 135
 136 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 137 {
 138     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 139 }
 140
 141 /* User read access to SPR */
 142 /* USPRx */
 143 /* UMMCRx */
 144 /* UPMCx */
 145 /* USIA */
 146 /* UDECR */
 147 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 148 {
 149     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 150 }
 151
 152 /* SPR common to all non-embedded PowerPC */
 153 /* DECR */
 154 #if !defined(CONFIG_USER_ONLY)
 155 static void spr_read_decr (void *opaque, int gprn, int sprn)
 156 {
 157     gen_helper_load_decr(cpu_gpr[gprn]);
 158 }
 159
 160 static void spr_write_decr (void *opaque, int sprn, int gprn)
 161 {
 162     gen_helper_store_decr(cpu_gpr[gprn]);
 163 }
 164 #endif
 165
 166 /* SPR common to all non-embedded PowerPC, except 601 */
 167 /* Time base */
 168 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 169 {
 170     gen_helper_load_tbl(cpu_gpr[gprn]);
 171 }
 172
 173 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 174 {
 175     gen_helper_load_tbu(cpu_gpr[gprn]);
 176 }
 177
 178 __attribute__ (( unused ))
 179 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 180 {
 181     gen_helper_load_atbl(cpu_gpr[gprn]);
 182 }
 183
 184 __attribute__ (( unused ))
 185 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 186 {
 187     gen_helper_load_atbu(cpu_gpr[gprn]);
 188 }
 189
 190 #if !defined(CONFIG_USER_ONLY)
 191 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 192 {
 193     gen_helper_store_tbl(cpu_gpr[gprn]);
 194 }
 195
 196 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 197 {
 198     gen_helper_store_tbu(cpu_gpr[gprn]);
 199 }
 200
 201 __attribute__ (( unused ))
 202 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 203 {
 204     gen_helper_store_atbl(cpu_gpr[gprn]);
 205 }
 206
 207 __attribute__ (( unused ))
 208 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 209 {
 210     gen_helper_store_atbu(cpu_gpr[gprn]);
 211 }
 212 #endif
 213
 214 #if !defined(CONFIG_USER_ONLY)
 215 /* IBAT0U...IBAT0U */
 216 /* IBAT0L...IBAT7L */
 217 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 218 {
 219     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 220 }
 221
 222 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 223 {
 224     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 225 }
 226
 227 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 228 {
 229     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 230     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 231     tcg_temp_free_i32(t0);
 232 }
 233
 234 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 235 {
 236     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
 237     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 238     tcg_temp_free_i32(t0);
 239 }
 240
 241 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 242 {
 243     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 244     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 245     tcg_temp_free_i32(t0);
 246 }
 247
 248 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 249 {
 250     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
 251     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 252     tcg_temp_free_i32(t0);
 253 }
 254
 255 /* DBAT0U...DBAT7U */
 256 /* DBAT0L...DBAT7L */
 257 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 258 {
 259     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 260 }
 261
 262 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 263 {
 264     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 265 }
 266
 267 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 268 {
 269     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 270     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 271     tcg_temp_free_i32(t0);
 272 }
 273
 274 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 275 {
 276     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 277     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 278     tcg_temp_free_i32(t0);
 279 }
 280
 281 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 282 {
 283     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 284     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 285     tcg_temp_free_i32(t0);
 286 }
 287
 288 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 289 {
 290     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 291     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 292     tcg_temp_free_i32(t0);
 293 }
 294
 295 /* SDR1 */
 296 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
 297 {
 298     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
 299 }
 300
 301 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 302 {
 303     gen_helper_store_sdr1(cpu_gpr[gprn]);
 304 }
 305
 306 /* 64 bits PowerPC specific SPRs */
 307 /* ASR */
 308 #if defined(TARGET_PPC64)
 309 static void spr_read_asr (void *opaque, int gprn, int sprn)
 310 {
 311     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 312 }
 313
 314 static void spr_write_asr (void *opaque, int sprn, int gprn)
 315 {
 316     gen_helper_store_asr(cpu_gpr[gprn]);
 317 }
 318 #endif
 319 #endif
 320
 321 /* PowerPC 601 specific registers */
 322 /* RTC */
 323 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 324 {
 325     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 326 }
 327
 328 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 329 {
 330     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 331 }
 332
 333 #if !defined(CONFIG_USER_ONLY)
 334 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 335 {
 336     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 337 }
 338
 339 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 340 {
 341     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 342 }
 343
 344 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 345 {
 346     DisasContext *ctx = opaque;
 347
 348     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 349     /* Must stop the translation as endianness may have changed */
 350     gen_stop_exception(ctx);
 351 }
 352 #endif
 353
 354 /* Unified bats */
 355 #if !defined(CONFIG_USER_ONLY)
 356 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 357 {
 358     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 359 }
 360
 361 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 362 {
 363     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 364     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 365     tcg_temp_free_i32(t0);
 366 }
 367
 368 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 369 {
 370     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 371     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 372     tcg_temp_free_i32(t0);
 373 }
 374 #endif
 375
 376 /* PowerPC 40x specific registers */
 377 #if !defined(CONFIG_USER_ONLY)
 378 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 379 {
 380     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 381 }
 382
 383 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 384 {
 385     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 386 }
 387
 388 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 389 {
 390     DisasContext *ctx = opaque;
 391
 392     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 393     /* We must stop translation as we may have rebooted */
 394     gen_stop_exception(ctx);
 395 }
 396
 397 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 398 {
 399     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 400 }
 401
 402 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 403 {
 404     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 405 }
 406
 407 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 408 {
 409     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 410 }
 411 #endif
 412
 413 /* PowerPC 403 specific registers */
 414 /* PBL1 / PBU1 / PBL2 / PBU2 */
 415 #if !defined(CONFIG_USER_ONLY)
 416 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 417 {
 418     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 419 }
 420
 421 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 422 {
 423     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 424     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 425     tcg_temp_free_i32(t0);
 426 }
 427
 428 static void spr_write_pir (void *opaque, int sprn, int gprn)
 429 {
 430     TCGv t0 = tcg_temp_new();
 431     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 432     gen_store_spr(SPR_PIR, t0);
 433     tcg_temp_free(t0);
 434 }
 435 #endif
 436
 437 #if !defined(CONFIG_USER_ONLY)
 438 /* Callback used to write the exception vector base */
 439 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 440 {
 441     TCGv t0 = tcg_temp_new();
 442     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 443     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 444     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 445     gen_store_spr(sprn, t0);
 446 }
 447
 448 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 449 {
 450     DisasContext *ctx = opaque;
 451
 452     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 453         TCGv t0 = tcg_temp_new();
 454         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 455         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 456         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 457         gen_store_spr(sprn, t0);
 458         tcg_temp_free(t0);
 459     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 460         TCGv t0 = tcg_temp_new();
 461         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 462         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 463         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 464         gen_store_spr(sprn, t0);
 465         tcg_temp_free(t0);
 466     } else {
 467         printf("Trying to write an unknown exception vector %d %03x\n",
 468                sprn, sprn);
 469         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 470     }
 471 }
 472 #endif
 473
 474 #if defined(CONFIG_USER_ONLY)
 475 #define spr_register(env, num, name, uea_read, uea_write,                     \
 476                      oea_read, oea_write, initial_value)                      \
 477 do {                                                                          \
 478      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 479 } while (0)
 480 static inline void _spr_register (CPUPPCState *env, int num,
 481                                   const char *name,
 482                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 483                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 484                                   target_ulong initial_value)
 485 #else
 486 static inline void spr_register (CPUPPCState *env, int num,
 487                                  const char *name,
 488                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 489                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 490                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 491                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 492                                  target_ulong initial_value)
 493 #endif
 494 {
 495     ppc_spr_t *spr;
 496
 497     spr = &env->spr_cb[num];
 498     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 499 #if !defined(CONFIG_USER_ONLY)
 500         spr->oea_read != NULL || spr->oea_write != NULL ||
 501 #endif
 502         spr->uea_read != NULL || spr->uea_write != NULL) {
 503         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 504         exit(1);
 505     }
 506 #if defined(PPC_DEBUG_SPR)
 507     printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
 508            initial_value);
 509 #endif
 510     spr->name = name;
 511     spr->uea_read = uea_read;
 512     spr->uea_write = uea_write;
 513 #if !defined(CONFIG_USER_ONLY)
 514     spr->oea_read = oea_read;
 515     spr->oea_write = oea_write;
 516 #endif
 517     env->spr[num] = initial_value;
 518 }
 519
 520 /* Generic PowerPC SPRs */
 521 static void gen_spr_generic (CPUPPCState *env)
 522 {
 523     /* Integer processing */
 524     spr_register(env, SPR_XER, "XER",
 525                  &spr_read_xer, &spr_write_xer,
 526                  &spr_read_xer, &spr_write_xer,
 527                  0x00000000);
 528     /* Branch contol */
 529     spr_register(env, SPR_LR, "LR",
 530                  &spr_read_lr, &spr_write_lr,
 531                  &spr_read_lr, &spr_write_lr,
 532                  0x00000000);
 533     spr_register(env, SPR_CTR, "CTR",
 534                  &spr_read_ctr, &spr_write_ctr,
 535                  &spr_read_ctr, &spr_write_ctr,
 536                  0x00000000);
 537     /* Interrupt processing */
 538     spr_register(env, SPR_SRR0, "SRR0",
 539                  SPR_NOACCESS, SPR_NOACCESS,
 540                  &spr_read_generic, &spr_write_generic,
 541                  0x00000000);
 542     spr_register(env, SPR_SRR1, "SRR1",
 543                  SPR_NOACCESS, SPR_NOACCESS,
 544                  &spr_read_generic, &spr_write_generic,
 545                  0x00000000);
 546     /* Processor control */
 547     spr_register(env, SPR_SPRG0, "SPRG0",
 548                  SPR_NOACCESS, SPR_NOACCESS,
 549                  &spr_read_generic, &spr_write_generic,
 550                  0x00000000);
 551     spr_register(env, SPR_SPRG1, "SPRG1",
 552                  SPR_NOACCESS, SPR_NOACCESS,
 553                  &spr_read_generic, &spr_write_generic,
 554                  0x00000000);
 555     spr_register(env, SPR_SPRG2, "SPRG2",
 556                  SPR_NOACCESS, SPR_NOACCESS,
 557                  &spr_read_generic, &spr_write_generic,
 558                  0x00000000);
 559     spr_register(env, SPR_SPRG3, "SPRG3",
 560                  SPR_NOACCESS, SPR_NOACCESS,
 561                  &spr_read_generic, &spr_write_generic,
 562                  0x00000000);
 563 }
 564
 565 /* SPR common to all non-embedded PowerPC, including 601 */
 566 static void gen_spr_ne_601 (CPUPPCState *env)
 567 {
 568     /* Exception processing */
 569     spr_register(env, SPR_DSISR, "DSISR",
 570                  SPR_NOACCESS, SPR_NOACCESS,
 571                  &spr_read_generic, &spr_write_generic,
 572                  0x00000000);
 573     spr_register(env, SPR_DAR, "DAR",
 574                  SPR_NOACCESS, SPR_NOACCESS,
 575                  &spr_read_generic, &spr_write_generic,
 576                  0x00000000);
 577     /* Timer */
 578     spr_register(env, SPR_DECR, "DECR",
 579                  SPR_NOACCESS, SPR_NOACCESS,
 580                  &spr_read_decr, &spr_write_decr,
 581                  0x00000000);
 582     /* Memory management */
 583     spr_register(env, SPR_SDR1, "SDR1",
 584                  SPR_NOACCESS, SPR_NOACCESS,
 585                  &spr_read_sdr1, &spr_write_sdr1,
 586                  0x00000000);
 587 }
 588
 589 /* BATs 0-3 */
 590 static void gen_low_BATs (CPUPPCState *env)
 591 {
 592 #if !defined(CONFIG_USER_ONLY)
 593     spr_register(env, SPR_IBAT0U, "IBAT0U",
 594                  SPR_NOACCESS, SPR_NOACCESS,
 595                  &spr_read_ibat, &spr_write_ibatu,
 596                  0x00000000);
 597     spr_register(env, SPR_IBAT0L, "IBAT0L",
 598                  SPR_NOACCESS, SPR_NOACCESS,
 599                  &spr_read_ibat, &spr_write_ibatl,
 600                  0x00000000);
 601     spr_register(env, SPR_IBAT1U, "IBAT1U",
 602                  SPR_NOACCESS, SPR_NOACCESS,
 603                  &spr_read_ibat, &spr_write_ibatu,
 604                  0x00000000);
 605     spr_register(env, SPR_IBAT1L, "IBAT1L",
 606                  SPR_NOACCESS, SPR_NOACCESS,
 607                  &spr_read_ibat, &spr_write_ibatl,
 608                  0x00000000);
 609     spr_register(env, SPR_IBAT2U, "IBAT2U",
 610                  SPR_NOACCESS, SPR_NOACCESS,
 611                  &spr_read_ibat, &spr_write_ibatu,
 612                  0x00000000);
 613     spr_register(env, SPR_IBAT2L, "IBAT2L",
 614                  SPR_NOACCESS, SPR_NOACCESS,
 615                  &spr_read_ibat, &spr_write_ibatl,
 616                  0x00000000);
 617     spr_register(env, SPR_IBAT3U, "IBAT3U",
 618                  SPR_NOACCESS, SPR_NOACCESS,
 619                  &spr_read_ibat, &spr_write_ibatu,
 620                  0x00000000);
 621     spr_register(env, SPR_IBAT3L, "IBAT3L",
 622                  SPR_NOACCESS, SPR_NOACCESS,
 623                  &spr_read_ibat, &spr_write_ibatl,
 624                  0x00000000);
 625     spr_register(env, SPR_DBAT0U, "DBAT0U",
 626                  SPR_NOACCESS, SPR_NOACCESS,
 627                  &spr_read_dbat, &spr_write_dbatu,
 628                  0x00000000);
 629     spr_register(env, SPR_DBAT0L, "DBAT0L",
 630                  SPR_NOACCESS, SPR_NOACCESS,
 631                  &spr_read_dbat, &spr_write_dbatl,
 632                  0x00000000);
 633     spr_register(env, SPR_DBAT1U, "DBAT1U",
 634                  SPR_NOACCESS, SPR_NOACCESS,
 635                  &spr_read_dbat, &spr_write_dbatu,
 636                  0x00000000);
 637     spr_register(env, SPR_DBAT1L, "DBAT1L",
 638                  SPR_NOACCESS, SPR_NOACCESS,
 639                  &spr_read_dbat, &spr_write_dbatl,
 640                  0x00000000);
 641     spr_register(env, SPR_DBAT2U, "DBAT2U",
 642                  SPR_NOACCESS, SPR_NOACCESS,
 643                  &spr_read_dbat, &spr_write_dbatu,
 644                  0x00000000);
 645     spr_register(env, SPR_DBAT2L, "DBAT2L",
 646                  SPR_NOACCESS, SPR_NOACCESS,
 647                  &spr_read_dbat, &spr_write_dbatl,
 648                  0x00000000);
 649     spr_register(env, SPR_DBAT3U, "DBAT3U",
 650                  SPR_NOACCESS, SPR_NOACCESS,
 651                  &spr_read_dbat, &spr_write_dbatu,
 652                  0x00000000);
 653     spr_register(env, SPR_DBAT3L, "DBAT3L",
 654                  SPR_NOACCESS, SPR_NOACCESS,
 655                  &spr_read_dbat, &spr_write_dbatl,
 656                  0x00000000);
 657     env->nb_BATs += 4;
 658 #endif
 659 }
 660
 661 /* BATs 4-7 */
 662 static void gen_high_BATs (CPUPPCState *env)
 663 {
 664 #if !defined(CONFIG_USER_ONLY)
 665     spr_register(env, SPR_IBAT4U, "IBAT4U",
 666                  SPR_NOACCESS, SPR_NOACCESS,
 667                  &spr_read_ibat_h, &spr_write_ibatu_h,
 668                  0x00000000);
 669     spr_register(env, SPR_IBAT4L, "IBAT4L",
 670                  SPR_NOACCESS, SPR_NOACCESS,
 671                  &spr_read_ibat_h, &spr_write_ibatl_h,
 672                  0x00000000);
 673     spr_register(env, SPR_IBAT5U, "IBAT5U",
 674                  SPR_NOACCESS, SPR_NOACCESS,
 675                  &spr_read_ibat_h, &spr_write_ibatu_h,
 676                  0x00000000);
 677     spr_register(env, SPR_IBAT5L, "IBAT5L",
 678                  SPR_NOACCESS, SPR_NOACCESS,
 679                  &spr_read_ibat_h, &spr_write_ibatl_h,
 680                  0x00000000);
 681     spr_register(env, SPR_IBAT6U, "IBAT6U",
 682                  SPR_NOACCESS, SPR_NOACCESS,
 683                  &spr_read_ibat_h, &spr_write_ibatu_h,
 684                  0x00000000);
 685     spr_register(env, SPR_IBAT6L, "IBAT6L",
 686                  SPR_NOACCESS, SPR_NOACCESS,
 687                  &spr_read_ibat_h, &spr_write_ibatl_h,
 688                  0x00000000);
 689     spr_register(env, SPR_IBAT7U, "IBAT7U",
 690                  SPR_NOACCESS, SPR_NOACCESS,
 691                  &spr_read_ibat_h, &spr_write_ibatu_h,
 692                  0x00000000);
 693     spr_register(env, SPR_IBAT7L, "IBAT7L",
 694                  SPR_NOACCESS, SPR_NOACCESS,
 695                  &spr_read_ibat_h, &spr_write_ibatl_h,
 696                  0x00000000);
 697     spr_register(env, SPR_DBAT4U, "DBAT4U",
 698                  SPR_NOACCESS, SPR_NOACCESS,
 699                  &spr_read_dbat_h, &spr_write_dbatu_h,
 700                  0x00000000);
 701     spr_register(env, SPR_DBAT4L, "DBAT4L",
 702                  SPR_NOACCESS, SPR_NOACCESS,
 703                  &spr_read_dbat_h, &spr_write_dbatl_h,
 704                  0x00000000);
 705     spr_register(env, SPR_DBAT5U, "DBAT5U",
 706                  SPR_NOACCESS, SPR_NOACCESS,
 707                  &spr_read_dbat_h, &spr_write_dbatu_h,
 708                  0x00000000);
 709     spr_register(env, SPR_DBAT5L, "DBAT5L",
 710                  SPR_NOACCESS, SPR_NOACCESS,
 711                  &spr_read_dbat_h, &spr_write_dbatl_h,
 712                  0x00000000);
 713     spr_register(env, SPR_DBAT6U, "DBAT6U",
 714                  SPR_NOACCESS, SPR_NOACCESS,
 715                  &spr_read_dbat_h, &spr_write_dbatu_h,
 716                  0x00000000);
 717     spr_register(env, SPR_DBAT6L, "DBAT6L",
 718                  SPR_NOACCESS, SPR_NOACCESS,
 719                  &spr_read_dbat_h, &spr_write_dbatl_h,
 720                  0x00000000);
 721     spr_register(env, SPR_DBAT7U, "DBAT7U",
 722                  SPR_NOACCESS, SPR_NOACCESS,
 723                  &spr_read_dbat_h, &spr_write_dbatu_h,
 724                  0x00000000);
 725     spr_register(env, SPR_DBAT7L, "DBAT7L",
 726                  SPR_NOACCESS, SPR_NOACCESS,
 727                  &spr_read_dbat_h, &spr_write_dbatl_h,
 728                  0x00000000);
 729     env->nb_BATs += 4;
 730 #endif
 731 }
 732
 733 /* Generic PowerPC time base */
 734 static void gen_tbl (CPUPPCState *env)
 735 {
 736     spr_register(env, SPR_VTBL,  "TBL",
 737                  &spr_read_tbl, SPR_NOACCESS,
 738                  &spr_read_tbl, SPR_NOACCESS,
 739                  0x00000000);
 740     spr_register(env, SPR_TBL,   "TBL",
 741                  SPR_NOACCESS, SPR_NOACCESS,
 742                  SPR_NOACCESS, &spr_write_tbl,
 743                  0x00000000);
 744     spr_register(env, SPR_VTBU,  "TBU",
 745                  &spr_read_tbu, SPR_NOACCESS,
 746                  &spr_read_tbu, SPR_NOACCESS,
 747                  0x00000000);
 748     spr_register(env, SPR_TBU,   "TBU",
 749                  SPR_NOACCESS, SPR_NOACCESS,
 750                  SPR_NOACCESS, &spr_write_tbu,
 751                  0x00000000);
 752 }
 753
 754 /* Softare table search registers */
 755 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 756 {
 757 #if !defined(CONFIG_USER_ONLY)
 758     env->nb_tlb = nb_tlbs;
 759     env->nb_ways = nb_ways;
 760     env->id_tlbs = 1;
 761     spr_register(env, SPR_DMISS, "DMISS",
 762                  SPR_NOACCESS, SPR_NOACCESS,
 763                  &spr_read_generic, SPR_NOACCESS,
 764                  0x00000000);
 765     spr_register(env, SPR_DCMP, "DCMP",
 766                  SPR_NOACCESS, SPR_NOACCESS,
 767                  &spr_read_generic, SPR_NOACCESS,
 768                  0x00000000);
 769     spr_register(env, SPR_HASH1, "HASH1",
 770                  SPR_NOACCESS, SPR_NOACCESS,
 771                  &spr_read_generic, SPR_NOACCESS,
 772                  0x00000000);
 773     spr_register(env, SPR_HASH2, "HASH2",
 774                  SPR_NOACCESS, SPR_NOACCESS,
 775                  &spr_read_generic, SPR_NOACCESS,
 776                  0x00000000);
 777     spr_register(env, SPR_IMISS, "IMISS",
 778                  SPR_NOACCESS, SPR_NOACCESS,
 779                  &spr_read_generic, SPR_NOACCESS,
 780                  0x00000000);
 781     spr_register(env, SPR_ICMP, "ICMP",
 782                  SPR_NOACCESS, SPR_NOACCESS,
 783                  &spr_read_generic, SPR_NOACCESS,
 784                  0x00000000);
 785     spr_register(env, SPR_RPA, "RPA",
 786                  SPR_NOACCESS, SPR_NOACCESS,
 787                  &spr_read_generic, &spr_write_generic,
 788                  0x00000000);
 789 #endif
 790 }
 791
 792 /* SPR common to MPC755 and G2 */
 793 static void gen_spr_G2_755 (CPUPPCState *env)
 794 {
 795     /* SGPRs */
 796     spr_register(env, SPR_SPRG4, "SPRG4",
 797                  SPR_NOACCESS, SPR_NOACCESS,
 798                  &spr_read_generic, &spr_write_generic,
 799                  0x00000000);
 800     spr_register(env, SPR_SPRG5, "SPRG5",
 801                  SPR_NOACCESS, SPR_NOACCESS,
 802                  &spr_read_generic, &spr_write_generic,
 803                  0x00000000);
 804     spr_register(env, SPR_SPRG6, "SPRG6",
 805                  SPR_NOACCESS, SPR_NOACCESS,
 806                  &spr_read_generic, &spr_write_generic,
 807                  0x00000000);
 808     spr_register(env, SPR_SPRG7, "SPRG7",
 809                  SPR_NOACCESS, SPR_NOACCESS,
 810                  &spr_read_generic, &spr_write_generic,
 811                  0x00000000);
 812 }
 813
 814 /* SPR common to all 7xx PowerPC implementations */
 815 static void gen_spr_7xx (CPUPPCState *env)
 816 {
 817     /* Breakpoints */
 818     /* XXX : not implemented */
 819     spr_register(env, SPR_DABR, "DABR",
 820                  SPR_NOACCESS, SPR_NOACCESS,
 821                  &spr_read_generic, &spr_write_generic,
 822                  0x00000000);
 823     /* XXX : not implemented */
 824     spr_register(env, SPR_IABR, "IABR",
 825                  SPR_NOACCESS, SPR_NOACCESS,
 826                  &spr_read_generic, &spr_write_generic,
 827                  0x00000000);
 828     /* Cache management */
 829     /* XXX : not implemented */
 830     spr_register(env, SPR_ICTC, "ICTC",
 831                  SPR_NOACCESS, SPR_NOACCESS,
 832                  &spr_read_generic, &spr_write_generic,
 833                  0x00000000);
 834     /* Performance monitors */
 835     /* XXX : not implemented */
 836     spr_register(env, SPR_MMCR0, "MMCR0",
 837                  SPR_NOACCESS, SPR_NOACCESS,
 838                  &spr_read_generic, &spr_write_generic,
 839                  0x00000000);
 840     /* XXX : not implemented */
 841     spr_register(env, SPR_MMCR1, "MMCR1",
 842                  SPR_NOACCESS, SPR_NOACCESS,
 843                  &spr_read_generic, &spr_write_generic,
 844                  0x00000000);
 845     /* XXX : not implemented */
 846     spr_register(env, SPR_PMC1, "PMC1",
 847                  SPR_NOACCESS, SPR_NOACCESS,
 848                  &spr_read_generic, &spr_write_generic,
 849                  0x00000000);
 850     /* XXX : not implemented */
 851     spr_register(env, SPR_PMC2, "PMC2",
 852                  SPR_NOACCESS, SPR_NOACCESS,
 853                  &spr_read_generic, &spr_write_generic,
 854                  0x00000000);
 855     /* XXX : not implemented */
 856     spr_register(env, SPR_PMC3, "PMC3",
 857                  SPR_NOACCESS, SPR_NOACCESS,
 858                  &spr_read_generic, &spr_write_generic,
 859                  0x00000000);
 860     /* XXX : not implemented */
 861     spr_register(env, SPR_PMC4, "PMC4",
 862                  SPR_NOACCESS, SPR_NOACCESS,
 863                  &spr_read_generic, &spr_write_generic,
 864                  0x00000000);
 865     /* XXX : not implemented */
 866     spr_register(env, SPR_SIAR, "SIAR",
 867                  SPR_NOACCESS, SPR_NOACCESS,
 868                  &spr_read_generic, SPR_NOACCESS,
 869                  0x00000000);
 870     /* XXX : not implemented */
 871     spr_register(env, SPR_UMMCR0, "UMMCR0",
 872                  &spr_read_ureg, SPR_NOACCESS,
 873                  &spr_read_ureg, SPR_NOACCESS,
 874                  0x00000000);
 875     /* XXX : not implemented */
 876     spr_register(env, SPR_UMMCR1, "UMMCR1",
 877                  &spr_read_ureg, SPR_NOACCESS,
 878                  &spr_read_ureg, SPR_NOACCESS,
 879                  0x00000000);
 880     /* XXX : not implemented */
 881     spr_register(env, SPR_UPMC1, "UPMC1",
 882                  &spr_read_ureg, SPR_NOACCESS,
 883                  &spr_read_ureg, SPR_NOACCESS,
 884                  0x00000000);
 885     /* XXX : not implemented */
 886     spr_register(env, SPR_UPMC2, "UPMC2",
 887                  &spr_read_ureg, SPR_NOACCESS,
 888                  &spr_read_ureg, SPR_NOACCESS,
 889                  0x00000000);
 890     /* XXX : not implemented */
 891     spr_register(env, SPR_UPMC3, "UPMC3",
 892                  &spr_read_ureg, SPR_NOACCESS,
 893                  &spr_read_ureg, SPR_NOACCESS,
 894                  0x00000000);
 895     /* XXX : not implemented */
 896     spr_register(env, SPR_UPMC4, "UPMC4",
 897                  &spr_read_ureg, SPR_NOACCESS,
 898                  &spr_read_ureg, SPR_NOACCESS,
 899                  0x00000000);
 900     /* XXX : not implemented */
 901     spr_register(env, SPR_USIAR, "USIAR",
 902                  &spr_read_ureg, SPR_NOACCESS,
 903                  &spr_read_ureg, SPR_NOACCESS,
 904                  0x00000000);
 905     /* External access control */
 906     /* XXX : not implemented */
 907     spr_register(env, SPR_EAR, "EAR",
 908                  SPR_NOACCESS, SPR_NOACCESS,
 909                  &spr_read_generic, &spr_write_generic,
 910                  0x00000000);
 911 }
 912
 913 static void gen_spr_thrm (CPUPPCState *env)
 914 {
 915     /* Thermal management */
 916     /* XXX : not implemented */
 917     spr_register(env, SPR_THRM1, "THRM1",
 918                  SPR_NOACCESS, SPR_NOACCESS,
 919                  &spr_read_generic, &spr_write_generic,
 920                  0x00000000);
 921     /* XXX : not implemented */
 922     spr_register(env, SPR_THRM2, "THRM2",
 923                  SPR_NOACCESS, SPR_NOACCESS,
 924                  &spr_read_generic, &spr_write_generic,
 925                  0x00000000);
 926     /* XXX : not implemented */
 927     spr_register(env, SPR_THRM3, "THRM3",
 928                  SPR_NOACCESS, SPR_NOACCESS,
 929                  &spr_read_generic, &spr_write_generic,
 930                  0x00000000);
 931 }
 932
 933 /* SPR specific to PowerPC 604 implementation */
 934 static void gen_spr_604 (CPUPPCState *env)
 935 {
 936     /* Processor identification */
 937     spr_register(env, SPR_PIR, "PIR",
 938                  SPR_NOACCESS, SPR_NOACCESS,
 939                  &spr_read_generic, &spr_write_pir,
 940                  0x00000000);
 941     /* Breakpoints */
 942     /* XXX : not implemented */
 943     spr_register(env, SPR_IABR, "IABR",
 944                  SPR_NOACCESS, SPR_NOACCESS,
 945                  &spr_read_generic, &spr_write_generic,
 946                  0x00000000);
 947     /* XXX : not implemented */
 948     spr_register(env, SPR_DABR, "DABR",
 949                  SPR_NOACCESS, SPR_NOACCESS,
 950                  &spr_read_generic, &spr_write_generic,
 951                  0x00000000);
 952     /* Performance counters */
 953     /* XXX : not implemented */
 954     spr_register(env, SPR_MMCR0, "MMCR0",
 955                  SPR_NOACCESS, SPR_NOACCESS,
 956                  &spr_read_generic, &spr_write_generic,
 957                  0x00000000);
 958     /* XXX : not implemented */
 959     spr_register(env, SPR_PMC1, "PMC1",
 960                  SPR_NOACCESS, SPR_NOACCESS,
 961                  &spr_read_generic, &spr_write_generic,
 962                  0x00000000);
 963     /* XXX : not implemented */
 964     spr_register(env, SPR_PMC2, "PMC2",
 965                  SPR_NOACCESS, SPR_NOACCESS,
 966                  &spr_read_generic, &spr_write_generic,
 967                  0x00000000);
 968     /* XXX : not implemented */
 969     spr_register(env, SPR_SIAR, "SIAR",
 970                  SPR_NOACCESS, SPR_NOACCESS,
 971                  &spr_read_generic, SPR_NOACCESS,
 972                  0x00000000);
 973     /* XXX : not implemented */
 974     spr_register(env, SPR_SDA, "SDA",
 975                  SPR_NOACCESS, SPR_NOACCESS,
 976                  &spr_read_generic, SPR_NOACCESS,
 977                  0x00000000);
 978     /* External access control */
 979     /* XXX : not implemented */
 980     spr_register(env, SPR_EAR, "EAR",
 981                  SPR_NOACCESS, SPR_NOACCESS,
 982                  &spr_read_generic, &spr_write_generic,
 983                  0x00000000);
 984 }
 985
 986 /* SPR specific to PowerPC 603 implementation */
 987 static void gen_spr_603 (CPUPPCState *env)
 988 {
 989     /* External access control */
 990     /* XXX : not implemented */
 991     spr_register(env, SPR_EAR, "EAR",
 992                  SPR_NOACCESS, SPR_NOACCESS,
 993                  &spr_read_generic, &spr_write_generic,
 994                  0x00000000);
 995 }
 996
 997 /* SPR specific to PowerPC G2 implementation */
 998 static void gen_spr_G2 (CPUPPCState *env)
 999 {
1000     /* Memory base address */
1001     /* MBAR */
1002     /* XXX : not implemented */
1003     spr_register(env, SPR_MBAR, "MBAR",
1004                  SPR_NOACCESS, SPR_NOACCESS,
1005                  &spr_read_generic, &spr_write_generic,
1006                  0x00000000);
1007     /* Exception processing */
1008     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1009                  SPR_NOACCESS, SPR_NOACCESS,
1010                  &spr_read_generic, &spr_write_generic,
1011                  0x00000000);
1012     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1013                  SPR_NOACCESS, SPR_NOACCESS,
1014                  &spr_read_generic, &spr_write_generic,
1015                  0x00000000);
1016     /* Breakpoints */
1017     /* XXX : not implemented */
1018     spr_register(env, SPR_DABR, "DABR",
1019                  SPR_NOACCESS, SPR_NOACCESS,
1020                  &spr_read_generic, &spr_write_generic,
1021                  0x00000000);
1022     /* XXX : not implemented */
1023     spr_register(env, SPR_DABR2, "DABR2",
1024                  SPR_NOACCESS, SPR_NOACCESS,
1025                  &spr_read_generic, &spr_write_generic,
1026                  0x00000000);
1027     /* XXX : not implemented */
1028     spr_register(env, SPR_IABR, "IABR",
1029                  SPR_NOACCESS, SPR_NOACCESS,
1030                  &spr_read_generic, &spr_write_generic,
1031                  0x00000000);
1032     /* XXX : not implemented */
1033     spr_register(env, SPR_IABR2, "IABR2",
1034                  SPR_NOACCESS, SPR_NOACCESS,
1035                  &spr_read_generic, &spr_write_generic,
1036                  0x00000000);
1037     /* XXX : not implemented */
1038     spr_register(env, SPR_IBCR, "IBCR",
1039                  SPR_NOACCESS, SPR_NOACCESS,
1040                  &spr_read_generic, &spr_write_generic,
1041                  0x00000000);
1042     /* XXX : not implemented */
1043     spr_register(env, SPR_DBCR, "DBCR",
1044                  SPR_NOACCESS, SPR_NOACCESS,
1045                  &spr_read_generic, &spr_write_generic,
1046                  0x00000000);
1047 }
1048
1049 /* SPR specific to PowerPC 602 implementation */
1050 static void gen_spr_602 (CPUPPCState *env)
1051 {
1052     /* ESA registers */
1053     /* XXX : not implemented */
1054     spr_register(env, SPR_SER, "SER",
1055                  SPR_NOACCESS, SPR_NOACCESS,
1056                  &spr_read_generic, &spr_write_generic,
1057                  0x00000000);
1058     /* XXX : not implemented */
1059     spr_register(env, SPR_SEBR, "SEBR",
1060                  SPR_NOACCESS, SPR_NOACCESS,
1061                  &spr_read_generic, &spr_write_generic,
1062                  0x00000000);
1063     /* XXX : not implemented */
1064     spr_register(env, SPR_ESASRR, "ESASRR",
1065                  SPR_NOACCESS, SPR_NOACCESS,
1066                  &spr_read_generic, &spr_write_generic,
1067                  0x00000000);
1068     /* Floating point status */
1069     /* XXX : not implemented */
1070     spr_register(env, SPR_SP, "SP",
1071                  SPR_NOACCESS, SPR_NOACCESS,
1072                  &spr_read_generic, &spr_write_generic,
1073                  0x00000000);
1074     /* XXX : not implemented */
1075     spr_register(env, SPR_LT, "LT",
1076                  SPR_NOACCESS, SPR_NOACCESS,
1077                  &spr_read_generic, &spr_write_generic,
1078                  0x00000000);
1079     /* Watchdog timer */
1080     /* XXX : not implemented */
1081     spr_register(env, SPR_TCR, "TCR",
1082                  SPR_NOACCESS, SPR_NOACCESS,
1083                  &spr_read_generic, &spr_write_generic,
1084                  0x00000000);
1085     /* Interrupt base */
1086     spr_register(env, SPR_IBR, "IBR",
1087                  SPR_NOACCESS, SPR_NOACCESS,
1088                  &spr_read_generic, &spr_write_generic,
1089                  0x00000000);
1090     /* XXX : not implemented */
1091     spr_register(env, SPR_IABR, "IABR",
1092                  SPR_NOACCESS, SPR_NOACCESS,
1093                  &spr_read_generic, &spr_write_generic,
1094                  0x00000000);
1095 }
1096
1097 /* SPR specific to PowerPC 601 implementation */
1098 static void gen_spr_601 (CPUPPCState *env)
1099 {
1100     /* Multiplication/division register */
1101     /* MQ */
1102     spr_register(env, SPR_MQ, "MQ",
1103                  &spr_read_generic, &spr_write_generic,
1104                  &spr_read_generic, &spr_write_generic,
1105                  0x00000000);
1106     /* RTC registers */
1107     spr_register(env, SPR_601_RTCU, "RTCU",
1108                  SPR_NOACCESS, SPR_NOACCESS,
1109                  SPR_NOACCESS, &spr_write_601_rtcu,
1110                  0x00000000);
1111     spr_register(env, SPR_601_VRTCU, "RTCU",
1112                  &spr_read_601_rtcu, SPR_NOACCESS,
1113                  &spr_read_601_rtcu, SPR_NOACCESS,
1114                  0x00000000);
1115     spr_register(env, SPR_601_RTCL, "RTCL",
1116                  SPR_NOACCESS, SPR_NOACCESS,
1117                  SPR_NOACCESS, &spr_write_601_rtcl,
1118                  0x00000000);
1119     spr_register(env, SPR_601_VRTCL, "RTCL",
1120                  &spr_read_601_rtcl, SPR_NOACCESS,
1121                  &spr_read_601_rtcl, SPR_NOACCESS,
1122                  0x00000000);
1123     /* Timer */
1124 #if 0 /* ? */
1125     spr_register(env, SPR_601_UDECR, "UDECR",
1126                  &spr_read_decr, SPR_NOACCESS,
1127                  &spr_read_decr, SPR_NOACCESS,
1128                  0x00000000);
1129 #endif
1130     /* External access control */
1131     /* XXX : not implemented */
1132     spr_register(env, SPR_EAR, "EAR",
1133                  SPR_NOACCESS, SPR_NOACCESS,
1134                  &spr_read_generic, &spr_write_generic,
1135                  0x00000000);
1136     /* Memory management */
1137 #if !defined(CONFIG_USER_ONLY)
1138     spr_register(env, SPR_IBAT0U, "IBAT0U",
1139                  SPR_NOACCESS, SPR_NOACCESS,
1140                  &spr_read_601_ubat, &spr_write_601_ubatu,
1141                  0x00000000);
1142     spr_register(env, SPR_IBAT0L, "IBAT0L",
1143                  SPR_NOACCESS, SPR_NOACCESS,
1144                  &spr_read_601_ubat, &spr_write_601_ubatl,
1145                  0x00000000);
1146     spr_register(env, SPR_IBAT1U, "IBAT1U",
1147                  SPR_NOACCESS, SPR_NOACCESS,
1148                  &spr_read_601_ubat, &spr_write_601_ubatu,
1149                  0x00000000);
1150     spr_register(env, SPR_IBAT1L, "IBAT1L",
1151                  SPR_NOACCESS, SPR_NOACCESS,
1152                  &spr_read_601_ubat, &spr_write_601_ubatl,
1153                  0x00000000);
1154     spr_register(env, SPR_IBAT2U, "IBAT2U",
1155                  SPR_NOACCESS, SPR_NOACCESS,
1156                  &spr_read_601_ubat, &spr_write_601_ubatu,
1157                  0x00000000);
1158     spr_register(env, SPR_IBAT2L, "IBAT2L",
1159                  SPR_NOACCESS, SPR_NOACCESS,
1160                  &spr_read_601_ubat, &spr_write_601_ubatl,
1161                  0x00000000);
1162     spr_register(env, SPR_IBAT3U, "IBAT3U",
1163                  SPR_NOACCESS, SPR_NOACCESS,
1164                  &spr_read_601_ubat, &spr_write_601_ubatu,
1165                  0x00000000);
1166     spr_register(env, SPR_IBAT3L, "IBAT3L",
1167                  SPR_NOACCESS, SPR_NOACCESS,
1168                  &spr_read_601_ubat, &spr_write_601_ubatl,
1169                  0x00000000);
1170     env->nb_BATs = 4;
1171 #endif
1172 }
1173
1174 static void gen_spr_74xx (CPUPPCState *env)
1175 {
1176     /* Processor identification */
1177     spr_register(env, SPR_PIR, "PIR",
1178                  SPR_NOACCESS, SPR_NOACCESS,
1179                  &spr_read_generic, &spr_write_pir,
1180                  0x00000000);
1181     /* XXX : not implemented */
1182     spr_register(env, SPR_MMCR2, "MMCR2",
1183                  SPR_NOACCESS, SPR_NOACCESS,
1184                  &spr_read_generic, &spr_write_generic,
1185                  0x00000000);
1186     /* XXX : not implemented */
1187     spr_register(env, SPR_UMMCR2, "UMMCR2",
1188                  &spr_read_ureg, SPR_NOACCESS,
1189                  &spr_read_ureg, SPR_NOACCESS,
1190                  0x00000000);
1191     /* XXX: not implemented */
1192     spr_register(env, SPR_BAMR, "BAMR",
1193                  SPR_NOACCESS, SPR_NOACCESS,
1194                  &spr_read_generic, &spr_write_generic,
1195                  0x00000000);
1196     /* XXX : not implemented */
1197     spr_register(env, SPR_MSSCR0, "MSSCR0",
1198                  SPR_NOACCESS, SPR_NOACCESS,
1199                  &spr_read_generic, &spr_write_generic,
1200                  0x00000000);
1201     /* Hardware implementation registers */
1202     /* XXX : not implemented */
1203     spr_register(env, SPR_HID0, "HID0",
1204                  SPR_NOACCESS, SPR_NOACCESS,
1205                  &spr_read_generic, &spr_write_generic,
1206                  0x00000000);
1207     /* XXX : not implemented */
1208     spr_register(env, SPR_HID1, "HID1",
1209                  SPR_NOACCESS, SPR_NOACCESS,
1210                  &spr_read_generic, &spr_write_generic,
1211                  0x00000000);
1212     /* Altivec */
1213     spr_register(env, SPR_VRSAVE, "VRSAVE",
1214                  &spr_read_generic, &spr_write_generic,
1215                  &spr_read_generic, &spr_write_generic,
1216                  0x00000000);
1217     /* XXX : not implemented */
1218     spr_register(env, SPR_L2CR, "L2CR",
1219                  SPR_NOACCESS, SPR_NOACCESS,
1220                  &spr_read_generic, &spr_write_generic,
1221                  0x00000000);
1222 }
1223
1224 static void gen_l3_ctrl (CPUPPCState *env)
1225 {
1226     /* L3CR */
1227     /* XXX : not implemented */
1228     spr_register(env, SPR_L3CR, "L3CR",
1229                  SPR_NOACCESS, SPR_NOACCESS,
1230                  &spr_read_generic, &spr_write_generic,
1231                  0x00000000);
1232     /* L3ITCR0 */
1233     /* XXX : not implemented */
1234     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1235                  SPR_NOACCESS, SPR_NOACCESS,
1236                  &spr_read_generic, &spr_write_generic,
1237                  0x00000000);
1238     /* L3PM */
1239     /* XXX : not implemented */
1240     spr_register(env, SPR_L3PM, "L3PM",
1241                  SPR_NOACCESS, SPR_NOACCESS,
1242                  &spr_read_generic, &spr_write_generic,
1243                  0x00000000);
1244 }
1245
1246 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1247 {
1248 #if !defined(CONFIG_USER_ONLY)
1249     env->nb_tlb = nb_tlbs;
1250     env->nb_ways = nb_ways;
1251     env->id_tlbs = 1;
1252     /* XXX : not implemented */
1253     spr_register(env, SPR_PTEHI, "PTEHI",
1254                  SPR_NOACCESS, SPR_NOACCESS,
1255                  &spr_read_generic, &spr_write_generic,
1256                  0x00000000);
1257     /* XXX : not implemented */
1258     spr_register(env, SPR_PTELO, "PTELO",
1259                  SPR_NOACCESS, SPR_NOACCESS,
1260                  &spr_read_generic, &spr_write_generic,
1261                  0x00000000);
1262     /* XXX : not implemented */
1263     spr_register(env, SPR_TLBMISS, "TLBMISS",
1264                  SPR_NOACCESS, SPR_NOACCESS,
1265                  &spr_read_generic, &spr_write_generic,
1266                  0x00000000);
1267 #endif
1268 }
1269
1270 static void gen_spr_usprgh (CPUPPCState *env)
1271 {
1272     spr_register(env, SPR_USPRG4, "USPRG4",
1273                  &spr_read_ureg, SPR_NOACCESS,
1274                  &spr_read_ureg, SPR_NOACCESS,
1275                  0x00000000);
1276     spr_register(env, SPR_USPRG5, "USPRG5",
1277                  &spr_read_ureg, SPR_NOACCESS,
1278                  &spr_read_ureg, SPR_NOACCESS,
1279                  0x00000000);
1280     spr_register(env, SPR_USPRG6, "USPRG6",
1281                  &spr_read_ureg, SPR_NOACCESS,
1282                  &spr_read_ureg, SPR_NOACCESS,
1283                  0x00000000);
1284     spr_register(env, SPR_USPRG7, "USPRG7",
1285                  &spr_read_ureg, SPR_NOACCESS,
1286                  &spr_read_ureg, SPR_NOACCESS,
1287                  0x00000000);
1288 }
1289
1290 /* PowerPC BookE SPR */
1291 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1292 {
1293     const char *ivor_names[64] = {
1294         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1295         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1296         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1297         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1298         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1299         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1300         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1301         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1302         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1303         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1304         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1305         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1306         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1307         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1308         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1309         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1310     };
1311 #define SPR_BOOKE_IVORxx (-1)
1312     int ivor_sprn[64] = {
1313         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1314         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1315         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1316         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1317         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1318         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1319         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1320         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1321         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1322         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1323         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1324         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1325         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1326         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1327         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1328         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1329     };
1330     int i;
1331
1332     /* Interrupt processing */
1333     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1334                  SPR_NOACCESS, SPR_NOACCESS,
1335                  &spr_read_generic, &spr_write_generic,
1336                  0x00000000);
1337     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1338                  SPR_NOACCESS, SPR_NOACCESS,
1339                  &spr_read_generic, &spr_write_generic,
1340                  0x00000000);
1341     /* Debug */
1342     /* XXX : not implemented */
1343     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1344                  SPR_NOACCESS, SPR_NOACCESS,
1345                  &spr_read_generic, &spr_write_generic,
1346                  0x00000000);
1347     /* XXX : not implemented */
1348     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1349                  SPR_NOACCESS, SPR_NOACCESS,
1350                  &spr_read_generic, &spr_write_generic,
1351                  0x00000000);
1352     /* XXX : not implemented */
1353     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1354                  SPR_NOACCESS, SPR_NOACCESS,
1355                  &spr_read_generic, &spr_write_generic,
1356                  0x00000000);
1357     /* XXX : not implemented */
1358     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1359                  SPR_NOACCESS, SPR_NOACCESS,
1360                  &spr_read_generic, &spr_write_generic,
1361                  0x00000000);
1362     /* XXX : not implemented */
1363     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1364                  SPR_NOACCESS, SPR_NOACCESS,
1365                  &spr_read_generic, &spr_write_generic,
1366                  0x00000000);
1367     /* XXX : not implemented */
1368     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1369                  SPR_NOACCESS, SPR_NOACCESS,
1370                  &spr_read_generic, &spr_write_generic,
1371                  0x00000000);
1372     /* XXX : not implemented */
1373     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1374                  SPR_NOACCESS, SPR_NOACCESS,
1375                  &spr_read_generic, &spr_write_generic,
1376                  0x00000000);
1377     /* XXX : not implemented */
1378     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1379                  SPR_NOACCESS, SPR_NOACCESS,
1380                  &spr_read_generic, &spr_write_clear,
1381                  0x00000000);
1382     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1383                  SPR_NOACCESS, SPR_NOACCESS,
1384                  &spr_read_generic, &spr_write_generic,
1385                  0x00000000);
1386     spr_register(env, SPR_BOOKE_ESR, "ESR",
1387                  SPR_NOACCESS, SPR_NOACCESS,
1388                  &spr_read_generic, &spr_write_generic,
1389                  0x00000000);
1390     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1391                  SPR_NOACCESS, SPR_NOACCESS,
1392                  &spr_read_generic, &spr_write_excp_prefix,
1393                  0x00000000);
1394     /* Exception vectors */
1395     for (i = 0; i < 64; i++) {
1396         if (ivor_mask & (1ULL << i)) {
1397             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1398                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1399                 exit(1);
1400             }
1401             spr_register(env, ivor_sprn[i], ivor_names[i],
1402                          SPR_NOACCESS, SPR_NOACCESS,
1403                          &spr_read_generic, &spr_write_excp_vector,
1404                          0x00000000);
1405         }
1406     }
1407     spr_register(env, SPR_BOOKE_PID, "PID",
1408                  SPR_NOACCESS, SPR_NOACCESS,
1409                  &spr_read_generic, &spr_write_generic,
1410                  0x00000000);
1411     spr_register(env, SPR_BOOKE_TCR, "TCR",
1412                  SPR_NOACCESS, SPR_NOACCESS,
1413                  &spr_read_generic, &spr_write_booke_tcr,
1414                  0x00000000);
1415     spr_register(env, SPR_BOOKE_TSR, "TSR",
1416                  SPR_NOACCESS, SPR_NOACCESS,
1417                  &spr_read_generic, &spr_write_booke_tsr,
1418                  0x00000000);
1419     /* Timer */
1420     spr_register(env, SPR_DECR, "DECR",
1421                  SPR_NOACCESS, SPR_NOACCESS,
1422                  &spr_read_decr, &spr_write_decr,
1423                  0x00000000);
1424     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1425                  SPR_NOACCESS, SPR_NOACCESS,
1426                  SPR_NOACCESS, &spr_write_generic,
1427                  0x00000000);
1428     /* SPRGs */
1429     spr_register(env, SPR_USPRG0, "USPRG0",
1430                  &spr_read_generic, &spr_write_generic,
1431                  &spr_read_generic, &spr_write_generic,
1432                  0x00000000);
1433     spr_register(env, SPR_SPRG4, "SPRG4",
1434                  SPR_NOACCESS, SPR_NOACCESS,
1435                  &spr_read_generic, &spr_write_generic,
1436                  0x00000000);
1437     spr_register(env, SPR_SPRG5, "SPRG5",
1438                  SPR_NOACCESS, SPR_NOACCESS,
1439                  &spr_read_generic, &spr_write_generic,
1440                  0x00000000);
1441     spr_register(env, SPR_SPRG6, "SPRG6",
1442                  SPR_NOACCESS, SPR_NOACCESS,
1443                  &spr_read_generic, &spr_write_generic,
1444                  0x00000000);
1445     spr_register(env, SPR_SPRG7, "SPRG7",
1446                  SPR_NOACCESS, SPR_NOACCESS,
1447                  &spr_read_generic, &spr_write_generic,
1448                  0x00000000);
1449 }
1450
1451 /* FSL storage control registers */
1452 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1453 {
1454 #if !defined(CONFIG_USER_ONLY)
1455     const char *mas_names[8] = {
1456         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1457     };
1458     int mas_sprn[8] = {
1459         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1460         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1461     };
1462     int i;
1463
1464     /* TLB assist registers */
1465     /* XXX : not implemented */
1466     for (i = 0; i < 8; i++) {
1467         if (mas_mask & (1 << i)) {
1468             spr_register(env, mas_sprn[i], mas_names[i],
1469                          SPR_NOACCESS, SPR_NOACCESS,
1470                          &spr_read_generic, &spr_write_generic,
1471                          0x00000000);
1472         }
1473     }
1474     if (env->nb_pids > 1) {
1475         /* XXX : not implemented */
1476         spr_register(env, SPR_BOOKE_PID1, "PID1",
1477                      SPR_NOACCESS, SPR_NOACCESS,
1478                      &spr_read_generic, &spr_write_generic,
1479                      0x00000000);
1480     }
1481     if (env->nb_pids > 2) {
1482         /* XXX : not implemented */
1483         spr_register(env, SPR_BOOKE_PID2, "PID2",
1484                      SPR_NOACCESS, SPR_NOACCESS,
1485                      &spr_read_generic, &spr_write_generic,
1486                      0x00000000);
1487     }
1488     /* XXX : not implemented */
1489     spr_register(env, SPR_MMUCFG, "MMUCFG",
1490                  SPR_NOACCESS, SPR_NOACCESS,
1491                  &spr_read_generic, SPR_NOACCESS,
1492                  0x00000000); /* TOFIX */
1493     /* XXX : not implemented */
1494     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1495                  SPR_NOACCESS, SPR_NOACCESS,
1496                  &spr_read_generic, &spr_write_generic,
1497                  0x00000000); /* TOFIX */
1498     switch (env->nb_ways) {
1499     case 4:
1500         /* XXX : not implemented */
1501         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1502                      SPR_NOACCESS, SPR_NOACCESS,
1503                      &spr_read_generic, SPR_NOACCESS,
1504                      0x00000000); /* TOFIX */
1505         /* Fallthru */
1506     case 3:
1507         /* XXX : not implemented */
1508         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1509                      SPR_NOACCESS, SPR_NOACCESS,
1510                      &spr_read_generic, SPR_NOACCESS,
1511                      0x00000000); /* TOFIX */
1512         /* Fallthru */
1513     case 2:
1514         /* XXX : not implemented */
1515         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1516                      SPR_NOACCESS, SPR_NOACCESS,
1517                      &spr_read_generic, SPR_NOACCESS,
1518                      0x00000000); /* TOFIX */
1519         /* Fallthru */
1520     case 1:
1521         /* XXX : not implemented */
1522         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1523                      SPR_NOACCESS, SPR_NOACCESS,
1524                      &spr_read_generic, SPR_NOACCESS,
1525                      0x00000000); /* TOFIX */
1526         /* Fallthru */
1527     case 0:
1528     default:
1529         break;
1530     }
1531 #endif
1532 }
1533
1534 /* SPR specific to PowerPC 440 implementation */
1535 static void gen_spr_440 (CPUPPCState *env)
1536 {
1537     /* Cache control */
1538     /* XXX : not implemented */
1539     spr_register(env, SPR_440_DNV0, "DNV0",
1540                  SPR_NOACCESS, SPR_NOACCESS,
1541                  &spr_read_generic, &spr_write_generic,
1542                  0x00000000);
1543     /* XXX : not implemented */
1544     spr_register(env, SPR_440_DNV1, "DNV1",
1545                  SPR_NOACCESS, SPR_NOACCESS,
1546                  &spr_read_generic, &spr_write_generic,
1547                  0x00000000);
1548     /* XXX : not implemented */
1549     spr_register(env, SPR_440_DNV2, "DNV2",
1550                  SPR_NOACCESS, SPR_NOACCESS,
1551                  &spr_read_generic, &spr_write_generic,
1552                  0x00000000);
1553     /* XXX : not implemented */
1554     spr_register(env, SPR_440_DNV3, "DNV3",
1555                  SPR_NOACCESS, SPR_NOACCESS,
1556                  &spr_read_generic, &spr_write_generic,
1557                  0x00000000);
1558     /* XXX : not implemented */
1559     spr_register(env, SPR_440_DTV0, "DTV0",
1560                  SPR_NOACCESS, SPR_NOACCESS,
1561                  &spr_read_generic, &spr_write_generic,
1562                  0x00000000);
1563     /* XXX : not implemented */
1564     spr_register(env, SPR_440_DTV1, "DTV1",
1565                  SPR_NOACCESS, SPR_NOACCESS,
1566                  &spr_read_generic, &spr_write_generic,
1567                  0x00000000);
1568     /* XXX : not implemented */
1569     spr_register(env, SPR_440_DTV2, "DTV2",
1570                  SPR_NOACCESS, SPR_NOACCESS,
1571                  &spr_read_generic, &spr_write_generic,
1572                  0x00000000);
1573     /* XXX : not implemented */
1574     spr_register(env, SPR_440_DTV3, "DTV3",
1575                  SPR_NOACCESS, SPR_NOACCESS,
1576                  &spr_read_generic, &spr_write_generic,
1577                  0x00000000);
1578     /* XXX : not implemented */
1579     spr_register(env, SPR_440_DVLIM, "DVLIM",
1580                  SPR_NOACCESS, SPR_NOACCESS,
1581                  &spr_read_generic, &spr_write_generic,
1582                  0x00000000);
1583     /* XXX : not implemented */
1584     spr_register(env, SPR_440_INV0, "INV0",
1585                  SPR_NOACCESS, SPR_NOACCESS,
1586                  &spr_read_generic, &spr_write_generic,
1587                  0x00000000);
1588     /* XXX : not implemented */
1589     spr_register(env, SPR_440_INV1, "INV1",
1590                  SPR_NOACCESS, SPR_NOACCESS,
1591                  &spr_read_generic, &spr_write_generic,
1592                  0x00000000);
1593     /* XXX : not implemented */
1594     spr_register(env, SPR_440_INV2, "INV2",
1595                  SPR_NOACCESS, SPR_NOACCESS,
1596                  &spr_read_generic, &spr_write_generic,
1597                  0x00000000);
1598     /* XXX : not implemented */
1599     spr_register(env, SPR_440_INV3, "INV3",
1600                  SPR_NOACCESS, SPR_NOACCESS,
1601                  &spr_read_generic, &spr_write_generic,
1602                  0x00000000);
1603     /* XXX : not implemented */
1604     spr_register(env, SPR_440_ITV0, "ITV0",
1605                  SPR_NOACCESS, SPR_NOACCESS,
1606                  &spr_read_generic, &spr_write_generic,
1607                  0x00000000);
1608     /* XXX : not implemented */
1609     spr_register(env, SPR_440_ITV1, "ITV1",
1610                  SPR_NOACCESS, SPR_NOACCESS,
1611                  &spr_read_generic, &spr_write_generic,
1612                  0x00000000);
1613     /* XXX : not implemented */
1614     spr_register(env, SPR_440_ITV2, "ITV2",
1615                  SPR_NOACCESS, SPR_NOACCESS,
1616                  &spr_read_generic, &spr_write_generic,
1617                  0x00000000);
1618     /* XXX : not implemented */
1619     spr_register(env, SPR_440_ITV3, "ITV3",
1620                  SPR_NOACCESS, SPR_NOACCESS,
1621                  &spr_read_generic, &spr_write_generic,
1622                  0x00000000);
1623     /* XXX : not implemented */
1624     spr_register(env, SPR_440_IVLIM, "IVLIM",
1625                  SPR_NOACCESS, SPR_NOACCESS,
1626                  &spr_read_generic, &spr_write_generic,
1627                  0x00000000);
1628     /* Cache debug */
1629     /* XXX : not implemented */
1630     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1631                  SPR_NOACCESS, SPR_NOACCESS,
1632                  &spr_read_generic, SPR_NOACCESS,
1633                  0x00000000);
1634     /* XXX : not implemented */
1635     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1636                  SPR_NOACCESS, SPR_NOACCESS,
1637                  &spr_read_generic, SPR_NOACCESS,
1638                  0x00000000);
1639     /* XXX : not implemented */
1640     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1641                  SPR_NOACCESS, SPR_NOACCESS,
1642                  &spr_read_generic, SPR_NOACCESS,
1643                  0x00000000);
1644     /* XXX : not implemented */
1645     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1646                  SPR_NOACCESS, SPR_NOACCESS,
1647                  &spr_read_generic, SPR_NOACCESS,
1648                  0x00000000);
1649     /* XXX : not implemented */
1650     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1651                  SPR_NOACCESS, SPR_NOACCESS,
1652                  &spr_read_generic, SPR_NOACCESS,
1653                  0x00000000);
1654     /* XXX : not implemented */
1655     spr_register(env, SPR_440_DBDR, "DBDR",
1656                  SPR_NOACCESS, SPR_NOACCESS,
1657                  &spr_read_generic, &spr_write_generic,
1658                  0x00000000);
1659     /* Processor control */
1660     spr_register(env, SPR_4xx_CCR0, "CCR0",
1661                  SPR_NOACCESS, SPR_NOACCESS,
1662                  &spr_read_generic, &spr_write_generic,
1663                  0x00000000);
1664     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1665                  SPR_NOACCESS, SPR_NOACCESS,
1666                  &spr_read_generic, SPR_NOACCESS,
1667                  0x00000000);
1668     /* Storage control */
1669     spr_register(env, SPR_440_MMUCR, "MMUCR",
1670                  SPR_NOACCESS, SPR_NOACCESS,
1671                  &spr_read_generic, &spr_write_generic,
1672                  0x00000000);
1673 }
1674
1675 /* SPR shared between PowerPC 40x implementations */
1676 static void gen_spr_40x (CPUPPCState *env)
1677 {
1678     /* Cache */
1679     /* not emulated, as Qemu do not emulate caches */
1680     spr_register(env, SPR_40x_DCCR, "DCCR",
1681                  SPR_NOACCESS, SPR_NOACCESS,
1682                  &spr_read_generic, &spr_write_generic,
1683                  0x00000000);
1684     /* not emulated, as Qemu do not emulate caches */
1685     spr_register(env, SPR_40x_ICCR, "ICCR",
1686                  SPR_NOACCESS, SPR_NOACCESS,
1687                  &spr_read_generic, &spr_write_generic,
1688                  0x00000000);
1689     /* not emulated, as Qemu do not emulate caches */
1690     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1691                  SPR_NOACCESS, SPR_NOACCESS,
1692                  &spr_read_generic, SPR_NOACCESS,
1693                  0x00000000);
1694     /* Exception */
1695     spr_register(env, SPR_40x_DEAR, "DEAR",
1696                  SPR_NOACCESS, SPR_NOACCESS,
1697                  &spr_read_generic, &spr_write_generic,
1698                  0x00000000);
1699     spr_register(env, SPR_40x_ESR, "ESR",
1700                  SPR_NOACCESS, SPR_NOACCESS,
1701                  &spr_read_generic, &spr_write_generic,
1702                  0x00000000);
1703     spr_register(env, SPR_40x_EVPR, "EVPR",
1704                  SPR_NOACCESS, SPR_NOACCESS,
1705                  &spr_read_generic, &spr_write_excp_prefix,
1706                  0x00000000);
1707     spr_register(env, SPR_40x_SRR2, "SRR2",
1708                  &spr_read_generic, &spr_write_generic,
1709                  &spr_read_generic, &spr_write_generic,
1710                  0x00000000);
1711     spr_register(env, SPR_40x_SRR3, "SRR3",
1712                  &spr_read_generic, &spr_write_generic,
1713                  &spr_read_generic, &spr_write_generic,
1714                  0x00000000);
1715     /* Timers */
1716     spr_register(env, SPR_40x_PIT, "PIT",
1717                  SPR_NOACCESS, SPR_NOACCESS,
1718                  &spr_read_40x_pit, &spr_write_40x_pit,
1719                  0x00000000);
1720     spr_register(env, SPR_40x_TCR, "TCR",
1721                  SPR_NOACCESS, SPR_NOACCESS,
1722                  &spr_read_generic, &spr_write_booke_tcr,
1723                  0x00000000);
1724     spr_register(env, SPR_40x_TSR, "TSR",
1725                  SPR_NOACCESS, SPR_NOACCESS,
1726                  &spr_read_generic, &spr_write_booke_tsr,
1727                  0x00000000);
1728 }
1729
1730 /* SPR specific to PowerPC 405 implementation */
1731 static void gen_spr_405 (CPUPPCState *env)
1732 {
1733     /* MMU */
1734     spr_register(env, SPR_40x_PID, "PID",
1735                  SPR_NOACCESS, SPR_NOACCESS,
1736                  &spr_read_generic, &spr_write_generic,
1737                  0x00000000);
1738     spr_register(env, SPR_4xx_CCR0, "CCR0",
1739                  SPR_NOACCESS, SPR_NOACCESS,
1740                  &spr_read_generic, &spr_write_generic,
1741                  0x00700000);
1742     /* Debug interface */
1743     /* XXX : not implemented */
1744     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1745                  SPR_NOACCESS, SPR_NOACCESS,
1746                  &spr_read_generic, &spr_write_40x_dbcr0,
1747                  0x00000000);
1748     /* XXX : not implemented */
1749     spr_register(env, SPR_405_DBCR1, "DBCR1",
1750                  SPR_NOACCESS, SPR_NOACCESS,
1751                  &spr_read_generic, &spr_write_generic,
1752                  0x00000000);
1753     /* XXX : not implemented */
1754     spr_register(env, SPR_40x_DBSR, "DBSR",
1755                  SPR_NOACCESS, SPR_NOACCESS,
1756                  &spr_read_generic, &spr_write_clear,
1757                  /* Last reset was system reset */
1758                  0x00000300);
1759     /* XXX : not implemented */
1760     spr_register(env, SPR_40x_DAC1, "DAC1",
1761                  SPR_NOACCESS, SPR_NOACCESS,
1762                  &spr_read_generic, &spr_write_generic,
1763                  0x00000000);
1764     spr_register(env, SPR_40x_DAC2, "DAC2",
1765                  SPR_NOACCESS, SPR_NOACCESS,
1766                  &spr_read_generic, &spr_write_generic,
1767                  0x00000000);
1768     /* XXX : not implemented */
1769     spr_register(env, SPR_405_DVC1, "DVC1",
1770                  SPR_NOACCESS, SPR_NOACCESS,
1771                  &spr_read_generic, &spr_write_generic,
1772                  0x00000000);
1773     /* XXX : not implemented */
1774     spr_register(env, SPR_405_DVC2, "DVC2",
1775                  SPR_NOACCESS, SPR_NOACCESS,
1776                  &spr_read_generic, &spr_write_generic,
1777                  0x00000000);
1778     /* XXX : not implemented */
1779     spr_register(env, SPR_40x_IAC1, "IAC1",
1780                  SPR_NOACCESS, SPR_NOACCESS,
1781                  &spr_read_generic, &spr_write_generic,
1782                  0x00000000);
1783     spr_register(env, SPR_40x_IAC2, "IAC2",
1784                  SPR_NOACCESS, SPR_NOACCESS,
1785                  &spr_read_generic, &spr_write_generic,
1786                  0x00000000);
1787     /* XXX : not implemented */
1788     spr_register(env, SPR_405_IAC3, "IAC3",
1789                  SPR_NOACCESS, SPR_NOACCESS,
1790                  &spr_read_generic, &spr_write_generic,
1791                  0x00000000);
1792     /* XXX : not implemented */
1793     spr_register(env, SPR_405_IAC4, "IAC4",
1794                  SPR_NOACCESS, SPR_NOACCESS,
1795                  &spr_read_generic, &spr_write_generic,
1796                  0x00000000);
1797     /* Storage control */
1798     /* XXX: TODO: not implemented */
1799     spr_register(env, SPR_405_SLER, "SLER",
1800                  SPR_NOACCESS, SPR_NOACCESS,
1801                  &spr_read_generic, &spr_write_40x_sler,
1802                  0x00000000);
1803     spr_register(env, SPR_40x_ZPR, "ZPR",
1804                  SPR_NOACCESS, SPR_NOACCESS,
1805                  &spr_read_generic, &spr_write_generic,
1806                  0x00000000);
1807     /* XXX : not implemented */
1808     spr_register(env, SPR_405_SU0R, "SU0R",
1809                  SPR_NOACCESS, SPR_NOACCESS,
1810                  &spr_read_generic, &spr_write_generic,
1811                  0x00000000);
1812     /* SPRG */
1813     spr_register(env, SPR_USPRG0, "USPRG0",
1814                  &spr_read_ureg, SPR_NOACCESS,
1815                  &spr_read_ureg, SPR_NOACCESS,
1816                  0x00000000);
1817     spr_register(env, SPR_SPRG4, "SPRG4",
1818                  SPR_NOACCESS, SPR_NOACCESS,
1819                  &spr_read_generic, &spr_write_generic,
1820                  0x00000000);
1821     spr_register(env, SPR_SPRG5, "SPRG5",
1822                  SPR_NOACCESS, SPR_NOACCESS,
1823                  spr_read_generic, &spr_write_generic,
1824                  0x00000000);
1825     spr_register(env, SPR_SPRG6, "SPRG6",
1826                  SPR_NOACCESS, SPR_NOACCESS,
1827                  spr_read_generic, &spr_write_generic,
1828                  0x00000000);
1829     spr_register(env, SPR_SPRG7, "SPRG7",
1830                  SPR_NOACCESS, SPR_NOACCESS,
1831                  spr_read_generic, &spr_write_generic,
1832                  0x00000000);
1833     gen_spr_usprgh(env);
1834 }
1835
1836 /* SPR shared between PowerPC 401 & 403 implementations */
1837 static void gen_spr_401_403 (CPUPPCState *env)
1838 {
1839     /* Time base */
1840     spr_register(env, SPR_403_VTBL,  "TBL",
1841                  &spr_read_tbl, SPR_NOACCESS,
1842                  &spr_read_tbl, SPR_NOACCESS,
1843                  0x00000000);
1844     spr_register(env, SPR_403_TBL,   "TBL",
1845                  SPR_NOACCESS, SPR_NOACCESS,
1846                  SPR_NOACCESS, &spr_write_tbl,
1847                  0x00000000);
1848     spr_register(env, SPR_403_VTBU,  "TBU",
1849                  &spr_read_tbu, SPR_NOACCESS,
1850                  &spr_read_tbu, SPR_NOACCESS,
1851                  0x00000000);
1852     spr_register(env, SPR_403_TBU,   "TBU",
1853                  SPR_NOACCESS, SPR_NOACCESS,
1854                  SPR_NOACCESS, &spr_write_tbu,
1855                  0x00000000);
1856     /* Debug */
1857     /* not emulated, as Qemu do not emulate caches */
1858     spr_register(env, SPR_403_CDBCR, "CDBCR",
1859                  SPR_NOACCESS, SPR_NOACCESS,
1860                  &spr_read_generic, &spr_write_generic,
1861                  0x00000000);
1862 }
1863
1864 /* SPR specific to PowerPC 401 implementation */
1865 static void gen_spr_401 (CPUPPCState *env)
1866 {
1867     /* Debug interface */
1868     /* XXX : not implemented */
1869     spr_register(env, SPR_40x_DBCR0, "DBCR",
1870                  SPR_NOACCESS, SPR_NOACCESS,
1871                  &spr_read_generic, &spr_write_40x_dbcr0,
1872                  0x00000000);
1873     /* XXX : not implemented */
1874     spr_register(env, SPR_40x_DBSR, "DBSR",
1875                  SPR_NOACCESS, SPR_NOACCESS,
1876                  &spr_read_generic, &spr_write_clear,
1877                  /* Last reset was system reset */
1878                  0x00000300);
1879     /* XXX : not implemented */
1880     spr_register(env, SPR_40x_DAC1, "DAC",
1881                  SPR_NOACCESS, SPR_NOACCESS,
1882                  &spr_read_generic, &spr_write_generic,
1883                  0x00000000);
1884     /* XXX : not implemented */
1885     spr_register(env, SPR_40x_IAC1, "IAC",
1886                  SPR_NOACCESS, SPR_NOACCESS,
1887                  &spr_read_generic, &spr_write_generic,
1888                  0x00000000);
1889     /* Storage control */
1890     /* XXX: TODO: not implemented */
1891     spr_register(env, SPR_405_SLER, "SLER",
1892                  SPR_NOACCESS, SPR_NOACCESS,
1893                  &spr_read_generic, &spr_write_40x_sler,
1894                  0x00000000);
1895     /* not emulated, as Qemu never does speculative access */
1896     spr_register(env, SPR_40x_SGR, "SGR",
1897                  SPR_NOACCESS, SPR_NOACCESS,
1898                  &spr_read_generic, &spr_write_generic,
1899                  0xFFFFFFFF);
1900     /* not emulated, as Qemu do not emulate caches */
1901     spr_register(env, SPR_40x_DCWR, "DCWR",
1902                  SPR_NOACCESS, SPR_NOACCESS,
1903                  &spr_read_generic, &spr_write_generic,
1904                  0x00000000);
1905 }
1906
1907 static void gen_spr_401x2 (CPUPPCState *env)
1908 {
1909     gen_spr_401(env);
1910     spr_register(env, SPR_40x_PID, "PID",
1911                  SPR_NOACCESS, SPR_NOACCESS,
1912                  &spr_read_generic, &spr_write_generic,
1913                  0x00000000);
1914     spr_register(env, SPR_40x_ZPR, "ZPR",
1915                  SPR_NOACCESS, SPR_NOACCESS,
1916                  &spr_read_generic, &spr_write_generic,
1917                  0x00000000);
1918 }
1919
1920 /* SPR specific to PowerPC 403 implementation */
1921 static void gen_spr_403 (CPUPPCState *env)
1922 {
1923     /* Debug interface */
1924     /* XXX : not implemented */
1925     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1926                  SPR_NOACCESS, SPR_NOACCESS,
1927                  &spr_read_generic, &spr_write_40x_dbcr0,
1928                  0x00000000);
1929     /* XXX : not implemented */
1930     spr_register(env, SPR_40x_DBSR, "DBSR",
1931                  SPR_NOACCESS, SPR_NOACCESS,
1932                  &spr_read_generic, &spr_write_clear,
1933                  /* Last reset was system reset */
1934                  0x00000300);
1935     /* XXX : not implemented */
1936     spr_register(env, SPR_40x_DAC1, "DAC1",
1937                  SPR_NOACCESS, SPR_NOACCESS,
1938                  &spr_read_generic, &spr_write_generic,
1939                  0x00000000);
1940     /* XXX : not implemented */
1941     spr_register(env, SPR_40x_DAC2, "DAC2",
1942                  SPR_NOACCESS, SPR_NOACCESS,
1943                  &spr_read_generic, &spr_write_generic,
1944                  0x00000000);
1945     /* XXX : not implemented */
1946     spr_register(env, SPR_40x_IAC1, "IAC1",
1947                  SPR_NOACCESS, SPR_NOACCESS,
1948                  &spr_read_generic, &spr_write_generic,
1949                  0x00000000);
1950     /* XXX : not implemented */
1951     spr_register(env, SPR_40x_IAC2, "IAC2",
1952                  SPR_NOACCESS, SPR_NOACCESS,
1953                  &spr_read_generic, &spr_write_generic,
1954                  0x00000000);
1955 }
1956
1957 static void gen_spr_403_real (CPUPPCState *env)
1958 {
1959     spr_register(env, SPR_403_PBL1,  "PBL1",
1960                  SPR_NOACCESS, SPR_NOACCESS,
1961                  &spr_read_403_pbr, &spr_write_403_pbr,
1962                  0x00000000);
1963     spr_register(env, SPR_403_PBU1,  "PBU1",
1964                  SPR_NOACCESS, SPR_NOACCESS,
1965                  &spr_read_403_pbr, &spr_write_403_pbr,
1966                  0x00000000);
1967     spr_register(env, SPR_403_PBL2,  "PBL2",
1968                  SPR_NOACCESS, SPR_NOACCESS,
1969                  &spr_read_403_pbr, &spr_write_403_pbr,
1970                  0x00000000);
1971     spr_register(env, SPR_403_PBU2,  "PBU2",
1972                  SPR_NOACCESS, SPR_NOACCESS,
1973                  &spr_read_403_pbr, &spr_write_403_pbr,
1974                  0x00000000);
1975 }
1976
1977 static void gen_spr_403_mmu (CPUPPCState *env)
1978 {
1979     /* MMU */
1980     spr_register(env, SPR_40x_PID, "PID",
1981                  SPR_NOACCESS, SPR_NOACCESS,
1982                  &spr_read_generic, &spr_write_generic,
1983                  0x00000000);
1984     spr_register(env, SPR_40x_ZPR, "ZPR",
1985                  SPR_NOACCESS, SPR_NOACCESS,
1986                  &spr_read_generic, &spr_write_generic,
1987                  0x00000000);
1988 }
1989
1990 /* SPR specific to PowerPC compression coprocessor extension */
1991 static void gen_spr_compress (CPUPPCState *env)
1992 {
1993     /* XXX : not implemented */
1994     spr_register(env, SPR_401_SKR, "SKR",
1995                  SPR_NOACCESS, SPR_NOACCESS,
1996                  &spr_read_generic, &spr_write_generic,
1997                  0x00000000);
1998 }
1999
2000 #if defined (TARGET_PPC64)
2001 /* SPR specific to PowerPC 620 */
2002 static void gen_spr_620 (CPUPPCState *env)
2003 {
2004     /* Processor identification */
2005     spr_register(env, SPR_PIR, "PIR",
2006                  SPR_NOACCESS, SPR_NOACCESS,
2007                  &spr_read_generic, &spr_write_pir,
2008                  0x00000000);
2009     spr_register(env, SPR_ASR, "ASR",
2010                  SPR_NOACCESS, SPR_NOACCESS,
2011                  &spr_read_asr, &spr_write_asr,
2012                  0x00000000);
2013     /* Breakpoints */
2014     /* XXX : not implemented */
2015     spr_register(env, SPR_IABR, "IABR",
2016                  SPR_NOACCESS, SPR_NOACCESS,
2017                  &spr_read_generic, &spr_write_generic,
2018                  0x00000000);
2019     /* XXX : not implemented */
2020     spr_register(env, SPR_DABR, "DABR",
2021                  SPR_NOACCESS, SPR_NOACCESS,
2022                  &spr_read_generic, &spr_write_generic,
2023                  0x00000000);
2024     /* XXX : not implemented */
2025     spr_register(env, SPR_SIAR, "SIAR",
2026                  SPR_NOACCESS, SPR_NOACCESS,
2027                  &spr_read_generic, SPR_NOACCESS,
2028                  0x00000000);
2029     /* XXX : not implemented */
2030     spr_register(env, SPR_SDA, "SDA",
2031                  SPR_NOACCESS, SPR_NOACCESS,
2032                  &spr_read_generic, SPR_NOACCESS,
2033                  0x00000000);
2034     /* XXX : not implemented */
2035     spr_register(env, SPR_620_PMC1R, "PMC1",
2036                  SPR_NOACCESS, SPR_NOACCESS,
2037                  &spr_read_generic, SPR_NOACCESS,
2038                  0x00000000);
2039     spr_register(env, SPR_620_PMC1W, "PMC1",
2040                  SPR_NOACCESS, SPR_NOACCESS,
2041                   SPR_NOACCESS, &spr_write_generic,
2042                  0x00000000);
2043     /* XXX : not implemented */
2044     spr_register(env, SPR_620_PMC2R, "PMC2",
2045                  SPR_NOACCESS, SPR_NOACCESS,
2046                  &spr_read_generic, SPR_NOACCESS,
2047                  0x00000000);
2048     spr_register(env, SPR_620_PMC2W, "PMC2",
2049                  SPR_NOACCESS, SPR_NOACCESS,
2050                   SPR_NOACCESS, &spr_write_generic,
2051                  0x00000000);
2052     /* XXX : not implemented */
2053     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2054                  SPR_NOACCESS, SPR_NOACCESS,
2055                  &spr_read_generic, SPR_NOACCESS,
2056                  0x00000000);
2057     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2058                  SPR_NOACCESS, SPR_NOACCESS,
2059                   SPR_NOACCESS, &spr_write_generic,
2060                  0x00000000);
2061     /* External access control */
2062     /* XXX : not implemented */
2063     spr_register(env, SPR_EAR, "EAR",
2064                  SPR_NOACCESS, SPR_NOACCESS,
2065                  &spr_read_generic, &spr_write_generic,
2066                  0x00000000);
2067 #if 0 // XXX: check this
2068     /* XXX : not implemented */
2069     spr_register(env, SPR_620_PMR0, "PMR0",
2070                  SPR_NOACCESS, SPR_NOACCESS,
2071                  &spr_read_generic, &spr_write_generic,
2072                  0x00000000);
2073     /* XXX : not implemented */
2074     spr_register(env, SPR_620_PMR1, "PMR1",
2075                  SPR_NOACCESS, SPR_NOACCESS,
2076                  &spr_read_generic, &spr_write_generic,
2077                  0x00000000);
2078     /* XXX : not implemented */
2079     spr_register(env, SPR_620_PMR2, "PMR2",
2080                  SPR_NOACCESS, SPR_NOACCESS,
2081                  &spr_read_generic, &spr_write_generic,
2082                  0x00000000);
2083     /* XXX : not implemented */
2084     spr_register(env, SPR_620_PMR3, "PMR3",
2085                  SPR_NOACCESS, SPR_NOACCESS,
2086                  &spr_read_generic, &spr_write_generic,
2087                  0x00000000);
2088     /* XXX : not implemented */
2089     spr_register(env, SPR_620_PMR4, "PMR4",
2090                  SPR_NOACCESS, SPR_NOACCESS,
2091                  &spr_read_generic, &spr_write_generic,
2092                  0x00000000);
2093     /* XXX : not implemented */
2094     spr_register(env, SPR_620_PMR5, "PMR5",
2095                  SPR_NOACCESS, SPR_NOACCESS,
2096                  &spr_read_generic, &spr_write_generic,
2097                  0x00000000);
2098     /* XXX : not implemented */
2099     spr_register(env, SPR_620_PMR6, "PMR6",
2100                  SPR_NOACCESS, SPR_NOACCESS,
2101                  &spr_read_generic, &spr_write_generic,
2102                  0x00000000);
2103     /* XXX : not implemented */
2104     spr_register(env, SPR_620_PMR7, "PMR7",
2105                  SPR_NOACCESS, SPR_NOACCESS,
2106                  &spr_read_generic, &spr_write_generic,
2107                  0x00000000);
2108     /* XXX : not implemented */
2109     spr_register(env, SPR_620_PMR8, "PMR8",
2110                  SPR_NOACCESS, SPR_NOACCESS,
2111                  &spr_read_generic, &spr_write_generic,
2112                  0x00000000);
2113     /* XXX : not implemented */
2114     spr_register(env, SPR_620_PMR9, "PMR9",
2115                  SPR_NOACCESS, SPR_NOACCESS,
2116                  &spr_read_generic, &spr_write_generic,
2117                  0x00000000);
2118     /* XXX : not implemented */
2119     spr_register(env, SPR_620_PMRA, "PMR10",
2120                  SPR_NOACCESS, SPR_NOACCESS,
2121                  &spr_read_generic, &spr_write_generic,
2122                  0x00000000);
2123     /* XXX : not implemented */
2124     spr_register(env, SPR_620_PMRB, "PMR11",
2125                  SPR_NOACCESS, SPR_NOACCESS,
2126                  &spr_read_generic, &spr_write_generic,
2127                  0x00000000);
2128     /* XXX : not implemented */
2129     spr_register(env, SPR_620_PMRC, "PMR12",
2130                  SPR_NOACCESS, SPR_NOACCESS,
2131                  &spr_read_generic, &spr_write_generic,
2132                  0x00000000);
2133     /* XXX : not implemented */
2134     spr_register(env, SPR_620_PMRD, "PMR13",
2135                  SPR_NOACCESS, SPR_NOACCESS,
2136                  &spr_read_generic, &spr_write_generic,
2137                  0x00000000);
2138     /* XXX : not implemented */
2139     spr_register(env, SPR_620_PMRE, "PMR14",
2140                  SPR_NOACCESS, SPR_NOACCESS,
2141                  &spr_read_generic, &spr_write_generic,
2142                  0x00000000);
2143     /* XXX : not implemented */
2144     spr_register(env, SPR_620_PMRF, "PMR15",
2145                  SPR_NOACCESS, SPR_NOACCESS,
2146                  &spr_read_generic, &spr_write_generic,
2147                  0x00000000);
2148 #endif
2149     /* XXX : not implemented */
2150     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2151                  SPR_NOACCESS, SPR_NOACCESS,
2152                  &spr_read_generic, &spr_write_generic,
2153                  0x00000000);
2154     /* XXX : not implemented */
2155     spr_register(env, SPR_620_L2CR, "L2CR",
2156                  SPR_NOACCESS, SPR_NOACCESS,
2157                  &spr_read_generic, &spr_write_generic,
2158                  0x00000000);
2159     /* XXX : not implemented */
2160     spr_register(env, SPR_620_L2SR, "L2SR",
2161                  SPR_NOACCESS, SPR_NOACCESS,
2162                  &spr_read_generic, &spr_write_generic,
2163                  0x00000000);
2164 }
2165 #endif /* defined (TARGET_PPC64) */
2166
2167 static void gen_spr_5xx_8xx (CPUPPCState *env)
2168 {
2169     /* Exception processing */
2170     spr_register(env, SPR_DSISR, "DSISR",
2171                  SPR_NOACCESS, SPR_NOACCESS,
2172                  &spr_read_generic, &spr_write_generic,
2173                  0x00000000);
2174     spr_register(env, SPR_DAR, "DAR",
2175                  SPR_NOACCESS, SPR_NOACCESS,
2176                  &spr_read_generic, &spr_write_generic,
2177                  0x00000000);
2178     /* Timer */
2179     spr_register(env, SPR_DECR, "DECR",
2180                  SPR_NOACCESS, SPR_NOACCESS,
2181                  &spr_read_decr, &spr_write_decr,
2182                  0x00000000);
2183     /* XXX : not implemented */
2184     spr_register(env, SPR_MPC_EIE, "EIE",
2185                  SPR_NOACCESS, SPR_NOACCESS,
2186                  &spr_read_generic, &spr_write_generic,
2187                  0x00000000);
2188     /* XXX : not implemented */
2189     spr_register(env, SPR_MPC_EID, "EID",
2190                  SPR_NOACCESS, SPR_NOACCESS,
2191                  &spr_read_generic, &spr_write_generic,
2192                  0x00000000);
2193     /* XXX : not implemented */
2194     spr_register(env, SPR_MPC_NRI, "NRI",
2195                  SPR_NOACCESS, SPR_NOACCESS,
2196                  &spr_read_generic, &spr_write_generic,
2197                  0x00000000);
2198     /* XXX : not implemented */
2199     spr_register(env, SPR_MPC_CMPA, "CMPA",
2200                  SPR_NOACCESS, SPR_NOACCESS,
2201                  &spr_read_generic, &spr_write_generic,
2202                  0x00000000);
2203     /* XXX : not implemented */
2204     spr_register(env, SPR_MPC_CMPB, "CMPB",
2205                  SPR_NOACCESS, SPR_NOACCESS,
2206                  &spr_read_generic, &spr_write_generic,
2207                  0x00000000);
2208     /* XXX : not implemented */
2209     spr_register(env, SPR_MPC_CMPC, "CMPC",
2210                  SPR_NOACCESS, SPR_NOACCESS,
2211                  &spr_read_generic, &spr_write_generic,
2212                  0x00000000);
2213     /* XXX : not implemented */
2214     spr_register(env, SPR_MPC_CMPD, "CMPD",
2215                  SPR_NOACCESS, SPR_NOACCESS,
2216                  &spr_read_generic, &spr_write_generic,
2217                  0x00000000);
2218     /* XXX : not implemented */
2219     spr_register(env, SPR_MPC_ECR, "ECR",
2220                  SPR_NOACCESS, SPR_NOACCESS,
2221                  &spr_read_generic, &spr_write_generic,
2222                  0x00000000);
2223     /* XXX : not implemented */
2224     spr_register(env, SPR_MPC_DER, "DER",
2225                  SPR_NOACCESS, SPR_NOACCESS,
2226                  &spr_read_generic, &spr_write_generic,
2227                  0x00000000);
2228     /* XXX : not implemented */
2229     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2230                  SPR_NOACCESS, SPR_NOACCESS,
2231                  &spr_read_generic, &spr_write_generic,
2232                  0x00000000);
2233     /* XXX : not implemented */
2234     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2235                  SPR_NOACCESS, SPR_NOACCESS,
2236                  &spr_read_generic, &spr_write_generic,
2237                  0x00000000);
2238     /* XXX : not implemented */
2239     spr_register(env, SPR_MPC_CMPE, "CMPE",
2240                  SPR_NOACCESS, SPR_NOACCESS,
2241                  &spr_read_generic, &spr_write_generic,
2242                  0x00000000);
2243     /* XXX : not implemented */
2244     spr_register(env, SPR_MPC_CMPF, "CMPF",
2245                  SPR_NOACCESS, SPR_NOACCESS,
2246                  &spr_read_generic, &spr_write_generic,
2247                  0x00000000);
2248     /* XXX : not implemented */
2249     spr_register(env, SPR_MPC_CMPG, "CMPG",
2250                  SPR_NOACCESS, SPR_NOACCESS,
2251                  &spr_read_generic, &spr_write_generic,
2252                  0x00000000);
2253     /* XXX : not implemented */
2254     spr_register(env, SPR_MPC_CMPH, "CMPH",
2255                  SPR_NOACCESS, SPR_NOACCESS,
2256                  &spr_read_generic, &spr_write_generic,
2257                  0x00000000);
2258     /* XXX : not implemented */
2259     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2260                  SPR_NOACCESS, SPR_NOACCESS,
2261                  &spr_read_generic, &spr_write_generic,
2262                  0x00000000);
2263     /* XXX : not implemented */
2264     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2265                  SPR_NOACCESS, SPR_NOACCESS,
2266                  &spr_read_generic, &spr_write_generic,
2267                  0x00000000);
2268     /* XXX : not implemented */
2269     spr_register(env, SPR_MPC_BAR, "BAR",
2270                  SPR_NOACCESS, SPR_NOACCESS,
2271                  &spr_read_generic, &spr_write_generic,
2272                  0x00000000);
2273     /* XXX : not implemented */
2274     spr_register(env, SPR_MPC_DPDR, "DPDR",
2275                  SPR_NOACCESS, SPR_NOACCESS,
2276                  &spr_read_generic, &spr_write_generic,
2277                  0x00000000);
2278     /* XXX : not implemented */
2279     spr_register(env, SPR_MPC_IMMR, "IMMR",
2280                  SPR_NOACCESS, SPR_NOACCESS,
2281                  &spr_read_generic, &spr_write_generic,
2282                  0x00000000);
2283 }
2284
2285 static void gen_spr_5xx (CPUPPCState *env)
2286 {
2287     /* XXX : not implemented */
2288     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2289                  SPR_NOACCESS, SPR_NOACCESS,
2290                  &spr_read_generic, &spr_write_generic,
2291                  0x00000000);
2292     /* XXX : not implemented */
2293     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2294                  SPR_NOACCESS, SPR_NOACCESS,
2295                  &spr_read_generic, &spr_write_generic,
2296                  0x00000000);
2297     /* XXX : not implemented */
2298     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2299                  SPR_NOACCESS, SPR_NOACCESS,
2300                  &spr_read_generic, &spr_write_generic,
2301                  0x00000000);
2302     /* XXX : not implemented */
2303     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2304                  SPR_NOACCESS, SPR_NOACCESS,
2305                  &spr_read_generic, &spr_write_generic,
2306                  0x00000000);
2307     /* XXX : not implemented */
2308     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2309                  SPR_NOACCESS, SPR_NOACCESS,
2310                  &spr_read_generic, &spr_write_generic,
2311                  0x00000000);
2312     /* XXX : not implemented */
2313     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2314                  SPR_NOACCESS, SPR_NOACCESS,
2315                  &spr_read_generic, &spr_write_generic,
2316                  0x00000000);
2317     /* XXX : not implemented */
2318     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2319                  SPR_NOACCESS, SPR_NOACCESS,
2320                  &spr_read_generic, &spr_write_generic,
2321                  0x00000000);
2322     /* XXX : not implemented */
2323     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2324                  SPR_NOACCESS, SPR_NOACCESS,
2325                  &spr_read_generic, &spr_write_generic,
2326                  0x00000000);
2327     /* XXX : not implemented */
2328     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2329                  SPR_NOACCESS, SPR_NOACCESS,
2330                  &spr_read_generic, &spr_write_generic,
2331                  0x00000000);
2332     /* XXX : not implemented */
2333     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2334                  SPR_NOACCESS, SPR_NOACCESS,
2335                  &spr_read_generic, &spr_write_generic,
2336                  0x00000000);
2337     /* XXX : not implemented */
2338     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2339                  SPR_NOACCESS, SPR_NOACCESS,
2340                  &spr_read_generic, &spr_write_generic,
2341                  0x00000000);
2342     /* XXX : not implemented */
2343     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2344                  SPR_NOACCESS, SPR_NOACCESS,
2345                  &spr_read_generic, &spr_write_generic,
2346                  0x00000000);
2347     /* XXX : not implemented */
2348     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2349                  SPR_NOACCESS, SPR_NOACCESS,
2350                  &spr_read_generic, &spr_write_generic,
2351                  0x00000000);
2352     /* XXX : not implemented */
2353     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2354                  SPR_NOACCESS, SPR_NOACCESS,
2355                  &spr_read_generic, &spr_write_generic,
2356                  0x00000000);
2357     /* XXX : not implemented */
2358     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2359                  SPR_NOACCESS, SPR_NOACCESS,
2360                  &spr_read_generic, &spr_write_generic,
2361                  0x00000000);
2362     /* XXX : not implemented */
2363     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2364                  SPR_NOACCESS, SPR_NOACCESS,
2365                  &spr_read_generic, &spr_write_generic,
2366                  0x00000000);
2367     /* XXX : not implemented */
2368     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2369                  SPR_NOACCESS, SPR_NOACCESS,
2370                  &spr_read_generic, &spr_write_generic,
2371                  0x00000000);
2372     /* XXX : not implemented */
2373     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2374                  SPR_NOACCESS, SPR_NOACCESS,
2375                  &spr_read_generic, &spr_write_generic,
2376                  0x00000000);
2377     /* XXX : not implemented */
2378     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2379                  SPR_NOACCESS, SPR_NOACCESS,
2380                  &spr_read_generic, &spr_write_generic,
2381                  0x00000000);
2382     /* XXX : not implemented */
2383     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2384                  SPR_NOACCESS, SPR_NOACCESS,
2385                  &spr_read_generic, &spr_write_generic,
2386                  0x00000000);
2387     /* XXX : not implemented */
2388     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2389                  SPR_NOACCESS, SPR_NOACCESS,
2390                  &spr_read_generic, &spr_write_generic,
2391                  0x00000000);
2392 }
2393
2394 static void gen_spr_8xx (CPUPPCState *env)
2395 {
2396     /* XXX : not implemented */
2397     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2398                  SPR_NOACCESS, SPR_NOACCESS,
2399                  &spr_read_generic, &spr_write_generic,
2400                  0x00000000);
2401     /* XXX : not implemented */
2402     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2403                  SPR_NOACCESS, SPR_NOACCESS,
2404                  &spr_read_generic, &spr_write_generic,
2405                  0x00000000);
2406     /* XXX : not implemented */
2407     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2408                  SPR_NOACCESS, SPR_NOACCESS,
2409                  &spr_read_generic, &spr_write_generic,
2410                  0x00000000);
2411     /* XXX : not implemented */
2412     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2413                  SPR_NOACCESS, SPR_NOACCESS,
2414                  &spr_read_generic, &spr_write_generic,
2415                  0x00000000);
2416     /* XXX : not implemented */
2417     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2418                  SPR_NOACCESS, SPR_NOACCESS,
2419                  &spr_read_generic, &spr_write_generic,
2420                  0x00000000);
2421     /* XXX : not implemented */
2422     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2423                  SPR_NOACCESS, SPR_NOACCESS,
2424                  &spr_read_generic, &spr_write_generic,
2425                  0x00000000);
2426     /* XXX : not implemented */
2427     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2428                  SPR_NOACCESS, SPR_NOACCESS,
2429                  &spr_read_generic, &spr_write_generic,
2430                  0x00000000);
2431     /* XXX : not implemented */
2432     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2433                  SPR_NOACCESS, SPR_NOACCESS,
2434                  &spr_read_generic, &spr_write_generic,
2435                  0x00000000);
2436     /* XXX : not implemented */
2437     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2438                  SPR_NOACCESS, SPR_NOACCESS,
2439                  &spr_read_generic, &spr_write_generic,
2440                  0x00000000);
2441     /* XXX : not implemented */
2442     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2443                  SPR_NOACCESS, SPR_NOACCESS,
2444                  &spr_read_generic, &spr_write_generic,
2445                  0x00000000);
2446     /* XXX : not implemented */
2447     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2448                  SPR_NOACCESS, SPR_NOACCESS,
2449                  &spr_read_generic, &spr_write_generic,
2450                  0x00000000);
2451     /* XXX : not implemented */
2452     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2453                  SPR_NOACCESS, SPR_NOACCESS,
2454                  &spr_read_generic, &spr_write_generic,
2455                  0x00000000);
2456     /* XXX : not implemented */
2457     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2458                  SPR_NOACCESS, SPR_NOACCESS,
2459                  &spr_read_generic, &spr_write_generic,
2460                  0x00000000);
2461     /* XXX : not implemented */
2462     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2463                  SPR_NOACCESS, SPR_NOACCESS,
2464                  &spr_read_generic, &spr_write_generic,
2465                  0x00000000);
2466     /* XXX : not implemented */
2467     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2468                  SPR_NOACCESS, SPR_NOACCESS,
2469                  &spr_read_generic, &spr_write_generic,
2470                  0x00000000);
2471     /* XXX : not implemented */
2472     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2473                  SPR_NOACCESS, SPR_NOACCESS,
2474                  &spr_read_generic, &spr_write_generic,
2475                  0x00000000);
2476     /* XXX : not implemented */
2477     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2478                  SPR_NOACCESS, SPR_NOACCESS,
2479                  &spr_read_generic, &spr_write_generic,
2480                  0x00000000);
2481     /* XXX : not implemented */
2482     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2483                  SPR_NOACCESS, SPR_NOACCESS,
2484                  &spr_read_generic, &spr_write_generic,
2485                  0x00000000);
2486     /* XXX : not implemented */
2487     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2488                  SPR_NOACCESS, SPR_NOACCESS,
2489                  &spr_read_generic, &spr_write_generic,
2490                  0x00000000);
2491     /* XXX : not implemented */
2492     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2493                  SPR_NOACCESS, SPR_NOACCESS,
2494                  &spr_read_generic, &spr_write_generic,
2495                  0x00000000);
2496     /* XXX : not implemented */
2497     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2498                  SPR_NOACCESS, SPR_NOACCESS,
2499                  &spr_read_generic, &spr_write_generic,
2500                  0x00000000);
2501     /* XXX : not implemented */
2502     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2503                  SPR_NOACCESS, SPR_NOACCESS,
2504                  &spr_read_generic, &spr_write_generic,
2505                  0x00000000);
2506     /* XXX : not implemented */
2507     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2508                  SPR_NOACCESS, SPR_NOACCESS,
2509                  &spr_read_generic, &spr_write_generic,
2510                  0x00000000);
2511     /* XXX : not implemented */
2512     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2513                  SPR_NOACCESS, SPR_NOACCESS,
2514                  &spr_read_generic, &spr_write_generic,
2515                  0x00000000);
2516     /* XXX : not implemented */
2517     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2518                  SPR_NOACCESS, SPR_NOACCESS,
2519                  &spr_read_generic, &spr_write_generic,
2520                  0x00000000);
2521 }
2522
2523 // XXX: TODO
2524 /*
2525  * AMR     => SPR 29 (Power 2.04)
2526  * CTRL    => SPR 136 (Power 2.04)
2527  * CTRL    => SPR 152 (Power 2.04)
2528  * SCOMC   => SPR 276 (64 bits ?)
2529  * SCOMD   => SPR 277 (64 bits ?)
2530  * TBU40   => SPR 286 (Power 2.04 hypv)
2531  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2532  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2533  * HDSISR  => SPR 306 (Power 2.04 hypv)
2534  * HDAR    => SPR 307 (Power 2.04 hypv)
2535  * PURR    => SPR 309 (Power 2.04 hypv)
2536  * HDEC    => SPR 310 (Power 2.04 hypv)
2537  * HIOR    => SPR 311 (hypv)
2538  * RMOR    => SPR 312 (970)
2539  * HRMOR   => SPR 313 (Power 2.04 hypv)
2540  * HSRR0   => SPR 314 (Power 2.04 hypv)
2541  * HSRR1   => SPR 315 (Power 2.04 hypv)
2542  * LPCR    => SPR 316 (970)
2543  * LPIDR   => SPR 317 (970)
2544  * SPEFSCR => SPR 512 (Power 2.04 emb)
2545  * EPR     => SPR 702 (Power 2.04 emb)
2546  * perf    => 768-783 (Power 2.04)
2547  * perf    => 784-799 (Power 2.04)
2548  * PPR     => SPR 896 (Power 2.04)
2549  * EPLC    => SPR 947 (Power 2.04 emb)
2550  * EPSC    => SPR 948 (Power 2.04 emb)
2551  * DABRX   => 1015    (Power 2.04 hypv)
2552  * FPECR   => SPR 1022 (?)
2553  * ... and more (thermal management, performance counters, ...)
2554  */
2555
2556 /*****************************************************************************/
2557 /* Exception vectors models                                                  */
2558 static void init_excp_4xx_real (CPUPPCState *env)
2559 {
2560 #if !defined(CONFIG_USER_ONLY)
2561     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2562     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2563     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2564     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2565     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2566     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2567     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2568     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2569     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2570     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2571     env->excp_prefix = 0x00000000UL;
2572     env->ivor_mask = 0x0000FFF0UL;
2573     env->ivpr_mask = 0xFFFF0000UL;
2574     /* Hardware reset vector */
2575     env->hreset_vector = 0xFFFFFFFCUL;
2576 #endif
2577 }
2578
2579 static void init_excp_4xx_softmmu (CPUPPCState *env)
2580 {
2581 #if !defined(CONFIG_USER_ONLY)
2582     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2583     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2584     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2585     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2586     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2588     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2589     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2590     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2591     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2592     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2593     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2594     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2595     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2596     env->excp_prefix = 0x00000000UL;
2597     env->ivor_mask = 0x0000FFF0UL;
2598     env->ivpr_mask = 0xFFFF0000UL;
2599     /* Hardware reset vector */
2600     env->hreset_vector = 0xFFFFFFFCUL;
2601 #endif
2602 }
2603
2604 static void init_excp_MPC5xx (CPUPPCState *env)
2605 {
2606 #if !defined(CONFIG_USER_ONLY)
2607     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2608     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2609     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2610     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2611     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2612     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2613     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2614     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2615     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2616     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2617     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2618     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2619     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2620     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2621     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2622     env->excp_prefix = 0x00000000UL;
2623     env->ivor_mask = 0x0000FFF0UL;
2624     env->ivpr_mask = 0xFFFF0000UL;
2625     /* Hardware reset vector */
2626     env->hreset_vector = 0xFFFFFFFCUL;
2627 #endif
2628 }
2629
2630 static void init_excp_MPC8xx (CPUPPCState *env)
2631 {
2632 #if !defined(CONFIG_USER_ONLY)
2633     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2634     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2635     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2636     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2637     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2638     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2639     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2640     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2641     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2642     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2643     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2644     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2645     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2646     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2647     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2648     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2649     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2650     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2651     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2652     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2653     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2654     env->excp_prefix = 0x00000000UL;
2655     env->ivor_mask = 0x0000FFF0UL;
2656     env->ivpr_mask = 0xFFFF0000UL;
2657     /* Hardware reset vector */
2658     env->hreset_vector = 0xFFFFFFFCUL;
2659 #endif
2660 }
2661
2662 static void init_excp_G2 (CPUPPCState *env)
2663 {
2664 #if !defined(CONFIG_USER_ONLY)
2665     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2666     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2667     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2668     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2669     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2670     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2671     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2672     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2673     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2674     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2675     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2676     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2677     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2678     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2679     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2680     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2681     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2682     env->excp_prefix = 0x00000000UL;
2683     /* Hardware reset vector */
2684     env->hreset_vector = 0xFFFFFFFCUL;
2685 #endif
2686 }
2687
2688 static void init_excp_e200 (CPUPPCState *env)
2689 {
2690 #if !defined(CONFIG_USER_ONLY)
2691     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2692     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2693     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2694     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2695     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2696     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2697     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2698     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2699     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2700     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2701     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2702     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2703     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2704     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2705     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2706     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2707     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2708     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2709     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2710     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2711     env->excp_prefix = 0x00000000UL;
2712     env->ivor_mask = 0x0000FFF7UL;
2713     env->ivpr_mask = 0xFFFF0000UL;
2714     /* Hardware reset vector */
2715     env->hreset_vector = 0xFFFFFFFCUL;
2716 #endif
2717 }
2718
2719 static void init_excp_BookE (CPUPPCState *env)
2720 {
2721 #if !defined(CONFIG_USER_ONLY)
2722     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2723     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2724     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2725     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2726     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2727     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2728     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2729     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2730     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2731     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2732     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2733     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2734     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2735     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2736     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2737     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2738     env->excp_prefix = 0x00000000UL;
2739     env->ivor_mask = 0x0000FFE0UL;
2740     env->ivpr_mask = 0xFFFF0000UL;
2741     /* Hardware reset vector */
2742     env->hreset_vector = 0xFFFFFFFCUL;
2743 #endif
2744 }
2745
2746 static void init_excp_601 (CPUPPCState *env)
2747 {
2748 #if !defined(CONFIG_USER_ONLY)
2749     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2750     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2751     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2752     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2753     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2755     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2756     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2757     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2758     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2759     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2760     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2761     env->excp_prefix = 0xFFF00000UL;
2762     /* Hardware reset vector */
2763     env->hreset_vector = 0x00000100UL;
2764 #endif
2765 }
2766
2767 static void init_excp_602 (CPUPPCState *env)
2768 {
2769 #if !defined(CONFIG_USER_ONLY)
2770     /* XXX: exception prefix has a special behavior on 602 */
2771     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2772     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2773     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2774     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2775     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2776     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2777     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2778     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2779     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2780     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2781     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2782     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2783     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2784     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2785     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2786     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2787     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2788     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2789     env->excp_prefix = 0xFFF00000UL;
2790     /* Hardware reset vector */
2791     env->hreset_vector = 0xFFFFFFFCUL;
2792 #endif
2793 }
2794
2795 static void init_excp_603 (CPUPPCState *env)
2796 {
2797 #if !defined(CONFIG_USER_ONLY)
2798     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2799     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2800     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2801     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2802     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2803     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2804     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2805     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2806     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2807     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2808     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2809     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2810     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2811     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2812     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2813     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2814     env->excp_prefix = 0x00000000UL;
2815     /* Hardware reset vector */
2816     env->hreset_vector = 0xFFFFFFFCUL;
2817 #endif
2818 }
2819
2820 static void init_excp_604 (CPUPPCState *env)
2821 {
2822 #if !defined(CONFIG_USER_ONLY)
2823     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2824     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2825     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2826     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2827     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2828     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2829     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2830     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2831     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2832     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2833     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2834     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2835     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2836     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2837     env->excp_prefix = 0x00000000UL;
2838     /* Hardware reset vector */
2839     env->hreset_vector = 0xFFFFFFFCUL;
2840 #endif
2841 }
2842
2843 #if defined(TARGET_PPC64)
2844 static void init_excp_620 (CPUPPCState *env)
2845 {
2846 #if !defined(CONFIG_USER_ONLY)
2847     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2848     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2849     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2850     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2851     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2852     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2853     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2854     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2855     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2856     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2857     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2858     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2859     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2860     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2861     env->excp_prefix = 0xFFF00000UL;
2862     /* Hardware reset vector */
2863     env->hreset_vector = 0x0000000000000100ULL;
2864 #endif
2865 }
2866 #endif /* defined(TARGET_PPC64) */
2867
2868 static void init_excp_7x0 (CPUPPCState *env)
2869 {
2870 #if !defined(CONFIG_USER_ONLY)
2871     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2872     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2873     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2874     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2875     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2876     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2877     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2878     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2879     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2880     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2881     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2882     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2883     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2884     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2885     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2886     env->excp_prefix = 0x00000000UL;
2887     /* Hardware reset vector */
2888     env->hreset_vector = 0xFFFFFFFCUL;
2889 #endif
2890 }
2891
2892 static void init_excp_750cl (CPUPPCState *env)
2893 {
2894 #if !defined(CONFIG_USER_ONLY)
2895     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2896     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2897     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2898     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2899     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2900     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2901     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2902     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2903     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2904     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2905     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2906     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2907     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2908     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2909     env->excp_prefix = 0x00000000UL;
2910     /* Hardware reset vector */
2911     env->hreset_vector = 0xFFFFFFFCUL;
2912 #endif
2913 }
2914
2915 static void init_excp_750cx (CPUPPCState *env)
2916 {
2917 #if !defined(CONFIG_USER_ONLY)
2918     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2919     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2920     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2921     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2922     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2923     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2924     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2925     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2926     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2927     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2928     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2929     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2930     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2931     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2932     env->excp_prefix = 0x00000000UL;
2933     /* Hardware reset vector */
2934     env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 /* XXX: Check if this is correct */
2939 static void init_excp_7x5 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2943     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2944     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2945     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2946     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2948     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2949     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2950     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2951     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2952     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2953     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2954     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2955     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2956     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2957     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2958     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2959     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2960     env->excp_prefix = 0x00000000UL;
2961     /* Hardware reset vector */
2962     env->hreset_vector = 0xFFFFFFFCUL;
2963 #endif
2964 }
2965
2966 static void init_excp_7400 (CPUPPCState *env)
2967 {
2968 #if !defined(CONFIG_USER_ONLY)
2969     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2970     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2971     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2972     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2973     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2974     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2975     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2976     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2977     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2978     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2979     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2980     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2981     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2982     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2983     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2984     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2985     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2986     env->excp_prefix = 0x00000000UL;
2987     /* Hardware reset vector */
2988     env->hreset_vector = 0xFFFFFFFCUL;
2989 #endif
2990 }
2991
2992 static void init_excp_7450 (CPUPPCState *env)
2993 {
2994 #if !defined(CONFIG_USER_ONLY)
2995     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2996     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2997     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2998     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2999     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3000     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3001     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3002     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3003     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3004     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3005     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3006     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3007     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3008     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3009     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3010     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3011     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3012     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3013     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3014     env->excp_prefix = 0x00000000UL;
3015     /* Hardware reset vector */
3016     env->hreset_vector = 0xFFFFFFFCUL;
3017 #endif
3018 }
3019
3020 #if defined (TARGET_PPC64)
3021 static void init_excp_970 (CPUPPCState *env)
3022 {
3023 #if !defined(CONFIG_USER_ONLY)
3024     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3025     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3026     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3027     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3028     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3029     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3030     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3031     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3032     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3033     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3034     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3035     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3036     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3037     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3038     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3039     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3040     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3041     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3042     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3043     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3044     env->excp_prefix   = 0x00000000FFF00000ULL;
3045     /* Hardware reset vector */
3046     env->hreset_vector = 0x0000000000000100ULL;
3047 #endif
3048 }
3049 #endif
3050
3051 /*****************************************************************************/
3052 /* Power management enable checks                                            */
3053 static int check_pow_none (CPUPPCState *env)
3054 {
3055     return 0;
3056 }
3057
3058 static int check_pow_nocheck (CPUPPCState *env)
3059 {
3060     return 1;
3061 }
3062
3063 static int check_pow_hid0 (CPUPPCState *env)
3064 {
3065     if (env->spr[SPR_HID0] & 0x00E00000)
3066         return 1;
3067
3068     return 0;
3069 }
3070
3071 static int check_pow_hid0_74xx (CPUPPCState *env)
3072 {
3073     if (env->spr[SPR_HID0] & 0x00600000)
3074         return 1;
3075
3076     return 0;
3077 }
3078
3079 /*****************************************************************************/
3080 /* PowerPC implementations definitions                                       */
3081
3082 /* PowerPC 401                                                               */
3083 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3084                               PPC_WRTEE | PPC_DCR |                           \
3085                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3086                               PPC_CACHE_DCBZ |                                \
3087                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3088                               PPC_4xx_COMMON | PPC_40x_EXCP)
3089 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3090 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3091 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3092 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3093 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3094 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3095                               POWERPC_FLAG_BUS_CLK)
3096 #define check_pow_401        check_pow_nocheck
3097
3098 static void init_proc_401 (CPUPPCState *env)
3099 {
3100     gen_spr_40x(env);
3101     gen_spr_401_403(env);
3102     gen_spr_401(env);
3103     init_excp_4xx_real(env);
3104     env->dcache_line_size = 32;
3105     env->icache_line_size = 32;
3106     /* Allocate hardware IRQ controller */
3107     ppc40x_irq_init(env);
3108 }
3109
3110 /* PowerPC 401x2                                                             */
3111 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3112                               PPC_DCR | PPC_WRTEE |                           \
3113                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3114                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3115                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3116                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3117                               PPC_4xx_COMMON | PPC_40x_EXCP)
3118 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3119 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3120 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3121 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3122 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3123 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3124                               POWERPC_FLAG_BUS_CLK)
3125 #define check_pow_401x2      check_pow_nocheck
3126
3127 static void init_proc_401x2 (CPUPPCState *env)
3128 {
3129     gen_spr_40x(env);
3130     gen_spr_401_403(env);
3131     gen_spr_401x2(env);
3132     gen_spr_compress(env);
3133     /* Memory management */
3134 #if !defined(CONFIG_USER_ONLY)
3135     env->nb_tlb = 64;
3136     env->nb_ways = 1;
3137     env->id_tlbs = 0;
3138 #endif
3139     init_excp_4xx_softmmu(env);
3140     env->dcache_line_size = 32;
3141     env->icache_line_size = 32;
3142     /* Allocate hardware IRQ controller */
3143     ppc40x_irq_init(env);
3144 }
3145
3146 /* PowerPC 401x3                                                             */
3147 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3148                               PPC_DCR | PPC_WRTEE |                           \
3149                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3150                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3151                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3152                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3153                               PPC_4xx_COMMON | PPC_40x_EXCP)
3154 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3155 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3156 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3157 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3158 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3159 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3160                               POWERPC_FLAG_BUS_CLK)
3161 #define check_pow_401x3      check_pow_nocheck
3162
3163 __attribute__ (( unused ))
3164 static void init_proc_401x3 (CPUPPCState *env)
3165 {
3166     gen_spr_40x(env);
3167     gen_spr_401_403(env);
3168     gen_spr_401(env);
3169     gen_spr_401x2(env);
3170     gen_spr_compress(env);
3171     init_excp_4xx_softmmu(env);
3172     env->dcache_line_size = 32;
3173     env->icache_line_size = 32;
3174     /* Allocate hardware IRQ controller */
3175     ppc40x_irq_init(env);
3176 }
3177
3178 /* IOP480                                                                    */
3179 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3180                               PPC_DCR | PPC_WRTEE |                           \
3181                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3182                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3183                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3184                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3185                               PPC_4xx_COMMON | PPC_40x_EXCP)
3186 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3187 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3188 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3189 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3190 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3191 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3192                               POWERPC_FLAG_BUS_CLK)
3193 #define check_pow_IOP480     check_pow_nocheck
3194
3195 static void init_proc_IOP480 (CPUPPCState *env)
3196 {
3197     gen_spr_40x(env);
3198     gen_spr_401_403(env);
3199     gen_spr_401x2(env);
3200     gen_spr_compress(env);
3201     /* Memory management */
3202 #if !defined(CONFIG_USER_ONLY)
3203     env->nb_tlb = 64;
3204     env->nb_ways = 1;
3205     env->id_tlbs = 0;
3206 #endif
3207     init_excp_4xx_softmmu(env);
3208     env->dcache_line_size = 32;
3209     env->icache_line_size = 32;
3210     /* Allocate hardware IRQ controller */
3211     ppc40x_irq_init(env);
3212 }
3213
3214 /* PowerPC 403                                                               */
3215 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3216                               PPC_DCR | PPC_WRTEE |                           \
3217                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3218                               PPC_CACHE_DCBZ |                                \
3219                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3220                               PPC_4xx_COMMON | PPC_40x_EXCP)
3221 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3222 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3223 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3224 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3225 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3226 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3227                               POWERPC_FLAG_BUS_CLK)
3228 #define check_pow_403        check_pow_nocheck
3229
3230 static void init_proc_403 (CPUPPCState *env)
3231 {
3232     gen_spr_40x(env);
3233     gen_spr_401_403(env);
3234     gen_spr_403(env);
3235     gen_spr_403_real(env);
3236     init_excp_4xx_real(env);
3237     env->dcache_line_size = 32;
3238     env->icache_line_size = 32;
3239     /* Allocate hardware IRQ controller */
3240     ppc40x_irq_init(env);
3241 }
3242
3243 /* PowerPC 403 GCX                                                           */
3244 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3245                               PPC_DCR | PPC_WRTEE |                           \
3246                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3247                               PPC_CACHE_DCBZ |                                \
3248                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3249                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3250                               PPC_4xx_COMMON | PPC_40x_EXCP)
3251 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3252 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3253 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3254 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3255 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3256 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3257                               POWERPC_FLAG_BUS_CLK)
3258 #define check_pow_403GCX     check_pow_nocheck
3259
3260 static void init_proc_403GCX (CPUPPCState *env)
3261 {
3262     gen_spr_40x(env);
3263     gen_spr_401_403(env);
3264     gen_spr_403(env);
3265     gen_spr_403_real(env);
3266     gen_spr_403_mmu(env);
3267     /* Bus access control */
3268     /* not emulated, as Qemu never does speculative access */
3269     spr_register(env, SPR_40x_SGR, "SGR",
3270                  SPR_NOACCESS, SPR_NOACCESS,
3271                  &spr_read_generic, &spr_write_generic,
3272                  0xFFFFFFFF);
3273     /* not emulated, as Qemu do not emulate caches */
3274     spr_register(env, SPR_40x_DCWR, "DCWR",
3275                  SPR_NOACCESS, SPR_NOACCESS,
3276                  &spr_read_generic, &spr_write_generic,
3277                  0x00000000);
3278     /* Memory management */
3279 #if !defined(CONFIG_USER_ONLY)
3280     env->nb_tlb = 64;
3281     env->nb_ways = 1;
3282     env->id_tlbs = 0;
3283 #endif
3284     init_excp_4xx_softmmu(env);
3285     env->dcache_line_size = 32;
3286     env->icache_line_size = 32;
3287     /* Allocate hardware IRQ controller */
3288     ppc40x_irq_init(env);
3289 }
3290
3291 /* PowerPC 405                                                               */
3292 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3293                               PPC_DCR | PPC_WRTEE |                           \
3294                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3295                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3296                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3297                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3298                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3299 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3300 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3301 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3302 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3303 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3304 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3305                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3306 #define check_pow_405        check_pow_nocheck
3307
3308 static void init_proc_405 (CPUPPCState *env)
3309 {
3310     /* Time base */
3311     gen_tbl(env);
3312     gen_spr_40x(env);
3313     gen_spr_405(env);
3314     /* Bus access control */
3315     /* not emulated, as Qemu never does speculative access */
3316     spr_register(env, SPR_40x_SGR, "SGR",
3317                  SPR_NOACCESS, SPR_NOACCESS,
3318                  &spr_read_generic, &spr_write_generic,
3319                  0xFFFFFFFF);
3320     /* not emulated, as Qemu do not emulate caches */
3321     spr_register(env, SPR_40x_DCWR, "DCWR",
3322                  SPR_NOACCESS, SPR_NOACCESS,
3323                  &spr_read_generic, &spr_write_generic,
3324                  0x00000000);
3325     /* Memory management */
3326 #if !defined(CONFIG_USER_ONLY)
3327     env->nb_tlb = 64;
3328     env->nb_ways = 1;
3329     env->id_tlbs = 0;
3330 #endif
3331     init_excp_4xx_softmmu(env);
3332     env->dcache_line_size = 32;
3333     env->icache_line_size = 32;
3334     /* Allocate hardware IRQ controller */
3335     ppc40x_irq_init(env);
3336 }
3337
3338 /* PowerPC 440 EP                                                            */
3339 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3340                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3341                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3342                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3343                               PPC_MEM_TLBSYNC |                               \
3344                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3345                               PPC_440_SPEC)
3346 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3347 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3348 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3349 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3350 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3351 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3352                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3353 #define check_pow_440EP      check_pow_nocheck
3354
3355 __attribute__ (( unused ))
3356 static void init_proc_440EP (CPUPPCState *env)
3357 {
3358     /* Time base */
3359     gen_tbl(env);
3360     gen_spr_BookE(env, 0x000000000000FFFFULL);
3361     gen_spr_440(env);
3362     gen_spr_usprgh(env);
3363     /* Processor identification */
3364     spr_register(env, SPR_BOOKE_PIR, "PIR",
3365                  SPR_NOACCESS, SPR_NOACCESS,
3366                  &spr_read_generic, &spr_write_pir,
3367                  0x00000000);
3368     /* XXX : not implemented */
3369     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3370                  SPR_NOACCESS, SPR_NOACCESS,
3371                  &spr_read_generic, &spr_write_generic,
3372                  0x00000000);
3373     /* XXX : not implemented */
3374     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3375                  SPR_NOACCESS, SPR_NOACCESS,
3376                  &spr_read_generic, &spr_write_generic,
3377                  0x00000000);
3378     /* XXX : not implemented */
3379     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3380                  SPR_NOACCESS, SPR_NOACCESS,
3381                  &spr_read_generic, &spr_write_generic,
3382                  0x00000000);
3383     /* XXX : not implemented */
3384     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3385                  SPR_NOACCESS, SPR_NOACCESS,
3386                  &spr_read_generic, &spr_write_generic,
3387                  0x00000000);
3388     /* XXX : not implemented */
3389     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3390                  SPR_NOACCESS, SPR_NOACCESS,
3391                  &spr_read_generic, &spr_write_generic,
3392                  0x00000000);
3393     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3394                  SPR_NOACCESS, SPR_NOACCESS,
3395                  &spr_read_generic, &spr_write_generic,
3396                  0x00000000);
3397     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3398                  SPR_NOACCESS, SPR_NOACCESS,
3399                  &spr_read_generic, &spr_write_generic,
3400                  0x00000000);
3401     /* XXX : not implemented */
3402     spr_register(env, SPR_440_CCR1, "CCR1",
3403                  SPR_NOACCESS, SPR_NOACCESS,
3404                  &spr_read_generic, &spr_write_generic,
3405                  0x00000000);
3406     /* Memory management */
3407 #if !defined(CONFIG_USER_ONLY)
3408     env->nb_tlb = 64;
3409     env->nb_ways = 1;
3410     env->id_tlbs = 0;
3411 #endif
3412     init_excp_BookE(env);
3413     env->dcache_line_size = 32;
3414     env->icache_line_size = 32;
3415     /* XXX: TODO: allocate internal IRQ controller */
3416 }
3417
3418 /* PowerPC 440 GP                                                            */
3419 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3420                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3421                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3422                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3423                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3424                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3425                               PPC_440_SPEC)
3426 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3427 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3428 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3429 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3430 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3431 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3432                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3433 #define check_pow_440GP      check_pow_nocheck
3434
3435 __attribute__ (( unused ))
3436 static void init_proc_440GP (CPUPPCState *env)
3437 {
3438     /* Time base */
3439     gen_tbl(env);
3440     gen_spr_BookE(env, 0x000000000000FFFFULL);
3441     gen_spr_440(env);
3442     gen_spr_usprgh(env);
3443     /* Processor identification */
3444     spr_register(env, SPR_BOOKE_PIR, "PIR",
3445                  SPR_NOACCESS, SPR_NOACCESS,
3446                  &spr_read_generic, &spr_write_pir,
3447                  0x00000000);
3448     /* XXX : not implemented */
3449     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3450                  SPR_NOACCESS, SPR_NOACCESS,
3451                  &spr_read_generic, &spr_write_generic,
3452                  0x00000000);
3453     /* XXX : not implemented */
3454     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3455                  SPR_NOACCESS, SPR_NOACCESS,
3456                  &spr_read_generic, &spr_write_generic,
3457                  0x00000000);
3458     /* XXX : not implemented */
3459     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3460                  SPR_NOACCESS, SPR_NOACCESS,
3461                  &spr_read_generic, &spr_write_generic,
3462                  0x00000000);
3463     /* XXX : not implemented */
3464     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3465                  SPR_NOACCESS, SPR_NOACCESS,
3466                  &spr_read_generic, &spr_write_generic,
3467                  0x00000000);
3468     /* Memory management */
3469 #if !defined(CONFIG_USER_ONLY)
3470     env->nb_tlb = 64;
3471     env->nb_ways = 1;
3472     env->id_tlbs = 0;
3473 #endif
3474     init_excp_BookE(env);
3475     env->dcache_line_size = 32;
3476     env->icache_line_size = 32;
3477     /* XXX: TODO: allocate internal IRQ controller */
3478 }
3479
3480 /* PowerPC 440x4                                                             */
3481 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3482                               PPC_DCR | PPC_WRTEE |                           \
3483                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3484                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3485                               PPC_MEM_TLBSYNC |                               \
3486                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3487                               PPC_440_SPEC)
3488 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3489 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3490 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3491 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3492 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3493 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3494                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3495 #define check_pow_440x4      check_pow_nocheck
3496
3497 __attribute__ (( unused ))
3498 static void init_proc_440x4 (CPUPPCState *env)
3499 {
3500     /* Time base */
3501     gen_tbl(env);
3502     gen_spr_BookE(env, 0x000000000000FFFFULL);
3503     gen_spr_440(env);
3504     gen_spr_usprgh(env);
3505     /* Processor identification */
3506     spr_register(env, SPR_BOOKE_PIR, "PIR",
3507                  SPR_NOACCESS, SPR_NOACCESS,
3508                  &spr_read_generic, &spr_write_pir,
3509                  0x00000000);
3510     /* XXX : not implemented */
3511     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3512                  SPR_NOACCESS, SPR_NOACCESS,
3513                  &spr_read_generic, &spr_write_generic,
3514                  0x00000000);
3515     /* XXX : not implemented */
3516     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3517                  SPR_NOACCESS, SPR_NOACCESS,
3518                  &spr_read_generic, &spr_write_generic,
3519                  0x00000000);
3520     /* XXX : not implemented */
3521     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3522                  SPR_NOACCESS, SPR_NOACCESS,
3523                  &spr_read_generic, &spr_write_generic,
3524                  0x00000000);
3525     /* XXX : not implemented */
3526     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3527                  SPR_NOACCESS, SPR_NOACCESS,
3528                  &spr_read_generic, &spr_write_generic,
3529                  0x00000000);
3530     /* Memory management */
3531 #if !defined(CONFIG_USER_ONLY)
3532     env->nb_tlb = 64;
3533     env->nb_ways = 1;
3534     env->id_tlbs = 0;
3535 #endif
3536     init_excp_BookE(env);
3537     env->dcache_line_size = 32;
3538     env->icache_line_size = 32;
3539     /* XXX: TODO: allocate internal IRQ controller */
3540 }
3541
3542 /* PowerPC 440x5                                                             */
3543 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3544                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3545                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3546                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3547                               PPC_MEM_TLBSYNC |                               \
3548                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3549                               PPC_440_SPEC)
3550 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3551 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3552 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3553 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3554 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3555 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3556                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3557 #define check_pow_440x5      check_pow_nocheck
3558
3559 __attribute__ (( unused ))
3560 static void init_proc_440x5 (CPUPPCState *env)
3561 {
3562     /* Time base */
3563     gen_tbl(env);
3564     gen_spr_BookE(env, 0x000000000000FFFFULL);
3565     gen_spr_440(env);
3566     gen_spr_usprgh(env);
3567     /* Processor identification */
3568     spr_register(env, SPR_BOOKE_PIR, "PIR",
3569                  SPR_NOACCESS, SPR_NOACCESS,
3570                  &spr_read_generic, &spr_write_pir,
3571                  0x00000000);
3572     /* XXX : not implemented */
3573     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3574                  SPR_NOACCESS, SPR_NOACCESS,
3575                  &spr_read_generic, &spr_write_generic,
3576                  0x00000000);
3577     /* XXX : not implemented */
3578     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3579                  SPR_NOACCESS, SPR_NOACCESS,
3580                  &spr_read_generic, &spr_write_generic,
3581                  0x00000000);
3582     /* XXX : not implemented */
3583     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3584                  SPR_NOACCESS, SPR_NOACCESS,
3585                  &spr_read_generic, &spr_write_generic,
3586                  0x00000000);
3587     /* XXX : not implemented */
3588     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3589                  SPR_NOACCESS, SPR_NOACCESS,
3590                  &spr_read_generic, &spr_write_generic,
3591                  0x00000000);
3592     /* XXX : not implemented */
3593     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3594                  SPR_NOACCESS, SPR_NOACCESS,
3595                  &spr_read_generic, &spr_write_generic,
3596                  0x00000000);
3597     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3598                  SPR_NOACCESS, SPR_NOACCESS,
3599                  &spr_read_generic, &spr_write_generic,
3600                  0x00000000);
3601     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3602                  SPR_NOACCESS, SPR_NOACCESS,
3603                  &spr_read_generic, &spr_write_generic,
3604                  0x00000000);
3605     /* XXX : not implemented */
3606     spr_register(env, SPR_440_CCR1, "CCR1",
3607                  SPR_NOACCESS, SPR_NOACCESS,
3608                  &spr_read_generic, &spr_write_generic,
3609                  0x00000000);
3610     /* Memory management */
3611 #if !defined(CONFIG_USER_ONLY)
3612     env->nb_tlb = 64;
3613     env->nb_ways = 1;
3614     env->id_tlbs = 0;
3615 #endif
3616     init_excp_BookE(env);
3617     env->dcache_line_size = 32;
3618     env->icache_line_size = 32;
3619     /* XXX: TODO: allocate internal IRQ controller */
3620 }
3621
3622 /* PowerPC 460 (guessed)                                                     */
3623 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3624                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3625                               PPC_WRTEE | PPC_MFAPIDI |                       \
3626                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3627                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3628                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3629                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3630                               PPC_440_SPEC)
3631 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3632 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3633 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3634 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3635 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3636 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3637                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3638 #define check_pow_460        check_pow_nocheck
3639
3640 __attribute__ (( unused ))
3641 static void init_proc_460 (CPUPPCState *env)
3642 {
3643     /* Time base */
3644     gen_tbl(env);
3645     gen_spr_BookE(env, 0x000000000000FFFFULL);
3646     gen_spr_440(env);
3647     gen_spr_usprgh(env);
3648     /* Processor identification */
3649     spr_register(env, SPR_BOOKE_PIR, "PIR",
3650                  SPR_NOACCESS, SPR_NOACCESS,
3651                  &spr_read_generic, &spr_write_pir,
3652                  0x00000000);
3653     /* XXX : not implemented */
3654     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3655                  SPR_NOACCESS, SPR_NOACCESS,
3656                  &spr_read_generic, &spr_write_generic,
3657                  0x00000000);
3658     /* XXX : not implemented */
3659     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3660                  SPR_NOACCESS, SPR_NOACCESS,
3661                  &spr_read_generic, &spr_write_generic,
3662                  0x00000000);
3663     /* XXX : not implemented */
3664     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3665                  SPR_NOACCESS, SPR_NOACCESS,
3666                  &spr_read_generic, &spr_write_generic,
3667                  0x00000000);
3668     /* XXX : not implemented */
3669     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3670                  SPR_NOACCESS, SPR_NOACCESS,
3671                  &spr_read_generic, &spr_write_generic,
3672                  0x00000000);
3673     /* XXX : not implemented */
3674     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3675                  SPR_NOACCESS, SPR_NOACCESS,
3676                  &spr_read_generic, &spr_write_generic,
3677                  0x00000000);
3678     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3679                  SPR_NOACCESS, SPR_NOACCESS,
3680                  &spr_read_generic, &spr_write_generic,
3681                  0x00000000);
3682     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3683                  SPR_NOACCESS, SPR_NOACCESS,
3684                  &spr_read_generic, &spr_write_generic,
3685                  0x00000000);
3686     /* XXX : not implemented */
3687     spr_register(env, SPR_440_CCR1, "CCR1",
3688                  SPR_NOACCESS, SPR_NOACCESS,
3689                  &spr_read_generic, &spr_write_generic,
3690                  0x00000000);
3691     /* XXX : not implemented */
3692     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3693                  &spr_read_generic, &spr_write_generic,
3694                  &spr_read_generic, &spr_write_generic,
3695                  0x00000000);
3696     /* Memory management */
3697 #if !defined(CONFIG_USER_ONLY)
3698     env->nb_tlb = 64;
3699     env->nb_ways = 1;
3700     env->id_tlbs = 0;
3701 #endif
3702     init_excp_BookE(env);
3703     env->dcache_line_size = 32;
3704     env->icache_line_size = 32;
3705     /* XXX: TODO: allocate internal IRQ controller */
3706 }
3707
3708 /* PowerPC 460F (guessed)                                                    */
3709 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3710                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3711                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3712                               PPC_FLOAT_STFIWX |                              \
3713                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3714                               PPC_WRTEE | PPC_MFAPIDI |                       \
3715                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3716                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3717                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3718                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3719                               PPC_440_SPEC)
3720 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3721 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3722 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3723 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3724 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3725 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3726                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3727 #define check_pow_460F       check_pow_nocheck
3728
3729 __attribute__ (( unused ))
3730 static void init_proc_460F (CPUPPCState *env)
3731 {
3732     /* Time base */
3733     gen_tbl(env);
3734     gen_spr_BookE(env, 0x000000000000FFFFULL);
3735     gen_spr_440(env);
3736     gen_spr_usprgh(env);
3737     /* Processor identification */
3738     spr_register(env, SPR_BOOKE_PIR, "PIR",
3739                  SPR_NOACCESS, SPR_NOACCESS,
3740                  &spr_read_generic, &spr_write_pir,
3741                  0x00000000);
3742     /* XXX : not implemented */
3743     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3744                  SPR_NOACCESS, SPR_NOACCESS,
3745                  &spr_read_generic, &spr_write_generic,
3746                  0x00000000);
3747     /* XXX : not implemented */
3748     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3749                  SPR_NOACCESS, SPR_NOACCESS,
3750                  &spr_read_generic, &spr_write_generic,
3751                  0x00000000);
3752     /* XXX : not implemented */
3753     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3754                  SPR_NOACCESS, SPR_NOACCESS,
3755                  &spr_read_generic, &spr_write_generic,
3756                  0x00000000);
3757     /* XXX : not implemented */
3758     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3759                  SPR_NOACCESS, SPR_NOACCESS,
3760                  &spr_read_generic, &spr_write_generic,
3761                  0x00000000);
3762     /* XXX : not implemented */
3763     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3764                  SPR_NOACCESS, SPR_NOACCESS,
3765                  &spr_read_generic, &spr_write_generic,
3766                  0x00000000);
3767     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3768                  SPR_NOACCESS, SPR_NOACCESS,
3769                  &spr_read_generic, &spr_write_generic,
3770                  0x00000000);
3771     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3772                  SPR_NOACCESS, SPR_NOACCESS,
3773                  &spr_read_generic, &spr_write_generic,
3774                  0x00000000);
3775     /* XXX : not implemented */
3776     spr_register(env, SPR_440_CCR1, "CCR1",
3777                  SPR_NOACCESS, SPR_NOACCESS,
3778                  &spr_read_generic, &spr_write_generic,
3779                  0x00000000);
3780     /* XXX : not implemented */
3781     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3782                  &spr_read_generic, &spr_write_generic,
3783                  &spr_read_generic, &spr_write_generic,
3784                  0x00000000);
3785     /* Memory management */
3786 #if !defined(CONFIG_USER_ONLY)
3787     env->nb_tlb = 64;
3788     env->nb_ways = 1;
3789     env->id_tlbs = 0;
3790 #endif
3791     init_excp_BookE(env);
3792     env->dcache_line_size = 32;
3793     env->icache_line_size = 32;
3794     /* XXX: TODO: allocate internal IRQ controller */
3795 }
3796
3797 /* Freescale 5xx cores (aka RCPU) */
3798 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3799                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3800                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3801                               PPC_MFTB)
3802 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3803 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3804 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3805 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3806 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3807 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3808                               POWERPC_FLAG_BUS_CLK)
3809 #define check_pow_MPC5xx     check_pow_none
3810
3811 __attribute__ (( unused ))
3812 static void init_proc_MPC5xx (CPUPPCState *env)
3813 {
3814     /* Time base */
3815     gen_tbl(env);
3816     gen_spr_5xx_8xx(env);
3817     gen_spr_5xx(env);
3818     init_excp_MPC5xx(env);
3819     env->dcache_line_size = 32;
3820     env->icache_line_size = 32;
3821     /* XXX: TODO: allocate internal IRQ controller */
3822 }
3823
3824 /* Freescale 8xx cores (aka PowerQUICC) */
3825 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3826                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3827                               PPC_CACHE_ICBI | PPC_MFTB)
3828 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3829 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3830 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3831 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3832 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3833 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3834                               POWERPC_FLAG_BUS_CLK)
3835 #define check_pow_MPC8xx     check_pow_none
3836
3837 __attribute__ (( unused ))
3838 static void init_proc_MPC8xx (CPUPPCState *env)
3839 {
3840     /* Time base */
3841     gen_tbl(env);
3842     gen_spr_5xx_8xx(env);
3843     gen_spr_8xx(env);
3844     init_excp_MPC8xx(env);
3845     env->dcache_line_size = 32;
3846     env->icache_line_size = 32;
3847     /* XXX: TODO: allocate internal IRQ controller */
3848 }
3849
3850 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3851 /* PowerPC G2                                                                */
3852 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3853                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3854                               PPC_FLOAT_STFIWX |                              \
3855                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3856                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3857                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3858                               PPC_SEGMENT | PPC_EXTERN)
3859 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3860 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3861 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3862 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3863 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3864 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3865                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3866 #define check_pow_G2         check_pow_hid0
3867
3868 static void init_proc_G2 (CPUPPCState *env)
3869 {
3870     gen_spr_ne_601(env);
3871     gen_spr_G2_755(env);
3872     gen_spr_G2(env);
3873     /* Time base */
3874     gen_tbl(env);
3875     /* External access control */
3876     /* XXX : not implemented */
3877     spr_register(env, SPR_EAR, "EAR",
3878                  SPR_NOACCESS, SPR_NOACCESS,
3879                  &spr_read_generic, &spr_write_generic,
3880                  0x00000000);
3881     /* Hardware implementation register */
3882     /* XXX : not implemented */
3883     spr_register(env, SPR_HID0, "HID0",
3884                  SPR_NOACCESS, SPR_NOACCESS,
3885                  &spr_read_generic, &spr_write_generic,
3886                  0x00000000);
3887     /* XXX : not implemented */
3888     spr_register(env, SPR_HID1, "HID1",
3889                  SPR_NOACCESS, SPR_NOACCESS,
3890                  &spr_read_generic, &spr_write_generic,
3891                  0x00000000);
3892     /* XXX : not implemented */
3893     spr_register(env, SPR_HID2, "HID2",
3894                  SPR_NOACCESS, SPR_NOACCESS,
3895                  &spr_read_generic, &spr_write_generic,
3896                  0x00000000);
3897     /* Memory management */
3898     gen_low_BATs(env);
3899     gen_high_BATs(env);
3900     gen_6xx_7xx_soft_tlb(env, 64, 2);
3901     init_excp_G2(env);
3902     env->dcache_line_size = 32;
3903     env->icache_line_size = 32;
3904     /* Allocate hardware IRQ controller */
3905     ppc6xx_irq_init(env);
3906 }
3907
3908 /* PowerPC G2LE                                                              */
3909 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3910                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3911                               PPC_FLOAT_STFIWX |                              \
3912                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3913                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3914                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3915                               PPC_SEGMENT | PPC_EXTERN)
3916 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3917 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3918 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3919 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3920 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3921 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3922                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3923 #define check_pow_G2LE       check_pow_hid0
3924
3925 static void init_proc_G2LE (CPUPPCState *env)
3926 {
3927     gen_spr_ne_601(env);
3928     gen_spr_G2_755(env);
3929     gen_spr_G2(env);
3930     /* Time base */
3931     gen_tbl(env);
3932     /* External access control */
3933     /* XXX : not implemented */
3934     spr_register(env, SPR_EAR, "EAR",
3935                  SPR_NOACCESS, SPR_NOACCESS,
3936                  &spr_read_generic, &spr_write_generic,
3937                  0x00000000);
3938     /* Hardware implementation register */
3939     /* XXX : not implemented */
3940     spr_register(env, SPR_HID0, "HID0",
3941                  SPR_NOACCESS, SPR_NOACCESS,
3942                  &spr_read_generic, &spr_write_generic,
3943                  0x00000000);
3944     /* XXX : not implemented */
3945     spr_register(env, SPR_HID1, "HID1",
3946                  SPR_NOACCESS, SPR_NOACCESS,
3947                  &spr_read_generic, &spr_write_generic,
3948                  0x00000000);
3949     /* XXX : not implemented */
3950     spr_register(env, SPR_HID2, "HID2",
3951                  SPR_NOACCESS, SPR_NOACCESS,
3952                  &spr_read_generic, &spr_write_generic,
3953                  0x00000000);
3954     /* Memory management */
3955     gen_low_BATs(env);
3956     gen_high_BATs(env);
3957     gen_6xx_7xx_soft_tlb(env, 64, 2);
3958     init_excp_G2(env);
3959     env->dcache_line_size = 32;
3960     env->icache_line_size = 32;
3961     /* Allocate hardware IRQ controller */
3962     ppc6xx_irq_init(env);
3963 }
3964
3965 /* e200 core                                                                 */
3966 /* XXX: unimplemented instructions:
3967  * dcblc
3968  * dcbtlst
3969  * dcbtstls
3970  * icblc
3971  * icbtls
3972  * tlbivax
3973  * all SPE multiply-accumulate instructions
3974  */
3975 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
3976                               PPC_SPE | PPC_SPEFPU |                          \
3977                               PPC_WRTEE | PPC_RFDI |                          \
3978                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
3979                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3980                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
3981                               PPC_BOOKE)
3982 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
3983 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
3984 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
3985 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
3986 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
3987 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
3988                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
3989                               POWERPC_FLAG_BUS_CLK)
3990 #define check_pow_e200       check_pow_hid0
3991
3992 __attribute__ (( unused ))
3993 static void init_proc_e200 (CPUPPCState *env)
3994 {
3995     /* Time base */
3996     gen_tbl(env);
3997     gen_spr_BookE(env, 0x000000070000FFFFULL);
3998     /* XXX : not implemented */
3999     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4000                  SPR_NOACCESS, SPR_NOACCESS,
4001                  &spr_read_generic, &spr_write_generic,
4002                  0x00000000);
4003     /* Memory management */
4004     gen_spr_BookE_FSL(env, 0x0000005D);
4005     /* XXX : not implemented */
4006     spr_register(env, SPR_HID0, "HID0",
4007                  SPR_NOACCESS, SPR_NOACCESS,
4008                  &spr_read_generic, &spr_write_generic,
4009                  0x00000000);
4010     /* XXX : not implemented */
4011     spr_register(env, SPR_HID1, "HID1",
4012                  SPR_NOACCESS, SPR_NOACCESS,
4013                  &spr_read_generic, &spr_write_generic,
4014                  0x00000000);
4015     /* XXX : not implemented */
4016     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4017                  SPR_NOACCESS, SPR_NOACCESS,
4018                  &spr_read_generic, &spr_write_generic,
4019                  0x00000000);
4020     /* XXX : not implemented */
4021     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4022                  SPR_NOACCESS, SPR_NOACCESS,
4023                  &spr_read_generic, &spr_write_generic,
4024                  0x00000000);
4025     /* XXX : not implemented */
4026     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4027                  SPR_NOACCESS, SPR_NOACCESS,
4028                  &spr_read_generic, &spr_write_generic,
4029                  0x00000000);
4030     /* XXX : not implemented */
4031     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4032                  SPR_NOACCESS, SPR_NOACCESS,
4033                  &spr_read_generic, &spr_write_generic,
4034                  0x00000000);
4035     /* XXX : not implemented */
4036     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4037                  SPR_NOACCESS, SPR_NOACCESS,
4038                  &spr_read_generic, &spr_write_generic,
4039                  0x00000000);
4040     /* XXX : not implemented */
4041     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4042                  SPR_NOACCESS, SPR_NOACCESS,
4043                  &spr_read_generic, &spr_write_generic,
4044                  0x00000000);
4045     /* XXX : not implemented */
4046     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4047                  SPR_NOACCESS, SPR_NOACCESS,
4048                  &spr_read_generic, &spr_write_generic,
4049                  0x00000000);
4050     /* XXX : not implemented */
4051     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4052                  SPR_NOACCESS, SPR_NOACCESS,
4053                  &spr_read_generic, &spr_write_generic,
4054                  0x00000000);
4055     /* XXX : not implemented */
4056     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4057                  SPR_NOACCESS, SPR_NOACCESS,
4058                  &spr_read_generic, &spr_write_generic,
4059                  0x00000000);
4060     /* XXX : not implemented */
4061     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4062                  SPR_NOACCESS, SPR_NOACCESS,
4063                  &spr_read_generic, &spr_write_generic,
4064                  0x00000000);
4065     /* XXX : not implemented */
4066     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4067                  SPR_NOACCESS, SPR_NOACCESS,
4068                  &spr_read_generic, &spr_write_generic,
4069                  0x00000000);
4070     /* XXX : not implemented */
4071     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4072                  SPR_NOACCESS, SPR_NOACCESS,
4073                  &spr_read_generic, &spr_write_generic,
4074                  0x00000000);
4075     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4076                  SPR_NOACCESS, SPR_NOACCESS,
4077                  &spr_read_generic, &spr_write_generic,
4078                  0x00000000);
4079     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4080                  SPR_NOACCESS, SPR_NOACCESS,
4081                  &spr_read_generic, &spr_write_generic,
4082                  0x00000000);
4083 #if !defined(CONFIG_USER_ONLY)
4084     env->nb_tlb = 64;
4085     env->nb_ways = 1;
4086     env->id_tlbs = 0;
4087 #endif
4088     init_excp_e200(env);
4089     env->dcache_line_size = 32;
4090     env->icache_line_size = 32;
4091     /* XXX: TODO: allocate internal IRQ controller */
4092 }
4093
4094 /* e300 core                                                                 */
4095 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4096                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4097                               PPC_FLOAT_STFIWX |                              \
4098                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4099                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4100                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4101                               PPC_SEGMENT | PPC_EXTERN)
4102 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4103 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4104 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4105 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4106 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4107 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4108                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4109 #define check_pow_e300       check_pow_hid0
4110
4111 __attribute__ (( unused ))
4112 static void init_proc_e300 (CPUPPCState *env)
4113 {
4114     gen_spr_ne_601(env);
4115     gen_spr_603(env);
4116     /* Time base */
4117     gen_tbl(env);
4118     /* hardware implementation registers */
4119     /* XXX : not implemented */
4120     spr_register(env, SPR_HID0, "HID0",
4121                  SPR_NOACCESS, SPR_NOACCESS,
4122                  &spr_read_generic, &spr_write_generic,
4123                  0x00000000);
4124     /* XXX : not implemented */
4125     spr_register(env, SPR_HID1, "HID1",
4126                  SPR_NOACCESS, SPR_NOACCESS,
4127                  &spr_read_generic, &spr_write_generic,
4128                  0x00000000);
4129     /* Memory management */
4130     gen_low_BATs(env);
4131     gen_6xx_7xx_soft_tlb(env, 64, 2);
4132     init_excp_603(env);
4133     env->dcache_line_size = 32;
4134     env->icache_line_size = 32;
4135     /* Allocate hardware IRQ controller */
4136     ppc6xx_irq_init(env);
4137 }
4138
4139 /* e500 core                                                                 */
4140 #define POWERPC_INSNS_e500   (PPC_INSNS_BASE | PPC_ISEL |                     \
4141                               PPC_SPE | PPC_SPEFPU |                          \
4142                               PPC_WRTEE | PPC_RFDI |                          \
4143                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4144                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4145                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4146                               PPC_BOOKE)
4147 #define POWERPC_MSRM_e500    (0x000000000606FF30ULL)
4148 #define POWERPC_MMU_e500     (POWERPC_MMU_BOOKE_FSL)
4149 #define POWERPC_EXCP_e500    (POWERPC_EXCP_BOOKE)
4150 #define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
4151 #define POWERPC_BFDM_e500    (bfd_mach_ppc_860)
4152 #define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4153                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4154                               POWERPC_FLAG_BUS_CLK)
4155 #define check_pow_e500       check_pow_hid0
4156
4157 __attribute__ (( unused ))
4158 static void init_proc_e500 (CPUPPCState *env)
4159 {
4160     /* Time base */
4161     gen_tbl(env);
4162     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4163     /* Processor identification */
4164     spr_register(env, SPR_BOOKE_PIR, "PIR",
4165                  SPR_NOACCESS, SPR_NOACCESS,
4166                  &spr_read_generic, &spr_write_pir,
4167                  0x00000000);
4168     /* XXX : not implemented */
4169     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4170                  SPR_NOACCESS, SPR_NOACCESS,
4171                  &spr_read_generic, &spr_write_generic,
4172                  0x00000000);
4173     /* Memory management */
4174 #if !defined(CONFIG_USER_ONLY)
4175     env->nb_pids = 3;
4176 #endif
4177     gen_spr_BookE_FSL(env, 0x0000005F);
4178     /* XXX : not implemented */
4179     spr_register(env, SPR_HID0, "HID0",
4180                  SPR_NOACCESS, SPR_NOACCESS,
4181                  &spr_read_generic, &spr_write_generic,
4182                  0x00000000);
4183     /* XXX : not implemented */
4184     spr_register(env, SPR_HID1, "HID1",
4185                  SPR_NOACCESS, SPR_NOACCESS,
4186                  &spr_read_generic, &spr_write_generic,
4187                  0x00000000);
4188     /* XXX : not implemented */
4189     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4190                  SPR_NOACCESS, SPR_NOACCESS,
4191                  &spr_read_generic, &spr_write_generic,
4192                  0x00000000);
4193     /* XXX : not implemented */
4194     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4195                  SPR_NOACCESS, SPR_NOACCESS,
4196                  &spr_read_generic, &spr_write_generic,
4197                  0x00000000);
4198     /* XXX : not implemented */
4199     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4200                  SPR_NOACCESS, SPR_NOACCESS,
4201                  &spr_read_generic, &spr_write_generic,
4202                  0x00000000);
4203     /* XXX : not implemented */
4204     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4205                  SPR_NOACCESS, SPR_NOACCESS,
4206                  &spr_read_generic, &spr_write_generic,
4207                  0x00000000);
4208     /* XXX : not implemented */
4209     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4210                  SPR_NOACCESS, SPR_NOACCESS,
4211                  &spr_read_generic, &spr_write_generic,
4212                  0x00000000);
4213     /* XXX : not implemented */
4214     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4215                  SPR_NOACCESS, SPR_NOACCESS,
4216                  &spr_read_generic, &spr_write_generic,
4217                  0x00000000);
4218     /* XXX : not implemented */
4219     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4220                  SPR_NOACCESS, SPR_NOACCESS,
4221                  &spr_read_generic, &spr_write_generic,
4222                  0x00000000);
4223     /* XXX : not implemented */
4224     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4225                  SPR_NOACCESS, SPR_NOACCESS,
4226                  &spr_read_generic, &spr_write_generic,
4227                  0x00000000);
4228     /* XXX : not implemented */
4229     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4230                  SPR_NOACCESS, SPR_NOACCESS,
4231                  &spr_read_generic, &spr_write_generic,
4232                  0x00000000);
4233     /* XXX : not implemented */
4234     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4235                  SPR_NOACCESS, SPR_NOACCESS,
4236                  &spr_read_generic, &spr_write_generic,
4237                  0x00000000);
4238     /* XXX : not implemented */
4239     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4240                  SPR_NOACCESS, SPR_NOACCESS,
4241                  &spr_read_generic, &spr_write_generic,
4242                  0x00000000);
4243     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4244                  SPR_NOACCESS, SPR_NOACCESS,
4245                  &spr_read_generic, &spr_write_generic,
4246                  0x00000000);
4247     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4248                  SPR_NOACCESS, SPR_NOACCESS,
4249                  &spr_read_generic, &spr_write_generic,
4250                  0x00000000);
4251 #if !defined(CONFIG_USER_ONLY)
4252     env->nb_tlb = 64;
4253     env->nb_ways = 1;
4254     env->id_tlbs = 0;
4255 #endif
4256     init_excp_e200(env);
4257     env->dcache_line_size = 32;
4258     env->icache_line_size = 32;
4259     /* XXX: TODO: allocate internal IRQ controller */
4260 }
4261
4262 /* Non-embedded PowerPC                                                      */
4263
4264 /* POWER : same as 601, without mfmsr, mfsr                                  */
4265 #if defined(TODO)
4266 #define POWERPC_INSNS_POWER  (XXX_TODO)
4267 /* POWER RSC (from RAD6000) */
4268 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4269 #endif /* TODO */
4270
4271 /* PowerPC 601                                                               */
4272 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4273                               PPC_FLOAT |                                     \
4274                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4275                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4276                               PPC_SEGMENT | PPC_EXTERN)
4277 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4278 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4279 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4280 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4281 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4282 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4283 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4284 #define check_pow_601        check_pow_none
4285
4286 static void init_proc_601 (CPUPPCState *env)
4287 {
4288     gen_spr_ne_601(env);
4289     gen_spr_601(env);
4290     /* Hardware implementation registers */
4291     /* XXX : not implemented */
4292     spr_register(env, SPR_HID0, "HID0",
4293                  SPR_NOACCESS, SPR_NOACCESS,
4294                  &spr_read_generic, &spr_write_hid0_601,
4295                  0x80010080);
4296     /* XXX : not implemented */
4297     spr_register(env, SPR_HID1, "HID1",
4298                  SPR_NOACCESS, SPR_NOACCESS,
4299                  &spr_read_generic, &spr_write_generic,
4300                  0x00000000);
4301     /* XXX : not implemented */
4302     spr_register(env, SPR_601_HID2, "HID2",
4303                  SPR_NOACCESS, SPR_NOACCESS,
4304                  &spr_read_generic, &spr_write_generic,
4305                  0x00000000);
4306     /* XXX : not implemented */
4307     spr_register(env, SPR_601_HID5, "HID5",
4308                  SPR_NOACCESS, SPR_NOACCESS,
4309                  &spr_read_generic, &spr_write_generic,
4310                  0x00000000);
4311     /* Memory management */
4312     init_excp_601(env);
4313     /* XXX: beware that dcache line size is 64
4314      *      but dcbz uses 32 bytes "sectors"
4315      * XXX: this breaks clcs instruction !
4316      */
4317     env->dcache_line_size = 32;
4318     env->icache_line_size = 64;
4319     /* Allocate hardware IRQ controller */
4320     ppc6xx_irq_init(env);
4321 }
4322
4323 /* PowerPC 601v                                                              */
4324 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4325                               PPC_FLOAT |                                     \
4326                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4327                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4328                               PPC_SEGMENT | PPC_EXTERN)
4329 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4330 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4331 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4332 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4333 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4334 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4335 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4336 #define check_pow_601v       check_pow_none
4337
4338 static void init_proc_601v (CPUPPCState *env)
4339 {
4340     init_proc_601(env);
4341     /* XXX : not implemented */
4342     spr_register(env, SPR_601_HID15, "HID15",
4343                  SPR_NOACCESS, SPR_NOACCESS,
4344                  &spr_read_generic, &spr_write_generic,
4345                  0x00000000);
4346 }
4347
4348 /* PowerPC 602                                                               */
4349 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4350                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4351                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4352                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4353                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4354                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4355                               PPC_SEGMENT | PPC_602_SPEC)
4356 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4357 /* XXX: 602 MMU is quite specific. Should add a special case */
4358 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4359 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4360 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4361 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4362 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4363                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4364 #define check_pow_602        check_pow_hid0
4365
4366 static void init_proc_602 (CPUPPCState *env)
4367 {
4368     gen_spr_ne_601(env);
4369     gen_spr_602(env);
4370     /* Time base */
4371     gen_tbl(env);
4372     /* hardware implementation registers */
4373     /* XXX : not implemented */
4374     spr_register(env, SPR_HID0, "HID0",
4375                  SPR_NOACCESS, SPR_NOACCESS,
4376                  &spr_read_generic, &spr_write_generic,
4377                  0x00000000);
4378     /* XXX : not implemented */
4379     spr_register(env, SPR_HID1, "HID1",
4380                  SPR_NOACCESS, SPR_NOACCESS,
4381                  &spr_read_generic, &spr_write_generic,
4382                  0x00000000);
4383     /* Memory management */
4384     gen_low_BATs(env);
4385     gen_6xx_7xx_soft_tlb(env, 64, 2);
4386     init_excp_602(env);
4387     env->dcache_line_size = 32;
4388     env->icache_line_size = 32;
4389     /* Allocate hardware IRQ controller */
4390     ppc6xx_irq_init(env);
4391 }
4392
4393 /* PowerPC 603                                                               */
4394 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4395                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4396                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4397                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4398                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4399                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4400                               PPC_SEGMENT | PPC_EXTERN)
4401 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4402 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4403 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4404 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4405 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4406 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4407                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4408 #define check_pow_603        check_pow_hid0
4409
4410 static void init_proc_603 (CPUPPCState *env)
4411 {
4412     gen_spr_ne_601(env);
4413     gen_spr_603(env);
4414     /* Time base */
4415     gen_tbl(env);
4416     /* hardware implementation registers */
4417     /* XXX : not implemented */
4418     spr_register(env, SPR_HID0, "HID0",
4419                  SPR_NOACCESS, SPR_NOACCESS,
4420                  &spr_read_generic, &spr_write_generic,
4421                  0x00000000);
4422     /* XXX : not implemented */
4423     spr_register(env, SPR_HID1, "HID1",
4424                  SPR_NOACCESS, SPR_NOACCESS,
4425                  &spr_read_generic, &spr_write_generic,
4426                  0x00000000);
4427     /* Memory management */
4428     gen_low_BATs(env);
4429     gen_6xx_7xx_soft_tlb(env, 64, 2);
4430     init_excp_603(env);
4431     env->dcache_line_size = 32;
4432     env->icache_line_size = 32;
4433     /* Allocate hardware IRQ controller */
4434     ppc6xx_irq_init(env);
4435 }
4436
4437 /* PowerPC 603e                                                              */
4438 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4439                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4440                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4441                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4442                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4443                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4444                               PPC_SEGMENT | PPC_EXTERN)
4445 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4446 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4447 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4448 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4449 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4450 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4451                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4452 #define check_pow_603E       check_pow_hid0
4453
4454 static void init_proc_603E (CPUPPCState *env)
4455 {
4456     gen_spr_ne_601(env);
4457     gen_spr_603(env);
4458     /* Time base */
4459     gen_tbl(env);
4460     /* hardware implementation registers */
4461     /* XXX : not implemented */
4462     spr_register(env, SPR_HID0, "HID0",
4463                  SPR_NOACCESS, SPR_NOACCESS,
4464                  &spr_read_generic, &spr_write_generic,
4465                  0x00000000);
4466     /* XXX : not implemented */
4467     spr_register(env, SPR_HID1, "HID1",
4468                  SPR_NOACCESS, SPR_NOACCESS,
4469                  &spr_read_generic, &spr_write_generic,
4470                  0x00000000);
4471     /* XXX : not implemented */
4472     spr_register(env, SPR_IABR, "IABR",
4473                  SPR_NOACCESS, SPR_NOACCESS,
4474                  &spr_read_generic, &spr_write_generic,
4475                  0x00000000);
4476     /* Memory management */
4477     gen_low_BATs(env);
4478     gen_6xx_7xx_soft_tlb(env, 64, 2);
4479     init_excp_603(env);
4480     env->dcache_line_size = 32;
4481     env->icache_line_size = 32;
4482     /* Allocate hardware IRQ controller */
4483     ppc6xx_irq_init(env);
4484 }
4485
4486 /* PowerPC 604                                                               */
4487 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4488                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4489                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4490                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4491                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4492                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4493                               PPC_SEGMENT | PPC_EXTERN)
4494 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4495 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4496 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4497 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4498 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4499 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4500                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4501 #define check_pow_604        check_pow_nocheck
4502
4503 static void init_proc_604 (CPUPPCState *env)
4504 {
4505     gen_spr_ne_601(env);
4506     gen_spr_604(env);
4507     /* Time base */
4508     gen_tbl(env);
4509     /* Hardware implementation registers */
4510     /* XXX : not implemented */
4511     spr_register(env, SPR_HID0, "HID0",
4512                  SPR_NOACCESS, SPR_NOACCESS,
4513                  &spr_read_generic, &spr_write_generic,
4514                  0x00000000);
4515     /* Memory management */
4516     gen_low_BATs(env);
4517     init_excp_604(env);
4518     env->dcache_line_size = 32;
4519     env->icache_line_size = 32;
4520     /* Allocate hardware IRQ controller */
4521     ppc6xx_irq_init(env);
4522 }
4523
4524 /* PowerPC 604E                                                              */
4525 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4526                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4527                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4528                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4529                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4530                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4531                               PPC_SEGMENT | PPC_EXTERN)
4532 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4533 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4534 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4535 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4536 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4537 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4538                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4539 #define check_pow_604E       check_pow_nocheck
4540
4541 static void init_proc_604E (CPUPPCState *env)
4542 {
4543     gen_spr_ne_601(env);
4544     gen_spr_604(env);
4545     /* XXX : not implemented */
4546     spr_register(env, SPR_MMCR1, "MMCR1",
4547                  SPR_NOACCESS, SPR_NOACCESS,
4548                  &spr_read_generic, &spr_write_generic,
4549                  0x00000000);
4550     /* XXX : not implemented */
4551     spr_register(env, SPR_PMC3, "PMC3",
4552                  SPR_NOACCESS, SPR_NOACCESS,
4553                  &spr_read_generic, &spr_write_generic,
4554                  0x00000000);
4555     /* XXX : not implemented */
4556     spr_register(env, SPR_PMC4, "PMC4",
4557                  SPR_NOACCESS, SPR_NOACCESS,
4558                  &spr_read_generic, &spr_write_generic,
4559                  0x00000000);
4560     /* Time base */
4561     gen_tbl(env);
4562     /* Hardware implementation registers */
4563     /* XXX : not implemented */
4564     spr_register(env, SPR_HID0, "HID0",
4565                  SPR_NOACCESS, SPR_NOACCESS,
4566                  &spr_read_generic, &spr_write_generic,
4567                  0x00000000);
4568     /* XXX : not implemented */
4569     spr_register(env, SPR_HID1, "HID1",
4570                  SPR_NOACCESS, SPR_NOACCESS,
4571                  &spr_read_generic, &spr_write_generic,
4572                  0x00000000);
4573     /* Memory management */
4574     gen_low_BATs(env);
4575     init_excp_604(env);
4576     env->dcache_line_size = 32;
4577     env->icache_line_size = 32;
4578     /* Allocate hardware IRQ controller */
4579     ppc6xx_irq_init(env);
4580 }
4581
4582 /* PowerPC 740                                                               */
4583 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4584                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4585                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4586                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4587                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4588                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4589                               PPC_SEGMENT | PPC_EXTERN)
4590 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4591 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4592 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4593 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4594 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4595 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4596                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4597 #define check_pow_740        check_pow_hid0
4598
4599 static void init_proc_740 (CPUPPCState *env)
4600 {
4601     gen_spr_ne_601(env);
4602     gen_spr_7xx(env);
4603     /* Time base */
4604     gen_tbl(env);
4605     /* Thermal management */
4606     gen_spr_thrm(env);
4607     /* Hardware implementation registers */
4608     /* XXX : not implemented */
4609     spr_register(env, SPR_HID0, "HID0",
4610                  SPR_NOACCESS, SPR_NOACCESS,
4611                  &spr_read_generic, &spr_write_generic,
4612                  0x00000000);
4613     /* XXX : not implemented */
4614     spr_register(env, SPR_HID1, "HID1",
4615                  SPR_NOACCESS, SPR_NOACCESS,
4616                  &spr_read_generic, &spr_write_generic,
4617                  0x00000000);
4618     /* Memory management */
4619     gen_low_BATs(env);
4620     init_excp_7x0(env);
4621     env->dcache_line_size = 32;
4622     env->icache_line_size = 32;
4623     /* Allocate hardware IRQ controller */
4624     ppc6xx_irq_init(env);
4625 }
4626
4627 /* PowerPC 750                                                               */
4628 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4629                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4630                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4631                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4632                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4633                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4634                               PPC_SEGMENT | PPC_EXTERN)
4635 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4636 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4637 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4638 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4639 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4640 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4641                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4642 #define check_pow_750        check_pow_hid0
4643
4644 static void init_proc_750 (CPUPPCState *env)
4645 {
4646     gen_spr_ne_601(env);
4647     gen_spr_7xx(env);
4648     /* XXX : not implemented */
4649     spr_register(env, SPR_L2CR, "L2CR",
4650                  SPR_NOACCESS, SPR_NOACCESS,
4651                  &spr_read_generic, &spr_write_generic,
4652                  0x00000000);
4653     /* Time base */
4654     gen_tbl(env);
4655     /* Thermal management */
4656     gen_spr_thrm(env);
4657     /* Hardware implementation registers */
4658     /* XXX : not implemented */
4659     spr_register(env, SPR_HID0, "HID0",
4660                  SPR_NOACCESS, SPR_NOACCESS,
4661                  &spr_read_generic, &spr_write_generic,
4662                  0x00000000);
4663     /* XXX : not implemented */
4664     spr_register(env, SPR_HID1, "HID1",
4665                  SPR_NOACCESS, SPR_NOACCESS,
4666                  &spr_read_generic, &spr_write_generic,
4667                  0x00000000);
4668     /* Memory management */
4669     gen_low_BATs(env);
4670     /* XXX: high BATs are also present but are known to be bugged on
4671      *      die version 1.x
4672      */
4673     init_excp_7x0(env);
4674     env->dcache_line_size = 32;
4675     env->icache_line_size = 32;
4676     /* Allocate hardware IRQ controller */
4677     ppc6xx_irq_init(env);
4678 }
4679
4680 /* PowerPC 750 CL                                                            */
4681 /* XXX: not implemented:
4682  * cache lock instructions:
4683  * dcbz_l
4684  * floating point paired instructions
4685  * psq_lux
4686  * psq_lx
4687  * psq_stux
4688  * psq_stx
4689  * ps_abs
4690  * ps_add
4691  * ps_cmpo0
4692  * ps_cmpo1
4693  * ps_cmpu0
4694  * ps_cmpu1
4695  * ps_div
4696  * ps_madd
4697  * ps_madds0
4698  * ps_madds1
4699  * ps_merge00
4700  * ps_merge01
4701  * ps_merge10
4702  * ps_merge11
4703  * ps_mr
4704  * ps_msub
4705  * ps_mul
4706  * ps_muls0
4707  * ps_muls1
4708  * ps_nabs
4709  * ps_neg
4710  * ps_nmadd
4711  * ps_nmsub
4712  * ps_res
4713  * ps_rsqrte
4714  * ps_sel
4715  * ps_sub
4716  * ps_sum0
4717  * ps_sum1
4718  */
4719 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4720                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4721                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4722                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4723                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4724                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4725                               PPC_SEGMENT | PPC_EXTERN)
4726 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4727 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4728 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4729 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4730 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4731 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4732                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4733 #define check_pow_750cl      check_pow_hid0
4734
4735 static void init_proc_750cl (CPUPPCState *env)
4736 {
4737     gen_spr_ne_601(env);
4738     gen_spr_7xx(env);
4739     /* XXX : not implemented */
4740     spr_register(env, SPR_L2CR, "L2CR",
4741                  SPR_NOACCESS, SPR_NOACCESS,
4742                  &spr_read_generic, &spr_write_generic,
4743                  0x00000000);
4744     /* Time base */
4745     gen_tbl(env);
4746     /* Thermal management */
4747     /* Those registers are fake on 750CL */
4748     spr_register(env, SPR_THRM1, "THRM1",
4749                  SPR_NOACCESS, SPR_NOACCESS,
4750                  &spr_read_generic, &spr_write_generic,
4751                  0x00000000);
4752     spr_register(env, SPR_THRM2, "THRM2",
4753                  SPR_NOACCESS, SPR_NOACCESS,
4754                  &spr_read_generic, &spr_write_generic,
4755                  0x00000000);
4756     spr_register(env, SPR_THRM3, "THRM3",
4757                  SPR_NOACCESS, SPR_NOACCESS,
4758                  &spr_read_generic, &spr_write_generic,
4759                  0x00000000);
4760     /* XXX: not implemented */
4761     spr_register(env, SPR_750_TDCL, "TDCL",
4762                  SPR_NOACCESS, SPR_NOACCESS,
4763                  &spr_read_generic, &spr_write_generic,
4764                  0x00000000);
4765     spr_register(env, SPR_750_TDCH, "TDCH",
4766                  SPR_NOACCESS, SPR_NOACCESS,
4767                  &spr_read_generic, &spr_write_generic,
4768                  0x00000000);
4769     /* DMA */
4770     /* XXX : not implemented */
4771     spr_register(env, SPR_750_WPAR, "WPAR",
4772                  SPR_NOACCESS, SPR_NOACCESS,
4773                  &spr_read_generic, &spr_write_generic,
4774                  0x00000000);
4775     spr_register(env, SPR_750_DMAL, "DMAL",
4776                  SPR_NOACCESS, SPR_NOACCESS,
4777                  &spr_read_generic, &spr_write_generic,
4778                  0x00000000);
4779     spr_register(env, SPR_750_DMAU, "DMAU",
4780                  SPR_NOACCESS, SPR_NOACCESS,
4781                  &spr_read_generic, &spr_write_generic,
4782                  0x00000000);
4783     /* Hardware implementation registers */
4784     /* XXX : not implemented */
4785     spr_register(env, SPR_HID0, "HID0",
4786                  SPR_NOACCESS, SPR_NOACCESS,
4787                  &spr_read_generic, &spr_write_generic,
4788                  0x00000000);
4789     /* XXX : not implemented */
4790     spr_register(env, SPR_HID1, "HID1",
4791                  SPR_NOACCESS, SPR_NOACCESS,
4792                  &spr_read_generic, &spr_write_generic,
4793                  0x00000000);
4794     /* XXX : not implemented */
4795     spr_register(env, SPR_750CL_HID2, "HID2",
4796                  SPR_NOACCESS, SPR_NOACCESS,
4797                  &spr_read_generic, &spr_write_generic,
4798                  0x00000000);
4799     /* XXX : not implemented */
4800     spr_register(env, SPR_750CL_HID4, "HID4",
4801                  SPR_NOACCESS, SPR_NOACCESS,
4802                  &spr_read_generic, &spr_write_generic,
4803                  0x00000000);
4804     /* Quantization registers */
4805     /* XXX : not implemented */
4806     spr_register(env, SPR_750_GQR0, "GQR0",
4807                  SPR_NOACCESS, SPR_NOACCESS,
4808                  &spr_read_generic, &spr_write_generic,
4809                  0x00000000);
4810     /* XXX : not implemented */
4811     spr_register(env, SPR_750_GQR1, "GQR1",
4812                  SPR_NOACCESS, SPR_NOACCESS,
4813                  &spr_read_generic, &spr_write_generic,
4814                  0x00000000);
4815     /* XXX : not implemented */
4816     spr_register(env, SPR_750_GQR2, "GQR2",
4817                  SPR_NOACCESS, SPR_NOACCESS,
4818                  &spr_read_generic, &spr_write_generic,
4819                  0x00000000);
4820     /* XXX : not implemented */
4821     spr_register(env, SPR_750_GQR3, "GQR3",
4822                  SPR_NOACCESS, SPR_NOACCESS,
4823                  &spr_read_generic, &spr_write_generic,
4824                  0x00000000);
4825     /* XXX : not implemented */
4826     spr_register(env, SPR_750_GQR4, "GQR4",
4827                  SPR_NOACCESS, SPR_NOACCESS,
4828                  &spr_read_generic, &spr_write_generic,
4829                  0x00000000);
4830     /* XXX : not implemented */
4831     spr_register(env, SPR_750_GQR5, "GQR5",
4832                  SPR_NOACCESS, SPR_NOACCESS,
4833                  &spr_read_generic, &spr_write_generic,
4834                  0x00000000);
4835     /* XXX : not implemented */
4836     spr_register(env, SPR_750_GQR6, "GQR6",
4837                  SPR_NOACCESS, SPR_NOACCESS,
4838                  &spr_read_generic, &spr_write_generic,
4839                  0x00000000);
4840     /* XXX : not implemented */
4841     spr_register(env, SPR_750_GQR7, "GQR7",
4842                  SPR_NOACCESS, SPR_NOACCESS,
4843                  &spr_read_generic, &spr_write_generic,
4844                  0x00000000);
4845     /* Memory management */
4846     gen_low_BATs(env);
4847     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4848     gen_high_BATs(env);
4849     init_excp_750cl(env);
4850     env->dcache_line_size = 32;
4851     env->icache_line_size = 32;
4852     /* Allocate hardware IRQ controller */
4853     ppc6xx_irq_init(env);
4854 }
4855
4856 /* PowerPC 750CX                                                             */
4857 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4858                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4859                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4860                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4861                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4862                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4863                               PPC_SEGMENT | PPC_EXTERN)
4864 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
4865 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
4866 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
4867 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
4868 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
4869 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4870                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4871 #define check_pow_750cx      check_pow_hid0
4872
4873 static void init_proc_750cx (CPUPPCState *env)
4874 {
4875     gen_spr_ne_601(env);
4876     gen_spr_7xx(env);
4877     /* XXX : not implemented */
4878     spr_register(env, SPR_L2CR, "L2CR",
4879                  SPR_NOACCESS, SPR_NOACCESS,
4880                  &spr_read_generic, &spr_write_generic,
4881                  0x00000000);
4882     /* Time base */
4883     gen_tbl(env);
4884     /* Thermal management */
4885     gen_spr_thrm(env);
4886     /* This register is not implemented but is present for compatibility */
4887     spr_register(env, SPR_SDA, "SDA",
4888                  SPR_NOACCESS, SPR_NOACCESS,
4889                  &spr_read_generic, &spr_write_generic,
4890                  0x00000000);
4891     /* Hardware implementation registers */
4892     /* XXX : not implemented */
4893     spr_register(env, SPR_HID0, "HID0",
4894                  SPR_NOACCESS, SPR_NOACCESS,
4895                  &spr_read_generic, &spr_write_generic,
4896                  0x00000000);
4897     /* XXX : not implemented */
4898     spr_register(env, SPR_HID1, "HID1",
4899                  SPR_NOACCESS, SPR_NOACCESS,
4900                  &spr_read_generic, &spr_write_generic,
4901                  0x00000000);
4902     /* Memory management */
4903     gen_low_BATs(env);
4904     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4905     gen_high_BATs(env);
4906     init_excp_750cx(env);
4907     env->dcache_line_size = 32;
4908     env->icache_line_size = 32;
4909     /* Allocate hardware IRQ controller */
4910     ppc6xx_irq_init(env);
4911 }
4912
4913 /* PowerPC 750FX                                                             */
4914 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4915                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4916                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4917                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4918                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4919                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4920                               PPC_SEGMENT  | PPC_EXTERN)
4921 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
4922 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
4923 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
4924 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
4925 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
4926 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4927                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4928 #define check_pow_750fx      check_pow_hid0
4929
4930 static void init_proc_750fx (CPUPPCState *env)
4931 {
4932     gen_spr_ne_601(env);
4933     gen_spr_7xx(env);
4934     /* XXX : not implemented */
4935     spr_register(env, SPR_L2CR, "L2CR",
4936                  SPR_NOACCESS, SPR_NOACCESS,
4937                  &spr_read_generic, &spr_write_generic,
4938                  0x00000000);
4939     /* Time base */
4940     gen_tbl(env);
4941     /* Thermal management */
4942     gen_spr_thrm(env);
4943     /* XXX : not implemented */
4944     spr_register(env, SPR_750_THRM4, "THRM4",
4945                  SPR_NOACCESS, SPR_NOACCESS,
4946                  &spr_read_generic, &spr_write_generic,
4947                  0x00000000);
4948     /* Hardware implementation registers */
4949     /* XXX : not implemented */
4950     spr_register(env, SPR_HID0, "HID0",
4951                  SPR_NOACCESS, SPR_NOACCESS,
4952                  &spr_read_generic, &spr_write_generic,
4953                  0x00000000);
4954     /* XXX : not implemented */
4955     spr_register(env, SPR_HID1, "HID1",
4956                  SPR_NOACCESS, SPR_NOACCESS,
4957                  &spr_read_generic, &spr_write_generic,
4958                  0x00000000);
4959     /* XXX : not implemented */
4960     spr_register(env, SPR_750FX_HID2, "HID2",
4961                  SPR_NOACCESS, SPR_NOACCESS,
4962                  &spr_read_generic, &spr_write_generic,
4963                  0x00000000);
4964     /* Memory management */
4965     gen_low_BATs(env);
4966     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4967     gen_high_BATs(env);
4968     init_excp_7x0(env);
4969     env->dcache_line_size = 32;
4970     env->icache_line_size = 32;
4971     /* Allocate hardware IRQ controller */
4972     ppc6xx_irq_init(env);
4973 }
4974
4975 /* PowerPC 750GX                                                             */
4976 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4977                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4978                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4979                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4980                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4981                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4982                               PPC_SEGMENT  | PPC_EXTERN)
4983 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
4984 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
4985 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
4986 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
4987 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
4988 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4989                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4990 #define check_pow_750gx      check_pow_hid0
4991
4992 static void init_proc_750gx (CPUPPCState *env)
4993 {
4994     gen_spr_ne_601(env);
4995     gen_spr_7xx(env);
4996     /* XXX : not implemented (XXX: different from 750fx) */
4997     spr_register(env, SPR_L2CR, "L2CR",
4998                  SPR_NOACCESS, SPR_NOACCESS,
4999                  &spr_read_generic, &spr_write_generic,
5000                  0x00000000);
5001     /* Time base */
5002     gen_tbl(env);
5003     /* Thermal management */
5004     gen_spr_thrm(env);
5005     /* XXX : not implemented */
5006     spr_register(env, SPR_750_THRM4, "THRM4",
5007                  SPR_NOACCESS, SPR_NOACCESS,
5008                  &spr_read_generic, &spr_write_generic,
5009                  0x00000000);
5010     /* Hardware implementation registers */
5011     /* XXX : not implemented (XXX: different from 750fx) */
5012     spr_register(env, SPR_HID0, "HID0",
5013                  SPR_NOACCESS, SPR_NOACCESS,
5014                  &spr_read_generic, &spr_write_generic,
5015                  0x00000000);
5016     /* XXX : not implemented */
5017     spr_register(env, SPR_HID1, "HID1",
5018                  SPR_NOACCESS, SPR_NOACCESS,
5019                  &spr_read_generic, &spr_write_generic,
5020                  0x00000000);
5021     /* XXX : not implemented (XXX: different from 750fx) */
5022     spr_register(env, SPR_750FX_HID2, "HID2",
5023                  SPR_NOACCESS, SPR_NOACCESS,
5024                  &spr_read_generic, &spr_write_generic,
5025                  0x00000000);
5026     /* Memory management */
5027     gen_low_BATs(env);
5028     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5029     gen_high_BATs(env);
5030     init_excp_7x0(env);
5031     env->dcache_line_size = 32;
5032     env->icache_line_size = 32;
5033     /* Allocate hardware IRQ controller */
5034     ppc6xx_irq_init(env);
5035 }
5036
5037 /* PowerPC 745                                                               */
5038 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5039                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5040                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5041                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5042                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5043                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5044                               PPC_SEGMENT | PPC_EXTERN)
5045 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5046 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5047 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5048 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5049 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5050 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5051                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5052 #define check_pow_745        check_pow_hid0
5053
5054 static void init_proc_745 (CPUPPCState *env)
5055 {
5056     gen_spr_ne_601(env);
5057     gen_spr_7xx(env);
5058     gen_spr_G2_755(env);
5059     /* Time base */
5060     gen_tbl(env);
5061     /* Thermal management */
5062     gen_spr_thrm(env);
5063     /* Hardware implementation registers */
5064     /* XXX : not implemented */
5065     spr_register(env, SPR_HID0, "HID0",
5066                  SPR_NOACCESS, SPR_NOACCESS,
5067                  &spr_read_generic, &spr_write_generic,
5068                  0x00000000);
5069     /* XXX : not implemented */
5070     spr_register(env, SPR_HID1, "HID1",
5071                  SPR_NOACCESS, SPR_NOACCESS,
5072                  &spr_read_generic, &spr_write_generic,
5073                  0x00000000);
5074     /* XXX : not implemented */
5075     spr_register(env, SPR_HID2, "HID2",
5076                  SPR_NOACCESS, SPR_NOACCESS,
5077                  &spr_read_generic, &spr_write_generic,
5078                  0x00000000);
5079     /* Memory management */
5080     gen_low_BATs(env);
5081     gen_high_BATs(env);
5082     gen_6xx_7xx_soft_tlb(env, 64, 2);
5083     init_excp_7x5(env);
5084     env->dcache_line_size = 32;
5085     env->icache_line_size = 32;
5086     /* Allocate hardware IRQ controller */
5087     ppc6xx_irq_init(env);
5088 }
5089
5090 /* PowerPC 755                                                               */
5091 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5092                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5093                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5094                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5095                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5096                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5097                               PPC_SEGMENT | PPC_EXTERN)
5098 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5099 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5100 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5101 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5102 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5103 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5104                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5105 #define check_pow_755        check_pow_hid0
5106
5107 static void init_proc_755 (CPUPPCState *env)
5108 {
5109     gen_spr_ne_601(env);
5110     gen_spr_7xx(env);
5111     gen_spr_G2_755(env);
5112     /* Time base */
5113     gen_tbl(env);
5114     /* L2 cache control */
5115     /* XXX : not implemented */
5116     spr_register(env, SPR_L2CR, "L2CR",
5117                  SPR_NOACCESS, SPR_NOACCESS,
5118                  &spr_read_generic, &spr_write_generic,
5119                  0x00000000);
5120     /* XXX : not implemented */
5121     spr_register(env, SPR_L2PMCR, "L2PMCR",
5122                  SPR_NOACCESS, SPR_NOACCESS,
5123                  &spr_read_generic, &spr_write_generic,
5124                  0x00000000);
5125     /* Thermal management */
5126     gen_spr_thrm(env);
5127     /* Hardware implementation registers */
5128     /* XXX : not implemented */
5129     spr_register(env, SPR_HID0, "HID0",
5130                  SPR_NOACCESS, SPR_NOACCESS,
5131                  &spr_read_generic, &spr_write_generic,
5132                  0x00000000);
5133     /* XXX : not implemented */
5134     spr_register(env, SPR_HID1, "HID1",
5135                  SPR_NOACCESS, SPR_NOACCESS,
5136                  &spr_read_generic, &spr_write_generic,
5137                  0x00000000);
5138     /* XXX : not implemented */
5139     spr_register(env, SPR_HID2, "HID2",
5140                  SPR_NOACCESS, SPR_NOACCESS,
5141                  &spr_read_generic, &spr_write_generic,
5142                  0x00000000);
5143     /* Memory management */
5144     gen_low_BATs(env);
5145     gen_high_BATs(env);
5146     gen_6xx_7xx_soft_tlb(env, 64, 2);
5147     init_excp_7x5(env);
5148     env->dcache_line_size = 32;
5149     env->icache_line_size = 32;
5150     /* Allocate hardware IRQ controller */
5151     ppc6xx_irq_init(env);
5152 }
5153
5154 /* PowerPC 7400 (aka G4)                                                     */
5155 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5156                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5157                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5158                               PPC_FLOAT_STFIWX |                              \
5159                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5160                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5161                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5162                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5163                               PPC_MEM_TLBIA |                                 \
5164                               PPC_SEGMENT | PPC_EXTERN |                      \
5165                               PPC_ALTIVEC)
5166 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5167 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5168 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5169 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5170 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5171 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5172                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5173                               POWERPC_FLAG_BUS_CLK)
5174 #define check_pow_7400       check_pow_hid0_74xx
5175
5176 static void init_proc_7400 (CPUPPCState *env)
5177 {
5178     gen_spr_ne_601(env);
5179     gen_spr_7xx(env);
5180     /* Time base */
5181     gen_tbl(env);
5182     /* 74xx specific SPR */
5183     gen_spr_74xx(env);
5184     /* XXX : not implemented */
5185     spr_register(env, SPR_UBAMR, "UBAMR",
5186                  &spr_read_ureg, SPR_NOACCESS,
5187                  &spr_read_ureg, SPR_NOACCESS,
5188                  0x00000000);
5189     /* XXX: this seems not implemented on all revisions. */
5190     /* XXX : not implemented */
5191     spr_register(env, SPR_MSSCR1, "MSSCR1",
5192                  SPR_NOACCESS, SPR_NOACCESS,
5193                  &spr_read_generic, &spr_write_generic,
5194                  0x00000000);
5195     /* Thermal management */
5196     gen_spr_thrm(env);
5197     /* Memory management */
5198     gen_low_BATs(env);
5199     init_excp_7400(env);
5200     env->dcache_line_size = 32;
5201     env->icache_line_size = 32;
5202     /* Allocate hardware IRQ controller */
5203     ppc6xx_irq_init(env);
5204 }
5205
5206 /* PowerPC 7410 (aka G4)                                                     */
5207 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5208                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5209                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5210                               PPC_FLOAT_STFIWX |                              \
5211                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5212                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5213                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5214                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5215                               PPC_MEM_TLBIA |                                 \
5216                               PPC_SEGMENT | PPC_EXTERN |                      \
5217                               PPC_ALTIVEC)
5218 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5219 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5220 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5221 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5222 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5223 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5224                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5225                               POWERPC_FLAG_BUS_CLK)
5226 #define check_pow_7410       check_pow_hid0_74xx
5227
5228 static void init_proc_7410 (CPUPPCState *env)
5229 {
5230     gen_spr_ne_601(env);
5231     gen_spr_7xx(env);
5232     /* Time base */
5233     gen_tbl(env);
5234     /* 74xx specific SPR */
5235     gen_spr_74xx(env);
5236     /* XXX : not implemented */
5237     spr_register(env, SPR_UBAMR, "UBAMR",
5238                  &spr_read_ureg, SPR_NOACCESS,
5239                  &spr_read_ureg, SPR_NOACCESS,
5240                  0x00000000);
5241     /* Thermal management */
5242     gen_spr_thrm(env);
5243     /* L2PMCR */
5244     /* XXX : not implemented */
5245     spr_register(env, SPR_L2PMCR, "L2PMCR",
5246                  SPR_NOACCESS, SPR_NOACCESS,
5247                  &spr_read_generic, &spr_write_generic,
5248                  0x00000000);
5249     /* LDSTDB */
5250     /* XXX : not implemented */
5251     spr_register(env, SPR_LDSTDB, "LDSTDB",
5252                  SPR_NOACCESS, SPR_NOACCESS,
5253                  &spr_read_generic, &spr_write_generic,
5254                  0x00000000);
5255     /* Memory management */
5256     gen_low_BATs(env);
5257     init_excp_7400(env);
5258     env->dcache_line_size = 32;
5259     env->icache_line_size = 32;
5260     /* Allocate hardware IRQ controller */
5261     ppc6xx_irq_init(env);
5262 }
5263
5264 /* PowerPC 7440 (aka G4)                                                     */
5265 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5266                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5267                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5268                               PPC_FLOAT_STFIWX |                              \
5269                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5270                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5271                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5272                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5273                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5274                               PPC_SEGMENT | PPC_EXTERN |                      \
5275                               PPC_ALTIVEC)
5276 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5277 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5278 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5279 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5280 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5281 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5282                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5283                               POWERPC_FLAG_BUS_CLK)
5284 #define check_pow_7440       check_pow_hid0_74xx
5285
5286 __attribute__ (( unused ))
5287 static void init_proc_7440 (CPUPPCState *env)
5288 {
5289     gen_spr_ne_601(env);
5290     gen_spr_7xx(env);
5291     /* Time base */
5292     gen_tbl(env);
5293     /* 74xx specific SPR */
5294     gen_spr_74xx(env);
5295     /* XXX : not implemented */
5296     spr_register(env, SPR_UBAMR, "UBAMR",
5297                  &spr_read_ureg, SPR_NOACCESS,
5298                  &spr_read_ureg, SPR_NOACCESS,
5299                  0x00000000);
5300     /* LDSTCR */
5301     /* XXX : not implemented */
5302     spr_register(env, SPR_LDSTCR, "LDSTCR",
5303                  SPR_NOACCESS, SPR_NOACCESS,
5304                  &spr_read_generic, &spr_write_generic,
5305                  0x00000000);
5306     /* ICTRL */
5307     /* XXX : not implemented */
5308     spr_register(env, SPR_ICTRL, "ICTRL",
5309                  SPR_NOACCESS, SPR_NOACCESS,
5310                  &spr_read_generic, &spr_write_generic,
5311                  0x00000000);
5312     /* MSSSR0 */
5313     /* XXX : not implemented */
5314     spr_register(env, SPR_MSSSR0, "MSSSR0",
5315                  SPR_NOACCESS, SPR_NOACCESS,
5316                  &spr_read_generic, &spr_write_generic,
5317                  0x00000000);
5318     /* PMC */
5319     /* XXX : not implemented */
5320     spr_register(env, SPR_PMC5, "PMC5",
5321                  SPR_NOACCESS, SPR_NOACCESS,
5322                  &spr_read_generic, &spr_write_generic,
5323                  0x00000000);
5324     /* XXX : not implemented */
5325     spr_register(env, SPR_UPMC5, "UPMC5",
5326                  &spr_read_ureg, SPR_NOACCESS,
5327                  &spr_read_ureg, SPR_NOACCESS,
5328                  0x00000000);
5329     /* XXX : not implemented */
5330     spr_register(env, SPR_PMC6, "PMC6",
5331                  SPR_NOACCESS, SPR_NOACCESS,
5332                  &spr_read_generic, &spr_write_generic,
5333                  0x00000000);
5334     /* XXX : not implemented */
5335     spr_register(env, SPR_UPMC6, "UPMC6",
5336                  &spr_read_ureg, SPR_NOACCESS,
5337                  &spr_read_ureg, SPR_NOACCESS,
5338                  0x00000000);
5339     /* Memory management */
5340     gen_low_BATs(env);
5341     gen_74xx_soft_tlb(env, 128, 2);
5342     init_excp_7450(env);
5343     env->dcache_line_size = 32;
5344     env->icache_line_size = 32;
5345     /* Allocate hardware IRQ controller */
5346     ppc6xx_irq_init(env);
5347 }
5348
5349 /* PowerPC 7450 (aka G4)                                                     */
5350 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5351                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5352                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5353                               PPC_FLOAT_STFIWX |                              \
5354                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5355                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5356                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5357                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5358                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5359                               PPC_SEGMENT | PPC_EXTERN |                      \
5360                               PPC_ALTIVEC)
5361 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5362 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5363 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5364 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5365 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5366 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5367                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5368                               POWERPC_FLAG_BUS_CLK)
5369 #define check_pow_7450       check_pow_hid0_74xx
5370
5371 __attribute__ (( unused ))
5372 static void init_proc_7450 (CPUPPCState *env)
5373 {
5374     gen_spr_ne_601(env);
5375     gen_spr_7xx(env);
5376     /* Time base */
5377     gen_tbl(env);
5378     /* 74xx specific SPR */
5379     gen_spr_74xx(env);
5380     /* Level 3 cache control */
5381     gen_l3_ctrl(env);
5382     /* L3ITCR1 */
5383     /* XXX : not implemented */
5384     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5385                  SPR_NOACCESS, SPR_NOACCESS,
5386                  &spr_read_generic, &spr_write_generic,
5387                  0x00000000);
5388     /* L3ITCR2 */
5389     /* XXX : not implemented */
5390     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5391                  SPR_NOACCESS, SPR_NOACCESS,
5392                  &spr_read_generic, &spr_write_generic,
5393                  0x00000000);
5394     /* L3ITCR3 */
5395     /* XXX : not implemented */
5396     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5397                  SPR_NOACCESS, SPR_NOACCESS,
5398                  &spr_read_generic, &spr_write_generic,
5399                  0x00000000);
5400     /* L3OHCR */
5401     /* XXX : not implemented */
5402     spr_register(env, SPR_L3OHCR, "L3OHCR",
5403                  SPR_NOACCESS, SPR_NOACCESS,
5404                  &spr_read_generic, &spr_write_generic,
5405                  0x00000000);
5406     /* XXX : not implemented */
5407     spr_register(env, SPR_UBAMR, "UBAMR",
5408                  &spr_read_ureg, SPR_NOACCESS,
5409                  &spr_read_ureg, SPR_NOACCESS,
5410                  0x00000000);
5411     /* LDSTCR */
5412     /* XXX : not implemented */
5413     spr_register(env, SPR_LDSTCR, "LDSTCR",
5414                  SPR_NOACCESS, SPR_NOACCESS,
5415                  &spr_read_generic, &spr_write_generic,
5416                  0x00000000);
5417     /* ICTRL */
5418     /* XXX : not implemented */
5419     spr_register(env, SPR_ICTRL, "ICTRL",
5420                  SPR_NOACCESS, SPR_NOACCESS,
5421                  &spr_read_generic, &spr_write_generic,
5422                  0x00000000);
5423     /* MSSSR0 */
5424     /* XXX : not implemented */
5425     spr_register(env, SPR_MSSSR0, "MSSSR0",
5426                  SPR_NOACCESS, SPR_NOACCESS,
5427                  &spr_read_generic, &spr_write_generic,
5428                  0x00000000);
5429     /* PMC */
5430     /* XXX : not implemented */
5431     spr_register(env, SPR_PMC5, "PMC5",
5432                  SPR_NOACCESS, SPR_NOACCESS,
5433                  &spr_read_generic, &spr_write_generic,
5434                  0x00000000);
5435     /* XXX : not implemented */
5436     spr_register(env, SPR_UPMC5, "UPMC5",
5437                  &spr_read_ureg, SPR_NOACCESS,
5438                  &spr_read_ureg, SPR_NOACCESS,
5439                  0x00000000);
5440     /* XXX : not implemented */
5441     spr_register(env, SPR_PMC6, "PMC6",
5442                  SPR_NOACCESS, SPR_NOACCESS,
5443                  &spr_read_generic, &spr_write_generic,
5444                  0x00000000);
5445     /* XXX : not implemented */
5446     spr_register(env, SPR_UPMC6, "UPMC6",
5447                  &spr_read_ureg, SPR_NOACCESS,
5448                  &spr_read_ureg, SPR_NOACCESS,
5449                  0x00000000);
5450     /* Memory management */
5451     gen_low_BATs(env);
5452     gen_74xx_soft_tlb(env, 128, 2);
5453     init_excp_7450(env);
5454     env->dcache_line_size = 32;
5455     env->icache_line_size = 32;
5456     /* Allocate hardware IRQ controller */
5457     ppc6xx_irq_init(env);
5458 }
5459
5460 /* PowerPC 7445 (aka G4)                                                     */
5461 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5462                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5463                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5464                               PPC_FLOAT_STFIWX |                              \
5465                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5466                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5467                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5468                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5469                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5470                               PPC_SEGMENT | PPC_EXTERN |                      \
5471                               PPC_ALTIVEC)
5472 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5473 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5474 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5475 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5476 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5477 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5478                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5479                               POWERPC_FLAG_BUS_CLK)
5480 #define check_pow_7445       check_pow_hid0_74xx
5481
5482 __attribute__ (( unused ))
5483 static void init_proc_7445 (CPUPPCState *env)
5484 {
5485     gen_spr_ne_601(env);
5486     gen_spr_7xx(env);
5487     /* Time base */
5488     gen_tbl(env);
5489     /* 74xx specific SPR */
5490     gen_spr_74xx(env);
5491     /* LDSTCR */
5492     /* XXX : not implemented */
5493     spr_register(env, SPR_LDSTCR, "LDSTCR",
5494                  SPR_NOACCESS, SPR_NOACCESS,
5495                  &spr_read_generic, &spr_write_generic,
5496                  0x00000000);
5497     /* ICTRL */
5498     /* XXX : not implemented */
5499     spr_register(env, SPR_ICTRL, "ICTRL",
5500                  SPR_NOACCESS, SPR_NOACCESS,
5501                  &spr_read_generic, &spr_write_generic,
5502                  0x00000000);
5503     /* MSSSR0 */
5504     /* XXX : not implemented */
5505     spr_register(env, SPR_MSSSR0, "MSSSR0",
5506                  SPR_NOACCESS, SPR_NOACCESS,
5507                  &spr_read_generic, &spr_write_generic,
5508                  0x00000000);
5509     /* PMC */
5510     /* XXX : not implemented */
5511     spr_register(env, SPR_PMC5, "PMC5",
5512                  SPR_NOACCESS, SPR_NOACCESS,
5513                  &spr_read_generic, &spr_write_generic,
5514                  0x00000000);
5515     /* XXX : not implemented */
5516     spr_register(env, SPR_UPMC5, "UPMC5",
5517                  &spr_read_ureg, SPR_NOACCESS,
5518                  &spr_read_ureg, SPR_NOACCESS,
5519                  0x00000000);
5520     /* XXX : not implemented */
5521     spr_register(env, SPR_PMC6, "PMC6",
5522                  SPR_NOACCESS, SPR_NOACCESS,
5523                  &spr_read_generic, &spr_write_generic,
5524                  0x00000000);
5525     /* XXX : not implemented */
5526     spr_register(env, SPR_UPMC6, "UPMC6",
5527                  &spr_read_ureg, SPR_NOACCESS,
5528                  &spr_read_ureg, SPR_NOACCESS,
5529                  0x00000000);
5530     /* SPRGs */
5531     spr_register(env, SPR_SPRG4, "SPRG4",
5532                  SPR_NOACCESS, SPR_NOACCESS,
5533                  &spr_read_generic, &spr_write_generic,
5534                  0x00000000);
5535     spr_register(env, SPR_USPRG4, "USPRG4",
5536                  &spr_read_ureg, SPR_NOACCESS,
5537                  &spr_read_ureg, SPR_NOACCESS,
5538                  0x00000000);
5539     spr_register(env, SPR_SPRG5, "SPRG5",
5540                  SPR_NOACCESS, SPR_NOACCESS,
5541                  &spr_read_generic, &spr_write_generic,
5542                  0x00000000);
5543     spr_register(env, SPR_USPRG5, "USPRG5",
5544                  &spr_read_ureg, SPR_NOACCESS,
5545                  &spr_read_ureg, SPR_NOACCESS,
5546                  0x00000000);
5547     spr_register(env, SPR_SPRG6, "SPRG6",
5548                  SPR_NOACCESS, SPR_NOACCESS,
5549                  &spr_read_generic, &spr_write_generic,
5550                  0x00000000);
5551     spr_register(env, SPR_USPRG6, "USPRG6",
5552                  &spr_read_ureg, SPR_NOACCESS,
5553                  &spr_read_ureg, SPR_NOACCESS,
5554                  0x00000000);
5555     spr_register(env, SPR_SPRG7, "SPRG7",
5556                  SPR_NOACCESS, SPR_NOACCESS,
5557                  &spr_read_generic, &spr_write_generic,
5558                  0x00000000);
5559     spr_register(env, SPR_USPRG7, "USPRG7",
5560                  &spr_read_ureg, SPR_NOACCESS,
5561                  &spr_read_ureg, SPR_NOACCESS,
5562                  0x00000000);
5563     /* Memory management */
5564     gen_low_BATs(env);
5565     gen_high_BATs(env);
5566     gen_74xx_soft_tlb(env, 128, 2);
5567     init_excp_7450(env);
5568     env->dcache_line_size = 32;
5569     env->icache_line_size = 32;
5570     /* Allocate hardware IRQ controller */
5571     ppc6xx_irq_init(env);
5572 }
5573
5574 /* PowerPC 7455 (aka G4)                                                     */
5575 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5576                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5577                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5578                               PPC_FLOAT_STFIWX |                              \
5579                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5580                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5581                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5582                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5583                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5584                               PPC_SEGMENT | PPC_EXTERN |                      \
5585                               PPC_ALTIVEC)
5586 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5587 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5588 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5589 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5590 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5591 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5592                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5593                               POWERPC_FLAG_BUS_CLK)
5594 #define check_pow_7455       check_pow_hid0_74xx
5595
5596 __attribute__ (( unused ))
5597 static void init_proc_7455 (CPUPPCState *env)
5598 {
5599     gen_spr_ne_601(env);
5600     gen_spr_7xx(env);
5601     /* Time base */
5602     gen_tbl(env);
5603     /* 74xx specific SPR */
5604     gen_spr_74xx(env);
5605     /* Level 3 cache control */
5606     gen_l3_ctrl(env);
5607     /* LDSTCR */
5608     /* XXX : not implemented */
5609     spr_register(env, SPR_LDSTCR, "LDSTCR",
5610                  SPR_NOACCESS, SPR_NOACCESS,
5611                  &spr_read_generic, &spr_write_generic,
5612                  0x00000000);
5613     /* ICTRL */
5614     /* XXX : not implemented */
5615     spr_register(env, SPR_ICTRL, "ICTRL",
5616                  SPR_NOACCESS, SPR_NOACCESS,
5617                  &spr_read_generic, &spr_write_generic,
5618                  0x00000000);
5619     /* MSSSR0 */
5620     /* XXX : not implemented */
5621     spr_register(env, SPR_MSSSR0, "MSSSR0",
5622                  SPR_NOACCESS, SPR_NOACCESS,
5623                  &spr_read_generic, &spr_write_generic,
5624                  0x00000000);
5625     /* PMC */
5626     /* XXX : not implemented */
5627     spr_register(env, SPR_PMC5, "PMC5",
5628                  SPR_NOACCESS, SPR_NOACCESS,
5629                  &spr_read_generic, &spr_write_generic,
5630                  0x00000000);
5631     /* XXX : not implemented */
5632     spr_register(env, SPR_UPMC5, "UPMC5",
5633                  &spr_read_ureg, SPR_NOACCESS,
5634                  &spr_read_ureg, SPR_NOACCESS,
5635                  0x00000000);
5636     /* XXX : not implemented */
5637     spr_register(env, SPR_PMC6, "PMC6",
5638                  SPR_NOACCESS, SPR_NOACCESS,
5639                  &spr_read_generic, &spr_write_generic,
5640                  0x00000000);
5641     /* XXX : not implemented */
5642     spr_register(env, SPR_UPMC6, "UPMC6",
5643                  &spr_read_ureg, SPR_NOACCESS,
5644                  &spr_read_ureg, SPR_NOACCESS,
5645                  0x00000000);
5646     /* SPRGs */
5647     spr_register(env, SPR_SPRG4, "SPRG4",
5648                  SPR_NOACCESS, SPR_NOACCESS,
5649                  &spr_read_generic, &spr_write_generic,
5650                  0x00000000);
5651     spr_register(env, SPR_USPRG4, "USPRG4",
5652                  &spr_read_ureg, SPR_NOACCESS,
5653                  &spr_read_ureg, SPR_NOACCESS,
5654                  0x00000000);
5655     spr_register(env, SPR_SPRG5, "SPRG5",
5656                  SPR_NOACCESS, SPR_NOACCESS,
5657                  &spr_read_generic, &spr_write_generic,
5658                  0x00000000);
5659     spr_register(env, SPR_USPRG5, "USPRG5",
5660                  &spr_read_ureg, SPR_NOACCESS,
5661                  &spr_read_ureg, SPR_NOACCESS,
5662                  0x00000000);
5663     spr_register(env, SPR_SPRG6, "SPRG6",
5664                  SPR_NOACCESS, SPR_NOACCESS,
5665                  &spr_read_generic, &spr_write_generic,
5666                  0x00000000);
5667     spr_register(env, SPR_USPRG6, "USPRG6",
5668                  &spr_read_ureg, SPR_NOACCESS,
5669                  &spr_read_ureg, SPR_NOACCESS,
5670                  0x00000000);
5671     spr_register(env, SPR_SPRG7, "SPRG7",
5672                  SPR_NOACCESS, SPR_NOACCESS,
5673                  &spr_read_generic, &spr_write_generic,
5674                  0x00000000);
5675     spr_register(env, SPR_USPRG7, "USPRG7",
5676                  &spr_read_ureg, SPR_NOACCESS,
5677                  &spr_read_ureg, SPR_NOACCESS,
5678                  0x00000000);
5679     /* Memory management */
5680     gen_low_BATs(env);
5681     gen_high_BATs(env);
5682     gen_74xx_soft_tlb(env, 128, 2);
5683     init_excp_7450(env);
5684     env->dcache_line_size = 32;
5685     env->icache_line_size = 32;
5686     /* Allocate hardware IRQ controller */
5687     ppc6xx_irq_init(env);
5688 }
5689
5690 /* PowerPC 7457 (aka G4)                                                     */
5691 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5692                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5693                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5694                               PPC_FLOAT_STFIWX |                              \
5695                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5696                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5697                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5698                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5699                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5700                               PPC_SEGMENT | PPC_EXTERN |                      \
5701                               PPC_ALTIVEC)
5702 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5703 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5704 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5705 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5706 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5707 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5708                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5709                               POWERPC_FLAG_BUS_CLK)
5710 #define check_pow_7457       check_pow_hid0_74xx
5711
5712 __attribute__ (( unused ))
5713 static void init_proc_7457 (CPUPPCState *env)
5714 {
5715     gen_spr_ne_601(env);
5716     gen_spr_7xx(env);
5717     /* Time base */
5718     gen_tbl(env);
5719     /* 74xx specific SPR */
5720     gen_spr_74xx(env);
5721     /* Level 3 cache control */
5722     gen_l3_ctrl(env);
5723     /* L3ITCR1 */
5724     /* XXX : not implemented */
5725     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5726                  SPR_NOACCESS, SPR_NOACCESS,
5727                  &spr_read_generic, &spr_write_generic,
5728                  0x00000000);
5729     /* L3ITCR2 */
5730     /* XXX : not implemented */
5731     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5732                  SPR_NOACCESS, SPR_NOACCESS,
5733                  &spr_read_generic, &spr_write_generic,
5734                  0x00000000);
5735     /* L3ITCR3 */
5736     /* XXX : not implemented */
5737     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5738                  SPR_NOACCESS, SPR_NOACCESS,
5739                  &spr_read_generic, &spr_write_generic,
5740                  0x00000000);
5741     /* L3OHCR */
5742     /* XXX : not implemented */
5743     spr_register(env, SPR_L3OHCR, "L3OHCR",
5744                  SPR_NOACCESS, SPR_NOACCESS,
5745                  &spr_read_generic, &spr_write_generic,
5746                  0x00000000);
5747     /* LDSTCR */
5748     /* XXX : not implemented */
5749     spr_register(env, SPR_LDSTCR, "LDSTCR",
5750                  SPR_NOACCESS, SPR_NOACCESS,
5751                  &spr_read_generic, &spr_write_generic,
5752                  0x00000000);
5753     /* ICTRL */
5754     /* XXX : not implemented */
5755     spr_register(env, SPR_ICTRL, "ICTRL",
5756                  SPR_NOACCESS, SPR_NOACCESS,
5757                  &spr_read_generic, &spr_write_generic,
5758                  0x00000000);
5759     /* MSSSR0 */
5760     /* XXX : not implemented */
5761     spr_register(env, SPR_MSSSR0, "MSSSR0",
5762                  SPR_NOACCESS, SPR_NOACCESS,
5763                  &spr_read_generic, &spr_write_generic,
5764                  0x00000000);
5765     /* PMC */
5766     /* XXX : not implemented */
5767     spr_register(env, SPR_PMC5, "PMC5",
5768                  SPR_NOACCESS, SPR_NOACCESS,
5769                  &spr_read_generic, &spr_write_generic,
5770                  0x00000000);
5771     /* XXX : not implemented */
5772     spr_register(env, SPR_UPMC5, "UPMC5",
5773                  &spr_read_ureg, SPR_NOACCESS,
5774                  &spr_read_ureg, SPR_NOACCESS,
5775                  0x00000000);
5776     /* XXX : not implemented */
5777     spr_register(env, SPR_PMC6, "PMC6",
5778                  SPR_NOACCESS, SPR_NOACCESS,
5779                  &spr_read_generic, &spr_write_generic,
5780                  0x00000000);
5781     /* XXX : not implemented */
5782     spr_register(env, SPR_UPMC6, "UPMC6",
5783                  &spr_read_ureg, SPR_NOACCESS,
5784                  &spr_read_ureg, SPR_NOACCESS,
5785                  0x00000000);
5786     /* SPRGs */
5787     spr_register(env, SPR_SPRG4, "SPRG4",
5788                  SPR_NOACCESS, SPR_NOACCESS,
5789                  &spr_read_generic, &spr_write_generic,
5790                  0x00000000);
5791     spr_register(env, SPR_USPRG4, "USPRG4",
5792                  &spr_read_ureg, SPR_NOACCESS,
5793                  &spr_read_ureg, SPR_NOACCESS,
5794                  0x00000000);
5795     spr_register(env, SPR_SPRG5, "SPRG5",
5796                  SPR_NOACCESS, SPR_NOACCESS,
5797                  &spr_read_generic, &spr_write_generic,
5798                  0x00000000);
5799     spr_register(env, SPR_USPRG5, "USPRG5",
5800                  &spr_read_ureg, SPR_NOACCESS,
5801                  &spr_read_ureg, SPR_NOACCESS,
5802                  0x00000000);
5803     spr_register(env, SPR_SPRG6, "SPRG6",
5804                  SPR_NOACCESS, SPR_NOACCESS,
5805                  &spr_read_generic, &spr_write_generic,
5806                  0x00000000);
5807     spr_register(env, SPR_USPRG6, "USPRG6",
5808                  &spr_read_ureg, SPR_NOACCESS,
5809                  &spr_read_ureg, SPR_NOACCESS,
5810                  0x00000000);
5811     spr_register(env, SPR_SPRG7, "SPRG7",
5812                  SPR_NOACCESS, SPR_NOACCESS,
5813                  &spr_read_generic, &spr_write_generic,
5814                  0x00000000);
5815     spr_register(env, SPR_USPRG7, "USPRG7",
5816                  &spr_read_ureg, SPR_NOACCESS,
5817                  &spr_read_ureg, SPR_NOACCESS,
5818                  0x00000000);
5819     /* Memory management */
5820     gen_low_BATs(env);
5821     gen_high_BATs(env);
5822     gen_74xx_soft_tlb(env, 128, 2);
5823     init_excp_7450(env);
5824     env->dcache_line_size = 32;
5825     env->icache_line_size = 32;
5826     /* Allocate hardware IRQ controller */
5827     ppc6xx_irq_init(env);
5828 }
5829
5830 #if defined (TARGET_PPC64)
5831 /* PowerPC 970                                                               */
5832 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5833                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5834                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5835                               PPC_FLOAT_STFIWX |                              \
5836                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5837                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5838                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5839                               PPC_64B | PPC_ALTIVEC |                         \
5840                               PPC_SEGMENT_64B | PPC_SLBI)
5841 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5842 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5843 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5844 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5845 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5846 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5847                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5848                               POWERPC_FLAG_BUS_CLK)
5849
5850 #if defined(CONFIG_USER_ONLY)
5851 #define POWERPC970_HID5_INIT 0x00000080
5852 #else
5853 #define POWERPC970_HID5_INIT 0x00000000
5854 #endif
5855
5856 static int check_pow_970 (CPUPPCState *env)
5857 {
5858     if (env->spr[SPR_HID0] & 0x00600000)
5859         return 1;
5860
5861     return 0;
5862 }
5863
5864 static void init_proc_970 (CPUPPCState *env)
5865 {
5866     gen_spr_ne_601(env);
5867     gen_spr_7xx(env);
5868     /* Time base */
5869     gen_tbl(env);
5870     /* Hardware implementation registers */
5871     /* XXX : not implemented */
5872     spr_register(env, SPR_HID0, "HID0",
5873                  SPR_NOACCESS, SPR_NOACCESS,
5874                  &spr_read_generic, &spr_write_clear,
5875                  0x60000000);
5876     /* XXX : not implemented */
5877     spr_register(env, SPR_HID1, "HID1",
5878                  SPR_NOACCESS, SPR_NOACCESS,
5879                  &spr_read_generic, &spr_write_generic,
5880                  0x00000000);
5881     /* XXX : not implemented */
5882     spr_register(env, SPR_750FX_HID2, "HID2",
5883                  SPR_NOACCESS, SPR_NOACCESS,
5884                  &spr_read_generic, &spr_write_generic,
5885                  0x00000000);
5886     /* XXX : not implemented */
5887     spr_register(env, SPR_970_HID5, "HID5",
5888                  SPR_NOACCESS, SPR_NOACCESS,
5889                  &spr_read_generic, &spr_write_generic,
5890                  POWERPC970_HID5_INIT);
5891     /* XXX : not implemented */
5892     spr_register(env, SPR_L2CR, "L2CR",
5893                  SPR_NOACCESS, SPR_NOACCESS,
5894                  &spr_read_generic, &spr_write_generic,
5895                  0x00000000);
5896     /* Memory management */
5897     /* XXX: not correct */
5898     gen_low_BATs(env);
5899     /* XXX : not implemented */
5900     spr_register(env, SPR_MMUCFG, "MMUCFG",
5901                  SPR_NOACCESS, SPR_NOACCESS,
5902                  &spr_read_generic, SPR_NOACCESS,
5903                  0x00000000); /* TOFIX */
5904     /* XXX : not implemented */
5905     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5906                  SPR_NOACCESS, SPR_NOACCESS,
5907                  &spr_read_generic, &spr_write_generic,
5908                  0x00000000); /* TOFIX */
5909     spr_register(env, SPR_HIOR, "SPR_HIOR",
5910                  SPR_NOACCESS, SPR_NOACCESS,
5911                  &spr_read_generic, &spr_write_generic,
5912                  0xFFF00000); /* XXX: This is a hack */
5913 #if !defined(CONFIG_USER_ONLY)
5914     env->slb_nr = 32;
5915 #endif
5916     init_excp_970(env);
5917     env->dcache_line_size = 128;
5918     env->icache_line_size = 128;
5919     /* Allocate hardware IRQ controller */
5920     ppc970_irq_init(env);
5921 }
5922
5923 /* PowerPC 970FX (aka G5)                                                    */
5924 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5925                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5926                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5927                               PPC_FLOAT_STFIWX |                              \
5928                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5929                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5930                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5931                               PPC_64B | PPC_ALTIVEC |                         \
5932                               PPC_SEGMENT_64B | PPC_SLBI)
5933 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
5934 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
5935 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
5936 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
5937 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
5938 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5939                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5940                               POWERPC_FLAG_BUS_CLK)
5941
5942 static int check_pow_970FX (CPUPPCState *env)
5943 {
5944     if (env->spr[SPR_HID0] & 0x00600000)
5945         return 1;
5946
5947     return 0;
5948 }
5949
5950 static void init_proc_970FX (CPUPPCState *env)
5951 {
5952     gen_spr_ne_601(env);
5953     gen_spr_7xx(env);
5954     /* Time base */
5955     gen_tbl(env);
5956     /* Hardware implementation registers */
5957     /* XXX : not implemented */
5958     spr_register(env, SPR_HID0, "HID0",
5959                  SPR_NOACCESS, SPR_NOACCESS,
5960                  &spr_read_generic, &spr_write_clear,
5961                  0x60000000);
5962     /* XXX : not implemented */
5963     spr_register(env, SPR_HID1, "HID1",
5964                  SPR_NOACCESS, SPR_NOACCESS,
5965                  &spr_read_generic, &spr_write_generic,
5966                  0x00000000);
5967     /* XXX : not implemented */
5968     spr_register(env, SPR_750FX_HID2, "HID2",
5969                  SPR_NOACCESS, SPR_NOACCESS,
5970                  &spr_read_generic, &spr_write_generic,
5971                  0x00000000);
5972     /* XXX : not implemented */
5973     spr_register(env, SPR_970_HID5, "HID5",
5974                  SPR_NOACCESS, SPR_NOACCESS,
5975                  &spr_read_generic, &spr_write_generic,
5976                  POWERPC970_HID5_INIT);
5977     /* XXX : not implemented */
5978     spr_register(env, SPR_L2CR, "L2CR",
5979                  SPR_NOACCESS, SPR_NOACCESS,
5980                  &spr_read_generic, &spr_write_generic,
5981                  0x00000000);
5982     /* Memory management */
5983     /* XXX: not correct */
5984     gen_low_BATs(env);
5985     /* XXX : not implemented */
5986     spr_register(env, SPR_MMUCFG, "MMUCFG",
5987                  SPR_NOACCESS, SPR_NOACCESS,
5988                  &spr_read_generic, SPR_NOACCESS,
5989                  0x00000000); /* TOFIX */
5990     /* XXX : not implemented */
5991     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5992                  SPR_NOACCESS, SPR_NOACCESS,
5993                  &spr_read_generic, &spr_write_generic,
5994                  0x00000000); /* TOFIX */
5995     spr_register(env, SPR_HIOR, "SPR_HIOR",
5996                  SPR_NOACCESS, SPR_NOACCESS,
5997                  &spr_read_generic, &spr_write_generic,
5998                  0xFFF00000); /* XXX: This is a hack */
5999 #if !defined(CONFIG_USER_ONLY)
6000     env->slb_nr = 32;
6001 #endif
6002     init_excp_970(env);
6003     env->dcache_line_size = 128;
6004     env->icache_line_size = 128;
6005     /* Allocate hardware IRQ controller */
6006     ppc970_irq_init(env);
6007 }
6008
6009 /* PowerPC 970 GX                                                            */
6010 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6011                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6012                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6013                               PPC_FLOAT_STFIWX |                              \
6014                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6015                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6016                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6017                               PPC_64B | PPC_ALTIVEC |                         \
6018                               PPC_SEGMENT_64B | PPC_SLBI)
6019 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6020 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6021 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6022 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6023 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6024 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6025                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6026                               POWERPC_FLAG_BUS_CLK)
6027
6028 static int check_pow_970GX (CPUPPCState *env)
6029 {
6030     if (env->spr[SPR_HID0] & 0x00600000)
6031         return 1;
6032
6033     return 0;
6034 }
6035
6036 static void init_proc_970GX (CPUPPCState *env)
6037 {
6038     gen_spr_ne_601(env);
6039     gen_spr_7xx(env);
6040     /* Time base */
6041     gen_tbl(env);
6042     /* Hardware implementation registers */
6043     /* XXX : not implemented */
6044     spr_register(env, SPR_HID0, "HID0",
6045                  SPR_NOACCESS, SPR_NOACCESS,
6046                  &spr_read_generic, &spr_write_clear,
6047                  0x60000000);
6048     /* XXX : not implemented */
6049     spr_register(env, SPR_HID1, "HID1",
6050                  SPR_NOACCESS, SPR_NOACCESS,
6051                  &spr_read_generic, &spr_write_generic,
6052                  0x00000000);
6053     /* XXX : not implemented */
6054     spr_register(env, SPR_750FX_HID2, "HID2",
6055                  SPR_NOACCESS, SPR_NOACCESS,
6056                  &spr_read_generic, &spr_write_generic,
6057                  0x00000000);
6058     /* XXX : not implemented */
6059     spr_register(env, SPR_970_HID5, "HID5",
6060                  SPR_NOACCESS, SPR_NOACCESS,
6061                  &spr_read_generic, &spr_write_generic,
6062                  POWERPC970_HID5_INIT);
6063     /* XXX : not implemented */
6064     spr_register(env, SPR_L2CR, "L2CR",
6065                  SPR_NOACCESS, SPR_NOACCESS,
6066                  &spr_read_generic, &spr_write_generic,
6067                  0x00000000);
6068     /* Memory management */
6069     /* XXX: not correct */
6070     gen_low_BATs(env);
6071     /* XXX : not implemented */
6072     spr_register(env, SPR_MMUCFG, "MMUCFG",
6073                  SPR_NOACCESS, SPR_NOACCESS,
6074                  &spr_read_generic, SPR_NOACCESS,
6075                  0x00000000); /* TOFIX */
6076     /* XXX : not implemented */
6077     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6078                  SPR_NOACCESS, SPR_NOACCESS,
6079                  &spr_read_generic, &spr_write_generic,
6080                  0x00000000); /* TOFIX */
6081     spr_register(env, SPR_HIOR, "SPR_HIOR",
6082                  SPR_NOACCESS, SPR_NOACCESS,
6083                  &spr_read_generic, &spr_write_generic,
6084                  0xFFF00000); /* XXX: This is a hack */
6085 #if !defined(CONFIG_USER_ONLY)
6086     env->slb_nr = 32;
6087 #endif
6088     init_excp_970(env);
6089     env->dcache_line_size = 128;
6090     env->icache_line_size = 128;
6091     /* Allocate hardware IRQ controller */
6092     ppc970_irq_init(env);
6093 }
6094
6095 /* PowerPC 970 MP                                                            */
6096 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6097                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6098                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6099                               PPC_FLOAT_STFIWX |                              \
6100                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6101                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6102                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6103                               PPC_64B | PPC_ALTIVEC |                         \
6104                               PPC_SEGMENT_64B | PPC_SLBI)
6105 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6106 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6107 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6108 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6109 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6110 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6111                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6112                               POWERPC_FLAG_BUS_CLK)
6113
6114 static int check_pow_970MP (CPUPPCState *env)
6115 {
6116     if (env->spr[SPR_HID0] & 0x01C00000)
6117         return 1;
6118
6119     return 0;
6120 }
6121
6122 static void init_proc_970MP (CPUPPCState *env)
6123 {
6124     gen_spr_ne_601(env);
6125     gen_spr_7xx(env);
6126     /* Time base */
6127     gen_tbl(env);
6128     /* Hardware implementation registers */
6129     /* XXX : not implemented */
6130     spr_register(env, SPR_HID0, "HID0",
6131                  SPR_NOACCESS, SPR_NOACCESS,
6132                  &spr_read_generic, &spr_write_clear,
6133                  0x60000000);
6134     /* XXX : not implemented */
6135     spr_register(env, SPR_HID1, "HID1",
6136                  SPR_NOACCESS, SPR_NOACCESS,
6137                  &spr_read_generic, &spr_write_generic,
6138                  0x00000000);
6139     /* XXX : not implemented */
6140     spr_register(env, SPR_750FX_HID2, "HID2",
6141                  SPR_NOACCESS, SPR_NOACCESS,
6142                  &spr_read_generic, &spr_write_generic,
6143                  0x00000000);
6144     /* XXX : not implemented */
6145     spr_register(env, SPR_970_HID5, "HID5",
6146                  SPR_NOACCESS, SPR_NOACCESS,
6147                  &spr_read_generic, &spr_write_generic,
6148                  POWERPC970_HID5_INIT);
6149     /* XXX : not implemented */
6150     spr_register(env, SPR_L2CR, "L2CR",
6151                  SPR_NOACCESS, SPR_NOACCESS,
6152                  &spr_read_generic, &spr_write_generic,
6153                  0x00000000);
6154     /* Memory management */
6155     /* XXX: not correct */
6156     gen_low_BATs(env);
6157     /* XXX : not implemented */
6158     spr_register(env, SPR_MMUCFG, "MMUCFG",
6159                  SPR_NOACCESS, SPR_NOACCESS,
6160                  &spr_read_generic, SPR_NOACCESS,
6161                  0x00000000); /* TOFIX */
6162     /* XXX : not implemented */
6163     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6164                  SPR_NOACCESS, SPR_NOACCESS,
6165                  &spr_read_generic, &spr_write_generic,
6166                  0x00000000); /* TOFIX */
6167     spr_register(env, SPR_HIOR, "SPR_HIOR",
6168                  SPR_NOACCESS, SPR_NOACCESS,
6169                  &spr_read_generic, &spr_write_generic,
6170                  0xFFF00000); /* XXX: This is a hack */
6171 #if !defined(CONFIG_USER_ONLY)
6172     env->slb_nr = 32;
6173 #endif
6174     init_excp_970(env);
6175     env->dcache_line_size = 128;
6176     env->icache_line_size = 128;
6177     /* Allocate hardware IRQ controller */
6178     ppc970_irq_init(env);
6179 }
6180
6181 /* PowerPC 620                                                               */
6182 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6183                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6184                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6185                               PPC_FLOAT_STFIWX |                              \
6186                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6187                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6188                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6189                               PPC_SEGMENT | PPC_EXTERN |                      \
6190                               PPC_64B | PPC_SLBI)
6191 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6192 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6193 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6194 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6195 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6196 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6197                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6198 #define check_pow_620        check_pow_nocheck /* Check this */
6199
6200 __attribute__ (( unused ))
6201 static void init_proc_620 (CPUPPCState *env)
6202 {
6203     gen_spr_ne_601(env);
6204     gen_spr_620(env);
6205     /* Time base */
6206     gen_tbl(env);
6207     /* Hardware implementation registers */
6208     /* XXX : not implemented */
6209     spr_register(env, SPR_HID0, "HID0",
6210                  SPR_NOACCESS, SPR_NOACCESS,
6211                  &spr_read_generic, &spr_write_generic,
6212                  0x00000000);
6213     /* Memory management */
6214     gen_low_BATs(env);
6215     init_excp_620(env);
6216     env->dcache_line_size = 64;
6217     env->icache_line_size = 64;
6218     /* Allocate hardware IRQ controller */
6219     ppc6xx_irq_init(env);
6220 }
6221 #endif /* defined (TARGET_PPC64) */
6222
6223 /* Default 32 bits PowerPC target will be 604 */
6224 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6225 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6226 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6227 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6228 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6229 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6230 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6231 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6232 #define check_pow_PPC32       check_pow_604
6233 #define init_proc_PPC32       init_proc_604
6234
6235 /* Default 64 bits PowerPC target will be 970 FX */
6236 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6237 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6238 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6239 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6240 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6241 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6242 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6243 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6244 #define check_pow_PPC64       check_pow_970FX
6245 #define init_proc_PPC64       init_proc_970FX
6246
6247 /* Default PowerPC target will be PowerPC 32 */
6248 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6249 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6250 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6251 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6252 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6253 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6254 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6255 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6256 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6257 #define check_pow_DEFAULT     check_pow_PPC64
6258 #define init_proc_DEFAULT     init_proc_PPC64
6259 #else
6260 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6261 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6262 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6263 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6264 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6265 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6266 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6267 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6268 #define check_pow_DEFAULT     check_pow_PPC32
6269 #define init_proc_DEFAULT     init_proc_PPC32
6270 #endif
6271
6272 /*****************************************************************************/
6273 /* PVR definitions for most known PowerPC                                    */
6274 enum {
6275     /* PowerPC 401 family */
6276     /* Generic PowerPC 401 */
6277 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6278     /* PowerPC 401 cores */
6279     CPU_POWERPC_401A1              = 0x00210000,
6280     CPU_POWERPC_401B2              = 0x00220000,
6281 #if 0
6282     CPU_POWERPC_401B3              = xxx,
6283 #endif
6284     CPU_POWERPC_401C2              = 0x00230000,
6285     CPU_POWERPC_401D2              = 0x00240000,
6286     CPU_POWERPC_401E2              = 0x00250000,
6287     CPU_POWERPC_401F2              = 0x00260000,
6288     CPU_POWERPC_401G2              = 0x00270000,
6289     /* PowerPC 401 microcontrolers */
6290 #if 0
6291     CPU_POWERPC_401GF              = xxx,
6292 #endif
6293 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6294     /* IBM Processor for Network Resources */
6295     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6296 #if 0
6297     CPU_POWERPC_XIPCHIP            = xxx,
6298 #endif
6299     /* PowerPC 403 family */
6300     /* Generic PowerPC 403 */
6301 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6302     /* PowerPC 403 microcontrollers */
6303     CPU_POWERPC_403GA              = 0x00200011,
6304     CPU_POWERPC_403GB              = 0x00200100,
6305     CPU_POWERPC_403GC              = 0x00200200,
6306     CPU_POWERPC_403GCX             = 0x00201400,
6307 #if 0
6308     CPU_POWERPC_403GP              = xxx,
6309 #endif
6310     /* PowerPC 405 family */
6311     /* Generic PowerPC 405 */
6312 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6313     /* PowerPC 405 cores */
6314 #if 0
6315     CPU_POWERPC_405A3              = xxx,
6316 #endif
6317 #if 0
6318     CPU_POWERPC_405A4              = xxx,
6319 #endif
6320 #if 0
6321     CPU_POWERPC_405B3              = xxx,
6322 #endif
6323 #if 0
6324     CPU_POWERPC_405B4              = xxx,
6325 #endif
6326 #if 0
6327     CPU_POWERPC_405C3              = xxx,
6328 #endif
6329 #if 0
6330     CPU_POWERPC_405C4              = xxx,
6331 #endif
6332     CPU_POWERPC_405D2              = 0x20010000,
6333 #if 0
6334     CPU_POWERPC_405D3              = xxx,
6335 #endif
6336     CPU_POWERPC_405D4              = 0x41810000,
6337 #if 0
6338     CPU_POWERPC_405D5              = xxx,
6339 #endif
6340 #if 0
6341     CPU_POWERPC_405E4              = xxx,
6342 #endif
6343 #if 0
6344     CPU_POWERPC_405F4              = xxx,
6345 #endif
6346 #if 0
6347     CPU_POWERPC_405F5              = xxx,
6348 #endif
6349 #if 0
6350     CPU_POWERPC_405F6              = xxx,
6351 #endif
6352     /* PowerPC 405 microcontrolers */
6353     /* XXX: missing 0x200108a0 */
6354 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6355     CPU_POWERPC_405CRa             = 0x40110041,
6356     CPU_POWERPC_405CRb             = 0x401100C5,
6357     CPU_POWERPC_405CRc             = 0x40110145,
6358     CPU_POWERPC_405EP              = 0x51210950,
6359 #if 0
6360     CPU_POWERPC_405EXr             = xxx,
6361 #endif
6362     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6363 #if 0
6364     CPU_POWERPC_405FX              = xxx,
6365 #endif
6366 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6367     CPU_POWERPC_405GPa             = 0x40110000,
6368     CPU_POWERPC_405GPb             = 0x40110040,
6369     CPU_POWERPC_405GPc             = 0x40110082,
6370     CPU_POWERPC_405GPd             = 0x401100C4,
6371 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6372     CPU_POWERPC_405GPR             = 0x50910951,
6373 #if 0
6374     CPU_POWERPC_405H               = xxx,
6375 #endif
6376 #if 0
6377     CPU_POWERPC_405L               = xxx,
6378 #endif
6379     CPU_POWERPC_405LP              = 0x41F10000,
6380 #if 0
6381     CPU_POWERPC_405PM              = xxx,
6382 #endif
6383 #if 0
6384     CPU_POWERPC_405PS              = xxx,
6385 #endif
6386 #if 0
6387     CPU_POWERPC_405S               = xxx,
6388 #endif
6389     /* IBM network processors */
6390     CPU_POWERPC_NPE405H            = 0x414100C0,
6391     CPU_POWERPC_NPE405H2           = 0x41410140,
6392     CPU_POWERPC_NPE405L            = 0x416100C0,
6393     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6394 #if 0
6395     CPU_POWERPC_NPCxx1             = xxx,
6396 #endif
6397 #if 0
6398     CPU_POWERPC_NPR161             = xxx,
6399 #endif
6400 #if 0
6401     CPU_POWERPC_LC77700            = xxx,
6402 #endif
6403     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6404 #if 0
6405     CPU_POWERPC_STB01000           = xxx,
6406 #endif
6407 #if 0
6408     CPU_POWERPC_STB01010           = xxx,
6409 #endif
6410 #if 0
6411     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6412 #endif
6413     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6414 #if 0
6415     CPU_POWERPC_STB043             = xxx,
6416 #endif
6417 #if 0
6418     CPU_POWERPC_STB045             = xxx,
6419 #endif
6420     CPU_POWERPC_STB04              = 0x41810000,
6421     CPU_POWERPC_STB25              = 0x51510950,
6422 #if 0
6423     CPU_POWERPC_STB130             = xxx,
6424 #endif
6425     /* Xilinx cores */
6426     CPU_POWERPC_X2VP4              = 0x20010820,
6427 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6428     CPU_POWERPC_X2VP20             = 0x20010860,
6429 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6430 #if 0
6431     CPU_POWERPC_ZL10310            = xxx,
6432 #endif
6433 #if 0
6434     CPU_POWERPC_ZL10311            = xxx,
6435 #endif
6436 #if 0
6437     CPU_POWERPC_ZL10320            = xxx,
6438 #endif
6439 #if 0
6440     CPU_POWERPC_ZL10321            = xxx,
6441 #endif
6442     /* PowerPC 440 family */
6443     /* Generic PowerPC 440 */
6444 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6445     /* PowerPC 440 cores */
6446 #if 0
6447     CPU_POWERPC_440A4              = xxx,
6448 #endif
6449 #if 0
6450     CPU_POWERPC_440A5              = xxx,
6451 #endif
6452 #if 0
6453     CPU_POWERPC_440B4              = xxx,
6454 #endif
6455 #if 0
6456     CPU_POWERPC_440F5              = xxx,
6457 #endif
6458 #if 0
6459     CPU_POWERPC_440G5              = xxx,
6460 #endif
6461 #if 0
6462     CPU_POWERPC_440H4              = xxx,
6463 #endif
6464 #if 0
6465     CPU_POWERPC_440H6              = xxx,
6466 #endif
6467     /* PowerPC 440 microcontrolers */
6468 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6469     CPU_POWERPC_440EPa             = 0x42221850,
6470     CPU_POWERPC_440EPb             = 0x422218D3,
6471 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6472     CPU_POWERPC_440GPb             = 0x40120440,
6473     CPU_POWERPC_440GPc             = 0x40120481,
6474 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6475 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6476     CPU_POWERPC_440GRX             = 0x200008D0,
6477 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6478 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6479     CPU_POWERPC_440GXa             = 0x51B21850,
6480     CPU_POWERPC_440GXb             = 0x51B21851,
6481     CPU_POWERPC_440GXc             = 0x51B21892,
6482     CPU_POWERPC_440GXf             = 0x51B21894,
6483 #if 0
6484     CPU_POWERPC_440S               = xxx,
6485 #endif
6486     CPU_POWERPC_440SP              = 0x53221850,
6487     CPU_POWERPC_440SP2             = 0x53221891,
6488     CPU_POWERPC_440SPE             = 0x53421890,
6489     /* PowerPC 460 family */
6490 #if 0
6491     /* Generic PowerPC 464 */
6492 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6493 #endif
6494     /* PowerPC 464 microcontrolers */
6495 #if 0
6496     CPU_POWERPC_464H90             = xxx,
6497 #endif
6498 #if 0
6499     CPU_POWERPC_464H90FP           = xxx,
6500 #endif
6501     /* Freescale embedded PowerPC cores */
6502     /* PowerPC MPC 5xx cores (aka RCPU) */
6503     CPU_POWERPC_MPC5xx             = 0x00020020,
6504 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6505 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6506 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6507 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6508 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6509 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6510 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6511 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6512 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6513 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6514 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6515 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6516 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6517     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6518     CPU_POWERPC_MPC8xx             = 0x00500000,
6519 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6520 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6521 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6522 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6523 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6524 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6525 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6526 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6527 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6528 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6529 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6530 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6531 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6532 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6533 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6534     /* G2 cores (aka PowerQUICC-II) */
6535     CPU_POWERPC_G2                 = 0x00810011,
6536     CPU_POWERPC_G2H4               = 0x80811010,
6537     CPU_POWERPC_G2gp               = 0x80821010,
6538     CPU_POWERPC_G2ls               = 0x90810010,
6539     CPU_POWERPC_MPC603             = 0x00810100,
6540     CPU_POWERPC_G2_HIP3            = 0x00810101,
6541     CPU_POWERPC_G2_HIP4            = 0x80811014,
6542     /*   G2_LE core (aka PowerQUICC-II) */
6543     CPU_POWERPC_G2LE               = 0x80820010,
6544     CPU_POWERPC_G2LEgp             = 0x80822010,
6545     CPU_POWERPC_G2LEls             = 0xA0822010,
6546     CPU_POWERPC_G2LEgp1            = 0x80822011,
6547     CPU_POWERPC_G2LEgp3            = 0x80822013,
6548     /* MPC52xx microcontrollers  */
6549     /* XXX: MPC 5121 ? */
6550 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6551 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6552 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6553 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6554 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6555 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6556 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6557 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6558     /* MPC82xx microcontrollers */
6559 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6560 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6561 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6562 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6563 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6564 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6565 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6566 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6567 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6568 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6569 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6570 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6571 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6572 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6573 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6574 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6575 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6576 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6577 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6578 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6579 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6580 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6581 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6582 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6583 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6584 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6585 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6586 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6587 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6588     /* e200 family */
6589     /* e200 cores */
6590 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6591 #if 0
6592     CPU_POWERPC_e200z0             = xxx,
6593 #endif
6594 #if 0
6595     CPU_POWERPC_e200z1             = xxx,
6596 #endif
6597 #if 0 /* ? */
6598     CPU_POWERPC_e200z3             = 0x81120000,
6599 #endif
6600     CPU_POWERPC_e200z5             = 0x81000000,
6601     CPU_POWERPC_e200z6             = 0x81120000,
6602     /* MPC55xx microcontrollers */
6603 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6604 #if 0
6605 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6606 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6607 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6608 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6609 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6610 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6611 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6612 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6613 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6614 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6615 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6616 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6617 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6618 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6619 #endif
6620 #if 0
6621 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6622 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6623 #endif
6624 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6625 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6626 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6627 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6628 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6629 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6630     /* e300 family */
6631     /* e300 cores */
6632 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6633     CPU_POWERPC_e300c1             = 0x00830010,
6634     CPU_POWERPC_e300c2             = 0x00840010,
6635     CPU_POWERPC_e300c3             = 0x00850010,
6636     CPU_POWERPC_e300c4             = 0x00860010,
6637     /* MPC83xx microcontrollers */
6638 #define CPU_POWERPC_MPC8313          CPU_POWERPC_e300c3
6639 #define CPU_POWERPC_MPC8313E         CPU_POWERPC_e300c3
6640 #define CPU_POWERPC_MPC8314          CPU_POWERPC_e300c3
6641 #define CPU_POWERPC_MPC8314E         CPU_POWERPC_e300c3
6642 #define CPU_POWERPC_MPC8315          CPU_POWERPC_e300c3
6643 #define CPU_POWERPC_MPC8315E         CPU_POWERPC_e300c3
6644 #define CPU_POWERPC_MPC8321          CPU_POWERPC_e300c2
6645 #define CPU_POWERPC_MPC8321E         CPU_POWERPC_e300c2
6646 #define CPU_POWERPC_MPC8323          CPU_POWERPC_e300c2
6647 #define CPU_POWERPC_MPC8323E         CPU_POWERPC_e300c2
6648 #define CPU_POWERPC_MPC8343A         CPU_POWERPC_e300c1
6649 #define CPU_POWERPC_MPC8343EA        CPU_POWERPC_e300c1
6650 #define CPU_POWERPC_MPC8347A         CPU_POWERPC_e300c1
6651 #define CPU_POWERPC_MPC8347AT        CPU_POWERPC_e300c1
6652 #define CPU_POWERPC_MPC8347AP        CPU_POWERPC_e300c1
6653 #define CPU_POWERPC_MPC8347EA        CPU_POWERPC_e300c1
6654 #define CPU_POWERPC_MPC8347EAT       CPU_POWERPC_e300c1
6655 #define CPU_POWERPC_MPC8347EAP       CPU_POWERPC_e300c1
6656 #define CPU_POWERPC_MPC8349          CPU_POWERPC_e300c1
6657 #define CPU_POWERPC_MPC8349A         CPU_POWERPC_e300c1
6658 #define CPU_POWERPC_MPC8349E         CPU_POWERPC_e300c1
6659 #define CPU_POWERPC_MPC8349EA        CPU_POWERPC_e300c1
6660 #define CPU_POWERPC_MPC8358E         CPU_POWERPC_e300c1
6661 #define CPU_POWERPC_MPC8360E         CPU_POWERPC_e300c1
6662 #define CPU_POWERPC_MPC8377          CPU_POWERPC_e300c4
6663 #define CPU_POWERPC_MPC8377E         CPU_POWERPC_e300c4
6664 #define CPU_POWERPC_MPC8378          CPU_POWERPC_e300c4
6665 #define CPU_POWERPC_MPC8378E         CPU_POWERPC_e300c4
6666 #define CPU_POWERPC_MPC8379          CPU_POWERPC_e300c4
6667 #define CPU_POWERPC_MPC8379E         CPU_POWERPC_e300c4
6668     /* e500 family */
6669     /* e500 cores  */
6670 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6671 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6672     CPU_POWERPC_e500_v10           = 0x80200010,
6673     CPU_POWERPC_e500_v20           = 0x80200020,
6674     CPU_POWERPC_e500v2_v10         = 0x80210010,
6675     CPU_POWERPC_e500v2_v11         = 0x80210011,
6676     CPU_POWERPC_e500v2_v20         = 0x80210020,
6677     CPU_POWERPC_e500v2_v21         = 0x80210021,
6678     CPU_POWERPC_e500v2_v22         = 0x80210022,
6679     CPU_POWERPC_e500v2_v30         = 0x80210030,
6680     /* MPC85xx microcontrollers */
6681 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6682 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6683 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6684 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6685 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6686 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6687 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6688 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500_v10
6689 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500_v20
6690 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500_v20
6691 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6692 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500_v20
6693 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500_v20
6694 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6695 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500_v20
6696 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500_v20
6697 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6698 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6699 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6700 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6701 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6702 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6703 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6704 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6705 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6706 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6707 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6708 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6709 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6710 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6711 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6712 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6713 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6714 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6715 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6716 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6717 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6718 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6719 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6720 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6721 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6722 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6723 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6724 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6725 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6726 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6727 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6728 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6729 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6730 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6731 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6732 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6733 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6734 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6735 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6736 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6737 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6738 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6739 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6740 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6741 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6742 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6743 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6744 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6745 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6746 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6747 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6748 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6749 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6750 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6751     /* e600 family */
6752     /* e600 cores */
6753     CPU_POWERPC_e600               = 0x80040010,
6754     /* MPC86xx microcontrollers */
6755 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6756 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6757 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6758     /* PowerPC 6xx cores */
6759 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6760     CPU_POWERPC_601_v0             = 0x00010001,
6761     CPU_POWERPC_601_v1             = 0x00010001,
6762 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6763     CPU_POWERPC_601_v2             = 0x00010002,
6764     CPU_POWERPC_602                = 0x00050100,
6765     CPU_POWERPC_603                = 0x00030100,
6766 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6767     CPU_POWERPC_603E_v11           = 0x00060101,
6768     CPU_POWERPC_603E_v12           = 0x00060102,
6769     CPU_POWERPC_603E_v13           = 0x00060103,
6770     CPU_POWERPC_603E_v14           = 0x00060104,
6771     CPU_POWERPC_603E_v22           = 0x00060202,
6772     CPU_POWERPC_603E_v3            = 0x00060300,
6773     CPU_POWERPC_603E_v4            = 0x00060400,
6774     CPU_POWERPC_603E_v41           = 0x00060401,
6775     CPU_POWERPC_603E7t             = 0x00071201,
6776     CPU_POWERPC_603E7v             = 0x00070100,
6777     CPU_POWERPC_603E7v1            = 0x00070101,
6778     CPU_POWERPC_603E7v2            = 0x00070201,
6779     CPU_POWERPC_603E7              = 0x00070200,
6780     CPU_POWERPC_603P               = 0x00070000,
6781 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6782     /* XXX: missing 0x00040303 (604) */
6783     CPU_POWERPC_604                = 0x00040103,
6784 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6785     /* XXX: missing 0x00091203 */
6786     /* XXX: missing 0x00092110 */
6787     /* XXX: missing 0x00092120 */
6788     CPU_POWERPC_604E_v10           = 0x00090100,
6789     CPU_POWERPC_604E_v22           = 0x00090202,
6790     CPU_POWERPC_604E_v24           = 0x00090204,
6791     /* XXX: missing 0x000a0100 */
6792     /* XXX: missing 0x00093102 */
6793     CPU_POWERPC_604R               = 0x000a0101,
6794 #if 0
6795     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
6796 #endif
6797     /* PowerPC 740/750 cores (aka G3) */
6798     /* XXX: missing 0x00084202 */
6799 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
6800     CPU_POWERPC_7x0_v10            = 0x00080100,
6801     CPU_POWERPC_7x0_v20            = 0x00080200,
6802     CPU_POWERPC_7x0_v21            = 0x00080201,
6803     CPU_POWERPC_7x0_v22            = 0x00080202,
6804     CPU_POWERPC_7x0_v30            = 0x00080300,
6805     CPU_POWERPC_7x0_v31            = 0x00080301,
6806     CPU_POWERPC_740E               = 0x00080100,
6807     CPU_POWERPC_750E               = 0x00080200,
6808     CPU_POWERPC_7x0P               = 0x10080000,
6809     /* XXX: missing 0x00087010 (CL ?) */
6810 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
6811     CPU_POWERPC_750CL_v10          = 0x00087200,
6812     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
6813 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
6814     CPU_POWERPC_750CX_v10          = 0x00082100,
6815     CPU_POWERPC_750CX_v20          = 0x00082200,
6816     CPU_POWERPC_750CX_v21          = 0x00082201,
6817     CPU_POWERPC_750CX_v22          = 0x00082202,
6818 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
6819     CPU_POWERPC_750CXE_v21         = 0x00082211,
6820     CPU_POWERPC_750CXE_v22         = 0x00082212,
6821     CPU_POWERPC_750CXE_v23         = 0x00082213,
6822     CPU_POWERPC_750CXE_v24         = 0x00082214,
6823     CPU_POWERPC_750CXE_v24b        = 0x00083214,
6824     CPU_POWERPC_750CXE_v30         = 0x00082310,
6825     CPU_POWERPC_750CXE_v31         = 0x00082311,
6826     CPU_POWERPC_750CXE_v31b        = 0x00083311,
6827     CPU_POWERPC_750CXR             = 0x00083410,
6828     CPU_POWERPC_750FL              = 0x70000203,
6829 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
6830     CPU_POWERPC_750FX_v10          = 0x70000100,
6831     CPU_POWERPC_750FX_v20          = 0x70000200,
6832     CPU_POWERPC_750FX_v21          = 0x70000201,
6833     CPU_POWERPC_750FX_v22          = 0x70000202,
6834     CPU_POWERPC_750FX_v23          = 0x70000203,
6835     CPU_POWERPC_750GL              = 0x70020102,
6836 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
6837     CPU_POWERPC_750GX_v10          = 0x70020100,
6838     CPU_POWERPC_750GX_v11          = 0x70020101,
6839     CPU_POWERPC_750GX_v12          = 0x70020102,
6840 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
6841     CPU_POWERPC_750L_v20           = 0x00088200,
6842     CPU_POWERPC_750L_v21           = 0x00088201,
6843     CPU_POWERPC_750L_v22           = 0x00088202,
6844     CPU_POWERPC_750L_v30           = 0x00088300,
6845     CPU_POWERPC_750L_v32           = 0x00088302,
6846     /* PowerPC 745/755 cores */
6847 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
6848     CPU_POWERPC_7x5_v10            = 0x00083100,
6849     CPU_POWERPC_7x5_v11            = 0x00083101,
6850     CPU_POWERPC_7x5_v20            = 0x00083200,
6851     CPU_POWERPC_7x5_v21            = 0x00083201,
6852     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
6853     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
6854     CPU_POWERPC_7x5_v24            = 0x00083204,
6855     CPU_POWERPC_7x5_v25            = 0x00083205,
6856     CPU_POWERPC_7x5_v26            = 0x00083206,
6857     CPU_POWERPC_7x5_v27            = 0x00083207,
6858     CPU_POWERPC_7x5_v28            = 0x00083208,
6859 #if 0
6860     CPU_POWERPC_7x5P               = xxx,
6861 #endif
6862     /* PowerPC 74xx cores (aka G4) */
6863     /* XXX: missing 0x000C1101 */
6864 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
6865     CPU_POWERPC_7400_v10           = 0x000C0100,
6866     CPU_POWERPC_7400_v11           = 0x000C0101,
6867     CPU_POWERPC_7400_v20           = 0x000C0200,
6868     CPU_POWERPC_7400_v21           = 0x000C0201,
6869     CPU_POWERPC_7400_v22           = 0x000C0202,
6870     CPU_POWERPC_7400_v26           = 0x000C0206,
6871     CPU_POWERPC_7400_v27           = 0x000C0207,
6872     CPU_POWERPC_7400_v28           = 0x000C0208,
6873     CPU_POWERPC_7400_v29           = 0x000C0209,
6874 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
6875     CPU_POWERPC_7410_v10           = 0x800C1100,
6876     CPU_POWERPC_7410_v11           = 0x800C1101,
6877     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
6878     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
6879     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
6880 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
6881     CPU_POWERPC_7448_v10           = 0x80040100,
6882     CPU_POWERPC_7448_v11           = 0x80040101,
6883     CPU_POWERPC_7448_v20           = 0x80040200,
6884     CPU_POWERPC_7448_v21           = 0x80040201,
6885 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
6886     CPU_POWERPC_7450_v10           = 0x80000100,
6887     CPU_POWERPC_7450_v11           = 0x80000101,
6888     CPU_POWERPC_7450_v12           = 0x80000102,
6889     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
6890     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
6891 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
6892     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
6893     /* XXX: this entry might be a bug in some documentation */
6894     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
6895 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
6896     CPU_POWERPC_74x5_v10           = 0x80010100,
6897     /* XXX: missing 0x80010200 */
6898     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
6899     CPU_POWERPC_74x5_v32           = 0x80010302,
6900     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
6901     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
6902 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
6903     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
6904     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
6905     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
6906 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
6907     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
6908     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
6909     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
6910     /* 64 bits PowerPC */
6911 #if defined(TARGET_PPC64)
6912     CPU_POWERPC_620                = 0x00140000,
6913     CPU_POWERPC_630                = 0x00400000,
6914     CPU_POWERPC_631                = 0x00410104,
6915     CPU_POWERPC_POWER4             = 0x00350000,
6916     CPU_POWERPC_POWER4P            = 0x00380000,
6917      /* XXX: missing 0x003A0201 */
6918     CPU_POWERPC_POWER5             = 0x003A0203,
6919 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
6920     CPU_POWERPC_POWER5P            = 0x003B0000,
6921 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
6922     CPU_POWERPC_POWER6             = 0x003E0000,
6923     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
6924     CPU_POWERPC_POWER6A            = 0x0F000002,
6925     CPU_POWERPC_970                = 0x00390202,
6926 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
6927     CPU_POWERPC_970FX_v10          = 0x00391100,
6928     CPU_POWERPC_970FX_v20          = 0x003C0200,
6929     CPU_POWERPC_970FX_v21          = 0x003C0201,
6930     CPU_POWERPC_970FX_v30          = 0x003C0300,
6931     CPU_POWERPC_970FX_v31          = 0x003C0301,
6932     CPU_POWERPC_970GX              = 0x00450000,
6933 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
6934     CPU_POWERPC_970MP_v10          = 0x00440100,
6935     CPU_POWERPC_970MP_v11          = 0x00440101,
6936 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
6937     CPU_POWERPC_CELL_v10           = 0x00700100,
6938     CPU_POWERPC_CELL_v20           = 0x00700400,
6939     CPU_POWERPC_CELL_v30           = 0x00700500,
6940     CPU_POWERPC_CELL_v31           = 0x00700501,
6941 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
6942     CPU_POWERPC_RS64               = 0x00330000,
6943     CPU_POWERPC_RS64II             = 0x00340000,
6944     CPU_POWERPC_RS64III            = 0x00360000,
6945     CPU_POWERPC_RS64IV             = 0x00370000,
6946 #endif /* defined(TARGET_PPC64) */
6947     /* Original POWER */
6948     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6949      * POWER2 (RIOS2) & RSC2 (P2SC) here
6950      */
6951 #if 0
6952     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
6953 #endif
6954 #if 0
6955     CPU_POWER2                     = xxx, /* 0x40000 ? */
6956 #endif
6957     /* PA Semi core */
6958     CPU_POWERPC_PA6T               = 0x00900000,
6959 };
6960
6961 /* System version register (used on MPC 8xxx)                                */
6962 enum {
6963     POWERPC_SVR_NONE               = 0x00000000,
6964 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
6965 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
6966     POWERPC_SVR_5200_v10           = 0x80110010,
6967     POWERPC_SVR_5200_v11           = 0x80110011,
6968     POWERPC_SVR_5200_v12           = 0x80110012,
6969 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
6970     POWERPC_SVR_5200B_v20          = 0x80110020,
6971     POWERPC_SVR_5200B_v21          = 0x80110021,
6972 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
6973 #if 0
6974     POWERPC_SVR_5533               = xxx,
6975 #endif
6976 #if 0
6977     POWERPC_SVR_5534               = xxx,
6978 #endif
6979 #if 0
6980     POWERPC_SVR_5553               = xxx,
6981 #endif
6982 #if 0
6983     POWERPC_SVR_5554               = xxx,
6984 #endif
6985 #if 0
6986     POWERPC_SVR_5561               = xxx,
6987 #endif
6988 #if 0
6989     POWERPC_SVR_5565               = xxx,
6990 #endif
6991 #if 0
6992     POWERPC_SVR_5566               = xxx,
6993 #endif
6994 #if 0
6995     POWERPC_SVR_5567               = xxx,
6996 #endif
6997 #if 0
6998     POWERPC_SVR_8313               = xxx,
6999 #endif
7000 #if 0
7001     POWERPC_SVR_8313E              = xxx,
7002 #endif
7003 #if 0
7004     POWERPC_SVR_8314               = xxx,
7005 #endif
7006 #if 0
7007     POWERPC_SVR_8314E              = xxx,
7008 #endif
7009 #if 0
7010     POWERPC_SVR_8315               = xxx,
7011 #endif
7012 #if 0
7013     POWERPC_SVR_8315E              = xxx,
7014 #endif
7015 #if 0
7016     POWERPC_SVR_8321               = xxx,
7017 #endif
7018 #if 0
7019     POWERPC_SVR_8321E              = xxx,
7020 #endif
7021 #if 0
7022     POWERPC_SVR_8323               = xxx,
7023 #endif
7024 #if 0
7025     POWERPC_SVR_8323E              = xxx,
7026 #endif
7027     POWERPC_SVR_8343A              = 0x80570030,
7028     POWERPC_SVR_8343EA             = 0x80560030,
7029 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7030     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7031     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7032 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7033     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7034     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7035     POWERPC_SVR_8349               = 0x80510010,
7036     POWERPC_SVR_8349A              = 0x80510030,
7037     POWERPC_SVR_8349E              = 0x80500010,
7038     POWERPC_SVR_8349EA             = 0x80500030,
7039 #if 0
7040     POWERPC_SVR_8358E              = xxx,
7041 #endif
7042 #if 0
7043     POWERPC_SVR_8360E              = xxx,
7044 #endif
7045 #define POWERPC_SVR_E500             0x40000000
7046     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7047     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7048     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7049     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7050     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7051     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7052 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7053     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7054     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7055 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7056     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7057     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7058 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7059     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7060     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7061     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7062 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7063     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7064     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7065 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7066     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7067     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7068 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7069     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7070     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7071     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7072     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7073 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7074     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7075     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7076     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7077     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7078 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7079     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7080     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7081 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7082     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7083     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7084 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7085     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7086     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7087 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7088     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7089     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7090 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7091     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7092     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7093 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7094     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7095     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7096     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7097     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7098 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7099     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7100     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7101     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7102     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7103 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7104     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7105     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7106 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7107     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7108     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7109 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7110     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7111     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7112     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7113     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7114     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7115     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7116     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7117     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7118     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7119 #if 0
7120     POWERPC_SVR_8610               = xxx,
7121 #endif
7122     POWERPC_SVR_8641               = 0x80900021,
7123     POWERPC_SVR_8641D              = 0x80900121,
7124 };
7125
7126 /*****************************************************************************/
7127 /* PowerPC CPU definitions                                                   */
7128 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7129     {                                                                         \
7130         .name        = _name,                                                 \
7131         .pvr         = _pvr,                                                  \
7132         .svr         = _svr,                                                  \
7133         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7134         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7135         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7136         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7137         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7138         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7139         .flags       = glue(POWERPC_FLAG_,_type),                             \
7140         .init_proc   = &glue(init_proc_,_type),                               \
7141         .check_pow   = &glue(check_pow_,_type),                               \
7142     }
7143 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7144 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7145
7146 static const ppc_def_t ppc_defs[] = {
7147     /* Embedded PowerPC                                                      */
7148     /* PowerPC 401 family                                                    */
7149     /* Generic PowerPC 401 */
7150     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7151     /* PowerPC 401 cores                                                     */
7152     /* PowerPC 401A1 */
7153     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7154     /* PowerPC 401B2                                                         */
7155     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7156 #if defined (TODO)
7157     /* PowerPC 401B3                                                         */
7158     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7159 #endif
7160     /* PowerPC 401C2                                                         */
7161     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7162     /* PowerPC 401D2                                                         */
7163     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7164     /* PowerPC 401E2                                                         */
7165     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7166     /* PowerPC 401F2                                                         */
7167     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7168     /* PowerPC 401G2                                                         */
7169     /* XXX: to be checked */
7170     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7171     /* PowerPC 401 microcontrolers                                           */
7172 #if defined (TODO)
7173     /* PowerPC 401GF                                                         */
7174     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7175 #endif
7176     /* IOP480 (401 microcontroler)                                           */
7177     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7178     /* IBM Processor for Network Resources                                   */
7179     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7180 #if defined (TODO)
7181     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7182 #endif
7183     /* PowerPC 403 family                                                    */
7184     /* Generic PowerPC 403                                                   */
7185     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7186     /* PowerPC 403 microcontrolers                                           */
7187     /* PowerPC 403 GA                                                        */
7188     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7189     /* PowerPC 403 GB                                                        */
7190     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7191     /* PowerPC 403 GC                                                        */
7192     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7193     /* PowerPC 403 GCX                                                       */
7194     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7195 #if defined (TODO)
7196     /* PowerPC 403 GP                                                        */
7197     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7198 #endif
7199     /* PowerPC 405 family                                                    */
7200     /* Generic PowerPC 405                                                   */
7201     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7202     /* PowerPC 405 cores                                                     */
7203 #if defined (TODO)
7204     /* PowerPC 405 A3                                                        */
7205     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7206 #endif
7207 #if defined (TODO)
7208     /* PowerPC 405 A4                                                        */
7209     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7210 #endif
7211 #if defined (TODO)
7212     /* PowerPC 405 B3                                                        */
7213     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7214 #endif
7215 #if defined (TODO)
7216     /* PowerPC 405 B4                                                        */
7217     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7218 #endif
7219 #if defined (TODO)
7220     /* PowerPC 405 C3                                                        */
7221     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7222 #endif
7223 #if defined (TODO)
7224     /* PowerPC 405 C4                                                        */
7225     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7226 #endif
7227     /* PowerPC 405 D2                                                        */
7228     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7229 #if defined (TODO)
7230     /* PowerPC 405 D3                                                        */
7231     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7232 #endif
7233     /* PowerPC 405 D4                                                        */
7234     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7235 #if defined (TODO)
7236     /* PowerPC 405 D5                                                        */
7237     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7238 #endif
7239 #if defined (TODO)
7240     /* PowerPC 405 E4                                                        */
7241     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7242 #endif
7243 #if defined (TODO)
7244     /* PowerPC 405 F4                                                        */
7245     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7246 #endif
7247 #if defined (TODO)
7248     /* PowerPC 405 F5                                                        */
7249     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7250 #endif
7251 #if defined (TODO)
7252     /* PowerPC 405 F6                                                        */
7253     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7254 #endif
7255     /* PowerPC 405 microcontrolers                                           */
7256     /* PowerPC 405 CR                                                        */
7257     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7258     /* PowerPC 405 CRa                                                       */
7259     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7260     /* PowerPC 405 CRb                                                       */
7261     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7262     /* PowerPC 405 CRc                                                       */
7263     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7264     /* PowerPC 405 EP                                                        */
7265     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7266 #if defined(TODO)
7267     /* PowerPC 405 EXr                                                       */
7268     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7269 #endif
7270     /* PowerPC 405 EZ                                                        */
7271     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7272 #if defined(TODO)
7273     /* PowerPC 405 FX                                                        */
7274     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7275 #endif
7276     /* PowerPC 405 GP                                                        */
7277     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7278     /* PowerPC 405 GPa                                                       */
7279     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7280     /* PowerPC 405 GPb                                                       */
7281     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7282     /* PowerPC 405 GPc                                                       */
7283     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7284     /* PowerPC 405 GPd                                                       */
7285     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7286     /* PowerPC 405 GPe                                                       */
7287     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7288     /* PowerPC 405 GPR                                                       */
7289     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7290 #if defined(TODO)
7291     /* PowerPC 405 H                                                         */
7292     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7293 #endif
7294 #if defined(TODO)
7295     /* PowerPC 405 L                                                         */
7296     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7297 #endif
7298     /* PowerPC 405 LP                                                        */
7299     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7300 #if defined(TODO)
7301     /* PowerPC 405 PM                                                        */
7302     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7303 #endif
7304 #if defined(TODO)
7305     /* PowerPC 405 PS                                                        */
7306     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7307 #endif
7308 #if defined(TODO)
7309     /* PowerPC 405 S                                                         */
7310     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7311 #endif
7312     /* Npe405 H                                                              */
7313     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7314     /* Npe405 H2                                                             */
7315     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7316     /* Npe405 L                                                              */
7317     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7318     /* Npe4GS3                                                               */
7319     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7320 #if defined (TODO)
7321     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7322 #endif
7323 #if defined (TODO)
7324     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7325 #endif
7326 #if defined (TODO)
7327     /* PowerPC LC77700 (Sanyo)                                               */
7328     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7329 #endif
7330     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7331 #if defined (TODO)
7332     /* STB010000                                                             */
7333     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7334 #endif
7335 #if defined (TODO)
7336     /* STB01010                                                              */
7337     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7338 #endif
7339 #if defined (TODO)
7340     /* STB0210                                                               */
7341     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7342 #endif
7343     /* STB03xx                                                               */
7344     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7345 #if defined (TODO)
7346     /* STB043x                                                               */
7347     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7348 #endif
7349 #if defined (TODO)
7350     /* STB045x                                                               */
7351     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7352 #endif
7353     /* STB04xx                                                               */
7354     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7355     /* STB25xx                                                               */
7356     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7357 #if defined (TODO)
7358     /* STB130                                                                */
7359     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7360 #endif
7361     /* Xilinx PowerPC 405 cores                                              */
7362     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7363     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7364     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7365     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7366 #if defined (TODO)
7367     /* Zarlink ZL10310                                                       */
7368     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7369 #endif
7370 #if defined (TODO)
7371     /* Zarlink ZL10311                                                       */
7372     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7373 #endif
7374 #if defined (TODO)
7375     /* Zarlink ZL10320                                                       */
7376     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7377 #endif
7378 #if defined (TODO)
7379     /* Zarlink ZL10321                                                       */
7380     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7381 #endif
7382     /* PowerPC 440 family                                                    */
7383 #if defined(TODO_USER_ONLY)
7384     /* Generic PowerPC 440                                                   */
7385     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7386 #endif
7387     /* PowerPC 440 cores                                                     */
7388 #if defined (TODO)
7389     /* PowerPC 440 A4                                                        */
7390     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7391 #endif
7392 #if defined (TODO)
7393     /* PowerPC 440 A5                                                        */
7394     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7395 #endif
7396 #if defined (TODO)
7397     /* PowerPC 440 B4                                                        */
7398     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7399 #endif
7400 #if defined (TODO)
7401     /* PowerPC 440 G4                                                        */
7402     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7403 #endif
7404 #if defined (TODO)
7405     /* PowerPC 440 F5                                                        */
7406     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7407 #endif
7408 #if defined (TODO)
7409     /* PowerPC 440 G5                                                        */
7410     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7411 #endif
7412 #if defined (TODO)
7413     /* PowerPC 440H4                                                         */
7414     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7415 #endif
7416 #if defined (TODO)
7417     /* PowerPC 440H6                                                         */
7418     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7419 #endif
7420     /* PowerPC 440 microcontrolers                                           */
7421 #if defined(TODO_USER_ONLY)
7422     /* PowerPC 440 EP                                                        */
7423     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7424 #endif
7425 #if defined(TODO_USER_ONLY)
7426     /* PowerPC 440 EPa                                                       */
7427     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7428 #endif
7429 #if defined(TODO_USER_ONLY)
7430     /* PowerPC 440 EPb                                                       */
7431     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7432 #endif
7433 #if defined(TODO_USER_ONLY)
7434     /* PowerPC 440 EPX                                                       */
7435     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7436 #endif
7437 #if defined(TODO_USER_ONLY)
7438     /* PowerPC 440 GP                                                        */
7439     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7440 #endif
7441 #if defined(TODO_USER_ONLY)
7442     /* PowerPC 440 GPb                                                       */
7443     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7444 #endif
7445 #if defined(TODO_USER_ONLY)
7446     /* PowerPC 440 GPc                                                       */
7447     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7448 #endif
7449 #if defined(TODO_USER_ONLY)
7450     /* PowerPC 440 GR                                                        */
7451     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7452 #endif
7453 #if defined(TODO_USER_ONLY)
7454     /* PowerPC 440 GRa                                                       */
7455     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7456 #endif
7457 #if defined(TODO_USER_ONLY)
7458     /* PowerPC 440 GRX                                                       */
7459     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7460 #endif
7461 #if defined(TODO_USER_ONLY)
7462     /* PowerPC 440 GX                                                        */
7463     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7464 #endif
7465 #if defined(TODO_USER_ONLY)
7466     /* PowerPC 440 GXa                                                       */
7467     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7468 #endif
7469 #if defined(TODO_USER_ONLY)
7470     /* PowerPC 440 GXb                                                       */
7471     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7472 #endif
7473 #if defined(TODO_USER_ONLY)
7474     /* PowerPC 440 GXc                                                       */
7475     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7476 #endif
7477 #if defined(TODO_USER_ONLY)
7478     /* PowerPC 440 GXf                                                       */
7479     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7480 #endif
7481 #if defined(TODO)
7482     /* PowerPC 440 S                                                         */
7483     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7484 #endif
7485 #if defined(TODO_USER_ONLY)
7486     /* PowerPC 440 SP                                                        */
7487     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7488 #endif
7489 #if defined(TODO_USER_ONLY)
7490     /* PowerPC 440 SP2                                                       */
7491     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7492 #endif
7493 #if defined(TODO_USER_ONLY)
7494     /* PowerPC 440 SPE                                                       */
7495     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7496 #endif
7497     /* PowerPC 460 family                                                    */
7498 #if defined (TODO)
7499     /* Generic PowerPC 464                                                   */
7500     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7501 #endif
7502     /* PowerPC 464 microcontrolers                                           */
7503 #if defined (TODO)
7504     /* PowerPC 464H90                                                        */
7505     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7506 #endif
7507 #if defined (TODO)
7508     /* PowerPC 464H90F                                                       */
7509     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7510 #endif
7511     /* Freescale embedded PowerPC cores                                      */
7512     /* MPC5xx family (aka RCPU)                                              */
7513 #if defined(TODO_USER_ONLY)
7514     /* Generic MPC5xx core                                                   */
7515     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7516 #endif
7517 #if defined(TODO_USER_ONLY)
7518     /* Codename for MPC5xx core                                              */
7519     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7520 #endif
7521     /* MPC5xx microcontrollers                                               */
7522 #if defined(TODO_USER_ONLY)
7523     /* MGT560                                                                */
7524     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7525 #endif
7526 #if defined(TODO_USER_ONLY)
7527     /* MPC509                                                                */
7528     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7529 #endif
7530 #if defined(TODO_USER_ONLY)
7531     /* MPC533                                                                */
7532     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7533 #endif
7534 #if defined(TODO_USER_ONLY)
7535     /* MPC534                                                                */
7536     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7537 #endif
7538 #if defined(TODO_USER_ONLY)
7539     /* MPC555                                                                */
7540     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7541 #endif
7542 #if defined(TODO_USER_ONLY)
7543     /* MPC556                                                                */
7544     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7545 #endif
7546 #if defined(TODO_USER_ONLY)
7547     /* MPC560                                                                */
7548     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7549 #endif
7550 #if defined(TODO_USER_ONLY)
7551     /* MPC561                                                                */
7552     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7553 #endif
7554 #if defined(TODO_USER_ONLY)
7555     /* MPC562                                                                */
7556     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7557 #endif
7558 #if defined(TODO_USER_ONLY)
7559     /* MPC563                                                                */
7560     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7561 #endif
7562 #if defined(TODO_USER_ONLY)
7563     /* MPC564                                                                */
7564     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7565 #endif
7566 #if defined(TODO_USER_ONLY)
7567     /* MPC565                                                                */
7568     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7569 #endif
7570 #if defined(TODO_USER_ONLY)
7571     /* MPC566                                                                */
7572     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7573 #endif
7574     /* MPC8xx family (aka PowerQUICC)                                        */
7575 #if defined(TODO_USER_ONLY)
7576     /* Generic MPC8xx core                                                   */
7577     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7578 #endif
7579 #if defined(TODO_USER_ONLY)
7580     /* Codename for MPC8xx core                                              */
7581     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7582 #endif
7583     /* MPC8xx microcontrollers                                               */
7584 #if defined(TODO_USER_ONLY)
7585     /* MGT823                                                                */
7586     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7587 #endif
7588 #if defined(TODO_USER_ONLY)
7589     /* MPC821                                                                */
7590     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7591 #endif
7592 #if defined(TODO_USER_ONLY)
7593     /* MPC823                                                                */
7594     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7595 #endif
7596 #if defined(TODO_USER_ONLY)
7597     /* MPC850                                                                */
7598     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7599 #endif
7600 #if defined(TODO_USER_ONLY)
7601     /* MPC852T                                                               */
7602     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7603 #endif
7604 #if defined(TODO_USER_ONLY)
7605     /* MPC855T                                                               */
7606     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7607 #endif
7608 #if defined(TODO_USER_ONLY)
7609     /* MPC857                                                                */
7610     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7611 #endif
7612 #if defined(TODO_USER_ONLY)
7613     /* MPC859                                                                */
7614     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7615 #endif
7616 #if defined(TODO_USER_ONLY)
7617     /* MPC860                                                                */
7618     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7619 #endif
7620 #if defined(TODO_USER_ONLY)
7621     /* MPC862                                                                */
7622     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7623 #endif
7624 #if defined(TODO_USER_ONLY)
7625     /* MPC866                                                                */
7626     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7627 #endif
7628 #if defined(TODO_USER_ONLY)
7629     /* MPC870                                                                */
7630     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7631 #endif
7632 #if defined(TODO_USER_ONLY)
7633     /* MPC875                                                                */
7634     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7635 #endif
7636 #if defined(TODO_USER_ONLY)
7637     /* MPC880                                                                */
7638     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7639 #endif
7640 #if defined(TODO_USER_ONLY)
7641     /* MPC885                                                                */
7642     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7643 #endif
7644     /* MPC82xx family (aka PowerQUICC-II)                                    */
7645     /* Generic MPC52xx core                                                  */
7646     POWERPC_DEF_SVR("MPC52xx",
7647                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7648     /* Generic MPC82xx core                                                  */
7649     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7650     /* Codename for MPC82xx                                                  */
7651     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7652     /* PowerPC G2 core                                                       */
7653     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7654     /* PowerPC G2 H4 core                                                    */
7655     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7656     /* PowerPC G2 GP core                                                    */
7657     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7658     /* PowerPC G2 LS core                                                    */
7659     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7660     /* PowerPC G2 HiP3 core                                                  */
7661     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7662     /* PowerPC G2 HiP4 core                                                  */
7663     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7664     /* PowerPC MPC603 core                                                   */
7665     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7666     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7667     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7668     /* PowerPC G2LE GP core                                                  */
7669     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7670     /* PowerPC G2LE LS core                                                  */
7671     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7672     /* PowerPC G2LE GP1 core                                                 */
7673     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7674     /* PowerPC G2LE GP3 core                                                 */
7675     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7676     /* PowerPC MPC603 microcontrollers                                       */
7677     /* MPC8240                                                               */
7678     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7679     /* PowerPC G2 microcontrollers                                           */
7680 #if defined(TODO)
7681     /* MPC5121                                                               */
7682     POWERPC_DEF_SVR("MPC5121",
7683                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7684 #endif
7685     /* MPC5200                                                               */
7686     POWERPC_DEF_SVR("MPC5200",
7687                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7688     /* MPC5200 v1.0                                                          */
7689     POWERPC_DEF_SVR("MPC5200_v10",
7690                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7691     /* MPC5200 v1.1                                                          */
7692     POWERPC_DEF_SVR("MPC5200_v11",
7693                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7694     /* MPC5200 v1.2                                                          */
7695     POWERPC_DEF_SVR("MPC5200_v12",
7696                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7697     /* MPC5200B                                                              */
7698     POWERPC_DEF_SVR("MPC5200B",
7699                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7700     /* MPC5200B v2.0                                                         */
7701     POWERPC_DEF_SVR("MPC5200B_v20",
7702                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7703     /* MPC5200B v2.1                                                         */
7704     POWERPC_DEF_SVR("MPC5200B_v21",
7705                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7706     /* MPC8241                                                               */
7707     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7708     /* MPC8245                                                               */
7709     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7710     /* MPC8247                                                               */
7711     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7712     /* MPC8248                                                               */
7713     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7714     /* MPC8250                                                               */
7715     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7716     /* MPC8250 HiP3                                                          */
7717     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7718     /* MPC8250 HiP4                                                          */
7719     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7720     /* MPC8255                                                               */
7721     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7722     /* MPC8255 HiP3                                                          */
7723     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7724     /* MPC8255 HiP4                                                          */
7725     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7726     /* MPC8260                                                               */
7727     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7728     /* MPC8260 HiP3                                                          */
7729     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7730     /* MPC8260 HiP4                                                          */
7731     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7732     /* MPC8264                                                               */
7733     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7734     /* MPC8264 HiP3                                                          */
7735     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7736     /* MPC8264 HiP4                                                          */
7737     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7738     /* MPC8265                                                               */
7739     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7740     /* MPC8265 HiP3                                                          */
7741     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7742     /* MPC8265 HiP4                                                          */
7743     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7744     /* MPC8266                                                               */
7745     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7746     /* MPC8266 HiP3                                                          */
7747     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7748     /* MPC8266 HiP4                                                          */
7749     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7750     /* MPC8270                                                               */
7751     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7752     /* MPC8271                                                               */
7753     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7754     /* MPC8272                                                               */
7755     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7756     /* MPC8275                                                               */
7757     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7758     /* MPC8280                                                               */
7759     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7760     /* e200 family                                                           */
7761     /* Generic PowerPC e200 core                                             */
7762     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7763     /* Generic MPC55xx core                                                  */
7764 #if defined (TODO)
7765     POWERPC_DEF_SVR("MPC55xx",
7766                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7767 #endif
7768 #if defined (TODO)
7769     /* PowerPC e200z0 core                                                   */
7770     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7771 #endif
7772 #if defined (TODO)
7773     /* PowerPC e200z1 core                                                   */
7774     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
7775 #endif
7776 #if defined (TODO)
7777     /* PowerPC e200z3 core                                                   */
7778     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
7779 #endif
7780     /* PowerPC e200z5 core                                                   */
7781     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
7782     /* PowerPC e200z6 core                                                   */
7783     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
7784     /* PowerPC e200 microcontrollers                                         */
7785 #if defined (TODO)
7786     /* MPC5514E                                                              */
7787     POWERPC_DEF_SVR("MPC5514E",
7788                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
7789 #endif
7790 #if defined (TODO)
7791     /* MPC5514E v0                                                           */
7792     POWERPC_DEF_SVR("MPC5514E_v0",
7793                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
7794 #endif
7795 #if defined (TODO)
7796     /* MPC5514E v1                                                           */
7797     POWERPC_DEF_SVR("MPC5514E_v1",
7798                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
7799 #endif
7800 #if defined (TODO)
7801     /* MPC5514G                                                              */
7802     POWERPC_DEF_SVR("MPC5514G",
7803                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
7804 #endif
7805 #if defined (TODO)
7806     /* MPC5514G v0                                                           */
7807     POWERPC_DEF_SVR("MPC5514G_v0",
7808                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
7809 #endif
7810 #if defined (TODO)
7811     /* MPC5514G v1                                                           */
7812     POWERPC_DEF_SVR("MPC5514G_v1",
7813                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
7814 #endif
7815 #if defined (TODO)
7816     /* MPC5515S                                                              */
7817     POWERPC_DEF_SVR("MPC5515S",
7818                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
7819 #endif
7820 #if defined (TODO)
7821     /* MPC5516E                                                              */
7822     POWERPC_DEF_SVR("MPC5516E",
7823                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
7824 #endif
7825 #if defined (TODO)
7826     /* MPC5516E v0                                                           */
7827     POWERPC_DEF_SVR("MPC5516E_v0",
7828                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
7829 #endif
7830 #if defined (TODO)
7831     /* MPC5516E v1                                                           */
7832     POWERPC_DEF_SVR("MPC5516E_v1",
7833                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
7834 #endif
7835 #if defined (TODO)
7836     /* MPC5516G                                                              */
7837     POWERPC_DEF_SVR("MPC5516G",
7838                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
7839 #endif
7840 #if defined (TODO)
7841     /* MPC5516G v0                                                           */
7842     POWERPC_DEF_SVR("MPC5516G_v0",
7843                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
7844 #endif
7845 #if defined (TODO)
7846     /* MPC5516G v1                                                           */
7847     POWERPC_DEF_SVR("MPC5516G_v1",
7848                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
7849 #endif
7850 #if defined (TODO)
7851     /* MPC5516S                                                              */
7852     POWERPC_DEF_SVR("MPC5516S",
7853                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
7854 #endif
7855 #if defined (TODO)
7856     /* MPC5533                                                               */
7857     POWERPC_DEF_SVR("MPC5533",
7858                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
7859 #endif
7860 #if defined (TODO)
7861     /* MPC5534                                                               */
7862     POWERPC_DEF_SVR("MPC5534",
7863                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
7864 #endif
7865 #if defined (TODO)
7866     /* MPC5553                                                               */
7867     POWERPC_DEF_SVR("MPC5553",
7868                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
7869 #endif
7870 #if defined (TODO)
7871     /* MPC5554                                                               */
7872     POWERPC_DEF_SVR("MPC5554",
7873                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
7874 #endif
7875 #if defined (TODO)
7876     /* MPC5561                                                               */
7877     POWERPC_DEF_SVR("MPC5561",
7878                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
7879 #endif
7880 #if defined (TODO)
7881     /* MPC5565                                                               */
7882     POWERPC_DEF_SVR("MPC5565",
7883                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
7884 #endif
7885 #if defined (TODO)
7886     /* MPC5566                                                               */
7887     POWERPC_DEF_SVR("MPC5566",
7888                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
7889 #endif
7890 #if defined (TODO)
7891     /* MPC5567                                                               */
7892     POWERPC_DEF_SVR("MPC5567",
7893                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
7894 #endif
7895     /* e300 family                                                           */
7896     /* Generic PowerPC e300 core                                             */
7897     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
7898     /* PowerPC e300c1 core                                                   */
7899     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
7900     /* PowerPC e300c2 core                                                   */
7901     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
7902     /* PowerPC e300c3 core                                                   */
7903     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
7904     /* PowerPC e300c4 core                                                   */
7905     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
7906     /* PowerPC e300 microcontrollers                                         */
7907 #if defined (TODO)
7908     /* MPC8313                                                               */
7909     POWERPC_DEF_SVR("MPC8313",
7910                     CPU_POWERPC_MPC8313,      POWERPC_SVR_8313,      e300),
7911 #endif
7912 #if defined (TODO)
7913     /* MPC8313E                                                              */
7914     POWERPC_DEF_SVR("MPC8313E",
7915                     CPU_POWERPC_MPC8313E,     POWERPC_SVR_8313E,     e300),
7916 #endif
7917 #if defined (TODO)
7918     /* MPC8314                                                               */
7919     POWERPC_DEF_SVR("MPC8314",
7920                     CPU_POWERPC_MPC8314,      POWERPC_SVR_8314,      e300),
7921 #endif
7922 #if defined (TODO)
7923     /* MPC8314E                                                              */
7924     POWERPC_DEF_SVR("MPC8314E",
7925                     CPU_POWERPC_MPC8314E,     POWERPC_SVR_8314E,     e300),
7926 #endif
7927 #if defined (TODO)
7928     /* MPC8315                                                               */
7929     POWERPC_DEF_SVR("MPC8315",
7930                     CPU_POWERPC_MPC8315,      POWERPC_SVR_8315,      e300),
7931 #endif
7932 #if defined (TODO)
7933     /* MPC8315E                                                              */
7934     POWERPC_DEF_SVR("MPC8315E",
7935                     CPU_POWERPC_MPC8315E,     POWERPC_SVR_8315E,     e300),
7936 #endif
7937 #if defined (TODO)
7938     /* MPC8321                                                               */
7939     POWERPC_DEF_SVR("MPC8321",
7940                     CPU_POWERPC_MPC8321,      POWERPC_SVR_8321,      e300),
7941 #endif
7942 #if defined (TODO)
7943     /* MPC8321E                                                              */
7944     POWERPC_DEF_SVR("MPC8321E",
7945                     CPU_POWERPC_MPC8321E,     POWERPC_SVR_8321E,     e300),
7946 #endif
7947 #if defined (TODO)
7948     /* MPC8323                                                               */
7949     POWERPC_DEF_SVR("MPC8323",
7950                     CPU_POWERPC_MPC8323,      POWERPC_SVR_8323,      e300),
7951 #endif
7952 #if defined (TODO)
7953     /* MPC8323E                                                              */
7954     POWERPC_DEF_SVR("MPC8323E",
7955                     CPU_POWERPC_MPC8323E,     POWERPC_SVR_8323E,     e300),
7956 #endif
7957     /* MPC8343A                                                              */
7958     POWERPC_DEF_SVR("MPC8343A",
7959                     CPU_POWERPC_MPC8343A,     POWERPC_SVR_8343A,     e300),
7960     /* MPC8343EA                                                             */
7961     POWERPC_DEF_SVR("MPC8343EA",
7962                     CPU_POWERPC_MPC8343EA,    POWERPC_SVR_8343EA,    e300),
7963     /* MPC8347A                                                              */
7964     POWERPC_DEF_SVR("MPC8347A",
7965                     CPU_POWERPC_MPC8347A,     POWERPC_SVR_8347A,     e300),
7966     /* MPC8347AT                                                             */
7967     POWERPC_DEF_SVR("MPC8347AT",
7968                     CPU_POWERPC_MPC8347AT,    POWERPC_SVR_8347AT,    e300),
7969     /* MPC8347AP                                                             */
7970     POWERPC_DEF_SVR("MPC8347AP",
7971                     CPU_POWERPC_MPC8347AP,    POWERPC_SVR_8347AP,    e300),
7972     /* MPC8347EA                                                             */
7973     POWERPC_DEF_SVR("MPC8347EA",
7974                     CPU_POWERPC_MPC8347EA,    POWERPC_SVR_8347EA,    e300),
7975     /* MPC8347EAT                                                            */
7976     POWERPC_DEF_SVR("MPC8347EAT",
7977                     CPU_POWERPC_MPC8347EAT,   POWERPC_SVR_8347EAT,   e300),
7978     /* MPC8343EAP                                                            */
7979     POWERPC_DEF_SVR("MPC8347EAP",
7980                     CPU_POWERPC_MPC8347EAP,   POWERPC_SVR_8347EAP,   e300),
7981     /* MPC8349                                                               */
7982     POWERPC_DEF_SVR("MPC8349",
7983                     CPU_POWERPC_MPC8349,      POWERPC_SVR_8349,      e300),
7984     /* MPC8349A                                                              */
7985     POWERPC_DEF_SVR("MPC8349A",
7986                     CPU_POWERPC_MPC8349A,     POWERPC_SVR_8349A,     e300),
7987     /* MPC8349E                                                              */
7988     POWERPC_DEF_SVR("MPC8349E",
7989                     CPU_POWERPC_MPC8349E,     POWERPC_SVR_8349E,     e300),
7990     /* MPC8349EA                                                             */
7991     POWERPC_DEF_SVR("MPC8349EA",
7992                     CPU_POWERPC_MPC8349EA,    POWERPC_SVR_8349EA,    e300),
7993 #if defined (TODO)
7994     /* MPC8358E                                                              */
7995     POWERPC_DEF_SVR("MPC8358E",
7996                     CPU_POWERPC_MPC8358E,     POWERPC_SVR_8358E,     e300),
7997 #endif
7998 #if defined (TODO)
7999     /* MPC8360E                                                              */
8000     POWERPC_DEF_SVR("MPC8360E",
8001                     CPU_POWERPC_MPC8360E,     POWERPC_SVR_8360E,     e300),
8002 #endif
8003     /* MPC8377                                                               */
8004     POWERPC_DEF_SVR("MPC8377",
8005                     CPU_POWERPC_MPC8377,      POWERPC_SVR_8377,      e300),
8006     /* MPC8377E                                                              */
8007     POWERPC_DEF_SVR("MPC8377E",
8008                     CPU_POWERPC_MPC8377E,     POWERPC_SVR_8377E,     e300),
8009     /* MPC8378                                                               */
8010     POWERPC_DEF_SVR("MPC8378",
8011                     CPU_POWERPC_MPC8378,      POWERPC_SVR_8378,      e300),
8012     /* MPC8378E                                                              */
8013     POWERPC_DEF_SVR("MPC8378E",
8014                     CPU_POWERPC_MPC8378E,     POWERPC_SVR_8378E,     e300),
8015     /* MPC8379                                                               */
8016     POWERPC_DEF_SVR("MPC8379",
8017                     CPU_POWERPC_MPC8379,      POWERPC_SVR_8379,      e300),
8018     /* MPC8379E                                                              */
8019     POWERPC_DEF_SVR("MPC8379E",
8020                     CPU_POWERPC_MPC8379E,     POWERPC_SVR_8379E,     e300),
8021     /* e500 family                                                           */
8022     /* PowerPC e500 core                                                     */
8023     POWERPC_DEF("e500",          CPU_POWERPC_e500,                   e500),
8024     /* PowerPC e500 v1.0 core                                                */
8025     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500_v10,               e500),
8026     /* PowerPC e500 v2.0 core                                                */
8027     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500_v20,               e500),
8028     /* PowerPC e500v2 core                                                   */
8029     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500),
8030     /* PowerPC e500v2 v1.0 core                                              */
8031     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500),
8032     /* PowerPC e500v2 v2.0 core                                              */
8033     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500),
8034     /* PowerPC e500v2 v2.1 core                                              */
8035     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500),
8036     /* PowerPC e500v2 v2.2 core                                              */
8037     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500),
8038     /* PowerPC e500v2 v3.0 core                                              */
8039     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500),
8040     /* PowerPC e500 microcontrollers                                         */
8041     /* MPC8533                                                               */
8042     POWERPC_DEF_SVR("MPC8533",
8043                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500),
8044     /* MPC8533 v1.0                                                          */
8045     POWERPC_DEF_SVR("MPC8533_v10",
8046                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500),
8047     /* MPC8533 v1.1                                                          */
8048     POWERPC_DEF_SVR("MPC8533_v11",
8049                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500),
8050     /* MPC8533E                                                              */
8051     POWERPC_DEF_SVR("MPC8533E",
8052                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500),
8053     /* MPC8533E v1.0                                                         */
8054     POWERPC_DEF_SVR("MPC8533E_v10",
8055                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
8056     POWERPC_DEF_SVR("MPC8533E_v11",
8057                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
8058     /* MPC8540                                                               */
8059     POWERPC_DEF_SVR("MPC8540",
8060                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500),
8061     /* MPC8540 v1.0                                                          */
8062     POWERPC_DEF_SVR("MPC8540_v10",
8063                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500),
8064     /* MPC8540 v2.0                                                          */
8065     POWERPC_DEF_SVR("MPC8540_v20",
8066                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500),
8067     /* MPC8540 v2.1                                                          */
8068     POWERPC_DEF_SVR("MPC8540_v21",
8069                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500),
8070     /* MPC8541                                                               */
8071     POWERPC_DEF_SVR("MPC8541",
8072                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500),
8073     /* MPC8541 v1.0                                                          */
8074     POWERPC_DEF_SVR("MPC8541_v10",
8075                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500),
8076     /* MPC8541 v1.1                                                          */
8077     POWERPC_DEF_SVR("MPC8541_v11",
8078                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500),
8079     /* MPC8541E                                                              */
8080     POWERPC_DEF_SVR("MPC8541E",
8081                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500),
8082     /* MPC8541E v1.0                                                         */
8083     POWERPC_DEF_SVR("MPC8541E_v10",
8084                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
8085     /* MPC8541E v1.1                                                         */
8086     POWERPC_DEF_SVR("MPC8541E_v11",
8087                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
8088     /* MPC8543                                                               */
8089     POWERPC_DEF_SVR("MPC8543",
8090                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500),
8091     /* MPC8543 v1.0                                                          */
8092     POWERPC_DEF_SVR("MPC8543_v10",
8093                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500),
8094     /* MPC8543 v1.1                                                          */
8095     POWERPC_DEF_SVR("MPC8543_v11",
8096                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500),
8097     /* MPC8543 v2.0                                                          */
8098     POWERPC_DEF_SVR("MPC8543_v20",
8099                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500),
8100     /* MPC8543 v2.1                                                          */
8101     POWERPC_DEF_SVR("MPC8543_v21",
8102                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500),
8103     /* MPC8543E                                                              */
8104     POWERPC_DEF_SVR("MPC8543E",
8105                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500),
8106     /* MPC8543E v1.0                                                         */
8107     POWERPC_DEF_SVR("MPC8543E_v10",
8108                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
8109     /* MPC8543E v1.1                                                         */
8110     POWERPC_DEF_SVR("MPC8543E_v11",
8111                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
8112     /* MPC8543E v2.0                                                         */
8113     POWERPC_DEF_SVR("MPC8543E_v20",
8114                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
8115     /* MPC8543E v2.1                                                         */
8116     POWERPC_DEF_SVR("MPC8543E_v21",
8117                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
8118     /* MPC8544                                                               */
8119     POWERPC_DEF_SVR("MPC8544",
8120                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500),
8121     /* MPC8544 v1.0                                                          */
8122     POWERPC_DEF_SVR("MPC8544_v10",
8123                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500),
8124     /* MPC8544 v1.1                                                          */
8125     POWERPC_DEF_SVR("MPC8544_v11",
8126                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500),
8127     /* MPC8544E                                                              */
8128     POWERPC_DEF_SVR("MPC8544E",
8129                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500),
8130     /* MPC8544E v1.0                                                         */
8131     POWERPC_DEF_SVR("MPC8544E_v10",
8132                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
8133     /* MPC8544E v1.1                                                         */
8134     POWERPC_DEF_SVR("MPC8544E_v11",
8135                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
8136     /* MPC8545                                                               */
8137     POWERPC_DEF_SVR("MPC8545",
8138                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500),
8139     /* MPC8545 v2.0                                                          */
8140     POWERPC_DEF_SVR("MPC8545_v20",
8141                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500),
8142     /* MPC8545 v2.1                                                          */
8143     POWERPC_DEF_SVR("MPC8545_v21",
8144                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500),
8145     /* MPC8545E                                                              */
8146     POWERPC_DEF_SVR("MPC8545E",
8147                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500),
8148     /* MPC8545E v2.0                                                         */
8149     POWERPC_DEF_SVR("MPC8545E_v20",
8150                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
8151     /* MPC8545E v2.1                                                         */
8152     POWERPC_DEF_SVR("MPC8545E_v21",
8153                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
8154     /* MPC8547E                                                              */
8155     POWERPC_DEF_SVR("MPC8547E",
8156                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500),
8157     /* MPC8547E v2.0                                                         */
8158     POWERPC_DEF_SVR("MPC8547E_v20",
8159                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
8160     /* MPC8547E v2.1                                                         */
8161     POWERPC_DEF_SVR("MPC8547E_v21",
8162                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
8163     /* MPC8548                                                               */
8164     POWERPC_DEF_SVR("MPC8548",
8165                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500),
8166     /* MPC8548 v1.0                                                          */
8167     POWERPC_DEF_SVR("MPC8548_v10",
8168                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500),
8169     /* MPC8548 v1.1                                                          */
8170     POWERPC_DEF_SVR("MPC8548_v11",
8171                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500),
8172     /* MPC8548 v2.0                                                          */
8173     POWERPC_DEF_SVR("MPC8548_v20",
8174                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500),
8175     /* MPC8548 v2.1                                                          */
8176     POWERPC_DEF_SVR("MPC8548_v21",
8177                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500),
8178     /* MPC8548E                                                              */
8179     POWERPC_DEF_SVR("MPC8548E",
8180                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500),
8181     /* MPC8548E v1.0                                                         */
8182     POWERPC_DEF_SVR("MPC8548E_v10",
8183                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
8184     /* MPC8548E v1.1                                                         */
8185     POWERPC_DEF_SVR("MPC8548E_v11",
8186                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
8187     /* MPC8548E v2.0                                                         */
8188     POWERPC_DEF_SVR("MPC8548E_v20",
8189                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
8190     /* MPC8548E v2.1                                                         */
8191     POWERPC_DEF_SVR("MPC8548E_v21",
8192                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
8193     /* MPC8555                                                               */
8194     POWERPC_DEF_SVR("MPC8555",
8195                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500),
8196     /* MPC8555 v1.0                                                          */
8197     POWERPC_DEF_SVR("MPC8555_v10",
8198                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500),
8199     /* MPC8555 v1.1                                                          */
8200     POWERPC_DEF_SVR("MPC8555_v11",
8201                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500),
8202     /* MPC8555E                                                              */
8203     POWERPC_DEF_SVR("MPC8555E",
8204                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500),
8205     /* MPC8555E v1.0                                                         */
8206     POWERPC_DEF_SVR("MPC8555E_v10",
8207                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
8208     /* MPC8555E v1.1                                                         */
8209     POWERPC_DEF_SVR("MPC8555E_v11",
8210                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
8211     /* MPC8560                                                               */
8212     POWERPC_DEF_SVR("MPC8560",
8213                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500),
8214     /* MPC8560 v1.0                                                          */
8215     POWERPC_DEF_SVR("MPC8560_v10",
8216                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500),
8217     /* MPC8560 v2.0                                                          */
8218     POWERPC_DEF_SVR("MPC8560_v20",
8219                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500),
8220     /* MPC8560 v2.1                                                          */
8221     POWERPC_DEF_SVR("MPC8560_v21",
8222                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500),
8223     /* MPC8567                                                               */
8224     POWERPC_DEF_SVR("MPC8567",
8225                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500),
8226     /* MPC8567E                                                              */
8227     POWERPC_DEF_SVR("MPC8567E",
8228                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500),
8229     /* MPC8568                                                               */
8230     POWERPC_DEF_SVR("MPC8568",
8231                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500),
8232     /* MPC8568E                                                              */
8233     POWERPC_DEF_SVR("MPC8568E",
8234                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500),
8235     /* MPC8572                                                               */
8236     POWERPC_DEF_SVR("MPC8572",
8237                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500),
8238     /* MPC8572E                                                              */
8239     POWERPC_DEF_SVR("MPC8572E",
8240                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500),
8241     /* e600 family                                                           */
8242     /* PowerPC e600 core                                                     */
8243     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8244     /* PowerPC e600 microcontrollers                                         */
8245 #if defined (TODO)
8246     /* MPC8610                                                               */
8247     POWERPC_DEF_SVR("MPC8610",
8248                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8249 #endif
8250     /* MPC8641                                                               */
8251     POWERPC_DEF_SVR("MPC8641",
8252                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8253     /* MPC8641D                                                              */
8254     POWERPC_DEF_SVR("MPC8641D",
8255                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8256     /* 32 bits "classic" PowerPC                                             */
8257     /* PowerPC 6xx family                                                    */
8258     /* PowerPC 601                                                           */
8259     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8260     /* PowerPC 601v0                                                         */
8261     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8262     /* PowerPC 601v1                                                         */
8263     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8264     /* PowerPC 601v                                                          */
8265     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8266     /* PowerPC 601v2                                                         */
8267     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8268     /* PowerPC 602                                                           */
8269     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8270     /* PowerPC 603                                                           */
8271     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8272     /* Code name for PowerPC 603                                             */
8273     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8274     /* PowerPC 603e (aka PID6)                                               */
8275     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8276     /* Code name for PowerPC 603e                                            */
8277     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8278     /* PowerPC 603e v1.1                                                     */
8279     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8280     /* PowerPC 603e v1.2                                                     */
8281     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8282     /* PowerPC 603e v1.3                                                     */
8283     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8284     /* PowerPC 603e v1.4                                                     */
8285     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8286     /* PowerPC 603e v2.2                                                     */
8287     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8288     /* PowerPC 603e v3                                                       */
8289     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8290     /* PowerPC 603e v4                                                       */
8291     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8292     /* PowerPC 603e v4.1                                                     */
8293     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8294     /* PowerPC 603e (aka PID7)                                               */
8295     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8296     /* PowerPC 603e7t                                                        */
8297     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8298     /* PowerPC 603e7v                                                        */
8299     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8300     /* Code name for PowerPC 603ev                                           */
8301     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8302     /* PowerPC 603e7v1                                                       */
8303     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8304     /* PowerPC 603e7v2                                                       */
8305     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8306     /* PowerPC 603p (aka PID7v)                                              */
8307     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8308     /* PowerPC 603r (aka PID7t)                                              */
8309     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8310     /* Code name for PowerPC 603r                                            */
8311     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8312     /* PowerPC 604                                                           */
8313     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8314     /* PowerPC 604e (aka PID9)                                               */
8315     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8316     /* Code name for PowerPC 604e                                            */
8317     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8318     /* PowerPC 604e v1.0                                                     */
8319     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8320     /* PowerPC 604e v2.2                                                     */
8321     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8322     /* PowerPC 604e v2.4                                                     */
8323     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8324     /* PowerPC 604r (aka PIDA)                                               */
8325     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8326     /* Code name for PowerPC 604r                                            */
8327     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8328 #if defined(TODO)
8329     /* PowerPC 604ev                                                         */
8330     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8331 #endif
8332     /* PowerPC 7xx family                                                    */
8333     /* Generic PowerPC 740 (G3)                                              */
8334     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8335     /* Code name for PowerPC 740                                             */
8336     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8337     /* Generic PowerPC 750 (G3)                                              */
8338     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8339     /* Code name for PowerPC 750                                             */
8340     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8341     /* PowerPC 740/750 is also known as G3                                   */
8342     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8343     /* PowerPC 740 v1.0 (G3)                                                 */
8344     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8345     /* PowerPC 750 v1.0 (G3)                                                 */
8346     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8347     /* PowerPC 740 v2.0 (G3)                                                 */
8348     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8349     /* PowerPC 750 v2.0 (G3)                                                 */
8350     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8351     /* PowerPC 740 v2.1 (G3)                                                 */
8352     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8353     /* PowerPC 750 v2.1 (G3)                                                 */
8354     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8355     /* PowerPC 740 v2.2 (G3)                                                 */
8356     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8357     /* PowerPC 750 v2.2 (G3)                                                 */
8358     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8359     /* PowerPC 740 v3.0 (G3)                                                 */
8360     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8361     /* PowerPC 750 v3.0 (G3)                                                 */
8362     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8363     /* PowerPC 740 v3.1 (G3)                                                 */
8364     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8365     /* PowerPC 750 v3.1 (G3)                                                 */
8366     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8367     /* PowerPC 740E (G3)                                                     */
8368     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8369     /* PowerPC 750E (G3)                                                     */
8370     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8371     /* PowerPC 740P (G3)                                                     */
8372     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8373     /* PowerPC 750P (G3)                                                     */
8374     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8375     /* Code name for PowerPC 740P/750P (G3)                                  */
8376     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8377     /* PowerPC 750CL (G3 embedded)                                           */
8378     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8379     /* PowerPC 750CL v1.0                                                    */
8380     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8381     /* PowerPC 750CL v2.0                                                    */
8382     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8383     /* PowerPC 750CX (G3 embedded)                                           */
8384     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8385     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8386     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8387     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8388     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8389     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8390     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8391     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8392     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8393     /* PowerPC 750CXe (G3 embedded)                                          */
8394     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8395     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8396     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8397     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8398     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8399     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8400     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8401     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8402     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8403     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8404     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8405     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8406     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8407     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8408     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8409     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8410     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8411     /* PowerPC 750CXr (G3 embedded)                                          */
8412     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8413     /* PowerPC 750FL (G3 embedded)                                           */
8414     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8415     /* PowerPC 750FX (G3 embedded)                                           */
8416     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8417     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8418     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8419     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8420     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8421     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8422     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8423     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8424     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8425     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8426     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8427     /* PowerPC 750GL (G3 embedded)                                           */
8428     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8429     /* PowerPC 750GX (G3 embedded)                                           */
8430     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8431     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8432     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8433     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8434     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8435     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8436     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8437     /* PowerPC 750L (G3 embedded)                                            */
8438     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8439     /* Code name for PowerPC 750L (G3 embedded)                              */
8440     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8441     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8442     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8443     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8444     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8445     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8446     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8447     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8448     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8449     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8450     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8451     /* Generic PowerPC 745                                                   */
8452     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8453     /* Generic PowerPC 755                                                   */
8454     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8455     /* Code name for PowerPC 745/755                                         */
8456     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8457     /* PowerPC 745 v1.0                                                      */
8458     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8459     /* PowerPC 755 v1.0                                                      */
8460     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8461     /* PowerPC 745 v1.1                                                      */
8462     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8463     /* PowerPC 755 v1.1                                                      */
8464     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8465     /* PowerPC 745 v2.0                                                      */
8466     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8467     /* PowerPC 755 v2.0                                                      */
8468     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8469     /* PowerPC 745 v2.1                                                      */
8470     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8471     /* PowerPC 755 v2.1                                                      */
8472     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8473     /* PowerPC 745 v2.2                                                      */
8474     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8475     /* PowerPC 755 v2.2                                                      */
8476     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8477     /* PowerPC 745 v2.3                                                      */
8478     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8479     /* PowerPC 755 v2.3                                                      */
8480     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8481     /* PowerPC 745 v2.4                                                      */
8482     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8483     /* PowerPC 755 v2.4                                                      */
8484     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8485     /* PowerPC 745 v2.5                                                      */
8486     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8487     /* PowerPC 755 v2.5                                                      */
8488     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8489     /* PowerPC 745 v2.6                                                      */
8490     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8491     /* PowerPC 755 v2.6                                                      */
8492     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8493     /* PowerPC 745 v2.7                                                      */
8494     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8495     /* PowerPC 755 v2.7                                                      */
8496     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8497     /* PowerPC 745 v2.8                                                      */
8498     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8499     /* PowerPC 755 v2.8                                                      */
8500     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8501 #if defined (TODO)
8502     /* PowerPC 745P (G3)                                                     */
8503     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8504     /* PowerPC 755P (G3)                                                     */
8505     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8506 #endif
8507     /* PowerPC 74xx family                                                   */
8508     /* PowerPC 7400 (G4)                                                     */
8509     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8510     /* Code name for PowerPC 7400                                            */
8511     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8512     /* PowerPC 74xx is also well known as G4                                 */
8513     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8514     /* PowerPC 7400 v1.0 (G4)                                                */
8515     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8516     /* PowerPC 7400 v1.1 (G4)                                                */
8517     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8518     /* PowerPC 7400 v2.0 (G4)                                                */
8519     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8520     /* PowerPC 7400 v2.1 (G4)                                                */
8521     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8522     /* PowerPC 7400 v2.2 (G4)                                                */
8523     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8524     /* PowerPC 7400 v2.6 (G4)                                                */
8525     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8526     /* PowerPC 7400 v2.7 (G4)                                                */
8527     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8528     /* PowerPC 7400 v2.8 (G4)                                                */
8529     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8530     /* PowerPC 7400 v2.9 (G4)                                                */
8531     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8532     /* PowerPC 7410 (G4)                                                     */
8533     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8534     /* Code name for PowerPC 7410                                            */
8535     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8536     /* PowerPC 7410 v1.0 (G4)                                                */
8537     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8538     /* PowerPC 7410 v1.1 (G4)                                                */
8539     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8540     /* PowerPC 7410 v1.2 (G4)                                                */
8541     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8542     /* PowerPC 7410 v1.3 (G4)                                                */
8543     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8544     /* PowerPC 7410 v1.4 (G4)                                                */
8545     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8546     /* PowerPC 7448 (G4)                                                     */
8547     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8548     /* PowerPC 7448 v1.0 (G4)                                                */
8549     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8550     /* PowerPC 7448 v1.1 (G4)                                                */
8551     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8552     /* PowerPC 7448 v2.0 (G4)                                                */
8553     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8554     /* PowerPC 7448 v2.1 (G4)                                                */
8555     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8556     /* PowerPC 7450 (G4)                                                     */
8557     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8558     /* Code name for PowerPC 7450                                            */
8559     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8560     /* PowerPC 7450 v1.0 (G4)                                                */
8561     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8562     /* PowerPC 7450 v1.1 (G4)                                                */
8563     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8564     /* PowerPC 7450 v1.2 (G4)                                                */
8565     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8566     /* PowerPC 7450 v2.0 (G4)                                                */
8567     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8568     /* PowerPC 7450 v2.1 (G4)                                                */
8569     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8570     /* PowerPC 7441 (G4)                                                     */
8571     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8572     /* PowerPC 7451 (G4)                                                     */
8573     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8574     /* PowerPC 7441 v2.1 (G4)                                                */
8575     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8576     /* PowerPC 7441 v2.3 (G4)                                                */
8577     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8578     /* PowerPC 7451 v2.3 (G4)                                                */
8579     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8580     /* PowerPC 7441 v2.10 (G4)                                                */
8581     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8582     /* PowerPC 7451 v2.10 (G4)                                               */
8583     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8584     /* PowerPC 7445 (G4)                                                     */
8585     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8586     /* PowerPC 7455 (G4)                                                     */
8587     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8588     /* Code name for PowerPC 7445/7455                                       */
8589     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8590     /* PowerPC 7445 v1.0 (G4)                                                */
8591     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8592     /* PowerPC 7455 v1.0 (G4)                                                */
8593     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8594     /* PowerPC 7445 v2.1 (G4)                                                */
8595     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8596     /* PowerPC 7455 v2.1 (G4)                                                */
8597     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8598     /* PowerPC 7445 v3.2 (G4)                                                */
8599     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8600     /* PowerPC 7455 v3.2 (G4)                                                */
8601     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8602     /* PowerPC 7445 v3.3 (G4)                                                */
8603     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8604     /* PowerPC 7455 v3.3 (G4)                                                */
8605     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8606     /* PowerPC 7445 v3.4 (G4)                                                */
8607     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8608     /* PowerPC 7455 v3.4 (G4)                                                */
8609     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8610     /* PowerPC 7447 (G4)                                                     */
8611     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8612     /* PowerPC 7457 (G4)                                                     */
8613     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8614     /* Code name for PowerPC 7447/7457                                       */
8615     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8616     /* PowerPC 7447 v1.0 (G4)                                                */
8617     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8618     /* PowerPC 7457 v1.0 (G4)                                                */
8619     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8620     /* PowerPC 7447 v1.1 (G4)                                                */
8621     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8622     /* PowerPC 7457 v1.1 (G4)                                                */
8623     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8624     /* PowerPC 7457 v1.2 (G4)                                                */
8625     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8626     /* PowerPC 7447A (G4)                                                    */
8627     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8628     /* PowerPC 7457A (G4)                                                    */
8629     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8630     /* PowerPC 7447A v1.0 (G4)                                               */
8631     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8632     /* PowerPC 7457A v1.0 (G4)                                               */
8633     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8634     /* Code name for PowerPC 7447A/7457A                                     */
8635     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8636     /* PowerPC 7447A v1.1 (G4)                                               */
8637     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8638     /* PowerPC 7457A v1.1 (G4)                                               */
8639     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8640     /* PowerPC 7447A v1.2 (G4)                                               */
8641     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8642     /* PowerPC 7457A v1.2 (G4)                                               */
8643     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8644     /* 64 bits PowerPC                                                       */
8645 #if defined (TARGET_PPC64)
8646     /* PowerPC 620                                                           */
8647     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8648     /* Code name for PowerPC 620                                             */
8649     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8650 #if defined (TODO)
8651     /* PowerPC 630 (POWER3)                                                  */
8652     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8653     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8654     /* Code names for POWER3                                                 */
8655     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8656     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8657 #endif
8658 #if defined (TODO)
8659     /* PowerPC 631 (Power 3+)                                                */
8660     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8661     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8662 #endif
8663 #if defined (TODO)
8664     /* POWER4                                                                */
8665     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8666 #endif
8667 #if defined (TODO)
8668     /* POWER4p                                                               */
8669     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8670 #endif
8671 #if defined (TODO)
8672     /* POWER5                                                                */
8673     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8674     /* POWER5GR                                                              */
8675     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8676 #endif
8677 #if defined (TODO)
8678     /* POWER5+                                                               */
8679     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8680     /* POWER5GS                                                              */
8681     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8682 #endif
8683 #if defined (TODO)
8684     /* POWER6                                                                */
8685     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8686     /* POWER6 running in POWER5 mode                                         */
8687     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8688     /* POWER6A                                                               */
8689     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8690 #endif
8691     /* PowerPC 970                                                           */
8692     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8693     /* PowerPC 970FX (G5)                                                    */
8694     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8695     /* PowerPC 970FX v1.0 (G5)                                               */
8696     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8697     /* PowerPC 970FX v2.0 (G5)                                               */
8698     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8699     /* PowerPC 970FX v2.1 (G5)                                               */
8700     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8701     /* PowerPC 970FX v3.0 (G5)                                               */
8702     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8703     /* PowerPC 970FX v3.1 (G5)                                               */
8704     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8705     /* PowerPC 970GX (G5)                                                    */
8706     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8707     /* PowerPC 970MP                                                         */
8708     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8709     /* PowerPC 970MP v1.0                                                    */
8710     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8711     /* PowerPC 970MP v1.1                                                    */
8712     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8713 #if defined (TODO)
8714     /* PowerPC Cell                                                          */
8715     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8716 #endif
8717 #if defined (TODO)
8718     /* PowerPC Cell v1.0                                                     */
8719     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8720 #endif
8721 #if defined (TODO)
8722     /* PowerPC Cell v2.0                                                     */
8723     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8724 #endif
8725 #if defined (TODO)
8726     /* PowerPC Cell v3.0                                                     */
8727     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8728 #endif
8729 #if defined (TODO)
8730     /* PowerPC Cell v3.1                                                     */
8731     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8732 #endif
8733 #if defined (TODO)
8734     /* PowerPC Cell v3.2                                                     */
8735     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8736 #endif
8737 #if defined (TODO)
8738     /* RS64 (Apache/A35)                                                     */
8739     /* This one seems to support the whole POWER2 instruction set
8740      * and the PowerPC 64 one.
8741      */
8742     /* What about A10 & A30 ? */
8743     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8744     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
8745     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
8746 #endif
8747 #if defined (TODO)
8748     /* RS64-II (NorthStar/A50)                                               */
8749     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
8750     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
8751     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
8752 #endif
8753 #if defined (TODO)
8754     /* RS64-III (Pulsar)                                                     */
8755     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
8756     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
8757 #endif
8758 #if defined (TODO)
8759     /* RS64-IV (IceStar/IStar/SStar)                                         */
8760     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
8761     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
8762     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
8763     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
8764 #endif
8765 #endif /* defined (TARGET_PPC64) */
8766     /* POWER                                                                 */
8767 #if defined (TODO)
8768     /* Original POWER                                                        */
8769     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
8770     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
8771     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
8772     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
8773     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
8774 #endif
8775 #if defined (TODO)
8776     /* POWER2                                                                */
8777     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
8778     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
8779     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
8780 #endif
8781     /* PA semi cores                                                         */
8782 #if defined (TODO)
8783     /* PA PA6T */
8784     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
8785 #endif
8786     /* Generic PowerPCs                                                      */
8787 #if defined (TARGET_PPC64)
8788     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
8789 #endif
8790     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
8791     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
8792     /* Fallback                                                              */
8793     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
8794 };
8795
8796 /*****************************************************************************/
8797 /* Generic CPU instanciation routine                                         */
8798 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8799 {
8800 #if !defined(CONFIG_USER_ONLY)
8801     int i;
8802
8803     env->irq_inputs = NULL;
8804     /* Set all exception vectors to an invalid address */
8805     for (i = 0; i < POWERPC_EXCP_NB; i++)
8806         env->excp_vectors[i] = (target_ulong)(-1ULL);
8807     env->excp_prefix = 0x00000000;
8808     env->ivor_mask = 0x00000000;
8809     env->ivpr_mask = 0x00000000;
8810     /* Default MMU definitions */
8811     env->nb_BATs = 0;
8812     env->nb_tlb = 0;
8813     env->nb_ways = 0;
8814 #endif
8815     /* Register SPR common to all PowerPC implementations */
8816     gen_spr_generic(env);
8817     spr_register(env, SPR_PVR, "PVR",
8818                  SPR_NOACCESS, SPR_NOACCESS,
8819                  &spr_read_generic, SPR_NOACCESS,
8820                  def->pvr);
8821     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8822     if (def->svr != POWERPC_SVR_NONE) {
8823         if (def->svr & POWERPC_SVR_E500) {
8824             spr_register(env, SPR_E500_SVR, "SVR",
8825                          SPR_NOACCESS, SPR_NOACCESS,
8826                          &spr_read_generic, SPR_NOACCESS,
8827                          def->svr & ~POWERPC_SVR_E500);
8828         } else {
8829             spr_register(env, SPR_SVR, "SVR",
8830                          SPR_NOACCESS, SPR_NOACCESS,
8831                          &spr_read_generic, SPR_NOACCESS,
8832                          def->svr);
8833         }
8834     }
8835     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8836     (*def->init_proc)(env);
8837     /* MSR bits & flags consistency checks */
8838     if (env->msr_mask & (1 << 25)) {
8839         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8840         case POWERPC_FLAG_SPE:
8841         case POWERPC_FLAG_VRE:
8842             break;
8843         default:
8844             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8845                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8846             exit(1);
8847         }
8848     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8849         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8850                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8851         exit(1);
8852     }
8853     if (env->msr_mask & (1 << 17)) {
8854         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8855         case POWERPC_FLAG_TGPR:
8856         case POWERPC_FLAG_CE:
8857             break;
8858         default:
8859             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8860                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8861             exit(1);
8862         }
8863     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8864         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8865                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8866         exit(1);
8867     }
8868     if (env->msr_mask & (1 << 10)) {
8869         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8870                               POWERPC_FLAG_UBLE)) {
8871         case POWERPC_FLAG_SE:
8872         case POWERPC_FLAG_DWE:
8873         case POWERPC_FLAG_UBLE:
8874             break;
8875         default:
8876             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8877                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8878                     "POWERPC_FLAG_UBLE\n");
8879             exit(1);
8880         }
8881     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8882                              POWERPC_FLAG_UBLE)) {
8883         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8884                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8885                 "POWERPC_FLAG_UBLE\n");
8886             exit(1);
8887     }
8888     if (env->msr_mask & (1 << 9)) {
8889         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8890         case POWERPC_FLAG_BE:
8891         case POWERPC_FLAG_DE:
8892             break;
8893         default:
8894             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8895                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8896             exit(1);
8897         }
8898     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8899         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8900                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8901         exit(1);
8902     }
8903     if (env->msr_mask & (1 << 2)) {
8904         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8905         case POWERPC_FLAG_PX:
8906         case POWERPC_FLAG_PMM:
8907             break;
8908         default:
8909             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8910                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8911             exit(1);
8912         }
8913     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8914         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8915                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8916         exit(1);
8917     }
8918     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8919         fprintf(stderr, "PowerPC flags inconsistency\n"
8920                 "Should define the time-base and decrementer clock source\n");
8921         exit(1);
8922     }
8923     /* Allocate TLBs buffer when needed */
8924 #if !defined(CONFIG_USER_ONLY)
8925     if (env->nb_tlb != 0) {
8926         int nb_tlb = env->nb_tlb;
8927         if (env->id_tlbs != 0)
8928             nb_tlb *= 2;
8929         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8930         /* Pre-compute some useful values */
8931         env->tlb_per_way = env->nb_tlb / env->nb_ways;
8932     }
8933     if (env->irq_inputs == NULL) {
8934         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8935                 " Attempt Qemu to crash very soon !\n");
8936     }
8937 #endif
8938     if (env->check_pow == NULL) {
8939         fprintf(stderr, "WARNING: no power management check handler "
8940                 "registered.\n"
8941                 " Attempt Qemu to crash very soon !\n");
8942     }
8943 }
8944
8945 #if defined(PPC_DUMP_CPU)
8946 static void dump_ppc_sprs (CPUPPCState *env)
8947 {
8948     ppc_spr_t *spr;
8949 #if !defined(CONFIG_USER_ONLY)
8950     uint32_t sr, sw;
8951 #endif
8952     uint32_t ur, uw;
8953     int i, j, n;
8954
8955     printf("Special purpose registers:\n");
8956     for (i = 0; i < 32; i++) {
8957         for (j = 0; j < 32; j++) {
8958             n = (i << 5) | j;
8959             spr = &env->spr_cb[n];
8960             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8961             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8962 #if !defined(CONFIG_USER_ONLY)
8963             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8964             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8965             if (sw || sr || uw || ur) {
8966                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8967                        (i << 5) | j, (i << 5) | j, spr->name,
8968                        sw ? 'w' : '-', sr ? 'r' : '-',
8969                        uw ? 'w' : '-', ur ? 'r' : '-');
8970             }
8971 #else
8972             if (uw || ur) {
8973                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8974                        (i << 5) | j, (i << 5) | j, spr->name,
8975                        uw ? 'w' : '-', ur ? 'r' : '-');
8976             }
8977 #endif
8978         }
8979     }
8980     fflush(stdout);
8981     fflush(stderr);
8982 }
8983 #endif
8984
8985 /*****************************************************************************/
8986 #include <stdlib.h>
8987 #include <string.h>
8988
8989 /* Opcode types */
8990 enum {
8991     PPC_DIRECT   = 0, /* Opcode routine        */
8992     PPC_INDIRECT = 1, /* Indirect opcode table */
8993 };
8994
8995 static inline int is_indirect_opcode (void *handler)
8996 {
8997     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
8998 }
8999
9000 static inline opc_handler_t **ind_table(void *handler)
9001 {
9002     return (opc_handler_t **)((unsigned long)handler & ~3);
9003 }
9004
9005 /* Instruction table creation */
9006 /* Opcodes tables creation */
9007 static void fill_new_table (opc_handler_t **table, int len)
9008 {
9009     int i;
9010
9011     for (i = 0; i < len; i++)
9012         table[i] = &invalid_handler;
9013 }
9014
9015 static int create_new_table (opc_handler_t **table, unsigned char idx)
9016 {
9017     opc_handler_t **tmp;
9018
9019     tmp = malloc(0x20 * sizeof(opc_handler_t));
9020     if (tmp == NULL)
9021         return -1;
9022     fill_new_table(tmp, 0x20);
9023     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9024
9025     return 0;
9026 }
9027
9028 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9029                             opc_handler_t *handler)
9030 {
9031     if (table[idx] != &invalid_handler)
9032         return -1;
9033     table[idx] = handler;
9034
9035     return 0;
9036 }
9037
9038 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9039                                  unsigned char idx, opc_handler_t *handler)
9040 {
9041     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9042         printf("*** ERROR: opcode %02x already assigned in main "
9043                "opcode table\n", idx);
9044 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9045         printf("           Registered handler '%s' - new handler '%s'\n",
9046                ppc_opcodes[idx]->oname, handler->oname);
9047 #endif
9048         return -1;
9049     }
9050
9051     return 0;
9052 }
9053
9054 static int register_ind_in_table (opc_handler_t **table,
9055                                   unsigned char idx1, unsigned char idx2,
9056                                   opc_handler_t *handler)
9057 {
9058     if (table[idx1] == &invalid_handler) {
9059         if (create_new_table(table, idx1) < 0) {
9060             printf("*** ERROR: unable to create indirect table "
9061                    "idx=%02x\n", idx1);
9062             return -1;
9063         }
9064     } else {
9065         if (!is_indirect_opcode(table[idx1])) {
9066             printf("*** ERROR: idx %02x already assigned to a direct "
9067                    "opcode\n", idx1);
9068 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9069             printf("           Registered handler '%s' - new handler '%s'\n",
9070                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9071 #endif
9072             return -1;
9073         }
9074     }
9075     if (handler != NULL &&
9076         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9077         printf("*** ERROR: opcode %02x already assigned in "
9078                "opcode table %02x\n", idx2, idx1);
9079 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9080         printf("           Registered handler '%s' - new handler '%s'\n",
9081                ind_table(table[idx1])[idx2]->oname, handler->oname);
9082 #endif
9083         return -1;
9084     }
9085
9086     return 0;
9087 }
9088
9089 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9090                               unsigned char idx1, unsigned char idx2,
9091                               opc_handler_t *handler)
9092 {
9093     int ret;
9094
9095     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9096
9097     return ret;
9098 }
9099
9100 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9101                                  unsigned char idx1, unsigned char idx2,
9102                                  unsigned char idx3, opc_handler_t *handler)
9103 {
9104     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9105         printf("*** ERROR: unable to join indirect table idx "
9106                "[%02x-%02x]\n", idx1, idx2);
9107         return -1;
9108     }
9109     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9110                               handler) < 0) {
9111         printf("*** ERROR: unable to insert opcode "
9112                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9113         return -1;
9114     }
9115
9116     return 0;
9117 }
9118
9119 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9120 {
9121     if (insn->opc2 != 0xFF) {
9122         if (insn->opc3 != 0xFF) {
9123             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9124                                      insn->opc3, &insn->handler) < 0)
9125                 return -1;
9126         } else {
9127             if (register_ind_insn(ppc_opcodes, insn->opc1,
9128                                   insn->opc2, &insn->handler) < 0)
9129                 return -1;
9130         }
9131     } else {
9132         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9133             return -1;
9134     }
9135
9136     return 0;
9137 }
9138
9139 static int test_opcode_table (opc_handler_t **table, int len)
9140 {
9141     int i, count, tmp;
9142
9143     for (i = 0, count = 0; i < len; i++) {
9144         /* Consistency fixup */
9145         if (table[i] == NULL)
9146             table[i] = &invalid_handler;
9147         if (table[i] != &invalid_handler) {
9148             if (is_indirect_opcode(table[i])) {
9149                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9150                 if (tmp == 0) {
9151                     free(table[i]);
9152                     table[i] = &invalid_handler;
9153                 } else {
9154                     count++;
9155                 }
9156             } else {
9157                 count++;
9158             }
9159         }
9160     }
9161
9162     return count;
9163 }
9164
9165 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9166 {
9167     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9168         printf("*** WARNING: no opcode defined !\n");
9169 }
9170
9171 /*****************************************************************************/
9172 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9173 {
9174     opcode_t *opc, *start, *end;
9175
9176     fill_new_table(env->opcodes, 0x40);
9177     if (&opc_start < &opc_end) {
9178         start = &opc_start;
9179         end = &opc_end;
9180     } else {
9181         start = &opc_end;
9182         end = &opc_start;
9183     }
9184     for (opc = start + 1; opc != end; opc++) {
9185         if ((opc->handler.type & def->insns_flags) != 0) {
9186             if (register_insn(env->opcodes, opc) < 0) {
9187                 printf("*** ERROR initializing PowerPC instruction "
9188                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9189                        opc->opc3);
9190                 return -1;
9191             }
9192         }
9193     }
9194     fix_opcode_tables(env->opcodes);
9195     fflush(stdout);
9196     fflush(stderr);
9197
9198     return 0;
9199 }
9200
9201 #if defined(PPC_DUMP_CPU)
9202 static void dump_ppc_insns (CPUPPCState *env)
9203 {
9204     opc_handler_t **table, *handler;
9205     const char *p, *q;
9206     uint8_t opc1, opc2, opc3;
9207
9208     printf("Instructions set:\n");
9209     /* opc1 is 6 bits long */
9210     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9211         table = env->opcodes;
9212         handler = table[opc1];
9213         if (is_indirect_opcode(handler)) {
9214             /* opc2 is 5 bits long */
9215             for (opc2 = 0; opc2 < 0x20; opc2++) {
9216                 table = env->opcodes;
9217                 handler = env->opcodes[opc1];
9218                 table = ind_table(handler);
9219                 handler = table[opc2];
9220                 if (is_indirect_opcode(handler)) {
9221                     table = ind_table(handler);
9222                     /* opc3 is 5 bits long */
9223                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9224                         handler = table[opc3];
9225                         if (handler->handler != &gen_invalid) {
9226                             /* Special hack to properly dump SPE insns */
9227                             p = strchr(handler->oname, '_');
9228                             if (p == NULL) {
9229                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9230                                        "%s\n",
9231                                        opc1, opc2, opc3, opc1,
9232                                        (opc3 << 5) | opc2,
9233                                        handler->oname);
9234                             } else {
9235                                 q = "speundef";
9236                                 if ((p - handler->oname) != strlen(q) ||
9237                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9238                                     /* First instruction */
9239                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9240                                            "%.*s\n",
9241                                            opc1, opc2 << 1, opc3, opc1,
9242                                            (opc3 << 6) | (opc2 << 1),
9243                                            (int)(p - handler->oname),
9244                                            handler->oname);
9245                                 }
9246                                 if (strcmp(p + 1, q) != 0) {
9247                                     /* Second instruction */
9248                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9249                                            "%s\n",
9250                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9251                                            (opc3 << 6) | (opc2 << 1) | 1,
9252                                            p + 1);
9253                                 }
9254                             }
9255                         }
9256                     }
9257                 } else {
9258                     if (handler->handler != &gen_invalid) {
9259                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9260                                opc1, opc2, opc1, opc2, handler->oname);
9261                     }
9262                 }
9263             }
9264         } else {
9265             if (handler->handler != &gen_invalid) {
9266                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9267                        opc1, opc1, handler->oname);
9268             }
9269         }
9270     }
9271 }
9272 #endif
9273
9274 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9275 {
9276     env->msr_mask = def->msr_mask;
9277     env->mmu_model = def->mmu_model;
9278     env->excp_model = def->excp_model;
9279     env->bus_model = def->bus_model;
9280     env->flags = def->flags;
9281     env->bfd_mach = def->bfd_mach;
9282     env->check_pow = def->check_pow;
9283     if (create_ppc_opcodes(env, def) < 0)
9284         return -1;
9285     init_ppc_proc(env, def);
9286 #if defined(PPC_DUMP_CPU)
9287     {
9288         const char *mmu_model, *excp_model, *bus_model;
9289         switch (env->mmu_model) {
9290         case POWERPC_MMU_32B:
9291             mmu_model = "PowerPC 32";
9292             break;
9293         case POWERPC_MMU_SOFT_6xx:
9294             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9295             break;
9296         case POWERPC_MMU_SOFT_74xx:
9297             mmu_model = "PowerPC 74xx with software driven TLBs";
9298             break;
9299         case POWERPC_MMU_SOFT_4xx:
9300             mmu_model = "PowerPC 4xx with software driven TLBs";
9301             break;
9302         case POWERPC_MMU_SOFT_4xx_Z:
9303             mmu_model = "PowerPC 4xx with software driven TLBs "
9304                 "and zones protections";
9305             break;
9306         case POWERPC_MMU_REAL:
9307             mmu_model = "PowerPC real mode only";
9308             break;
9309         case POWERPC_MMU_MPC8xx:
9310             mmu_model = "PowerPC MPC8xx";
9311             break;
9312         case POWERPC_MMU_BOOKE:
9313             mmu_model = "PowerPC BookE";
9314             break;
9315         case POWERPC_MMU_BOOKE_FSL:
9316             mmu_model = "PowerPC BookE FSL";
9317             break;
9318         case POWERPC_MMU_601:
9319             mmu_model = "PowerPC 601";
9320             break;
9321 #if defined (TARGET_PPC64)
9322         case POWERPC_MMU_64B:
9323             mmu_model = "PowerPC 64";
9324             break;
9325         case POWERPC_MMU_620:
9326             mmu_model = "PowerPC 620";
9327             break;
9328 #endif
9329         default:
9330             mmu_model = "Unknown or invalid";
9331             break;
9332         }
9333         switch (env->excp_model) {
9334         case POWERPC_EXCP_STD:
9335             excp_model = "PowerPC";
9336             break;
9337         case POWERPC_EXCP_40x:
9338             excp_model = "PowerPC 40x";
9339             break;
9340         case POWERPC_EXCP_601:
9341             excp_model = "PowerPC 601";
9342             break;
9343         case POWERPC_EXCP_602:
9344             excp_model = "PowerPC 602";
9345             break;
9346         case POWERPC_EXCP_603:
9347             excp_model = "PowerPC 603";
9348             break;
9349         case POWERPC_EXCP_603E:
9350             excp_model = "PowerPC 603e";
9351             break;
9352         case POWERPC_EXCP_604:
9353             excp_model = "PowerPC 604";
9354             break;
9355         case POWERPC_EXCP_7x0:
9356             excp_model = "PowerPC 740/750";
9357             break;
9358         case POWERPC_EXCP_7x5:
9359             excp_model = "PowerPC 745/755";
9360             break;
9361         case POWERPC_EXCP_74xx:
9362             excp_model = "PowerPC 74xx";
9363             break;
9364         case POWERPC_EXCP_BOOKE:
9365             excp_model = "PowerPC BookE";
9366             break;
9367 #if defined (TARGET_PPC64)
9368         case POWERPC_EXCP_970:
9369             excp_model = "PowerPC 970";
9370             break;
9371 #endif
9372         default:
9373             excp_model = "Unknown or invalid";
9374             break;
9375         }
9376         switch (env->bus_model) {
9377         case PPC_FLAGS_INPUT_6xx:
9378             bus_model = "PowerPC 6xx";
9379             break;
9380         case PPC_FLAGS_INPUT_BookE:
9381             bus_model = "PowerPC BookE";
9382             break;
9383         case PPC_FLAGS_INPUT_405:
9384             bus_model = "PowerPC 405";
9385             break;
9386         case PPC_FLAGS_INPUT_401:
9387             bus_model = "PowerPC 401/403";
9388             break;
9389         case PPC_FLAGS_INPUT_RCPU:
9390             bus_model = "RCPU / MPC8xx";
9391             break;
9392 #if defined (TARGET_PPC64)
9393         case PPC_FLAGS_INPUT_970:
9394             bus_model = "PowerPC 970";
9395             break;
9396 #endif
9397         default:
9398             bus_model = "Unknown or invalid";
9399             break;
9400         }
9401         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9402                "    MMU model        : %s\n",
9403                def->name, def->pvr, def->msr_mask, mmu_model);
9404 #if !defined(CONFIG_USER_ONLY)
9405         if (env->tlb != NULL) {
9406             printf("                       %d %s TLB in %d ways\n",
9407                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9408                    env->nb_ways);
9409         }
9410 #endif
9411         printf("    Exceptions model : %s\n"
9412                "    Bus model        : %s\n",
9413                excp_model, bus_model);
9414         printf("    MSR features     :\n");
9415         if (env->flags & POWERPC_FLAG_SPE)
9416             printf("                        signal processing engine enable"
9417                    "\n");
9418         else if (env->flags & POWERPC_FLAG_VRE)
9419             printf("                        vector processor enable\n");
9420         if (env->flags & POWERPC_FLAG_TGPR)
9421             printf("                        temporary GPRs\n");
9422         else if (env->flags & POWERPC_FLAG_CE)
9423             printf("                        critical input enable\n");
9424         if (env->flags & POWERPC_FLAG_SE)
9425             printf("                        single-step trace mode\n");
9426         else if (env->flags & POWERPC_FLAG_DWE)
9427             printf("                        debug wait enable\n");
9428         else if (env->flags & POWERPC_FLAG_UBLE)
9429             printf("                        user BTB lock enable\n");
9430         if (env->flags & POWERPC_FLAG_BE)
9431             printf("                        branch-step trace mode\n");
9432         else if (env->flags & POWERPC_FLAG_DE)
9433             printf("                        debug interrupt enable\n");
9434         if (env->flags & POWERPC_FLAG_PX)
9435             printf("                        inclusive protection\n");
9436         else if (env->flags & POWERPC_FLAG_PMM)
9437             printf("                        performance monitor mark\n");
9438         if (env->flags == POWERPC_FLAG_NONE)
9439             printf("                        none\n");
9440         printf("    Time-base/decrementer clock source: %s\n",
9441                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9442     }
9443     dump_ppc_insns(env);
9444     dump_ppc_sprs(env);
9445     fflush(stdout);
9446 #endif
9447
9448     return 0;
9449 }
9450
9451 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9452 {
9453     const ppc_def_t *ret;
9454     uint32_t pvr_rev;
9455     int i, best, match, best_match, max;
9456
9457     ret = NULL;
9458     max = ARRAY_SIZE(ppc_defs);
9459     best = -1;
9460     pvr_rev = pvr & 0xFFFF;
9461     /* We want all specified bits to match */
9462     best_match = 32 - ctz32(pvr_rev);
9463     for (i = 0; i < max; i++) {
9464         /* We check that the 16 higher bits are the same to ensure the CPU
9465          * model will be the choosen one.
9466          */
9467         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9468             /* We want as much as possible of the low-level 16 bits
9469              * to be the same but we allow inexact matches.
9470              */
9471             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9472             /* We check '>=' instead of '>' because the PPC_defs table
9473              * is ordered by increasing revision.
9474              * Then, we will match the higher revision compatible
9475              * with the requested PVR
9476              */
9477             if (match >= best_match) {
9478                 best = i;
9479                 best_match = match;
9480             }
9481         }
9482     }
9483     if (best != -1)
9484         ret = &ppc_defs[best];
9485
9486     return ret;
9487 }
9488
9489 #include <ctype.h>
9490
9491 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9492 {
9493     const ppc_def_t *ret;
9494     const char *p;
9495     int i, max, len;
9496
9497     /* Check if the given name is a PVR */
9498     len = strlen(name);
9499     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9500         p = name + 2;
9501         goto check_pvr;
9502     } else if (len == 8) {
9503         p = name;
9504     check_pvr:
9505         for (i = 0; i < 8; i++) {
9506             if (!qemu_isxdigit(*p++))
9507                 break;
9508         }
9509         if (i == 8)
9510             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9511     }
9512     ret = NULL;
9513     max = ARRAY_SIZE(ppc_defs);
9514     for (i = 0; i < max; i++) {
9515         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9516             ret = &ppc_defs[i];
9517             break;
9518         }
9519     }
9520
9521     return ret;
9522 }
9523
9524 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9525 {
9526     int i, max;
9527
9528     max = ARRAY_SIZE(ppc_defs);
9529     for (i = 0; i < max; i++) {
9530         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9531                        ppc_defs[i].name, ppc_defs[i].pvr);
9532     }
9533 }