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Fix Thumb variable shift condition code bug.
[qemu/mini2440.git] / mips-dis.c
blobf6128955ca402f749ce5acd4a6d7ecbbef3f5d3b
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23 #include "dis-asm.h"
24
25 /* mips.h. Mips opcode list for GDB, the GNU debugger.
26 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
27 Free Software Foundation, Inc.
28 Contributed by Ralph Campbell and OSF
29 Commented and modified by Ian Lance Taylor, Cygnus Support
30
31 This file is part of GDB, GAS, and the GNU binutils.
32
33 GDB, GAS, and the GNU binutils are free software; you can redistribute
34 them and/or modify them under the terms of the GNU General Public
35 License as published by the Free Software Foundation; either version
36 1, or (at your option) any later version.
37
38 GDB, GAS, and the GNU binutils are distributed in the hope that they
39 will be useful, but WITHOUT ANY WARRANTY; without even the implied
40 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
41 the GNU General Public License for more details.
42
43 You should have received a copy of the GNU General Public License
44 along with this file; see the file COPYING. If not, write to the Free
45 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
46
47 /* mips.h. Mips opcode list for GDB, the GNU debugger.
48 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
49 Free Software Foundation, Inc.
50 Contributed by Ralph Campbell and OSF
51 Commented and modified by Ian Lance Taylor, Cygnus Support
52
53 This file is part of GDB, GAS, and the GNU binutils.
54
55 GDB, GAS, and the GNU binutils are free software; you can redistribute
56 them and/or modify them under the terms of the GNU General Public
57 License as published by the Free Software Foundation; either version
58 1, or (at your option) any later version.
59
60 GDB, GAS, and the GNU binutils are distributed in the hope that they
61 will be useful, but WITHOUT ANY WARRANTY; without even the implied
62 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
63 the GNU General Public License for more details.
64
65 You should have received a copy of the GNU General Public License
66 along with this file; see the file COPYING. If not, write to the Free
67 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
68
69 /* These are bit masks and shift counts to use to access the various
70 fields of an instruction. To retrieve the X field of an
71 instruction, use the expression
72 (i >> OP_SH_X) & OP_MASK_X
73 To set the same field (to j), use
74 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
75
76 Make sure you use fields that are appropriate for the instruction,
77 of course.
78
79 The 'i' format uses OP, RS, RT and IMMEDIATE.
80
81 The 'j' format uses OP and TARGET.
82
83 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
84
85 The 'b' format uses OP, RS, RT and DELTA.
86
87 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
88
89 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
90
91 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
92 breakpoint instruction are not defined; Kane says the breakpoint
93 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
94 only use ten bits). An optional two-operand form of break/sdbbp
95 allows the lower ten bits to be set too, and MIPS32 and later
96 architectures allow 20 bits to be set with a signal operand
97 (using CODE20).
98
99 The syscall instruction uses CODE20.
100
101 The general coprocessor instructions use COPZ. */
102
103 #define OP_MASK_OP 0x3f
104 #define OP_SH_OP 26
105 #define OP_MASK_RS 0x1f
106 #define OP_SH_RS 21
107 #define OP_MASK_FR 0x1f
108 #define OP_SH_FR 21
109 #define OP_MASK_FMT 0x1f
110 #define OP_SH_FMT 21
111 #define OP_MASK_BCC 0x7
112 #define OP_SH_BCC 18
113 #define OP_MASK_CODE 0x3ff
114 #define OP_SH_CODE 16
115 #define OP_MASK_CODE2 0x3ff
116 #define OP_SH_CODE2 6
117 #define OP_MASK_RT 0x1f
118 #define OP_SH_RT 16
119 #define OP_MASK_FT 0x1f
120 #define OP_SH_FT 16
121 #define OP_MASK_CACHE 0x1f
122 #define OP_SH_CACHE 16
123 #define OP_MASK_RD 0x1f
124 #define OP_SH_RD 11
125 #define OP_MASK_FS 0x1f
126 #define OP_SH_FS 11
127 #define OP_MASK_PREFX 0x1f
128 #define OP_SH_PREFX 11
129 #define OP_MASK_CCC 0x7
130 #define OP_SH_CCC 8
131 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
132 #define OP_SH_CODE20 6
133 #define OP_MASK_SHAMT 0x1f
134 #define OP_SH_SHAMT 6
135 #define OP_MASK_FD 0x1f
136 #define OP_SH_FD 6
137 #define OP_MASK_TARGET 0x3ffffff
138 #define OP_SH_TARGET 0
139 #define OP_MASK_COPZ 0x1ffffff
140 #define OP_SH_COPZ 0
141 #define OP_MASK_IMMEDIATE 0xffff
142 #define OP_SH_IMMEDIATE 0
143 #define OP_MASK_DELTA 0xffff
144 #define OP_SH_DELTA 0
145 #define OP_MASK_FUNCT 0x3f
146 #define OP_SH_FUNCT 0
147 #define OP_MASK_SPEC 0x3f
148 #define OP_SH_SPEC 0
149 #define OP_SH_LOCC 8 /* FP condition code. */
150 #define OP_SH_HICC 18 /* FP condition code. */
151 #define OP_MASK_CC 0x7
152 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
153 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
154 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
155 #define OP_MASK_COP1SPEC 0xf
156 #define OP_MASK_COP1SCLR 0x4
157 #define OP_MASK_COP1CMP 0x3
158 #define OP_SH_COP1CMP 4
159 #define OP_SH_FORMAT 21 /* FP short format field. */
160 #define OP_MASK_FORMAT 0x7
161 #define OP_SH_TRUE 16
162 #define OP_MASK_TRUE 0x1
163 #define OP_SH_GE 17
164 #define OP_MASK_GE 0x01
165 #define OP_SH_UNSIGNED 16
166 #define OP_MASK_UNSIGNED 0x1
167 #define OP_SH_HINT 16
168 #define OP_MASK_HINT 0x1f
169 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
170 #define OP_MASK_MMI 0x3f
171 #define OP_SH_MMISUB 6
172 #define OP_MASK_MMISUB 0x1f
173 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
174 #define OP_SH_PERFREG 1
175 #define OP_SH_SEL 0 /* Coprocessor select field. */
176 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
177 #define OP_SH_CODE19 6 /* 19 bit wait code. */
178 #define OP_MASK_CODE19 0x7ffff
179 #define OP_SH_ALN 21
180 #define OP_MASK_ALN 0x7
181 #define OP_SH_VSEL 21
182 #define OP_MASK_VSEL 0x1f
183 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
184 but 0x8-0xf don't select bytes. */
185 #define OP_SH_VECBYTE 22
186 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
187 #define OP_SH_VECALIGN 21
188 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
189 #define OP_SH_INSMSB 11
190 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
191 #define OP_SH_EXTMSBD 11
192
193 #define OP_OP_COP0 0x10
194 #define OP_OP_COP1 0x11
195 #define OP_OP_COP2 0x12
196 #define OP_OP_COP3 0x13
197 #define OP_OP_LWC1 0x31
198 #define OP_OP_LWC2 0x32
199 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
200 #define OP_OP_LDC1 0x35
201 #define OP_OP_LDC2 0x36
202 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
203 #define OP_OP_SWC1 0x39
204 #define OP_OP_SWC2 0x3a
205 #define OP_OP_SWC3 0x3b
206 #define OP_OP_SDC1 0x3d
207 #define OP_OP_SDC2 0x3e
208 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
209
210 /* Values in the 'VSEL' field. */
211 #define MDMX_FMTSEL_IMM_QH 0x1d
212 #define MDMX_FMTSEL_IMM_OB 0x1e
213 #define MDMX_FMTSEL_VEC_QH 0x15
214 #define MDMX_FMTSEL_VEC_OB 0x16
215
216 /* This structure holds information for a particular instruction. */
217
218 struct mips_opcode
219 {
220 /* The name of the instruction. */
221 const char *name;
222 /* A string describing the arguments for this instruction. */
223 const char *args;
224 /* The basic opcode for the instruction. When assembling, this
225 opcode is modified by the arguments to produce the actual opcode
226 that is used. If pinfo is INSN_MACRO, then this is 0. */
227 unsigned long match;
228 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
229 relevant portions of the opcode when disassembling. If the
230 actual opcode anded with the match field equals the opcode field,
231 then we have found the correct instruction. If pinfo is
232 INSN_MACRO, then this field is the macro identifier. */
233 unsigned long mask;
234 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
235 of bits describing the instruction, notably any relevant hazard
236 information. */
237 unsigned long pinfo;
238 /* A collection of bits describing the instruction sets of which this
239 instruction or macro is a member. */
240 unsigned long membership;
241 };
242
243 /* These are the characters which may appear in the args field of an
244 instruction. They appear in the order in which the fields appear
245 when the instruction is used. Commas and parentheses in the args
246 string are ignored when assembling, and written into the output
247 when disassembling.
248
249 Each of these characters corresponds to a mask field defined above.
250
251 "<" 5 bit shift amount (OP_*_SHAMT)
252 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
253 "a" 26 bit target address (OP_*_TARGET)
254 "b" 5 bit base register (OP_*_RS)
255 "c" 10 bit breakpoint code (OP_*_CODE)
256 "d" 5 bit destination register specifier (OP_*_RD)
257 "h" 5 bit prefx hint (OP_*_PREFX)
258 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
259 "j" 16 bit signed immediate (OP_*_DELTA)
260 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
261 Also used for immediate operands in vr5400 vector insns.
262 "o" 16 bit signed offset (OP_*_DELTA)
263 "p" 16 bit PC relative branch target address (OP_*_DELTA)
264 "q" 10 bit extra breakpoint code (OP_*_CODE2)
265 "r" 5 bit same register used as both source and target (OP_*_RS)
266 "s" 5 bit source register specifier (OP_*_RS)
267 "t" 5 bit target register (OP_*_RT)
268 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
269 "v" 5 bit same register used as both source and destination (OP_*_RS)
270 "w" 5 bit same register used as both target and destination (OP_*_RT)
271 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
272 (used by clo and clz)
273 "C" 25 bit coprocessor function code (OP_*_COPZ)
274 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
275 "J" 19 bit wait function code (OP_*_CODE19)
276 "x" accept and ignore register name
277 "z" must be zero register
278 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
279 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
280 Enforces: 0 <= pos < 32.
281 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
282 Requires that "+A" or "+E" occur first to set position.
283 Enforces: 0 < (pos+size) <= 32.
284 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
285 Requires that "+A" or "+E" occur first to set position.
286 Enforces: 0 < (pos+size) <= 32.
287 (Also used by "dext" w/ different limits, but limits for
288 that are checked by the M_DEXT macro.)
289 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
290 Enforces: 32 <= pos < 64.
291 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
292 Requires that "+A" or "+E" occur first to set position.
293 Enforces: 32 < (pos+size) <= 64.
294 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
295 Requires that "+A" or "+E" occur first to set position.
296 Enforces: 32 < (pos+size) <= 64.
297 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
298 Requires that "+A" or "+E" occur first to set position.
299 Enforces: 32 < (pos+size) <= 64.
300
301 Floating point instructions:
302 "D" 5 bit destination register (OP_*_FD)
303 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
304 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
305 "S" 5 bit fs source 1 register (OP_*_FS)
306 "T" 5 bit ft source 2 register (OP_*_FT)
307 "R" 5 bit fr source 3 register (OP_*_FR)
308 "V" 5 bit same register used as floating source and destination (OP_*_FS)
309 "W" 5 bit same register used as floating target and destination (OP_*_FT)
310
311 Coprocessor instructions:
312 "E" 5 bit target register (OP_*_RT)
313 "G" 5 bit destination register (OP_*_RD)
314 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
315 "P" 5 bit performance-monitor register (OP_*_PERFREG)
316 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
317 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
318 see also "k" above
319 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
320 for pretty-printing in disassembly only.
321
322 Macro instructions:
323 "A" General 32 bit expression
324 "I" 32 bit immediate (value placed in imm_expr).
325 "+I" 32 bit immediate (value placed in imm2_expr).
326 "F" 64 bit floating point constant in .rdata
327 "L" 64 bit floating point constant in .lit8
328 "f" 32 bit floating point constant
329 "l" 32 bit floating point constant in .lit4
330
331 MDMX instruction operands (note that while these use the FP register
332 fields, they accept both $fN and $vN names for the registers):
333 "O" MDMX alignment offset (OP_*_ALN)
334 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
335 "X" MDMX destination register (OP_*_FD)
336 "Y" MDMX source register (OP_*_FS)
337 "Z" MDMX source register (OP_*_FT)
338
339 Other:
340 "()" parens surrounding optional value
341 "," separates operands
342 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
343 "+" Start of extension sequence.
344
345 Characters used so far, for quick reference when adding more:
346 "%[]<>(),+"
347 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
348 "abcdefhijklopqrstuvwxz"
349
350 Extension character sequences used so far ("+" followed by the
351 following), for quick reference when adding more:
352 "ABCDEFGHI"
353 */
354
355 /* These are the bits which may be set in the pinfo field of an
356 instructions, if it is not equal to INSN_MACRO. */
357
358 /* Modifies the general purpose register in OP_*_RD. */
359 #define INSN_WRITE_GPR_D 0x00000001
360 /* Modifies the general purpose register in OP_*_RT. */
361 #define INSN_WRITE_GPR_T 0x00000002
362 /* Modifies general purpose register 31. */
363 #define INSN_WRITE_GPR_31 0x00000004
364 /* Modifies the floating point register in OP_*_FD. */
365 #define INSN_WRITE_FPR_D 0x00000008
366 /* Modifies the floating point register in OP_*_FS. */
367 #define INSN_WRITE_FPR_S 0x00000010
368 /* Modifies the floating point register in OP_*_FT. */
369 #define INSN_WRITE_FPR_T 0x00000020
370 /* Reads the general purpose register in OP_*_RS. */
371 #define INSN_READ_GPR_S 0x00000040
372 /* Reads the general purpose register in OP_*_RT. */
373 #define INSN_READ_GPR_T 0x00000080
374 /* Reads the floating point register in OP_*_FS. */
375 #define INSN_READ_FPR_S 0x00000100
376 /* Reads the floating point register in OP_*_FT. */
377 #define INSN_READ_FPR_T 0x00000200
378 /* Reads the floating point register in OP_*_FR. */
379 #define INSN_READ_FPR_R 0x00000400
380 /* Modifies coprocessor condition code. */
381 #define INSN_WRITE_COND_CODE 0x00000800
382 /* Reads coprocessor condition code. */
383 #define INSN_READ_COND_CODE 0x00001000
384 /* TLB operation. */
385 #define INSN_TLB 0x00002000
386 /* Reads coprocessor register other than floating point register. */
387 #define INSN_COP 0x00004000
388 /* Instruction loads value from memory, requiring delay. */
389 #define INSN_LOAD_MEMORY_DELAY 0x00008000
390 /* Instruction loads value from coprocessor, requiring delay. */
391 #define INSN_LOAD_COPROC_DELAY 0x00010000
392 /* Instruction has unconditional branch delay slot. */
393 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
394 /* Instruction has conditional branch delay slot. */
395 #define INSN_COND_BRANCH_DELAY 0x00040000
396 /* Conditional branch likely: if branch not taken, insn nullified. */
397 #define INSN_COND_BRANCH_LIKELY 0x00080000
398 /* Moves to coprocessor register, requiring delay. */
399 #define INSN_COPROC_MOVE_DELAY 0x00100000
400 /* Loads coprocessor register from memory, requiring delay. */
401 #define INSN_COPROC_MEMORY_DELAY 0x00200000
402 /* Reads the HI register. */
403 #define INSN_READ_HI 0x00400000
404 /* Reads the LO register. */
405 #define INSN_READ_LO 0x00800000
406 /* Modifies the HI register. */
407 #define INSN_WRITE_HI 0x01000000
408 /* Modifies the LO register. */
409 #define INSN_WRITE_LO 0x02000000
410 /* Takes a trap (easier to keep out of delay slot). */
411 #define INSN_TRAP 0x04000000
412 /* Instruction stores value into memory. */
413 #define INSN_STORE_MEMORY 0x08000000
414 /* Instruction uses single precision floating point. */
415 #define FP_S 0x10000000
416 /* Instruction uses double precision floating point. */
417 #define FP_D 0x20000000
418 /* Instruction is part of the tx39's integer multiply family. */
419 #define INSN_MULT 0x40000000
420 /* Instruction synchronize shared memory. */
421 #define INSN_SYNC 0x80000000
422 /* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
423 #define INSN_READ_MDMX_ACC 0
424 /* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
425 #define INSN_WRITE_MDMX_ACC 0
426
427 /* Instruction is actually a macro. It should be ignored by the
428 disassembler, and requires special treatment by the assembler. */
429 #define INSN_MACRO 0xffffffff
430
431 /* Masks used to mark instructions to indicate which MIPS ISA level
432 they were introduced in. ISAs, as defined below, are logical
433 ORs of these bits, indicating that they support the instructions
434 defined at the given level. */
435
436 #define INSN_ISA_MASK 0x00000fff
437 #define INSN_ISA1 0x00000001
438 #define INSN_ISA2 0x00000002
439 #define INSN_ISA3 0x00000004
440 #define INSN_ISA4 0x00000008
441 #define INSN_ISA5 0x00000010
442 #define INSN_ISA32 0x00000020
443 #define INSN_ISA64 0x00000040
444 #define INSN_ISA32R2 0x00000080
445 #define INSN_ISA64R2 0x00000100
446
447 /* Masks used for MIPS-defined ASEs. */
448 #define INSN_ASE_MASK 0x0000f000
449
450 /* MIPS 16 ASE */
451 #define INSN_MIPS16 0x00002000
452 /* MIPS-3D ASE */
453 #define INSN_MIPS3D 0x00004000
454 /* MDMX ASE */
455 #define INSN_MDMX 0x00008000
456
457 /* Chip specific instructions. These are bitmasks. */
458
459 /* MIPS R4650 instruction. */
460 #define INSN_4650 0x00010000
461 /* LSI R4010 instruction. */
462 #define INSN_4010 0x00020000
463 /* NEC VR4100 instruction. */
464 #define INSN_4100 0x00040000
465 /* Toshiba R3900 instruction. */
466 #define INSN_3900 0x00080000
467 /* MIPS R10000 instruction. */
468 #define INSN_10000 0x00100000
469 /* Broadcom SB-1 instruction. */
470 #define INSN_SB1 0x00200000
471 /* NEC VR4111/VR4181 instruction. */
472 #define INSN_4111 0x00400000
473 /* NEC VR4120 instruction. */
474 #define INSN_4120 0x00800000
475 /* NEC VR5400 instruction. */
476 #define INSN_5400 0x01000000
477 /* NEC VR5500 instruction. */
478 #define INSN_5500 0x02000000
479
480 /* MIPS ISA defines, use instead of hardcoding ISA level. */
481
482 #define ISA_UNKNOWN 0 /* Gas internal use. */
483 #define ISA_MIPS1 (INSN_ISA1)
484 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
485 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
486 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
487 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
488
489 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
490 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
491
492 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
493 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
494
495
496 /* CPU defines, use instead of hardcoding processor number. Keep this
497 in sync with bfd/archures.c in order for machine selection to work. */
498 #define CPU_UNKNOWN 0 /* Gas internal use. */
499 #define CPU_R3000 3000
500 #define CPU_R3900 3900
501 #define CPU_R4000 4000
502 #define CPU_R4010 4010
503 #define CPU_VR4100 4100
504 #define CPU_R4111 4111
505 #define CPU_VR4120 4120
506 #define CPU_R4300 4300
507 #define CPU_R4400 4400
508 #define CPU_R4600 4600
509 #define CPU_R4650 4650
510 #define CPU_R5000 5000
511 #define CPU_VR5400 5400
512 #define CPU_VR5500 5500
513 #define CPU_R6000 6000
514 #define CPU_RM7000 7000
515 #define CPU_R8000 8000
516 #define CPU_R10000 10000
517 #define CPU_R12000 12000
518 #define CPU_MIPS16 16
519 #define CPU_MIPS32 32
520 #define CPU_MIPS32R2 33
521 #define CPU_MIPS5 5
522 #define CPU_MIPS64 64
523 #define CPU_MIPS64R2 65
524 #define CPU_SB1 12310201 /* octal 'SB', 01. */
525
526 /* Test for membership in an ISA including chip specific ISAs. INSN
527 is pointer to an element of the opcode table; ISA is the specified
528 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
529 test, or zero if no CPU specific ISA test is desired. */
530
531 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
532 (((insn)->membership & isa) != 0 \
533 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
534 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
535 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
536 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
537 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
538 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
539 && ((insn)->membership & INSN_10000) != 0) \
540 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
541 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
542 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
543 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
544 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
545 || 0) /* Please keep this term for easier source merging. */
546
547 /* This is a list of macro expanded instructions.
548
549 _I appended means immediate
550 _A appended means address
551 _AB appended means address with base register
552 _D appended means 64 bit floating point constant
553 _S appended means 32 bit floating point constant. */
554
555 enum
556 {
557 M_ABS,
558 M_ADD_I,
559 M_ADDU_I,
560 M_AND_I,
561 M_BEQ,
562 M_BEQ_I,
563 M_BEQL_I,
564 M_BGE,
565 M_BGEL,
566 M_BGE_I,
567 M_BGEL_I,
568 M_BGEU,
569 M_BGEUL,
570 M_BGEU_I,
571 M_BGEUL_I,
572 M_BGT,
573 M_BGTL,
574 M_BGT_I,
575 M_BGTL_I,
576 M_BGTU,
577 M_BGTUL,
578 M_BGTU_I,
579 M_BGTUL_I,
580 M_BLE,
581 M_BLEL,
582 M_BLE_I,
583 M_BLEL_I,
584 M_BLEU,
585 M_BLEUL,
586 M_BLEU_I,
587 M_BLEUL_I,
588 M_BLT,
589 M_BLTL,
590 M_BLT_I,
591 M_BLTL_I,
592 M_BLTU,
593 M_BLTUL,
594 M_BLTU_I,
595 M_BLTUL_I,
596 M_BNE,
597 M_BNE_I,
598 M_BNEL_I,
599 M_DABS,
600 M_DADD_I,
601 M_DADDU_I,
602 M_DDIV_3,
603 M_DDIV_3I,
604 M_DDIVU_3,
605 M_DDIVU_3I,
606 M_DEXT,
607 M_DINS,
608 M_DIV_3,
609 M_DIV_3I,
610 M_DIVU_3,
611 M_DIVU_3I,
612 M_DLA_AB,
613 M_DLCA_AB,
614 M_DLI,
615 M_DMUL,
616 M_DMUL_I,
617 M_DMULO,
618 M_DMULO_I,
619 M_DMULOU,
620 M_DMULOU_I,
621 M_DREM_3,
622 M_DREM_3I,
623 M_DREMU_3,
624 M_DREMU_3I,
625 M_DSUB_I,
626 M_DSUBU_I,
627 M_DSUBU_I_2,
628 M_J_A,
629 M_JAL_1,
630 M_JAL_2,
631 M_JAL_A,
632 M_L_DOB,
633 M_L_DAB,
634 M_LA_AB,
635 M_LB_A,
636 M_LB_AB,
637 M_LBU_A,
638 M_LBU_AB,
639 M_LCA_AB,
640 M_LD_A,
641 M_LD_OB,
642 M_LD_AB,
643 M_LDC1_AB,
644 M_LDC2_AB,
645 M_LDC3_AB,
646 M_LDL_AB,
647 M_LDR_AB,
648 M_LH_A,
649 M_LH_AB,
650 M_LHU_A,
651 M_LHU_AB,
652 M_LI,
653 M_LI_D,
654 M_LI_DD,
655 M_LI_S,
656 M_LI_SS,
657 M_LL_AB,
658 M_LLD_AB,
659 M_LS_A,
660 M_LW_A,
661 M_LW_AB,
662 M_LWC0_A,
663 M_LWC0_AB,
664 M_LWC1_A,
665 M_LWC1_AB,
666 M_LWC2_A,
667 M_LWC2_AB,
668 M_LWC3_A,
669 M_LWC3_AB,
670 M_LWL_A,
671 M_LWL_AB,
672 M_LWR_A,
673 M_LWR_AB,
674 M_LWU_AB,
675 M_MOVE,
676 M_MUL,
677 M_MUL_I,
678 M_MULO,
679 M_MULO_I,
680 M_MULOU,
681 M_MULOU_I,
682 M_NOR_I,
683 M_OR_I,
684 M_REM_3,
685 M_REM_3I,
686 M_REMU_3,
687 M_REMU_3I,
688 M_DROL,
689 M_ROL,
690 M_DROL_I,
691 M_ROL_I,
692 M_DROR,
693 M_ROR,
694 M_DROR_I,
695 M_ROR_I,
696 M_S_DA,
697 M_S_DOB,
698 M_S_DAB,
699 M_S_S,
700 M_SC_AB,
701 M_SCD_AB,
702 M_SD_A,
703 M_SD_OB,
704 M_SD_AB,
705 M_SDC1_AB,
706 M_SDC2_AB,
707 M_SDC3_AB,
708 M_SDL_AB,
709 M_SDR_AB,
710 M_SEQ,
711 M_SEQ_I,
712 M_SGE,
713 M_SGE_I,
714 M_SGEU,
715 M_SGEU_I,
716 M_SGT,
717 M_SGT_I,
718 M_SGTU,
719 M_SGTU_I,
720 M_SLE,
721 M_SLE_I,
722 M_SLEU,
723 M_SLEU_I,
724 M_SLT_I,
725 M_SLTU_I,
726 M_SNE,
727 M_SNE_I,
728 M_SB_A,
729 M_SB_AB,
730 M_SH_A,
731 M_SH_AB,
732 M_SW_A,
733 M_SW_AB,
734 M_SWC0_A,
735 M_SWC0_AB,
736 M_SWC1_A,
737 M_SWC1_AB,
738 M_SWC2_A,
739 M_SWC2_AB,
740 M_SWC3_A,
741 M_SWC3_AB,
742 M_SWL_A,
743 M_SWL_AB,
744 M_SWR_A,
745 M_SWR_AB,
746 M_SUB_I,
747 M_SUBU_I,
748 M_SUBU_I_2,
749 M_TEQ_I,
750 M_TGE_I,
751 M_TGEU_I,
752 M_TLT_I,
753 M_TLTU_I,
754 M_TNE_I,
755 M_TRUNCWD,
756 M_TRUNCWS,
757 M_ULD,
758 M_ULD_A,
759 M_ULH,
760 M_ULH_A,
761 M_ULHU,
762 M_ULHU_A,
763 M_ULW,
764 M_ULW_A,
765 M_USH,
766 M_USH_A,
767 M_USW,
768 M_USW_A,
769 M_USD,
770 M_USD_A,
771 M_XOR_I,
772 M_COP0,
773 M_COP1,
774 M_COP2,
775 M_COP3,
776 M_NUM_MACROS
777 };
778
779
780 /* The order of overloaded instructions matters. Label arguments and
781 register arguments look the same. Instructions that can have either
782 for arguments must apear in the correct order in this table for the
783 assembler to pick the right one. In other words, entries with
784 immediate operands must apear after the same instruction with
785 registers.
786
787 Many instructions are short hand for other instructions (i.e., The
788 jal <register> instruction is short for jalr <register>). */
789
790 extern const struct mips_opcode mips_builtin_opcodes[];
791 extern const int bfd_mips_num_builtin_opcodes;
792 extern struct mips_opcode *mips_opcodes;
793 extern int bfd_mips_num_opcodes;
794 #define NUMOPCODES bfd_mips_num_opcodes
795
796 \f
797 /* The rest of this file adds definitions for the mips16 TinyRISC
798 processor. */
799
800 /* These are the bitmasks and shift counts used for the different
801 fields in the instruction formats. Other than OP, no masks are
802 provided for the fixed portions of an instruction, since they are
803 not needed.
804
805 The I format uses IMM11.
806
807 The RI format uses RX and IMM8.
808
809 The RR format uses RX, and RY.
810
811 The RRI format uses RX, RY, and IMM5.
812
813 The RRR format uses RX, RY, and RZ.
814
815 The RRI_A format uses RX, RY, and IMM4.
816
817 The SHIFT format uses RX, RY, and SHAMT.
818
819 The I8 format uses IMM8.
820
821 The I8_MOVR32 format uses RY and REGR32.
822
823 The IR_MOV32R format uses REG32R and MOV32Z.
824
825 The I64 format uses IMM8.
826
827 The RI64 format uses RY and IMM5.
828 */
829
830 #define MIPS16OP_MASK_OP 0x1f
831 #define MIPS16OP_SH_OP 11
832 #define MIPS16OP_MASK_IMM11 0x7ff
833 #define MIPS16OP_SH_IMM11 0
834 #define MIPS16OP_MASK_RX 0x7
835 #define MIPS16OP_SH_RX 8
836 #define MIPS16OP_MASK_IMM8 0xff
837 #define MIPS16OP_SH_IMM8 0
838 #define MIPS16OP_MASK_RY 0x7
839 #define MIPS16OP_SH_RY 5
840 #define MIPS16OP_MASK_IMM5 0x1f
841 #define MIPS16OP_SH_IMM5 0
842 #define MIPS16OP_MASK_RZ 0x7
843 #define MIPS16OP_SH_RZ 2
844 #define MIPS16OP_MASK_IMM4 0xf
845 #define MIPS16OP_SH_IMM4 0
846 #define MIPS16OP_MASK_REGR32 0x1f
847 #define MIPS16OP_SH_REGR32 0
848 #define MIPS16OP_MASK_REG32R 0x1f
849 #define MIPS16OP_SH_REG32R 3
850 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
851 #define MIPS16OP_MASK_MOVE32Z 0x7
852 #define MIPS16OP_SH_MOVE32Z 0
853 #define MIPS16OP_MASK_IMM6 0x3f
854 #define MIPS16OP_SH_IMM6 5
855
856 /* These are the characters which may appears in the args field of an
857 instruction. They appear in the order in which the fields appear
858 when the instruction is used. Commas and parentheses in the args
859 string are ignored when assembling, and written into the output
860 when disassembling.
861
862 "y" 3 bit register (MIPS16OP_*_RY)
863 "x" 3 bit register (MIPS16OP_*_RX)
864 "z" 3 bit register (MIPS16OP_*_RZ)
865 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
866 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
867 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
868 "0" zero register ($0)
869 "S" stack pointer ($sp or $29)
870 "P" program counter
871 "R" return address register ($ra or $31)
872 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
873 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
874 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
875 "a" 26 bit jump address
876 "e" 11 bit extension value
877 "l" register list for entry instruction
878 "L" register list for exit instruction
879
880 The remaining codes may be extended. Except as otherwise noted,
881 the full extended operand is a 16 bit signed value.
882 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
883 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
884 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
885 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
886 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
887 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
888 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
889 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
890 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
891 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
892 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
893 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
894 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
895 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
896 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
897 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
898 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
899 "q" 11 bit branch address (MIPS16OP_*_IMM11)
900 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
901 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
902 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
903 */
904
905 /* For the mips16, we use the same opcode table format and a few of
906 the same flags. However, most of the flags are different. */
907
908 /* Modifies the register in MIPS16OP_*_RX. */
909 #define MIPS16_INSN_WRITE_X 0x00000001
910 /* Modifies the register in MIPS16OP_*_RY. */
911 #define MIPS16_INSN_WRITE_Y 0x00000002
912 /* Modifies the register in MIPS16OP_*_RZ. */
913 #define MIPS16_INSN_WRITE_Z 0x00000004
914 /* Modifies the T ($24) register. */
915 #define MIPS16_INSN_WRITE_T 0x00000008
916 /* Modifies the SP ($29) register. */
917 #define MIPS16_INSN_WRITE_SP 0x00000010
918 /* Modifies the RA ($31) register. */
919 #define MIPS16_INSN_WRITE_31 0x00000020
920 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
921 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
922 /* Reads the register in MIPS16OP_*_RX. */
923 #define MIPS16_INSN_READ_X 0x00000080
924 /* Reads the register in MIPS16OP_*_RY. */
925 #define MIPS16_INSN_READ_Y 0x00000100
926 /* Reads the register in MIPS16OP_*_MOVE32Z. */
927 #define MIPS16_INSN_READ_Z 0x00000200
928 /* Reads the T ($24) register. */
929 #define MIPS16_INSN_READ_T 0x00000400
930 /* Reads the SP ($29) register. */
931 #define MIPS16_INSN_READ_SP 0x00000800
932 /* Reads the RA ($31) register. */
933 #define MIPS16_INSN_READ_31 0x00001000
934 /* Reads the program counter. */
935 #define MIPS16_INSN_READ_PC 0x00002000
936 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
937 #define MIPS16_INSN_READ_GPR_X 0x00004000
938 /* Is a branch insn. */
939 #define MIPS16_INSN_BRANCH 0x00010000
940
941 /* The following flags have the same value for the mips16 opcode
942 table:
943 INSN_UNCOND_BRANCH_DELAY
944 INSN_COND_BRANCH_DELAY
945 INSN_COND_BRANCH_LIKELY (never used)
946 INSN_READ_HI
947 INSN_READ_LO
948 INSN_WRITE_HI
949 INSN_WRITE_LO
950 INSN_TRAP
951 INSN_ISA3
952 */
953
954 extern const struct mips_opcode mips16_opcodes[];
955 extern const int bfd_mips16_num_opcodes;
956
957 /* Short hand so the lines aren't too long. */
958
959 #define LDD INSN_LOAD_MEMORY_DELAY
960 #define LCD INSN_LOAD_COPROC_DELAY
961 #define UBD INSN_UNCOND_BRANCH_DELAY
962 #define CBD INSN_COND_BRANCH_DELAY
963 #define COD INSN_COPROC_MOVE_DELAY
964 #define CLD INSN_COPROC_MEMORY_DELAY
965 #define CBL INSN_COND_BRANCH_LIKELY
966 #define TRAP INSN_TRAP
967 #define SM INSN_STORE_MEMORY
968
969 #define WR_d INSN_WRITE_GPR_D
970 #define WR_t INSN_WRITE_GPR_T
971 #define WR_31 INSN_WRITE_GPR_31
972 #define WR_D INSN_WRITE_FPR_D
973 #define WR_T INSN_WRITE_FPR_T
974 #define WR_S INSN_WRITE_FPR_S
975 #define RD_s INSN_READ_GPR_S
976 #define RD_b INSN_READ_GPR_S
977 #define RD_t INSN_READ_GPR_T
978 #define RD_S INSN_READ_FPR_S
979 #define RD_T INSN_READ_FPR_T
980 #define RD_R INSN_READ_FPR_R
981 #define WR_CC INSN_WRITE_COND_CODE
982 #define RD_CC INSN_READ_COND_CODE
983 #define RD_C0 INSN_COP
984 #define RD_C1 INSN_COP
985 #define RD_C2 INSN_COP
986 #define RD_C3 INSN_COP
987 #define WR_C0 INSN_COP
988 #define WR_C1 INSN_COP
989 #define WR_C2 INSN_COP
990 #define WR_C3 INSN_COP
991
992 #define WR_HI INSN_WRITE_HI
993 #define RD_HI INSN_READ_HI
994 #define MOD_HI WR_HI|RD_HI
995
996 #define WR_LO INSN_WRITE_LO
997 #define RD_LO INSN_READ_LO
998 #define MOD_LO WR_LO|RD_LO
999
1000 #define WR_HILO WR_HI|WR_LO
1001 #define RD_HILO RD_HI|RD_LO
1002 #define MOD_HILO WR_HILO|RD_HILO
1003
1004 #define IS_M INSN_MULT
1005
1006 #define WR_MACC INSN_WRITE_MDMX_ACC
1007 #define RD_MACC INSN_READ_MDMX_ACC
1008
1009 #define I1 INSN_ISA1
1010 #define I2 INSN_ISA2
1011 #define I3 INSN_ISA3
1012 #define I4 INSN_ISA4
1013 #define I5 INSN_ISA5
1014 #define I32 INSN_ISA32
1015 #define I64 INSN_ISA64
1016 #define I33 INSN_ISA32R2
1017 #define I65 INSN_ISA64R2
1018
1019 /* MIPS64 MIPS-3D ASE support. */
1020 #define I16 INSN_MIPS16
1021
1022 /* MIPS64 MIPS-3D ASE support. */
1023 #define M3D INSN_MIPS3D
1024
1025 /* MIPS64 MDMX ASE support. */
1026 #define MX INSN_MDMX
1027
1028 #define P3 INSN_4650
1029 #define L1 INSN_4010
1030 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1031 #define T3 INSN_3900
1032 #define M1 INSN_10000
1033 #define SB1 INSN_SB1
1034 #define N411 INSN_4111
1035 #define N412 INSN_4120
1036 #define N5 (INSN_5400 | INSN_5500)
1037 #define N54 INSN_5400
1038 #define N55 INSN_5500
1039
1040 #define G1 (T3 \
1041 )
1042
1043 #define G2 (T3 \
1044 )
1045
1046 #define G3 (I4 \
1047 )
1048
1049 /* The order of overloaded instructions matters. Label arguments and
1050 register arguments look the same. Instructions that can have either
1051 for arguments must apear in the correct order in this table for the
1052 assembler to pick the right one. In other words, entries with
1053 immediate operands must apear after the same instruction with
1054 registers.
1055
1056 Because of the lookup algorithm used, entries with the same opcode
1057 name must be contiguous.
1058
1059 Many instructions are short hand for other instructions (i.e., The
1060 jal <register> instruction is short for jalr <register>). */
1061
1062 const struct mips_opcode mips_builtin_opcodes[] =
1063 {
1064 /* These instructions appear first so that the disassembler will find
1065 them first. The assemblers uses a hash table based on the
1066 instruction name anyhow. */
1067 /* name, args, match, mask, pinfo, membership */
1068 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 },
1069 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
1070 {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */
1071 {"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */
1072 {"ehb", "", 0x000000c0, 0xffffffff, 0, I33 }, /* sll */
1073 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
1074 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
1075 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
1076 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
1077 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
1078 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
1079 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
1080 {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
1081 {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
1082 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
1083
1084 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
1085 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1086 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1087 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1088 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1089 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
1090 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1091 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1092 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1093 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1094 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1095 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1096 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1097 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1098 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1099 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1100 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
1101 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
1102 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1103 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1104 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1105 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1106 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
1107 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1108 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, N54 },
1109 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
1110 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
1111 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 },
1112 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
1113 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1114 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
1115 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1116 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1117 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1118 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1119 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1120 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
1121 /* b is at the top of the table. */
1122 /* bal is at the top of the table. */
1123 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
1124 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
1125 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
1126 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
1127 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1128 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1129 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1130 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1131 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
1132 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
1133 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
1134 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
1135 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
1136 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
1137 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
1138 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
1139 /* bc2* are at the bottom of the table. */
1140 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
1141 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
1142 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
1143 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
1144 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
1145 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1146 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
1147 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 },
1148 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
1149 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 },
1150 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 },
1151 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 },
1152 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 },
1153 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 },
1154 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 },
1155 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 },
1156 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 },
1157 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 },
1158 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
1159 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1160 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
1161 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 },
1162 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 },
1163 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 },
1164 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 },
1165 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 },
1166 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 },
1167 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 },
1168 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 },
1169 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 },
1170 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
1171 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1172 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 },
1173 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 },
1174 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 },
1175 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 },
1176 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 },
1177 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 },
1178 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 },
1179 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 },
1180 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
1181 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1182 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 },
1183 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 },
1184 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 },
1185 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 },
1186 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 },
1187 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 },
1188 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 },
1189 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 },
1190 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
1191 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1192 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
1193 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 },
1194 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
1195 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1196 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
1197 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 },
1198 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
1199 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 },
1200 {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
1201 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
1202 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
1203 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1204 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1205 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1206 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1207 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1208 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1209 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1210 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1211 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1212 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1213 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1214 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1215 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1216 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1217 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1218 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1219 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1220 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1221 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1222 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1223 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1224 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1225 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1226 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1227 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1228 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1229 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1230 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1231 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1232 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1233 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1234 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1235 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1236 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1237 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1238 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1239 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1240 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1241 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1242 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1243 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1244 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1245 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1246 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1247 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1248 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1249 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1250 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1251 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1252 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1253 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1254 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1255 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1256 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1257 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1258 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1259 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1260 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1261 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1262 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1263 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1264 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1265 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1266 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1267 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1268 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1269 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1270 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1271 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1272 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1273 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1274 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1275 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1276 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1277 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1278 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1279 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1280 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1281 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1282 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1283 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1284 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1285 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1286 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1287 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1288 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1289 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1290 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1291 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1292 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1293 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1294 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1295 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1296 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1297 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1298 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1299 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1300 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1301 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1302 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1303 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1304 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1305 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1306 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1307 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1308 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1309 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1310 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1311 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1312 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1313 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1314 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1315 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1316 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1317 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1318 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1319 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1320 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1321 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1322 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1323 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1324 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1325 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1326 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1327 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1328 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1329 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1330 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1331 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1332 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1333 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1334 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1335 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1336 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1337 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1338 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1339 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1340 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1341 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1342 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1343 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1344 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1345 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1346 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1347 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1348 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1349 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1350 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1351 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1352 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1353 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1354 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1355 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1356 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1357 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1358 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1359 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1360 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1361 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1362 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3},
1363 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1364 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1365 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1366 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1367 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
1368 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
1369 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
1370 /* cfc2 is at the bottom of the table. */
1371 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
1372 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
1373 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
1374 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
1375 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
1376 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
1377 /* ctc2 is at the bottom of the table. */
1378 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
1379 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1380 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
1381 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1382 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1383 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1384 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1385 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
1386 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1387 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
1388 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
1389 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1390 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1391 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
1392 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1393 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
1394 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
1395 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1396 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
1397 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
1398 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
1399 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1400 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
1401 {"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 },
1402 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 },
1403 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 },
1404 /* dctr and dctw are used on the r5000. */
1405 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
1406 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
1407 {"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 },
1408 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 },
1409 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 },
1410 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 },
1411 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 },
1412 /* For ddiv, see the comments about div. */
1413 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1414 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
1415 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
1416 /* For ddivu, see the comments about div. */
1417 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1418 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
1419 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
1420 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 },
1421 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 },
1422 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 },
1423 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 },
1424 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 },
1425 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 },
1426 /* The MIPS assembler treats the div opcode with two operands as
1427 though the first operand appeared twice (the first operand is both
1428 a source and a destination). To get the div machine instruction,
1429 you must use an explicit destination of $0. */
1430 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1431 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
1432 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
1433 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
1434 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1435 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1436 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1437 /* For divu, see the comments about div. */
1438 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1439 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
1440 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
1441 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
1442 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
1443 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, I3 },
1444 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
1445 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
1446 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
1447 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1448 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1449 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1450 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1451 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1452 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1453 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1454 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1455 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 },
1456 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
1457 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
1458 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
1459 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
1460 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
1461 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
1462 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
1463 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
1464 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
1465 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
1466 /* dmfc2 is at the bottom of the table. */
1467 /* dmtc2 is at the bottom of the table. */
1468 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 },
1469 {"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 },
1470 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 },
1471 {"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 },
1472 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
1473 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
1474 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
1475 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
1476 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
1477 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
1478 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1479 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1480 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
1481 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
1482 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1483 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
1484 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
1485 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1486 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
1487 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
1488 {"dret", "", 0x7000003e, 0xffffffff, 0, N5 },
1489 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
1490 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
1491 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
1492 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
1493 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 },
1494 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I65 },
1495 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5|I65 },
1496 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 },
1497 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 },
1498 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 },
1499 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 },
1500 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, I65 },
1501 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 },
1502 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 },
1503 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, I65 },
1504 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1505 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
1506 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
1507 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
1508 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
1509 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1510 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
1511 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
1512 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
1513 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
1514 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1515 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
1516 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
1517 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
1518 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
1519 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1520 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
1521 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1522 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
1523 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 },
1524 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 },
1525 {"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 },
1526 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 },
1527 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1528 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1529 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1530 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1531 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
1532 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
1533 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
1534 {"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
1535 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, I33 },
1536 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
1537 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, I33 },
1538 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
1539 /* SVR4 PIC code requires special handling for j, so it must be a
1540 macro. */
1541 {"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
1542 /* This form of j is used by the disassembler and internally by the
1543 assembler, but will never match user input (because the line above
1544 will match first). */
1545 {"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
1546 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
1547 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
1548 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, I33 },
1549 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, I33 },
1550 /* SVR4 PIC code requires special handling for jal, so it must be a
1551 macro. */
1552 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
1553 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
1554 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
1555 /* This form of jal is used by the disassembler and internally by the
1556 assembler, but will never match user input (because the line above
1557 will match first). */
1558 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
1559 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 },
1560 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
1561 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1562 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
1563 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1564 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
1565 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, I1 },
1566 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
1567 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
1568 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
1569 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
1570 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
1571 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
1572 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
1573 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
1574 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
1575 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
1576 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
1577 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
1578 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
1579 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
1580 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
1581 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
1582 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
1583 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
1584 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
1585 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1586 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
1587 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1588 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
1589 /* li is at the start of the table. */
1590 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
1591 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
1592 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
1593 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
1594 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
1595 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
1596 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
1597 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
1598 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
1599 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5|N55 },
1600 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1601 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
1602 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1603 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
1604 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
1605 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
1606 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1607 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1608 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
1609 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1610 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1611 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
1612 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1613 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
1614 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1615 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
1616 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
1617 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
1618 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1619 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
1620 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
1621 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
1622 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
1623 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
1624 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
1625 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1626 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1627 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1628 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1629 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1630 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1631 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1632 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1633 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1634 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1635 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1636 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1637 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
1638 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
1639 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1640 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1641 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1642 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1643 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
1644 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
1645 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1646 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1647 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
1648 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
1649 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1650 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N411 },
1651 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1652 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1653 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1654 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1655 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1656 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 },
1657 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 },
1658 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
1659 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
1660 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
1661 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
1662 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
1663 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
1664 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
1665 /* mfc2 is at the bottom of the table. */
1666 /* mfhc2 is at the bottom of the table. */
1667 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
1668 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
1669 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 },
1670 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
1671 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
1672 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1673 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1674 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1675 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1676 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1677 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1678 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1679 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1680 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
1681 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
1682 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1683 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1684 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
1685 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
1686 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
1687 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
1688 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
1689 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1690 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1691 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
1692 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
1693 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
1694 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
1695 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1696 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1697 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
1698 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
1699 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
1700 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
1701 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
1702 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1703 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1704 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
1705 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
1706 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1707 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1708 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1709 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1710 /* move is at the top of the table. */
1711 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1712 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1713 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1714 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1715 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1716 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 },
1717 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1718 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 },
1719 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 },
1720 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 },
1721 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
1722 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
1723 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
1724 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
1725 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
1726 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
1727 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
1728 /* mtc2 is at the bottom of the table. */
1729 /* mthc2 is at the bottom of the table. */
1730 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
1731 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
1732 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 },
1733 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
1734 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
1735 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1736 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1737 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1738 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1739 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1740 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1741 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1742 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1743 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3|N55},
1744 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N54 },
1745 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
1746 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
1747 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1748 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1749 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1750 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1751 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1752 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1753 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1754 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1755 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1756 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1757 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1758 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1759 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
1760 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
1761 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
1762 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
1763 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1764 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1765 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1766 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1767 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1768 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1769 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1770 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1771 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1772 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1773 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1774 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1775 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1776 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1777 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1778 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
1779 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1780 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
1781 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1782 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1783 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
1784 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
1785 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1786 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1787 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1788 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1789 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1790 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1791 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1792 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1793 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1794 /* nop is at the start of the table. */
1795 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1796 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
1797 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1798 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1799 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1800 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1801 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1802 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
1803 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1804 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
1805 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1806 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1807 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1808 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1809 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1810 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
1811 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1812 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1 },
1813 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1814 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1815 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1816 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1817 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1818 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1819 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1820 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1821 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1822 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1823 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1824 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1825 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1826 /* pref and prefx are at the start of the table. */
1827 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1828 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1829 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1830 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N54 },
1831 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1832 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1833 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N54 },
1834 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1835 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1836 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N54 },
1837 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1838 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
1839 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1840 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
1841 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D },
1842 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1843 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1844 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1845 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1846 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1847 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1848 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
1849 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
1850 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1851 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
1852 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
1853 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, I33 },
1854 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, I33 },
1855 {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
1856 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1857 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1858 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1859 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1860 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1861 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1862 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
1863 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
1864 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
1865 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
1866 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5|I33 },
1867 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I33 },
1868 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I33 },
1869 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I33 },
1870 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I33 },
1871 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I33 },
1872 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, I33 },
1873 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1874 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1875 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1876 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1877 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
1878 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1879 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
1880 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D },
1881 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1882 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1883 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1884 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1885 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1886 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1887 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1888 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, N54 },
1889 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1890 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
1891 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
1892 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
1893 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 },
1894 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
1895 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 },
1896 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1897 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
1898 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
1899 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
1900 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 },
1901 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 },
1902 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
1903 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
1904 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1905 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1906 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
1907 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
1908 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
1909 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 },
1910 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
1911 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 },
1912 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1913 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 },
1914 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 },
1915 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1916 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 },
1917 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1918 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
1919 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
1920 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, I33 },
1921 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, I33 },
1922 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
1923 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
1924 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
1925 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 },
1926 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 },
1927 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 },
1928 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 },
1929 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 },
1930 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 },
1931 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 },
1932 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 },
1933 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
1934 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
1935 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
1936 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1937 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1938 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1939 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1940 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1941 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1942 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1943 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1944 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1945 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1946 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1947 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1948 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1949 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1950 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
1951 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
1952 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
1953 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 },
1954 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1955 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
1956 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
1957 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1958 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1959 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1960 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1961 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1962 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
1963 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
1964 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
1965 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1966 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 },
1967 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 },
1968 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 },
1969 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1970 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1971 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1972 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1973 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
1974 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
1975 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1976 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1977 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
1978 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
1979 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1980 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1981 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1982 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1983 /* ssnop is at the start of the table. */
1984 {"standby", "", 0x42000021, 0xffffffff, 0, V1 },
1985 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1986 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
1987 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1988 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1989 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1990 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1991 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1992 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1993 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1994 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1995 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1996 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1997 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1998 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1999 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
2000 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
2001 {"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
2002 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5|N55 },
2003 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2004 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 },
2005 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
2006 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 },
2007 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
2008 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
2009 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2010 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2011 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
2012 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2013 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
2014 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 },
2015 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
2016 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 },
2017 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2018 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 },
2019 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
2020 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */
2021 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2022 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 },
2023 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
2024 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */
2025 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
2026 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
2027 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
2028 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
2029 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, I33 },
2030 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
2031 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
2032 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
2033 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2034 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2035 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
2036 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 },
2037 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
2038 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2039 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2040 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
2041 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
2042 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
2043 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2044 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2045 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
2046 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
2047 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
2048 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
2049 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
2050 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 },
2051 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
2052 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2053 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2054 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
2055 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
2056 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
2057 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2058 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2059 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
2060 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
2061 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
2062 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2063 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2064 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
2065 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
2066 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
2067 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
2068 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
2069 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
2070 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 },
2071 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
2072 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
2073 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 },
2074 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 },
2075 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 },
2076 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 },
2077 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 },
2078 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 },
2079 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 },
2080 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 },
2081 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 },
2082 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 },
2083 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 },
2084 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 },
2085 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
2086 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
2087 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
2088 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 },
2089 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N54 },
2090 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
2091 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
2092 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, N54 },
2093 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
2094 {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 },
2095 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32|N55 },
2096 {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
2097 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
2098 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, I33 },
2099 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, I33 },
2100 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
2101 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
2102 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
2103 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
2104 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
2105 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
2106 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
2107 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
2108
2109 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2110 instructions so they are here for the latters to take precedence. */
2111 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
2112 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
2113 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
2114 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
2115 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
2116 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
2117 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
2118 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
2119 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
2120 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
2121 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
2122 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
2123 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
2124 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
2125 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
2126 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
2127
2128 /* No hazard protection on coprocessor instructions--they shouldn't
2129 change the state of the processor and if they do it's up to the
2130 user to put in nops as necessary. These are at the end so that the
2131 disassembler recognizes more specific versions first. */
2132 {"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
2133 {"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
2134 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
2135 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
2136 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
2137 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
2138 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
2139 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
2140
2141 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
2142 4010 any more, so move this insn out of the way. If the object
2143 format gave us more info, we could do this right. */
2144 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 },
2145 };
2146
2147 #define MIPS_NUM_OPCODES \
2148 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2149 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2150
2151 /* const removed from the following to allow for dynamic extensions to the
2152 * built-in instruction set. */
2153 struct mips_opcode *mips_opcodes =
2154 (struct mips_opcode *) mips_builtin_opcodes;
2155 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2156 #undef MIPS_NUM_OPCODES
2157
2158 /* Mips instructions are at maximum this many bytes long. */
2159 #define INSNLEN 4
2160
2161 static void set_default_mips_dis_options
2162 PARAMS ((struct disassemble_info *));
2163 static void parse_mips_dis_option
2164 PARAMS ((const char *, unsigned int));
2165 static void parse_mips_dis_options
2166 PARAMS ((const char *));
2167 static int _print_insn_mips
2168 PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
2169 static int print_insn_mips
2170 PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
2171 static void print_insn_args
2172 PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
2173 #if 0
2174 static int print_insn_mips16
2175 PARAMS ((bfd_vma, struct disassemble_info *));
2176 #endif
2177 #if 0
2178 static int is_newabi
2179 PARAMS ((Elf32_Ehdr *));
2180 #endif
2181 #if 0
2182 static void print_mips16_insn_arg
2183 PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
2184 struct disassemble_info *));
2185 #endif
2186 \f
2187 /* FIXME: These should be shared with gdb somehow. */
2188
2189 struct mips_cp0sel_name {
2190 unsigned int cp0reg;
2191 unsigned int sel;
2192 const char * const name;
2193 };
2194
2195 /* The mips16 register names. */
2196 static const char * const mips16_reg_names[] = {
2197 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
2198 };
2199
2200 static const char * const mips_gpr_names_numeric[32] = {
2201 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2202 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2203 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2204 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2205 };
2206
2207 static const char * const mips_gpr_names_oldabi[32] = {
2208 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2209 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2210 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2211 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2212 };
2213
2214 static const char * const mips_gpr_names_newabi[32] = {
2215 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2216 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
2217 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2218 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2219 };
2220
2221 static const char * const mips_fpr_names_numeric[32] = {
2222 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
2223 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2224 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2225 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2226 };
2227
2228 static const char * const mips_fpr_names_32[32] = {
2229 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
2230 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
2231 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
2232 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
2233 };
2234
2235 static const char * const mips_fpr_names_n32[32] = {
2236 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
2237 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2238 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
2239 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
2240 };
2241
2242 static const char * const mips_fpr_names_64[32] = {
2243 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
2244 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2245 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
2246 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
2247 };
2248
2249 static const char * const mips_cp0_names_numeric[32] = {
2250 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2251 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2252 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2253 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2254 };
2255
2256 static const char * const mips_cp0_names_mips3264[32] = {
2257 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2258 "c0_context", "c0_pagemask", "c0_wired", "$7",
2259 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2260 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2261 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2262 "c0_xcontext", "$21", "$22", "c0_debug",
2263 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2264 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2265 };
2266
2267 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
2268 { 16, 1, "c0_config1" },
2269 { 16, 2, "c0_config2" },
2270 { 16, 3, "c0_config3" },
2271 { 18, 1, "c0_watchlo,1" },
2272 { 18, 2, "c0_watchlo,2" },
2273 { 18, 3, "c0_watchlo,3" },
2274 { 18, 4, "c0_watchlo,4" },
2275 { 18, 5, "c0_watchlo,5" },
2276 { 18, 6, "c0_watchlo,6" },
2277 { 18, 7, "c0_watchlo,7" },
2278 { 19, 1, "c0_watchhi,1" },
2279 { 19, 2, "c0_watchhi,2" },
2280 { 19, 3, "c0_watchhi,3" },
2281 { 19, 4, "c0_watchhi,4" },
2282 { 19, 5, "c0_watchhi,5" },
2283 { 19, 6, "c0_watchhi,6" },
2284 { 19, 7, "c0_watchhi,7" },
2285 { 25, 1, "c0_perfcnt,1" },
2286 { 25, 2, "c0_perfcnt,2" },
2287 { 25, 3, "c0_perfcnt,3" },
2288 { 25, 4, "c0_perfcnt,4" },
2289 { 25, 5, "c0_perfcnt,5" },
2290 { 25, 6, "c0_perfcnt,6" },
2291 { 25, 7, "c0_perfcnt,7" },
2292 { 27, 1, "c0_cacheerr,1" },
2293 { 27, 2, "c0_cacheerr,2" },
2294 { 27, 3, "c0_cacheerr,3" },
2295 { 28, 1, "c0_datalo" },
2296 { 29, 1, "c0_datahi" }
2297 };
2298
2299 static const char * const mips_cp0_names_mips3264r2[32] = {
2300 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2301 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
2302 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2303 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2304 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2305 "c0_xcontext", "$21", "$22", "c0_debug",
2306 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2307 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2308 };
2309
2310 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
2311 { 4, 1, "c0_contextconfig" },
2312 { 5, 1, "c0_pagegrain" },
2313 { 12, 1, "c0_intctl" },
2314 { 12, 2, "c0_srsctl" },
2315 { 12, 3, "c0_srsmap" },
2316 { 15, 1, "c0_ebase" },
2317 { 16, 1, "c0_config1" },
2318 { 16, 2, "c0_config2" },
2319 { 16, 3, "c0_config3" },
2320 { 18, 1, "c0_watchlo,1" },
2321 { 18, 2, "c0_watchlo,2" },
2322 { 18, 3, "c0_watchlo,3" },
2323 { 18, 4, "c0_watchlo,4" },
2324 { 18, 5, "c0_watchlo,5" },
2325 { 18, 6, "c0_watchlo,6" },
2326 { 18, 7, "c0_watchlo,7" },
2327 { 19, 1, "c0_watchhi,1" },
2328 { 19, 2, "c0_watchhi,2" },
2329 { 19, 3, "c0_watchhi,3" },
2330 { 19, 4, "c0_watchhi,4" },
2331 { 19, 5, "c0_watchhi,5" },
2332 { 19, 6, "c0_watchhi,6" },
2333 { 19, 7, "c0_watchhi,7" },
2334 { 23, 1, "c0_tracecontrol" },
2335 { 23, 2, "c0_tracecontrol2" },
2336 { 23, 3, "c0_usertracedata" },
2337 { 23, 4, "c0_tracebpc" },
2338 { 25, 1, "c0_perfcnt,1" },
2339 { 25, 2, "c0_perfcnt,2" },
2340 { 25, 3, "c0_perfcnt,3" },
2341 { 25, 4, "c0_perfcnt,4" },
2342 { 25, 5, "c0_perfcnt,5" },
2343 { 25, 6, "c0_perfcnt,6" },
2344 { 25, 7, "c0_perfcnt,7" },
2345 { 27, 1, "c0_cacheerr,1" },
2346 { 27, 2, "c0_cacheerr,2" },
2347 { 27, 3, "c0_cacheerr,3" },
2348 { 28, 1, "c0_datalo" },
2349 { 28, 2, "c0_taglo1" },
2350 { 28, 3, "c0_datalo1" },
2351 { 28, 4, "c0_taglo2" },
2352 { 28, 5, "c0_datalo2" },
2353 { 28, 6, "c0_taglo3" },
2354 { 28, 7, "c0_datalo3" },
2355 { 29, 1, "c0_datahi" },
2356 { 29, 2, "c0_taghi1" },
2357 { 29, 3, "c0_datahi1" },
2358 { 29, 4, "c0_taghi2" },
2359 { 29, 5, "c0_datahi2" },
2360 { 29, 6, "c0_taghi3" },
2361 { 29, 7, "c0_datahi3" },
2362 };
2363
2364 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
2365 static const char * const mips_cp0_names_sb1[32] = {
2366 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2367 "c0_context", "c0_pagemask", "c0_wired", "$7",
2368 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2369 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2370 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2371 "c0_xcontext", "$21", "$22", "c0_debug",
2372 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
2373 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
2374 };
2375
2376 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
2377 { 16, 1, "c0_config1" },
2378 { 18, 1, "c0_watchlo,1" },
2379 { 19, 1, "c0_watchhi,1" },
2380 { 22, 0, "c0_perftrace" },
2381 { 23, 3, "c0_edebug" },
2382 { 25, 1, "c0_perfcnt,1" },
2383 { 25, 2, "c0_perfcnt,2" },
2384 { 25, 3, "c0_perfcnt,3" },
2385 { 25, 4, "c0_perfcnt,4" },
2386 { 25, 5, "c0_perfcnt,5" },
2387 { 25, 6, "c0_perfcnt,6" },
2388 { 25, 7, "c0_perfcnt,7" },
2389 { 26, 1, "c0_buserr_pa" },
2390 { 27, 1, "c0_cacheerr_d" },
2391 { 27, 3, "c0_cacheerr_d_pa" },
2392 { 28, 1, "c0_datalo_i" },
2393 { 28, 2, "c0_taglo_d" },
2394 { 28, 3, "c0_datalo_d" },
2395 { 29, 1, "c0_datahi_i" },
2396 { 29, 2, "c0_taghi_d" },
2397 { 29, 3, "c0_datahi_d" },
2398 };
2399
2400 static const char * const mips_hwr_names_numeric[32] = {
2401 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2402 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2403 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2404 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2405 };
2406
2407 static const char * const mips_hwr_names_mips3264r2[32] = {
2408 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
2409 "$4", "$5", "$6", "$7",
2410 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2411 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2412 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2413 };
2414
2415 struct mips_abi_choice {
2416 const char *name;
2417 const char * const *gpr_names;
2418 const char * const *fpr_names;
2419 };
2420
2421 struct mips_abi_choice mips_abi_choices[] = {
2422 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
2423 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
2424 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
2425 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
2426 };
2427
2428 struct mips_arch_choice {
2429 const char *name;
2430 int bfd_mach_valid;
2431 unsigned long bfd_mach;
2432 int processor;
2433 int isa;
2434 const char * const *cp0_names;
2435 const struct mips_cp0sel_name *cp0sel_names;
2436 unsigned int cp0sel_names_len;
2437 const char * const *hwr_names;
2438 };
2439
2440 #define bfd_mach_mips3000 3000
2441 #define bfd_mach_mips3900 3900
2442 #define bfd_mach_mips4000 4000
2443 #define bfd_mach_mips4010 4010
2444 #define bfd_mach_mips4100 4100
2445 #define bfd_mach_mips4111 4111
2446 #define bfd_mach_mips4120 4120
2447 #define bfd_mach_mips4300 4300
2448 #define bfd_mach_mips4400 4400
2449 #define bfd_mach_mips4600 4600
2450 #define bfd_mach_mips4650 4650
2451 #define bfd_mach_mips5000 5000
2452 #define bfd_mach_mips5400 5400
2453 #define bfd_mach_mips5500 5500
2454 #define bfd_mach_mips6000 6000
2455 #define bfd_mach_mips7000 7000
2456 #define bfd_mach_mips8000 8000
2457 #define bfd_mach_mips10000 10000
2458 #define bfd_mach_mips12000 12000
2459 #define bfd_mach_mips16 16
2460 #define bfd_mach_mips5 5
2461 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
2462 #define bfd_mach_mipsisa32 32
2463 #define bfd_mach_mipsisa32r2 33
2464 #define bfd_mach_mipsisa64 64
2465 #define bfd_mach_mipsisa64r2 65
2466
2467 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
2468
2469 const struct mips_arch_choice mips_arch_choices[] = {
2470 { "numeric", 0, 0, 0, 0,
2471 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2472
2473 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
2474 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2475 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
2476 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2477 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
2478 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2479 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
2480 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2481 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
2482 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2483 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
2484 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2485 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
2486 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2487 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
2488 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2489 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
2490 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2491 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
2492 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2493 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
2494 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2495 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
2496 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2497 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
2498 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2499 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
2500 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2501 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
2502 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2503 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
2504 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2505 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
2506 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2507 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
2508 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2509 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
2510 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2511 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
2512 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2513 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
2514 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2515
2516 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
2517 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
2518 _MIPS32 Architecture For Programmers Volume I: Introduction to the
2519 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
2520 page 1. */
2521 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
2522 ISA_MIPS32 | INSN_MIPS16,
2523 mips_cp0_names_mips3264,
2524 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
2525 mips_hwr_names_numeric },
2526
2527 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
2528 ISA_MIPS32R2 | INSN_MIPS16,
2529 mips_cp0_names_mips3264r2,
2530 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
2531 mips_hwr_names_mips3264r2 },
2532
2533 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
2534 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
2535 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
2536 mips_cp0_names_mips3264,
2537 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
2538 mips_hwr_names_numeric },
2539
2540 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
2541 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
2542 mips_cp0_names_mips3264r2,
2543 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
2544 mips_hwr_names_mips3264r2 },
2545
2546 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
2547 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
2548 mips_cp0_names_sb1,
2549 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
2550 mips_hwr_names_numeric },
2551
2552 /* This entry, mips16, is here only for ISA/processor selection; do
2553 not print its name. */
2554 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
2555 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2556 };
2557
2558 /* ISA and processor type to disassemble for, and register names to use.
2559 set_default_mips_dis_options and parse_mips_dis_options fill in these
2560 values. */
2561 static int mips_processor;
2562 static int mips_isa;
2563 static const char * const *mips_gpr_names;
2564 static const char * const *mips_fpr_names;
2565 static const char * const *mips_cp0_names;
2566 static const struct mips_cp0sel_name *mips_cp0sel_names;
2567 static int mips_cp0sel_names_len;
2568 static const char * const *mips_hwr_names;
2569
2570 static const struct mips_abi_choice *choose_abi_by_name
2571 PARAMS ((const char *, unsigned int));
2572 static const struct mips_arch_choice *choose_arch_by_name
2573 PARAMS ((const char *, unsigned int));
2574 static const struct mips_arch_choice *choose_arch_by_number
2575 PARAMS ((unsigned long));
2576 static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
2577 PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
2578 unsigned int));
2579 \f
2580 static const struct mips_abi_choice *
2581 choose_abi_by_name (name, namelen)
2582 const char *name;
2583 unsigned int namelen;
2584 {
2585 const struct mips_abi_choice *c;
2586 unsigned int i;
2587
2588 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
2589 {
2590 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
2591 && strlen (mips_abi_choices[i].name) == namelen)
2592 c = &mips_abi_choices[i];
2593 }
2594 return c;
2595 }
2596
2597 static const struct mips_arch_choice *
2598 choose_arch_by_name (name, namelen)
2599 const char *name;
2600 unsigned int namelen;
2601 {
2602 const struct mips_arch_choice *c = NULL;
2603 unsigned int i;
2604
2605 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
2606 {
2607 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
2608 && strlen (mips_arch_choices[i].name) == namelen)
2609 c = &mips_arch_choices[i];
2610 }
2611 return c;
2612 }
2613
2614 static const struct mips_arch_choice *
2615 choose_arch_by_number (mach)
2616 unsigned long mach;
2617 {
2618 static unsigned long hint_bfd_mach;
2619 static const struct mips_arch_choice *hint_arch_choice;
2620 const struct mips_arch_choice *c;
2621 unsigned int i;
2622
2623 /* We optimize this because even if the user specifies no
2624 flags, this will be done for every instruction! */
2625 if (hint_bfd_mach == mach
2626 && hint_arch_choice != NULL
2627 && hint_arch_choice->bfd_mach == hint_bfd_mach)
2628 return hint_arch_choice;
2629
2630 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
2631 {
2632 if (mips_arch_choices[i].bfd_mach_valid
2633 && mips_arch_choices[i].bfd_mach == mach)
2634 {
2635 c = &mips_arch_choices[i];
2636 hint_bfd_mach = mach;
2637 hint_arch_choice = c;
2638 }
2639 }
2640 return c;
2641 }
2642
2643 void
2644 set_default_mips_dis_options (info)
2645 struct disassemble_info *info;
2646 {
2647 const struct mips_arch_choice *chosen_arch;
2648
2649 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
2650 and numeric FPR, CP0 register, and HWR names. */
2651 mips_isa = ISA_MIPS3;
2652 mips_processor = CPU_R3000;
2653 mips_gpr_names = mips_gpr_names_oldabi;
2654 mips_fpr_names = mips_fpr_names_numeric;
2655 mips_cp0_names = mips_cp0_names_numeric;
2656 mips_cp0sel_names = NULL;
2657 mips_cp0sel_names_len = 0;
2658 mips_hwr_names = mips_hwr_names_numeric;
2659
2660 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
2661 #if 0
2662 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
2663 {
2664 Elf_Internal_Ehdr *header;
2665
2666 header = elf_elfheader (info->section->owner);
2667 if (is_newabi (header))
2668 mips_gpr_names = mips_gpr_names_newabi;
2669 }
2670 #endif
2671
2672 /* Set ISA, architecture, and cp0 register names as best we can. */
2673 #if ! SYMTAB_AVAILABLE && 0
2674 /* This is running out on a target machine, not in a host tool.
2675 FIXME: Where does mips_target_info come from? */
2676 target_processor = mips_target_info.processor;
2677 mips_isa = mips_target_info.isa;
2678 #else
2679 chosen_arch = choose_arch_by_number (info->mach);
2680 if (chosen_arch != NULL)
2681 {
2682 mips_processor = chosen_arch->processor;
2683 mips_isa = chosen_arch->isa;
2684 mips_cp0_names = chosen_arch->cp0_names;
2685 mips_cp0sel_names = chosen_arch->cp0sel_names;
2686 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
2687 mips_hwr_names = chosen_arch->hwr_names;
2688 }
2689 #endif
2690 }
2691
2692 void
2693 parse_mips_dis_option (option, len)
2694 const char *option;
2695 unsigned int len;
2696 {
2697 unsigned int i, optionlen, vallen;
2698 const char *val;
2699 const struct mips_abi_choice *chosen_abi;
2700 const struct mips_arch_choice *chosen_arch;
2701
2702 /* Look for the = that delimits the end of the option name. */
2703 for (i = 0; i < len; i++)
2704 {
2705 if (option[i] == '=')
2706 break;
2707 }
2708 if (i == 0) /* Invalid option: no name before '='. */
2709 return;
2710 if (i == len) /* Invalid option: no '='. */
2711 return;
2712 if (i == (len - 1)) /* Invalid option: no value after '='. */
2713 return;
2714
2715 optionlen = i;
2716 val = option + (optionlen + 1);
2717 vallen = len - (optionlen + 1);
2718
2719 if (strncmp("gpr-names", option, optionlen) == 0
2720 && strlen("gpr-names") == optionlen)
2721 {
2722 chosen_abi = choose_abi_by_name (val, vallen);
2723 if (chosen_abi != NULL)
2724 mips_gpr_names = chosen_abi->gpr_names;
2725 return;
2726 }
2727
2728 if (strncmp("fpr-names", option, optionlen) == 0
2729 && strlen("fpr-names") == optionlen)
2730 {
2731 chosen_abi = choose_abi_by_name (val, vallen);
2732 if (chosen_abi != NULL)
2733 mips_fpr_names = chosen_abi->fpr_names;
2734 return;
2735 }
2736
2737 if (strncmp("cp0-names", option, optionlen) == 0
2738 && strlen("cp0-names") == optionlen)
2739 {
2740 chosen_arch = choose_arch_by_name (val, vallen);
2741 if (chosen_arch != NULL)
2742 {
2743 mips_cp0_names = chosen_arch->cp0_names;
2744 mips_cp0sel_names = chosen_arch->cp0sel_names;
2745 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
2746 }
2747 return;
2748 }
2749
2750 if (strncmp("hwr-names", option, optionlen) == 0
2751 && strlen("hwr-names") == optionlen)
2752 {
2753 chosen_arch = choose_arch_by_name (val, vallen);
2754 if (chosen_arch != NULL)
2755 mips_hwr_names = chosen_arch->hwr_names;
2756 return;
2757 }
2758
2759 if (strncmp("reg-names", option, optionlen) == 0
2760 && strlen("reg-names") == optionlen)
2761 {
2762 /* We check both ABI and ARCH here unconditionally, so
2763 that "numeric" will do the desirable thing: select
2764 numeric register names for all registers. Other than
2765 that, a given name probably won't match both. */
2766 chosen_abi = choose_abi_by_name (val, vallen);
2767 if (chosen_abi != NULL)
2768 {
2769 mips_gpr_names = chosen_abi->gpr_names;
2770 mips_fpr_names = chosen_abi->fpr_names;
2771 }
2772 chosen_arch = choose_arch_by_name (val, vallen);
2773 if (chosen_arch != NULL)
2774 {
2775 mips_cp0_names = chosen_arch->cp0_names;
2776 mips_cp0sel_names = chosen_arch->cp0sel_names;
2777 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
2778 mips_hwr_names = chosen_arch->hwr_names;
2779 }
2780 return;
2781 }
2782
2783 /* Invalid option. */
2784 }
2785
2786 void
2787 parse_mips_dis_options (options)
2788 const char *options;
2789 {
2790 const char *option_end;
2791
2792 if (options == NULL)
2793 return;
2794
2795 while (*options != '\0')
2796 {
2797 /* Skip empty options. */
2798 if (*options == ',')
2799 {
2800 options++;
2801 continue;
2802 }
2803
2804 /* We know that *options is neither NUL or a comma. */
2805 option_end = options + 1;
2806 while (*option_end != ',' && *option_end != '\0')
2807 option_end++;
2808
2809 parse_mips_dis_option (options, option_end - options);
2810
2811 /* Go on to the next one. If option_end points to a comma, it
2812 will be skipped above. */
2813 options = option_end;
2814 }
2815 }
2816
2817 static const struct mips_cp0sel_name *
2818 lookup_mips_cp0sel_name(names, len, cp0reg, sel)
2819 const struct mips_cp0sel_name *names;
2820 unsigned int len, cp0reg, sel;
2821 {
2822 unsigned int i;
2823
2824 for (i = 0; i < len; i++)
2825 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
2826 return &names[i];
2827 return NULL;
2828 }
2829 \f
2830 /* Print insn arguments for 32/64-bit code. */
2831
2832 static void
2833 print_insn_args (d, l, pc, info)
2834 const char *d;
2835 register unsigned long int l;
2836 bfd_vma pc;
2837 struct disassemble_info *info;
2838 {
2839 int op, delta;
2840 unsigned int lsb, msb, msbd;
2841
2842 lsb = 0;
2843
2844 for (; *d != '\0'; d++)
2845 {
2846 switch (*d)
2847 {
2848 case ',':
2849 case '(':
2850 case ')':
2851 case '[':
2852 case ']':
2853 (*info->fprintf_func) (info->stream, "%c", *d);
2854 break;
2855
2856 case '+':
2857 /* Extension character; switch for second char. */
2858 d++;
2859 switch (*d)
2860 {
2861 case '\0':
2862 /* xgettext:c-format */
2863 (*info->fprintf_func) (info->stream,
2864 _("# internal error, incomplete extension sequence (+)"));
2865 return;
2866
2867 case 'A':
2868 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
2869 (*info->fprintf_func) (info->stream, "0x%x", lsb);
2870 break;
2871
2872 case 'B':
2873 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
2874 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
2875 break;
2876
2877 case 'C':
2878 case 'H':
2879 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
2880 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
2881 break;
2882
2883 case 'D':
2884 {
2885 const struct mips_cp0sel_name *n;
2886 unsigned int cp0reg, sel;
2887
2888 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
2889 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
2890
2891 /* CP0 register including 'sel' code for mtcN (et al.), to be
2892 printed textually if known. If not known, print both
2893 CP0 register name and sel numerically since CP0 register
2894 with sel 0 may have a name unrelated to register being
2895 printed. */
2896 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
2897 mips_cp0sel_names_len, cp0reg, sel);
2898 if (n != NULL)
2899 (*info->fprintf_func) (info->stream, "%s", n->name);
2900 else
2901 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
2902 break;
2903 }
2904
2905 case 'E':
2906 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
2907 (*info->fprintf_func) (info->stream, "0x%x", lsb);
2908 break;
2909
2910 case 'F':
2911 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
2912 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
2913 break;
2914
2915 case 'G':
2916 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
2917 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
2918 break;
2919
2920 default:
2921 /* xgettext:c-format */
2922 (*info->fprintf_func) (info->stream,
2923 _("# internal error, undefined extension sequence (+%c)"),
2924 *d);
2925 return;
2926 }
2927 break;
2928
2929 case 's':
2930 case 'b':
2931 case 'r':
2932 case 'v':
2933 (*info->fprintf_func) (info->stream, "%s",
2934 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
2935 break;
2936
2937 case 't':
2938 case 'w':
2939 (*info->fprintf_func) (info->stream, "%s",
2940 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
2941 break;
2942
2943 case 'i':
2944 case 'u':
2945 (*info->fprintf_func) (info->stream, "0x%x",
2946 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
2947 break;
2948
2949 case 'j': /* Same as i, but sign-extended. */
2950 case 'o':
2951 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
2952 if (delta & 0x8000)
2953 delta |= ~0xffff;
2954 (*info->fprintf_func) (info->stream, "%d",
2955 delta);
2956 break;
2957
2958 case 'h':
2959 (*info->fprintf_func) (info->stream, "0x%x",
2960 (unsigned int) ((l >> OP_SH_PREFX)
2961 & OP_MASK_PREFX));
2962 break;
2963
2964 case 'k':
2965 (*info->fprintf_func) (info->stream, "0x%x",
2966 (unsigned int) ((l >> OP_SH_CACHE)
2967 & OP_MASK_CACHE));
2968 break;
2969
2970 case 'a':
2971 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
2972 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
2973 (*info->print_address_func) (info->target, info);
2974 break;
2975
2976 case 'p':
2977 /* Sign extend the displacement. */
2978 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
2979 if (delta & 0x8000)
2980 delta |= ~0xffff;
2981 info->target = (delta << 2) + pc + INSNLEN;
2982 (*info->print_address_func) (info->target, info);
2983 break;
2984
2985 case 'd':
2986 (*info->fprintf_func) (info->stream, "%s",
2987 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
2988 break;
2989
2990 case 'U':
2991 {
2992 /* First check for both rd and rt being equal. */
2993 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
2994 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
2995 (*info->fprintf_func) (info->stream, "%s",
2996 mips_gpr_names[reg]);
2997 else
2998 {
2999 /* If one is zero use the other. */
3000 if (reg == 0)
3001 (*info->fprintf_func) (info->stream, "%s",
3002 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3003 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3004 (*info->fprintf_func) (info->stream, "%s",
3005 mips_gpr_names[reg]);
3006 else /* Bogus, result depends on processor. */
3007 (*info->fprintf_func) (info->stream, "%s or %s",
3008 mips_gpr_names[reg],
3009 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3010 }
3011 }
3012 break;
3013
3014 case 'z':
3015 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3016 break;
3017
3018 case '<':
3019 (*info->fprintf_func) (info->stream, "0x%x",
3020 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3021 break;
3022
3023 case 'c':
3024 (*info->fprintf_func) (info->stream, "0x%x",
3025 (l >> OP_SH_CODE) & OP_MASK_CODE);
3026 break;
3027
3028 case 'q':
3029 (*info->fprintf_func) (info->stream, "0x%x",
3030 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3031 break;
3032
3033 case 'C':
3034 (*info->fprintf_func) (info->stream, "0x%x",
3035 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3036 break;
3037
3038 case 'B':
3039 (*info->fprintf_func) (info->stream, "0x%x",
3040 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3041 break;
3042
3043 case 'J':
3044 (*info->fprintf_func) (info->stream, "0x%x",
3045 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3046 break;
3047
3048 case 'S':
3049 case 'V':
3050 (*info->fprintf_func) (info->stream, "%s",
3051 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3052 break;
3053
3054 case 'T':
3055 case 'W':
3056 (*info->fprintf_func) (info->stream, "%s",
3057 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3058 break;
3059
3060 case 'D':
3061 (*info->fprintf_func) (info->stream, "%s",
3062 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3063 break;
3064
3065 case 'R':
3066 (*info->fprintf_func) (info->stream, "%s",
3067 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3068 break;
3069
3070 case 'E':
3071 /* Coprocessor register for lwcN instructions, et al.
3072
3073 Note that there is no load/store cp0 instructions, and
3074 that FPU (cp1) instructions disassemble this field using
3075 'T' format. Therefore, until we gain understanding of
3076 cp2 register names, we can simply print the register
3077 numbers. */
3078 (*info->fprintf_func) (info->stream, "$%d",
3079 (l >> OP_SH_RT) & OP_MASK_RT);
3080 break;
3081
3082 case 'G':
3083 /* Coprocessor register for mtcN instructions, et al. Note
3084 that FPU (cp1) instructions disassemble this field using
3085 'S' format. Therefore, we only need to worry about cp0,
3086 cp2, and cp3. */
3087 op = (l >> OP_SH_OP) & OP_MASK_OP;
3088 if (op == OP_OP_COP0)
3089 (*info->fprintf_func) (info->stream, "%s",
3090 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3091 else
3092 (*info->fprintf_func) (info->stream, "$%d",
3093 (l >> OP_SH_RD) & OP_MASK_RD);
3094 break;
3095
3096 case 'K':
3097 (*info->fprintf_func) (info->stream, "%s",
3098 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3099 break;
3100
3101 case 'N':
3102 (*info->fprintf_func) (info->stream, "$fcc%d",
3103 (l >> OP_SH_BCC) & OP_MASK_BCC);
3104 break;
3105
3106 case 'M':
3107 (*info->fprintf_func) (info->stream, "$fcc%d",
3108 (l >> OP_SH_CCC) & OP_MASK_CCC);
3109 break;
3110
3111 case 'P':
3112 (*info->fprintf_func) (info->stream, "%d",
3113 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3114 break;
3115
3116 case 'e':
3117 (*info->fprintf_func) (info->stream, "%d",
3118 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3119 break;
3120
3121 case '%':
3122 (*info->fprintf_func) (info->stream, "%d",
3123 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3124 break;
3125
3126 case 'H':
3127 (*info->fprintf_func) (info->stream, "%d",
3128 (l >> OP_SH_SEL) & OP_MASK_SEL);
3129 break;
3130
3131 case 'O':
3132 (*info->fprintf_func) (info->stream, "%d",
3133 (l >> OP_SH_ALN) & OP_MASK_ALN);
3134 break;
3135
3136 case 'Q':
3137 {
3138 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3139 if ((vsel & 0x10) == 0)
3140 {
3141 int fmt;
3142 vsel &= 0x0f;
3143 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3144 if ((vsel & 1) == 0)
3145 break;
3146 (*info->fprintf_func) (info->stream, "$v%d[%d]",
3147 (l >> OP_SH_FT) & OP_MASK_FT,
3148 vsel >> 1);
3149 }
3150 else if ((vsel & 0x08) == 0)
3151 {
3152 (*info->fprintf_func) (info->stream, "$v%d",
3153 (l >> OP_SH_FT) & OP_MASK_FT);
3154 }
3155 else
3156 {
3157 (*info->fprintf_func) (info->stream, "0x%x",
3158 (l >> OP_SH_FT) & OP_MASK_FT);
3159 }
3160 }
3161 break;
3162
3163 case 'X':
3164 (*info->fprintf_func) (info->stream, "$v%d",
3165 (l >> OP_SH_FD) & OP_MASK_FD);
3166 break;
3167
3168 case 'Y':
3169 (*info->fprintf_func) (info->stream, "$v%d",
3170 (l >> OP_SH_FS) & OP_MASK_FS);
3171 break;
3172
3173 case 'Z':
3174 (*info->fprintf_func) (info->stream, "$v%d",
3175 (l >> OP_SH_FT) & OP_MASK_FT);
3176 break;
3177
3178 default:
3179 /* xgettext:c-format */
3180 (*info->fprintf_func) (info->stream,
3181 _("# internal error, undefined modifier(%c)"),
3182 *d);
3183 return;
3184 }
3185 }
3186 }
3187 \f
3188 /* Check if the object uses NewABI conventions. */
3189 #if 0
3190 static int
3191 is_newabi (header)
3192 Elf_Internal_Ehdr *header;
3193 {
3194 /* There are no old-style ABIs which use 64-bit ELF. */
3195 if (header->e_ident[EI_CLASS] == ELFCLASS64)
3196 return 1;
3197
3198 /* If a 32-bit ELF file, n32 is a new-style ABI. */
3199 if ((header->e_flags & EF_MIPS_ABI2) != 0)
3200 return 1;
3201
3202 return 0;
3203 }
3204 #endif
3205 \f
3206 /* Print the mips instruction at address MEMADDR in debugged memory,
3207 on using INFO. Returns length of the instruction, in bytes, which is
3208 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
3209 this is little-endian code. */
3210
3211 static int
3212 print_insn_mips (memaddr, word, info)
3213 bfd_vma memaddr;
3214 unsigned long int word;
3215 struct disassemble_info *info;
3216 {
3217 register const struct mips_opcode *op;
3218 static bfd_boolean init = 0;
3219 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
3220
3221 /* Build a hash table to shorten the search time. */
3222 if (! init)
3223 {
3224 unsigned int i;
3225
3226 for (i = 0; i <= OP_MASK_OP; i++)
3227 {
3228 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
3229 {
3230 if (op->pinfo == INSN_MACRO)
3231 continue;
3232 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
3233 {
3234 mips_hash[i] = op;
3235 break;
3236 }
3237 }
3238 }
3239
3240 init = 1;
3241 }
3242
3243 info->bytes_per_chunk = INSNLEN;
3244 info->display_endian = info->endian;
3245 info->insn_info_valid = 1;
3246 info->branch_delay_insns = 0;
3247 info->data_size = 0;
3248 info->insn_type = dis_nonbranch;
3249 info->target = 0;
3250 info->target2 = 0;
3251
3252 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
3253 if (op != NULL)
3254 {
3255 for (; op < &mips_opcodes[NUMOPCODES]; op++)
3256 {
3257 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
3258 {
3259 register const char *d;
3260
3261 /* We always allow to disassemble the jalx instruction. */
3262 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3263 && strcmp (op->name, "jalx"))
3264 continue;
3265
3266 /* Figure out instruction type and branch delay information. */
3267 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3268 {
3269 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
3270 info->insn_type = dis_jsr;
3271 else
3272 info->insn_type = dis_branch;
3273 info->branch_delay_insns = 1;
3274 }
3275 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
3276 | INSN_COND_BRANCH_LIKELY)) != 0)
3277 {
3278 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
3279 info->insn_type = dis_condjsr;
3280 else
3281 info->insn_type = dis_condbranch;
3282 info->branch_delay_insns = 1;
3283 }
3284 else if ((op->pinfo & (INSN_STORE_MEMORY
3285 | INSN_LOAD_MEMORY_DELAY)) != 0)
3286 info->insn_type = dis_dref;
3287
3288 (*info->fprintf_func) (info->stream, "%s", op->name);
3289
3290 d = op->args;
3291 if (d != NULL && *d != '\0')
3292 {
3293 (*info->fprintf_func) (info->stream, "\t");
3294 print_insn_args (d, word, memaddr, info);
3295 }
3296
3297 return INSNLEN;
3298 }
3299 }
3300 }
3301
3302 /* Handle undefined instructions. */
3303 info->insn_type = dis_noninsn;
3304 (*info->fprintf_func) (info->stream, "0x%x", word);
3305 return INSNLEN;
3306 }
3307 \f
3308 /* In an environment where we do not know the symbol type of the
3309 instruction we are forced to assume that the low order bit of the
3310 instructions' address may mark it as a mips16 instruction. If we
3311 are single stepping, or the pc is within the disassembled function,
3312 this works. Otherwise, we need a clue. Sometimes. */
3313
3314 static int
3315 _print_insn_mips (memaddr, info, endianness)
3316 bfd_vma memaddr;
3317 struct disassemble_info *info;
3318 enum bfd_endian endianness;
3319 {
3320 bfd_byte buffer[INSNLEN];
3321 int status;
3322
3323 set_default_mips_dis_options (info);
3324 parse_mips_dis_options (info->disassembler_options);
3325
3326 #if 0
3327 #if 1
3328 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
3329 /* Only a few tools will work this way. */
3330 if (memaddr & 0x01)
3331 return print_insn_mips16 (memaddr, info);
3332 #endif
3333
3334 #if SYMTAB_AVAILABLE
3335 if (info->mach == bfd_mach_mips16
3336 || (info->flavour == bfd_target_elf_flavour
3337 && info->symbols != NULL
3338 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
3339 == STO_MIPS16)))
3340 return print_insn_mips16 (memaddr, info);
3341 #endif
3342 #endif
3343
3344 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
3345 if (status == 0)
3346 {
3347 unsigned long insn;
3348
3349 if (endianness == BFD_ENDIAN_BIG)
3350 insn = (unsigned long) bfd_getb32 (buffer);
3351 else
3352 insn = (unsigned long) bfd_getl32 (buffer);
3353
3354 return print_insn_mips (memaddr, insn, info);
3355 }
3356 else
3357 {
3358 (*info->memory_error_func) (status, memaddr, info);
3359 return -1;
3360 }
3361 }
3362
3363 int
3364 print_insn_big_mips (memaddr, info)
3365 bfd_vma memaddr;
3366 struct disassemble_info *info;
3367 {
3368 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
3369 }
3370
3371 int
3372 print_insn_little_mips (memaddr, info)
3373 bfd_vma memaddr;
3374 struct disassemble_info *info;
3375 {
3376 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
3377 }
3378 \f
3379 /* Disassemble mips16 instructions. */
3380 #if 0
3381 static int
3382 print_insn_mips16 (memaddr, info)
3383 bfd_vma memaddr;
3384 struct disassemble_info *info;
3385 {
3386 int status;
3387 bfd_byte buffer[2];
3388 int length;
3389 int insn;
3390 bfd_boolean use_extend;
3391 int extend = 0;
3392 const struct mips_opcode *op, *opend;
3393
3394 info->bytes_per_chunk = 2;
3395 info->display_endian = info->endian;
3396 info->insn_info_valid = 1;
3397 info->branch_delay_insns = 0;
3398 info->data_size = 0;
3399 info->insn_type = dis_nonbranch;
3400 info->target = 0;
3401 info->target2 = 0;
3402
3403 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
3404 if (status != 0)
3405 {
3406 (*info->memory_error_func) (status, memaddr, info);
3407 return -1;
3408 }
3409
3410 length = 2;
3411
3412 if (info->endian == BFD_ENDIAN_BIG)
3413 insn = bfd_getb16 (buffer);
3414 else
3415 insn = bfd_getl16 (buffer);
3416
3417 /* Handle the extend opcode specially. */
3418 use_extend = FALSE;
3419 if ((insn & 0xf800) == 0xf000)
3420 {
3421 use_extend = TRUE;
3422 extend = insn & 0x7ff;
3423
3424 memaddr += 2;
3425
3426 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
3427 if (status != 0)
3428 {
3429 (*info->fprintf_func) (info->stream, "extend 0x%x",
3430 (unsigned int) extend);
3431 (*info->memory_error_func) (status, memaddr, info);
3432 return -1;
3433 }
3434
3435 if (info->endian == BFD_ENDIAN_BIG)
3436 insn = bfd_getb16 (buffer);
3437 else
3438 insn = bfd_getl16 (buffer);
3439
3440 /* Check for an extend opcode followed by an extend opcode. */
3441 if ((insn & 0xf800) == 0xf000)
3442 {
3443 (*info->fprintf_func) (info->stream, "extend 0x%x",
3444 (unsigned int) extend);
3445 info->insn_type = dis_noninsn;
3446 return length;
3447 }
3448
3449 length += 2;
3450 }
3451
3452 /* FIXME: Should probably use a hash table on the major opcode here. */
3453
3454 opend = mips16_opcodes + bfd_mips16_num_opcodes;
3455 for (op = mips16_opcodes; op < opend; op++)
3456 {
3457 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
3458 {
3459 const char *s;
3460
3461 if (strchr (op->args, 'a') != NULL)
3462 {
3463 if (use_extend)
3464 {
3465 (*info->fprintf_func) (info->stream, "extend 0x%x",
3466 (unsigned int) extend);
3467 info->insn_type = dis_noninsn;
3468 return length - 2;
3469 }
3470
3471 use_extend = FALSE;
3472
3473 memaddr += 2;
3474
3475 status = (*info->read_memory_func) (memaddr, buffer, 2,
3476 info);
3477 if (status == 0)
3478 {
3479 use_extend = TRUE;
3480 if (info->endian == BFD_ENDIAN_BIG)
3481 extend = bfd_getb16 (buffer);
3482 else
3483 extend = bfd_getl16 (buffer);
3484 length += 2;
3485 }
3486 }
3487
3488 (*info->fprintf_func) (info->stream, "%s", op->name);
3489 if (op->args[0] != '\0')
3490 (*info->fprintf_func) (info->stream, "\t");
3491
3492 for (s = op->args; *s != '\0'; s++)
3493 {
3494 if (*s == ','
3495 && s[1] == 'w'
3496 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
3497 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
3498 {
3499 /* Skip the register and the comma. */
3500 ++s;
3501 continue;
3502 }
3503 if (*s == ','
3504 && s[1] == 'v'
3505 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
3506 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
3507 {
3508 /* Skip the register and the comma. */
3509 ++s;
3510 continue;
3511 }
3512 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
3513 info);
3514 }
3515
3516 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3517 {
3518 info->branch_delay_insns = 1;
3519 if (info->insn_type != dis_jsr)
3520 info->insn_type = dis_branch;
3521 }
3522
3523 return length;
3524 }
3525 }
3526
3527 if (use_extend)
3528 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
3529 (*info->fprintf_func) (info->stream, "0x%x", insn);
3530 info->insn_type = dis_noninsn;
3531
3532 return length;
3533 }
3534
3535 /* Disassemble an operand for a mips16 instruction. */
3536
3537 static void
3538 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
3539 char type;
3540 const struct mips_opcode *op;
3541 int l;
3542 bfd_boolean use_extend;
3543 int extend;
3544 bfd_vma memaddr;
3545 struct disassemble_info *info;
3546 {
3547 switch (type)
3548 {
3549 case ',':
3550 case '(':
3551 case ')':
3552 (*info->fprintf_func) (info->stream, "%c", type);
3553 break;
3554
3555 case 'y':
3556 case 'w':
3557 (*info->fprintf_func) (info->stream, "%s",
3558 mips16_reg_names[((l >> MIPS16OP_SH_RY)
3559 & MIPS16OP_MASK_RY)]);
3560 break;
3561
3562 case 'x':
3563 case 'v':
3564 (*info->fprintf_func) (info->stream, "%s",
3565 mips16_reg_names[((l >> MIPS16OP_SH_RX)
3566 & MIPS16OP_MASK_RX)]);
3567 break;
3568
3569 case 'z':
3570 (*info->fprintf_func) (info->stream, "%s",
3571 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
3572 & MIPS16OP_MASK_RZ)]);
3573 break;
3574
3575 case 'Z':
3576 (*info->fprintf_func) (info->stream, "%s",
3577 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
3578 & MIPS16OP_MASK_MOVE32Z)]);
3579 break;
3580
3581 case '0':
3582 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3583 break;
3584
3585 case 'S':
3586 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
3587 break;
3588
3589 case 'P':
3590 (*info->fprintf_func) (info->stream, "$pc");
3591 break;
3592
3593 case 'R':
3594 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
3595 break;
3596
3597 case 'X':
3598 (*info->fprintf_func) (info->stream, "%s",
3599 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
3600 & MIPS16OP_MASK_REGR32)]);
3601 break;
3602
3603 case 'Y':
3604 (*info->fprintf_func) (info->stream, "%s",
3605 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
3606 break;
3607
3608 case '<':
3609 case '>':
3610 case '[':
3611 case ']':
3612 case '4':
3613 case '5':
3614 case 'H':
3615 case 'W':
3616 case 'D':
3617 case 'j':
3618 case '6':
3619 case '8':
3620 case 'V':
3621 case 'C':
3622 case 'U':
3623 case 'k':
3624 case 'K':
3625 case 'p':
3626 case 'q':
3627 case 'A':
3628 case 'B':
3629 case 'E':
3630 {
3631 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
3632
3633 shift = 0;
3634 signedp = 0;
3635 extbits = 16;
3636 pcrel = 0;
3637 extu = 0;
3638 branch = 0;
3639 switch (type)
3640 {
3641 case '<':
3642 nbits = 3;
3643 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
3644 extbits = 5;
3645 extu = 1;
3646 break;
3647 case '>':
3648 nbits = 3;
3649 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
3650 extbits = 5;
3651 extu = 1;
3652 break;
3653 case '[':
3654 nbits = 3;
3655 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
3656 extbits = 6;
3657 extu = 1;
3658 break;
3659 case ']':
3660 nbits = 3;
3661 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
3662 extbits = 6;
3663 extu = 1;
3664 break;
3665 case '4':
3666 nbits = 4;
3667 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
3668 signedp = 1;
3669 extbits = 15;
3670 break;
3671 case '5':
3672 nbits = 5;
3673 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3674 info->insn_type = dis_dref;
3675 info->data_size = 1;
3676 break;
3677 case 'H':
3678 nbits = 5;
3679 shift = 1;
3680 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3681 info->insn_type = dis_dref;
3682 info->data_size = 2;
3683 break;
3684 case 'W':
3685 nbits = 5;
3686 shift = 2;
3687 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3688 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
3689 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
3690 {
3691 info->insn_type = dis_dref;
3692 info->data_size = 4;
3693 }
3694 break;
3695 case 'D':
3696 nbits = 5;
3697 shift = 3;
3698 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3699 info->insn_type = dis_dref;
3700 info->data_size = 8;
3701 break;
3702 case 'j':
3703 nbits = 5;
3704 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3705 signedp = 1;
3706 break;
3707 case '6':
3708 nbits = 6;
3709 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
3710 break;
3711 case '8':
3712 nbits = 8;
3713 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3714 break;
3715 case 'V':
3716 nbits = 8;
3717 shift = 2;
3718 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3719 /* FIXME: This might be lw, or it might be addiu to $sp or
3720 $pc. We assume it's load. */
3721 info->insn_type = dis_dref;
3722 info->data_size = 4;
3723 break;
3724 case 'C':
3725 nbits = 8;
3726 shift = 3;
3727 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3728 info->insn_type = dis_dref;
3729 info->data_size = 8;
3730 break;
3731 case 'U':
3732 nbits = 8;
3733 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3734 extu = 1;
3735 break;
3736 case 'k':
3737 nbits = 8;
3738 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3739 signedp = 1;
3740 break;
3741 case 'K':
3742 nbits = 8;
3743 shift = 3;
3744 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3745 signedp = 1;
3746 break;
3747 case 'p':
3748 nbits = 8;
3749 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3750 signedp = 1;
3751 pcrel = 1;
3752 branch = 1;
3753 info->insn_type = dis_condbranch;
3754 break;
3755 case 'q':
3756 nbits = 11;
3757 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
3758 signedp = 1;
3759 pcrel = 1;
3760 branch = 1;
3761 info->insn_type = dis_branch;
3762 break;
3763 case 'A':
3764 nbits = 8;
3765 shift = 2;
3766 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
3767 pcrel = 1;
3768 /* FIXME: This can be lw or la. We assume it is lw. */
3769 info->insn_type = dis_dref;
3770 info->data_size = 4;
3771 break;
3772 case 'B':
3773 nbits = 5;
3774 shift = 3;
3775 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3776 pcrel = 1;
3777 info->insn_type = dis_dref;
3778 info->data_size = 8;
3779 break;
3780 case 'E':
3781 nbits = 5;
3782 shift = 2;
3783 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
3784 pcrel = 1;
3785 break;
3786 default:
3787 abort ();
3788 }
3789
3790 if (! use_extend)
3791 {
3792 if (signedp && immed >= (1 << (nbits - 1)))
3793 immed -= 1 << nbits;
3794 immed <<= shift;
3795 if ((type == '<' || type == '>' || type == '[' || type == ']')
3796 && immed == 0)
3797 immed = 8;
3798 }
3799 else
3800 {
3801 if (extbits == 16)
3802 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
3803 else if (extbits == 15)
3804 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
3805 else
3806 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
3807 immed &= (1 << extbits) - 1;
3808 if (! extu && immed >= (1 << (extbits - 1)))
3809 immed -= 1 << extbits;
3810 }
3811
3812 if (! pcrel)
3813 (*info->fprintf_func) (info->stream, "%d", immed);
3814 else
3815 {
3816 bfd_vma baseaddr;
3817
3818 if (branch)
3819 {
3820 immed *= 2;
3821 baseaddr = memaddr + 2;
3822 }
3823 else if (use_extend)
3824 baseaddr = memaddr - 2;
3825 else
3826 {
3827 int status;
3828 bfd_byte buffer[2];
3829
3830 baseaddr = memaddr;
3831
3832 /* If this instruction is in the delay slot of a jr
3833 instruction, the base address is the address of the
3834 jr instruction. If it is in the delay slot of jalr
3835 instruction, the base address is the address of the
3836 jalr instruction. This test is unreliable: we have
3837 no way of knowing whether the previous word is
3838 instruction or data. */
3839 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
3840 info);
3841 if (status == 0
3842 && (((info->endian == BFD_ENDIAN_BIG
3843 ? bfd_getb16 (buffer)
3844 : bfd_getl16 (buffer))
3845 & 0xf800) == 0x1800))
3846 baseaddr = memaddr - 4;
3847 else
3848 {
3849 status = (*info->read_memory_func) (memaddr - 2, buffer,
3850 2, info);
3851 if (status == 0
3852 && (((info->endian == BFD_ENDIAN_BIG
3853 ? bfd_getb16 (buffer)
3854 : bfd_getl16 (buffer))
3855 & 0xf81f) == 0xe800))
3856 baseaddr = memaddr - 2;
3857 }
3858 }
3859 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
3860 (*info->print_address_func) (info->target, info);
3861 }
3862 }
3863 break;
3864
3865 case 'a':
3866 if (! use_extend)
3867 extend = 0;
3868 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
3869 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
3870 (*info->print_address_func) (info->target, info);
3871 info->insn_type = dis_jsr;
3872 info->branch_delay_insns = 1;
3873 break;
3874
3875 case 'l':
3876 case 'L':
3877 {
3878 int need_comma, amask, smask;
3879
3880 need_comma = 0;
3881
3882 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
3883
3884 amask = (l >> 3) & 7;
3885
3886 if (amask > 0 && amask < 5)
3887 {
3888 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
3889 if (amask > 1)
3890 (*info->fprintf_func) (info->stream, "-%s",
3891 mips_gpr_names[amask + 3]);
3892 need_comma = 1;
3893 }
3894
3895 smask = (l >> 1) & 3;
3896 if (smask == 3)
3897 {
3898 (*info->fprintf_func) (info->stream, "%s??",
3899 need_comma ? "," : "");
3900 need_comma = 1;
3901 }
3902 else if (smask > 0)
3903 {
3904 (*info->fprintf_func) (info->stream, "%s%s",
3905 need_comma ? "," : "",
3906 mips_gpr_names[16]);
3907 if (smask > 1)
3908 (*info->fprintf_func) (info->stream, "-%s",
3909 mips_gpr_names[smask + 15]);
3910 need_comma = 1;
3911 }
3912
3913 if (l & 1)
3914 {
3915 (*info->fprintf_func) (info->stream, "%s%s",
3916 need_comma ? "," : "",
3917 mips_gpr_names[31]);
3918 need_comma = 1;
3919 }
3920
3921 if (amask == 5 || amask == 6)
3922 {
3923 (*info->fprintf_func) (info->stream, "%s$f0",
3924 need_comma ? "," : "");
3925 if (amask == 6)
3926 (*info->fprintf_func) (info->stream, "-$f1");
3927 }
3928 }
3929 break;
3930
3931 default:
3932 /* xgettext:c-format */
3933 (*info->fprintf_func)
3934 (info->stream,
3935 _("# internal disassembler error, unrecognised modifier (%c)"),
3936 type);
3937 abort ();
3938 }
3939 }
3940 #endif
3941
3942 void
3943 print_mips_disassembler_options (stream)
3944 FILE *stream;
3945 {
3946 unsigned int i;
3947
3948 fprintf (stream, _("\n\
3949 The following MIPS specific disassembler options are supported for use\n\
3950 with the -M switch (multiple options should be separated by commas):\n"));
3951
3952 fprintf (stream, _("\n\
3953 gpr-names=ABI Print GPR names according to specified ABI.\n\
3954 Default: based on binary being disassembled.\n"));
3955
3956 fprintf (stream, _("\n\
3957 fpr-names=ABI Print FPR names according to specified ABI.\n\
3958 Default: numeric.\n"));
3959
3960 fprintf (stream, _("\n\
3961 cp0-names=ARCH Print CP0 register names according to\n\
3962 specified architecture.\n\
3963 Default: based on binary being disassembled.\n"));
3964
3965 fprintf (stream, _("\n\
3966 hwr-names=ARCH Print HWR names according to specified \n\
3967 architecture.\n\
3968 Default: based on binary being disassembled.\n"));
3969
3970 fprintf (stream, _("\n\
3971 reg-names=ABI Print GPR and FPR names according to\n\
3972 specified ABI.\n"));
3973
3974 fprintf (stream, _("\n\
3975 reg-names=ARCH Print CP0 register and HWR names according to\n\
3976 specified architecture.\n"));
3977
3978 fprintf (stream, _("\n\
3979 For the options above, the following values are supported for \"ABI\":\n\
3980 "));
3981 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
3982 fprintf (stream, " %s", mips_abi_choices[i].name);
3983 fprintf (stream, _("\n"));
3984
3985 fprintf (stream, _("\n\
3986 For the options above, The following values are supported for \"ARCH\":\n\
3987 "));
3988 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
3989 if (*mips_arch_choices[i].name != '\0')
3990 fprintf (stream, " %s", mips_arch_choices[i].name);
3991 fprintf (stream, _("\n"));
3992
3993 fprintf (stream, _("\n"));
3994 }
Samsung s3c2440 and arm920t support for the mini2440 dev board