Add "cache" parameter to "-drive" (Laurent Vivier).
[qemu/mini2440.git] / hw / ppc4xx_devs.c
blobc4da27f4aad9bb3a82a6973a386b312da5391bfb
1 /*
2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc4xx.h"
27 #include "sysemu.h"
29 extern int loglevel;
30 extern FILE *logfile;
32 //#define DEBUG_MMIO
33 //#define DEBUG_UNASSIGNED
34 #define DEBUG_UIC
36 /*****************************************************************************/
37 /* Generic PowerPC 4xx processor instanciation */
38 CPUState *ppc4xx_init (const unsigned char *cpu_model,
39 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
40 uint32_t sysclk)
42 CPUState *env;
44 /* init CPUs */
45 env = cpu_init(cpu_model);
46 if (!env) {
47 fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
48 cpu_model);
49 exit(1);
51 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
52 cpu_clk->opaque = env;
53 /* Set time-base frequency to sysclk */
54 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
55 tb_clk->opaque = env;
56 ppc_dcr_init(env, NULL, NULL);
57 /* Register qemu callbacks */
58 qemu_register_reset(&cpu_ppc_reset, env);
59 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
61 return env;
64 /*****************************************************************************/
65 /* Fake device used to map multiple devices in a single memory page */
66 #define MMIO_AREA_BITS 8
67 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
68 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
69 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
70 struct ppc4xx_mmio_t {
71 target_phys_addr_t base;
72 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
73 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
74 void *opaque[MMIO_AREA_NB];
77 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
79 #ifdef DEBUG_UNASSIGNED
80 ppc4xx_mmio_t *mmio;
82 mmio = opaque;
83 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
84 addr, mmio->base);
85 #endif
87 return 0;
90 static void unassigned_mmio_writeb (void *opaque,
91 target_phys_addr_t addr, uint32_t val)
93 #ifdef DEBUG_UNASSIGNED
94 ppc4xx_mmio_t *mmio;
96 mmio = opaque;
97 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
98 addr, val, mmio->base);
99 #endif
102 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
103 unassigned_mmio_readb,
104 unassigned_mmio_readb,
105 unassigned_mmio_readb,
108 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
109 unassigned_mmio_writeb,
110 unassigned_mmio_writeb,
111 unassigned_mmio_writeb,
114 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
115 target_phys_addr_t addr, int len)
117 CPUReadMemoryFunc **mem_read;
118 uint32_t ret;
119 int idx;
121 idx = MMIO_IDX(addr - mmio->base);
122 #if defined(DEBUG_MMIO)
123 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
124 mmio, len, addr, idx);
125 #endif
126 mem_read = mmio->mem_read[idx];
127 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
129 return ret;
132 static void mmio_writelen (ppc4xx_mmio_t *mmio,
133 target_phys_addr_t addr, uint32_t value, int len)
135 CPUWriteMemoryFunc **mem_write;
136 int idx;
138 idx = MMIO_IDX(addr - mmio->base);
139 #if defined(DEBUG_MMIO)
140 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
141 __func__, mmio, len, addr, idx, value);
142 #endif
143 mem_write = mmio->mem_write[idx];
144 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
147 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
149 #if defined(DEBUG_MMIO)
150 printf("%s: addr " PADDRX "\n", __func__, addr);
151 #endif
153 return mmio_readlen(opaque, addr, 0);
156 static void mmio_writeb (void *opaque,
157 target_phys_addr_t addr, uint32_t value)
159 #if defined(DEBUG_MMIO)
160 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
161 #endif
162 mmio_writelen(opaque, addr, value, 0);
165 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
167 #if defined(DEBUG_MMIO)
168 printf("%s: addr " PADDRX "\n", __func__, addr);
169 #endif
171 return mmio_readlen(opaque, addr, 1);
174 static void mmio_writew (void *opaque,
175 target_phys_addr_t addr, uint32_t value)
177 #if defined(DEBUG_MMIO)
178 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
179 #endif
180 mmio_writelen(opaque, addr, value, 1);
183 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
185 #if defined(DEBUG_MMIO)
186 printf("%s: addr " PADDRX "\n", __func__, addr);
187 #endif
189 return mmio_readlen(opaque, addr, 2);
192 static void mmio_writel (void *opaque,
193 target_phys_addr_t addr, uint32_t value)
195 #if defined(DEBUG_MMIO)
196 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
197 #endif
198 mmio_writelen(opaque, addr, value, 2);
201 static CPUReadMemoryFunc *mmio_read[] = {
202 &mmio_readb,
203 &mmio_readw,
204 &mmio_readl,
207 static CPUWriteMemoryFunc *mmio_write[] = {
208 &mmio_writeb,
209 &mmio_writew,
210 &mmio_writel,
213 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
214 target_phys_addr_t offset, uint32_t len,
215 CPUReadMemoryFunc **mem_read,
216 CPUWriteMemoryFunc **mem_write, void *opaque)
218 target_phys_addr_t end;
219 int idx, eidx;
221 if ((offset + len) > TARGET_PAGE_SIZE)
222 return -1;
223 idx = MMIO_IDX(offset);
224 end = offset + len - 1;
225 eidx = MMIO_IDX(end);
226 #if defined(DEBUG_MMIO)
227 printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
228 __func__, offset, len, end, idx, eidx);
229 #endif
230 for (; idx <= eidx; idx++) {
231 mmio->mem_read[idx] = mem_read;
232 mmio->mem_write[idx] = mem_write;
233 mmio->opaque[idx] = opaque;
236 return 0;
239 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
241 ppc4xx_mmio_t *mmio;
242 int mmio_memory;
244 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
245 if (mmio != NULL) {
246 mmio->base = base;
247 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
248 #if defined(DEBUG_MMIO)
249 printf("%s: base " PADDRX " len %08x %d\n", __func__,
250 base, TARGET_PAGE_SIZE, mmio_memory);
251 #endif
252 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
253 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
254 unassigned_mmio_read, unassigned_mmio_write,
255 mmio);
258 return mmio;
261 /*****************************************************************************/
262 /* "Universal" Interrupt controller */
263 enum {
264 DCR_UICSR = 0x000,
265 DCR_UICSRS = 0x001,
266 DCR_UICER = 0x002,
267 DCR_UICCR = 0x003,
268 DCR_UICPR = 0x004,
269 DCR_UICTR = 0x005,
270 DCR_UICMSR = 0x006,
271 DCR_UICVR = 0x007,
272 DCR_UICVCR = 0x008,
273 DCR_UICMAX = 0x009,
276 #define UIC_MAX_IRQ 32
277 typedef struct ppcuic_t ppcuic_t;
278 struct ppcuic_t {
279 uint32_t dcr_base;
280 int use_vectors;
281 uint32_t uicsr; /* Status register */
282 uint32_t uicer; /* Enable register */
283 uint32_t uiccr; /* Critical register */
284 uint32_t uicpr; /* Polarity register */
285 uint32_t uictr; /* Triggering register */
286 uint32_t uicvcr; /* Vector configuration register */
287 uint32_t uicvr;
288 qemu_irq *irqs;
291 static void ppcuic_trigger_irq (ppcuic_t *uic)
293 uint32_t ir, cr;
294 int start, end, inc, i;
296 /* Trigger interrupt if any is pending */
297 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
298 cr = uic->uicsr & uic->uicer & uic->uiccr;
299 #ifdef DEBUG_UIC
300 if (loglevel & CPU_LOG_INT) {
301 fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
302 " uiccr %08" PRIx32 "\n"
303 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
304 __func__, uic->uicsr, uic->uicer, uic->uiccr,
305 uic->uicsr & uic->uicer, ir, cr);
307 #endif
308 if (ir != 0x0000000) {
309 #ifdef DEBUG_UIC
310 if (loglevel & CPU_LOG_INT) {
311 fprintf(logfile, "Raise UIC interrupt\n");
313 #endif
314 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
315 } else {
316 #ifdef DEBUG_UIC
317 if (loglevel & CPU_LOG_INT) {
318 fprintf(logfile, "Lower UIC interrupt\n");
320 #endif
321 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
323 /* Trigger critical interrupt if any is pending and update vector */
324 if (cr != 0x0000000) {
325 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
326 if (uic->use_vectors) {
327 /* Compute critical IRQ vector */
328 if (uic->uicvcr & 1) {
329 start = 31;
330 end = 0;
331 inc = -1;
332 } else {
333 start = 0;
334 end = 31;
335 inc = 1;
337 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
338 for (i = start; i <= end; i += inc) {
339 if (cr & (1 << i)) {
340 uic->uicvr += (i - start) * 512 * inc;
341 break;
345 #ifdef DEBUG_UIC
346 if (loglevel & CPU_LOG_INT) {
347 fprintf(logfile, "Raise UIC critical interrupt - "
348 "vector %08" PRIx32 "\n", uic->uicvr);
350 #endif
351 } else {
352 #ifdef DEBUG_UIC
353 if (loglevel & CPU_LOG_INT) {
354 fprintf(logfile, "Lower UIC critical interrupt\n");
356 #endif
357 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
358 uic->uicvr = 0x00000000;
362 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
364 ppcuic_t *uic;
365 uint32_t mask, sr;
367 uic = opaque;
368 mask = 1 << irq_num;
369 #ifdef DEBUG_UIC
370 if (loglevel & CPU_LOG_INT) {
371 fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
372 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
373 __func__, irq_num, level,
374 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
376 #endif
377 if (irq_num < 0 || irq_num > 31)
378 return;
379 sr = uic->uicsr;
380 if (!(uic->uicpr & mask)) {
381 /* Negatively asserted IRQ */
382 level = level == 0 ? 1 : 0;
384 /* Update status register */
385 if (uic->uictr & mask) {
386 /* Edge sensitive interrupt */
387 if (level == 1)
388 uic->uicsr |= mask;
389 } else {
390 /* Level sensitive interrupt */
391 if (level == 1)
392 uic->uicsr |= mask;
393 else
394 uic->uicsr &= ~mask;
396 #ifdef DEBUG_UIC
397 if (loglevel & CPU_LOG_INT) {
398 fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
399 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
401 #endif
402 if (sr != uic->uicsr)
403 ppcuic_trigger_irq(uic);
406 static target_ulong dcr_read_uic (void *opaque, int dcrn)
408 ppcuic_t *uic;
409 target_ulong ret;
411 uic = opaque;
412 dcrn -= uic->dcr_base;
413 switch (dcrn) {
414 case DCR_UICSR:
415 case DCR_UICSRS:
416 ret = uic->uicsr;
417 break;
418 case DCR_UICER:
419 ret = uic->uicer;
420 break;
421 case DCR_UICCR:
422 ret = uic->uiccr;
423 break;
424 case DCR_UICPR:
425 ret = uic->uicpr;
426 break;
427 case DCR_UICTR:
428 ret = uic->uictr;
429 break;
430 case DCR_UICMSR:
431 ret = uic->uicsr & uic->uicer;
432 break;
433 case DCR_UICVR:
434 if (!uic->use_vectors)
435 goto no_read;
436 ret = uic->uicvr;
437 break;
438 case DCR_UICVCR:
439 if (!uic->use_vectors)
440 goto no_read;
441 ret = uic->uicvcr;
442 break;
443 default:
444 no_read:
445 ret = 0x00000000;
446 break;
449 return ret;
452 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
454 ppcuic_t *uic;
456 uic = opaque;
457 dcrn -= uic->dcr_base;
458 #ifdef DEBUG_UIC
459 if (loglevel & CPU_LOG_INT) {
460 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
462 #endif
463 switch (dcrn) {
464 case DCR_UICSR:
465 uic->uicsr &= ~val;
466 ppcuic_trigger_irq(uic);
467 break;
468 case DCR_UICSRS:
469 uic->uicsr |= val;
470 ppcuic_trigger_irq(uic);
471 break;
472 case DCR_UICER:
473 uic->uicer = val;
474 ppcuic_trigger_irq(uic);
475 break;
476 case DCR_UICCR:
477 uic->uiccr = val;
478 ppcuic_trigger_irq(uic);
479 break;
480 case DCR_UICPR:
481 uic->uicpr = val;
482 ppcuic_trigger_irq(uic);
483 break;
484 case DCR_UICTR:
485 uic->uictr = val;
486 ppcuic_trigger_irq(uic);
487 break;
488 case DCR_UICMSR:
489 break;
490 case DCR_UICVR:
491 break;
492 case DCR_UICVCR:
493 uic->uicvcr = val & 0xFFFFFFFD;
494 ppcuic_trigger_irq(uic);
495 break;
499 static void ppcuic_reset (void *opaque)
501 ppcuic_t *uic;
503 uic = opaque;
504 uic->uiccr = 0x00000000;
505 uic->uicer = 0x00000000;
506 uic->uicpr = 0x00000000;
507 uic->uicsr = 0x00000000;
508 uic->uictr = 0x00000000;
509 if (uic->use_vectors) {
510 uic->uicvcr = 0x00000000;
511 uic->uicvr = 0x0000000;
515 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
516 uint32_t dcr_base, int has_ssr, int has_vr)
518 ppcuic_t *uic;
519 int i;
521 uic = qemu_mallocz(sizeof(ppcuic_t));
522 if (uic != NULL) {
523 uic->dcr_base = dcr_base;
524 uic->irqs = irqs;
525 if (has_vr)
526 uic->use_vectors = 1;
527 for (i = 0; i < DCR_UICMAX; i++) {
528 ppc_dcr_register(env, dcr_base + i, uic,
529 &dcr_read_uic, &dcr_write_uic);
531 qemu_register_reset(ppcuic_reset, uic);
532 ppcuic_reset(uic);
535 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);