exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 struct TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 64
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 /* Maximum size a TCG op can expand to.  This is complicated because a
  40    single op may require several host instructions and regirster reloads.
  41    For now take a wild guess at 128 bytes, which should allow at least
  42    a couple of fixup instructions per argument.  */
  43 #define TCG_MAX_OP_SIZE 128
  44
  45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  46
  47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  51 extern target_ulong gen_opc_jump_pc[2];
  52 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  53
  54 typedef void (GenOpFunc)(void);
  55 typedef void (GenOpFunc1)(long);
  56 typedef void (GenOpFunc2)(long, long);
  57 typedef void (GenOpFunc3)(long, long, long);
  58
  59 extern FILE *logfile;
  60 extern int loglevel;
  61
  62 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  63 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  64 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  65                  unsigned long searched_pc, int pc_pos, void *puc);
  66
  67 unsigned long code_gen_max_block_size(void);
  68 void cpu_gen_init(void);
  69 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  70                  int *gen_code_size_ptr);
  71 int cpu_restore_state(struct TranslationBlock *tb,
  72                       CPUState *env, unsigned long searched_pc,
  73                       void *puc);
  74 int cpu_restore_state_copy(struct TranslationBlock *tb,
  75                            CPUState *env, unsigned long searched_pc,
  76                            void *puc);
  77 void cpu_resume_from_signal(CPUState *env1, void *puc);
  78 void cpu_exec_init(CPUState *env);
  79 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  80 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  81                                    int is_cpu_write_access);
  82 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  83 void tlb_flush_page(CPUState *env, target_ulong addr);
  84 void tlb_flush(CPUState *env, int flush_global);
  85 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  86                       target_phys_addr_t paddr, int prot,
  87                       int mmu_idx, int is_softmmu);
  88 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  89                                target_phys_addr_t paddr, int prot,
  90                                int mmu_idx, int is_softmmu)
  91 {
  92     if (prot & PAGE_READ)
  93         prot |= PAGE_EXEC;
  94     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
  95 }
  96
  97 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  98
  99 #define CODE_GEN_PHYS_HASH_BITS     15
 100 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 101
 102 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 103
 104 /* estimated block size for TB allocation */
 105 /* XXX: use a per code average code fragment size and modulate it
 106    according to the host CPU */
 107 #if defined(CONFIG_SOFTMMU)
 108 #define CODE_GEN_AVG_BLOCK_SIZE 128
 109 #else
 110 #define CODE_GEN_AVG_BLOCK_SIZE 64
 111 #endif
 112
 113 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
 114 #define USE_DIRECT_JUMP
 115 #endif
 116 #if defined(__i386__) && !defined(_WIN32)
 117 #define USE_DIRECT_JUMP
 118 #endif
 119
 120 typedef struct TranslationBlock {
 121     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 122     target_ulong cs_base; /* CS base for this block */
 123     uint64_t flags; /* flags defining in which context the code was generated */
 124     uint16_t size;      /* size of target code for this block (1 <=
 125                            size <= TARGET_PAGE_SIZE) */
 126     uint16_t cflags;    /* compile flags */
 127 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 128 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 129 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 130
 131     uint8_t *tc_ptr;    /* pointer to the translated code */
 132     /* next matching tb for physical address. */
 133     struct TranslationBlock *phys_hash_next;
 134     /* first and second physical page containing code. The lower bit
 135        of the pointer tells the index in page_next[] */
 136     struct TranslationBlock *page_next[2];
 137     target_ulong page_addr[2];
 138
 139     /* the following data are used to directly call another TB from
 140        the code of this one. */
 141     uint16_t tb_next_offset[2]; /* offset of original jump target */
 142 #ifdef USE_DIRECT_JUMP
 143     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 144 #else
 145     unsigned long tb_next[2]; /* address of jump generated code */
 146 #endif
 147     /* list of TBs jumping to this one. This is a circular list using
 148        the two least significant bits of the pointers to tell what is
 149        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 150        jmp_first */
 151     struct TranslationBlock *jmp_next[2];
 152     struct TranslationBlock *jmp_first;
 153 } TranslationBlock;
 154
 155 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 156 {
 157     target_ulong tmp;
 158     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 159     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 160 }
 161
 162 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 163 {
 164     target_ulong tmp;
 165     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 166     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 167             | (tmp & TB_JMP_ADDR_MASK));
 168 }
 169
 170 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 171 {
 172     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 173 }
 174
 175 TranslationBlock *tb_alloc(target_ulong pc);
 176 void tb_flush(CPUState *env);
 177 void tb_link_phys(TranslationBlock *tb,
 178                   target_ulong phys_pc, target_ulong phys_page2);
 179
 180 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 181 extern uint8_t *code_gen_ptr;
 182 extern int code_gen_max_blocks;
 183
 184 #if defined(USE_DIRECT_JUMP)
 185
 186 #if defined(__powerpc__)
 187 static inline void flush_icache_range(unsigned long start, unsigned long stop);
 188 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 189 {
 190     /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
 191     uint32_t *ptr;
 192     long disp = addr - jmp_addr;
 193     unsigned long patch_size;
 194
 195     ptr = (uint32_t *)jmp_addr;
 196
 197     if ((disp << 6) >> 6 != disp) {
 198         ptr[0] = 0x3c000000 | (addr >> 16);    /* lis 0,addr@ha */
 199         ptr[1] = 0x60000000 | (addr & 0xffff); /* la  0,addr@l(0) */
 200         ptr[2] = 0x7c0903a6;                   /* mtctr 0 */
 201         ptr[3] = 0x4e800420;                   /* brctr */
 202         patch_size = 16;
 203     } else {
 204         /* patch the branch destination */
 205         if (disp != 16) {
 206             *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
 207             patch_size = 4;
 208         } else {
 209             ptr[0] = 0x60000000; /* nop */
 210             ptr[1] = 0x60000000;
 211             ptr[2] = 0x60000000;
 212             ptr[3] = 0x60000000;
 213             patch_size = 16;
 214         }
 215     }
 216     /* flush icache */
 217     flush_icache_range(jmp_addr, jmp_addr + patch_size);
 218 }
 219 #elif defined(__i386__) || defined(__x86_64__)
 220 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 221 {
 222     /* patch the branch destination */
 223     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 224     /* no need to flush icache explicitly */
 225 }
 226 #elif defined(__arm__)
 227 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 228 {
 229     register unsigned long _beg __asm ("a1");
 230     register unsigned long _end __asm ("a2");
 231     register unsigned long _flg __asm ("a3");
 232
 233     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 234     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 235
 236     /* flush icache */
 237     _beg = jmp_addr;
 238     _end = jmp_addr + 4;
 239     _flg = 0;
 240     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 241 }
 242 #endif
 243
 244 static inline void tb_set_jmp_target(TranslationBlock *tb,
 245                                      int n, unsigned long addr)
 246 {
 247     unsigned long offset;
 248
 249     offset = tb->tb_jmp_offset[n];
 250     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 251     offset = tb->tb_jmp_offset[n + 2];
 252     if (offset != 0xffff)
 253         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 254 }
 255
 256 #else
 257
 258 /* set the jump target */
 259 static inline void tb_set_jmp_target(TranslationBlock *tb,
 260                                      int n, unsigned long addr)
 261 {
 262     tb->tb_next[n] = addr;
 263 }
 264
 265 #endif
 266
 267 static inline void tb_add_jump(TranslationBlock *tb, int n,
 268                                TranslationBlock *tb_next)
 269 {
 270     /* NOTE: this test is only needed for thread safety */
 271     if (!tb->jmp_next[n]) {
 272         /* patch the native jump address */
 273         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 274
 275         /* add in TB jmp circular list */
 276         tb->jmp_next[n] = tb_next->jmp_first;
 277         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 278     }
 279 }
 280
 281 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 282
 283 #ifndef offsetof
 284 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 285 #endif
 286
 287 #if defined(_WIN32)
 288 #define ASM_DATA_SECTION ".section \".data\"\n"
 289 #define ASM_PREVIOUS_SECTION ".section .text\n"
 290 #elif defined(__APPLE__)
 291 #define ASM_DATA_SECTION ".data\n"
 292 #define ASM_PREVIOUS_SECTION ".text\n"
 293 #else
 294 #define ASM_DATA_SECTION ".section \".data\"\n"
 295 #define ASM_PREVIOUS_SECTION ".previous\n"
 296 #endif
 297
 298 #define ASM_OP_LABEL_NAME(n, opname) \
 299     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 300
 301 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 302 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 303 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 304
 305 #include "qemu-lock.h"
 306
 307 extern spinlock_t tb_lock;
 308
 309 extern int tb_invalidated_flag;
 310
 311 #if !defined(CONFIG_USER_ONLY)
 312
 313 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 314               void *retaddr);
 315
 316 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 317 #define MEMSUFFIX _code
 318 #define env cpu_single_env
 319
 320 #define DATA_SIZE 1
 321 #include "softmmu_header.h"
 322
 323 #define DATA_SIZE 2
 324 #include "softmmu_header.h"
 325
 326 #define DATA_SIZE 4
 327 #include "softmmu_header.h"
 328
 329 #define DATA_SIZE 8
 330 #include "softmmu_header.h"
 331
 332 #undef ACCESS_TYPE
 333 #undef MEMSUFFIX
 334 #undef env
 335
 336 #endif
 337
 338 #if defined(CONFIG_USER_ONLY)
 339 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 340 {
 341     return addr;
 342 }
 343 #else
 344 /* NOTE: this function can trigger an exception */
 345 /* NOTE2: the returned address is not exactly the physical address: it
 346    is the offset relative to phys_ram_base */
 347 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 348 {
 349     int mmu_idx, page_index, pd;
 350
 351     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 352     mmu_idx = cpu_mmu_index(env1);
 353     if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
 354                          (addr & TARGET_PAGE_MASK), 0)) {
 355         ldub_code(addr);
 356     }
 357     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 358     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 359 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 360         do_unassigned_access(addr, 0, 1, 0);
 361 #else
 362         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 363 #endif
 364     }
 365     return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 366 }
 367 #endif
 368
 369 #ifdef USE_KQEMU
 370 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 371
 372 #define MSR_QPI_COMMBASE 0xfabe0010
 373
 374 int kqemu_init(CPUState *env);
 375 int kqemu_cpu_exec(CPUState *env);
 376 void kqemu_flush_page(CPUState *env, target_ulong addr);
 377 void kqemu_flush(CPUState *env, int global);
 378 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 379 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 380 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
 381                         ram_addr_t phys_offset);
 382 void kqemu_cpu_interrupt(CPUState *env);
 383 void kqemu_record_dump(void);
 384
 385 extern uint32_t kqemu_comm_base;
 386
 387 static inline int kqemu_is_ok(CPUState *env)
 388 {
 389     return(env->kqemu_enabled &&
 390            (env->cr[0] & CR0_PE_MASK) &&
 391            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 392            (env->eflags & IF_MASK) &&
 393            !(env->eflags & VM_MASK) &&
 394            (env->kqemu_enabled == 2 ||
 395             ((env->hflags & HF_CPL_MASK) == 3 &&
 396              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 397 }
 398
 399 #endif