hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27
  28 #define VERBOSE
  29 #define EMBED_STDVGA
  30 #undef DIRECT_VRAM
  31 #define HW_RECT_ACCEL
  32 #define HW_FILL_ACCEL
  33 #define HW_MOUSE_ACCEL
  34
  35 #ifdef EMBED_STDVGA
  36 # include "vga_int.h"
  37 #endif
  38
  39 struct vmsvga_state_s {
  40 #ifdef EMBED_STDVGA
  41     VGA_STATE_COMMON
  42 #endif
  43
  44     int width;
  45     int height;
  46     int invalidated;
  47     int depth;
  48     int bypp;
  49     int enable;
  50     int config;
  51     struct {
  52         int id;
  53         int x;
  54         int y;
  55         int on;
  56     } cursor;
  57
  58 #ifndef EMBED_STDVGA
  59     DisplayState *ds;
  60     int vram_size;
  61 #endif
  62     uint8_t *vram;
  63     target_phys_addr_t vram_base;
  64
  65     int index;
  66     int scratch_size;
  67     uint32_t *scratch;
  68     int new_width;
  69     int new_height;
  70     uint32_t guest;
  71     uint32_t svgaid;
  72     uint32_t wred;
  73     uint32_t wgreen;
  74     uint32_t wblue;
  75     int syncing;
  76     int fb_size;
  77
  78     union {
  79         uint32_t *fifo;
  80         struct __attribute__((__packed__)) {
  81             uint32_t min;
  82             uint32_t max;
  83             uint32_t next_cmd;
  84             uint32_t stop;
  85             /* Add registers here when adding capabilities.  */
  86             uint32_t fifo[0];
  87         } *cmd;
  88     };
  89
  90 #define REDRAW_FIFO_LEN 512
  91     struct vmsvga_rect_s {
  92         int x, y, w, h;
  93     } redraw_fifo[REDRAW_FIFO_LEN];
  94     int redraw_fifo_first, redraw_fifo_last;
  95 };
  96
  97 struct pci_vmsvga_state_s {
  98     PCIDevice card;
  99     struct vmsvga_state_s chip;
 100 };
 101
 102 #define SVGA_MAGIC              0x900000UL
 103 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 104 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 105 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 106 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 107
 108 #define SVGA_LEGACY_BASE_PORT   0x4560
 109 #define SVGA_INDEX_PORT         0x0
 110 #define SVGA_VALUE_PORT         0x1
 111 #define SVGA_BIOS_PORT          0x2
 112
 113 #define SVGA_VERSION_2
 114
 115 #ifdef SVGA_VERSION_2
 116 # define SVGA_ID                SVGA_ID_2
 117 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 118 # define SVGA_IO_MUL            1
 119 # define SVGA_FIFO_SIZE         0x10000
 120 # define SVGA_MEM_BASE          0xe0000000
 121 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 122 #else
 123 # define SVGA_ID                SVGA_ID_1
 124 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 125 # define SVGA_IO_MUL            4
 126 # define SVGA_FIFO_SIZE         0x10000
 127 # define SVGA_MEM_BASE          0xe0000000
 128 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 129 #endif
 130
 131 enum {
 132     /* ID 0, 1 and 2 registers */
 133     SVGA_REG_ID = 0,
 134     SVGA_REG_ENABLE = 1,
 135     SVGA_REG_WIDTH = 2,
 136     SVGA_REG_HEIGHT = 3,
 137     SVGA_REG_MAX_WIDTH = 4,
 138     SVGA_REG_MAX_HEIGHT = 5,
 139     SVGA_REG_DEPTH = 6,
 140     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 141     SVGA_REG_PSEUDOCOLOR = 8,
 142     SVGA_REG_RED_MASK = 9,
 143     SVGA_REG_GREEN_MASK = 10,
 144     SVGA_REG_BLUE_MASK = 11,
 145     SVGA_REG_BYTES_PER_LINE = 12,
 146     SVGA_REG_FB_START = 13,
 147     SVGA_REG_FB_OFFSET = 14,
 148     SVGA_REG_VRAM_SIZE = 15,
 149     SVGA_REG_FB_SIZE = 16,
 150
 151     /* ID 1 and 2 registers */
 152     SVGA_REG_CAPABILITIES = 17,
 153     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 154     SVGA_REG_MEM_SIZE = 19,
 155     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 156     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 157     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 158     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 159     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 160     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 161     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 162     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 163     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 164     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 165     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 166     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 167     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 168
 169     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 170     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 171     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 172 };
 173
 174 #define SVGA_CAP_NONE                   0
 175 #define SVGA_CAP_RECT_FILL              (1 << 0)
 176 #define SVGA_CAP_RECT_COPY              (1 << 1)
 177 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 178 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 179 #define SVGA_CAP_RASTER_OP              (1 << 4)
 180 #define SVGA_CAP_CURSOR                 (1 << 5)
 181 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 182 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 183 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 184 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 185 #define SVGA_CAP_GLYPH                  (1 << 10)
 186 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 187 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 188 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 189 #define SVGA_CAP_3D                     (1 << 14)
 190 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 191 #define SVGA_CAP_MULTIMON               (1 << 16)
 192 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 193
 194 /*
 195  * FIFO offsets (seen as an array of 32-bit words)
 196  */
 197 enum {
 198     /*
 199      * The original defined FIFO offsets
 200      */
 201     SVGA_FIFO_MIN = 0,
 202     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 203     SVGA_FIFO_NEXT_CMD,
 204     SVGA_FIFO_STOP,
 205
 206     /*
 207      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 208      */
 209     SVGA_FIFO_CAPABILITIES = 4,
 210     SVGA_FIFO_FLAGS,
 211     SVGA_FIFO_FENCE,
 212     SVGA_FIFO_3D_HWVERSION,
 213     SVGA_FIFO_PITCHLOCK,
 214 };
 215
 216 #define SVGA_FIFO_CAP_NONE              0
 217 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 218 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 219 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 220
 221 #define SVGA_FIFO_FLAG_NONE             0
 222 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 223
 224 /* These values can probably be changed arbitrarily.  */
 225 #define SVGA_SCRATCH_SIZE               0x8000
 226 #define SVGA_MAX_WIDTH                  2360
 227 #define SVGA_MAX_HEIGHT                 1770
 228
 229 #ifdef VERBOSE
 230 # define GUEST_OS_BASE          0x5001
 231 static const char *vmsvga_guest_id[] = {
 232     [0x00 ... 0x15] = "an unknown OS",
 233     [0x00] = "Dos",
 234     [0x01] = "Windows 3.1",
 235     [0x02] = "Windows 95",
 236     [0x03] = "Windows 98",
 237     [0x04] = "Windows ME",
 238     [0x05] = "Windows NT",
 239     [0x06] = "Windows 2000",
 240     [0x07] = "Linux",
 241     [0x08] = "OS/2",
 242     [0x0a] = "BSD",
 243     [0x0b] = "Whistler",
 244     [0x15] = "Windows 2003",
 245 };
 246 #endif
 247
 248 enum {
 249     SVGA_CMD_INVALID_CMD = 0,
 250     SVGA_CMD_UPDATE = 1,
 251     SVGA_CMD_RECT_FILL = 2,
 252     SVGA_CMD_RECT_COPY = 3,
 253     SVGA_CMD_DEFINE_BITMAP = 4,
 254     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 255     SVGA_CMD_DEFINE_PIXMAP = 6,
 256     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 257     SVGA_CMD_RECT_BITMAP_FILL = 8,
 258     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 259     SVGA_CMD_RECT_BITMAP_COPY = 10,
 260     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 261     SVGA_CMD_FREE_OBJECT = 12,
 262     SVGA_CMD_RECT_ROP_FILL = 13,
 263     SVGA_CMD_RECT_ROP_COPY = 14,
 264     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 265     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 266     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 267     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 268     SVGA_CMD_DEFINE_CURSOR = 19,
 269     SVGA_CMD_DISPLAY_CURSOR = 20,
 270     SVGA_CMD_MOVE_CURSOR = 21,
 271     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 272     SVGA_CMD_DRAW_GLYPH = 23,
 273     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 274     SVGA_CMD_UPDATE_VERBOSE = 25,
 275     SVGA_CMD_SURFACE_FILL = 26,
 276     SVGA_CMD_SURFACE_COPY = 27,
 277     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 278     SVGA_CMD_FRONT_ROP_FILL = 29,
 279     SVGA_CMD_FENCE = 30,
 280 };
 281
 282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 283 enum {
 284     SVGA_CURSOR_ON_HIDE = 0,
 285     SVGA_CURSOR_ON_SHOW = 1,
 286     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 287     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 288 };
 289
 290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 291                 int x, int y, int w, int h)
 292 {
 293 #ifndef DIRECT_VRAM
 294     int line = h;
 295     int bypl = s->bypp * s->width;
 296     int width = s->bypp * w;
 297     int start = s->bypp * x + bypl * y;
 298     uint8_t *src = s->vram + start;
 299     uint8_t *dst = s->ds->data + start;
 300
 301     for (; line > 0; line --, src += bypl, dst += bypl)
 302         memcpy(dst, src, width);
 303 #endif
 304
 305     dpy_update(s->ds, x, y, w, h);
 306 }
 307
 308 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 309 {
 310 #ifndef DIRECT_VRAM
 311     memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
 312 #endif
 313
 314     dpy_update(s->ds, 0, 0, s->width, s->height);
 315 }
 316
 317 #ifdef DIRECT_VRAM
 318 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 319 #else
 320 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 321                 int x, int y, int w, int h)
 322 {
 323     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 324     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 325     rect->x = x;
 326     rect->y = y;
 327     rect->w = w;
 328     rect->h = h;
 329 }
 330 #endif
 331
 332 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 333 {
 334     struct vmsvga_rect_s *rect;
 335     if (s->invalidated) {
 336         s->redraw_fifo_first = s->redraw_fifo_last;
 337         return;
 338     }
 339     /* Overlapping region updates can be optimised out here - if someone
 340      * knows a smart algorithm to do that, please share.  */
 341     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 342         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 343         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 344         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 345     }
 346 }
 347
 348 #ifdef HW_RECT_ACCEL
 349 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 350                 int x0, int y0, int x1, int y1, int w, int h)
 351 {
 352 # ifdef DIRECT_VRAM
 353     uint8_t *vram = s->ds->data;
 354 # else
 355     uint8_t *vram = s->vram;
 356 # endif
 357     int bypl = s->bypp * s->width;
 358     int width = s->bypp * w;
 359     int line = h;
 360     uint8_t *ptr[2];
 361
 362 # ifdef DIRECT_VRAM
 363     if (s->ds->dpy_copy)
 364         s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
 365     else
 366 # endif
 367     {
 368         if (y1 > y0) {
 369             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 370             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 371             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 372                 memmove(ptr[1], ptr[0], width);
 373         } else {
 374             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 375             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 376             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 377                 memmove(ptr[1], ptr[0], width);
 378         }
 379     }
 380
 381     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 382 }
 383 #endif
 384
 385 #ifdef HW_FILL_ACCEL
 386 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 387                 uint32_t c, int x, int y, int w, int h)
 388 {
 389 # ifdef DIRECT_VRAM
 390     uint8_t *vram = s->ds->data;
 391 # else
 392     uint8_t *vram = s->vram;
 393 # endif
 394     int bypp = s->bypp;
 395     int bypl = bypp * s->width;
 396     int width = bypp * w;
 397     int line = h;
 398     int column;
 399     uint8_t *fst = vram + bypp * x + bypl * y;
 400     uint8_t *dst;
 401     uint8_t *src;
 402     uint8_t col[4];
 403
 404 # ifdef DIRECT_VRAM
 405     if (s->ds->dpy_fill)
 406         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 407     else
 408 # endif
 409     {
 410         col[0] = c;
 411         col[1] = c >> 8;
 412         col[2] = c >> 16;
 413         col[3] = c >> 24;
 414
 415         if (line --) {
 416             dst = fst;
 417             src = col;
 418             for (column = width; column > 0; column --) {
 419                 *(dst ++) = *(src ++);
 420                 if (src - col == bypp)
 421                     src = col;
 422             }
 423             dst = fst;
 424             for (; line > 0; line --) {
 425                 dst += bypl;
 426                 memcpy(dst, fst, width);
 427             }
 428         }
 429     }
 430
 431     vmsvga_update_rect_delayed(s, x, y, w, h);
 432 }
 433 #endif
 434
 435 struct vmsvga_cursor_definition_s {
 436     int width;
 437     int height;
 438     int id;
 439     int bpp;
 440     int hot_x;
 441     int hot_y;
 442     uint32_t mask[1024];
 443     uint32_t image[1024];
 444 };
 445
 446 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 447 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 448
 449 #ifdef HW_MOUSE_ACCEL
 450 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 451                 struct vmsvga_cursor_definition_s *c)
 452 {
 453     int i;
 454     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 455         c->mask[i] = ~c->mask[i];
 456
 457     if (s->ds->cursor_define)
 458         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 459                         (uint8_t *) c->image, (uint8_t *) c->mask);
 460 }
 461 #endif
 462
 463 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 464 {
 465     if (!s->config || !s->enable)
 466         return 1;
 467     return (s->cmd->next_cmd == s->cmd->stop);
 468 }
 469
 470 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 471 {
 472     uint32_t cmd = s->fifo[s->cmd->stop >> 2];
 473     s->cmd->stop += 4;
 474     if (s->cmd->stop >= s->cmd->max)
 475         s->cmd->stop = s->cmd->min;
 476     return cmd;
 477 }
 478
 479 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 480 {
 481     uint32_t cmd, colour;
 482     int args = 0;
 483     int x, y, dx, dy, width, height;
 484     struct vmsvga_cursor_definition_s cursor;
 485     while (!vmsvga_fifo_empty(s))
 486         switch (cmd = vmsvga_fifo_read(s)) {
 487         case SVGA_CMD_UPDATE:
 488         case SVGA_CMD_UPDATE_VERBOSE:
 489             x = vmsvga_fifo_read(s);
 490             y = vmsvga_fifo_read(s);
 491             width = vmsvga_fifo_read(s);
 492             height = vmsvga_fifo_read(s);
 493             vmsvga_update_rect_delayed(s, x, y, width, height);
 494             break;
 495
 496         case SVGA_CMD_RECT_FILL:
 497             colour = vmsvga_fifo_read(s);
 498             x = vmsvga_fifo_read(s);
 499             y = vmsvga_fifo_read(s);
 500             width = vmsvga_fifo_read(s);
 501             height = vmsvga_fifo_read(s);
 502 #ifdef HW_FILL_ACCEL
 503             vmsvga_fill_rect(s, colour, x, y, width, height);
 504             break;
 505 #else
 506             goto badcmd;
 507 #endif
 508
 509         case SVGA_CMD_RECT_COPY:
 510             x = vmsvga_fifo_read(s);
 511             y = vmsvga_fifo_read(s);
 512             dx = vmsvga_fifo_read(s);
 513             dy = vmsvga_fifo_read(s);
 514             width = vmsvga_fifo_read(s);
 515             height = vmsvga_fifo_read(s);
 516 #ifdef HW_RECT_ACCEL
 517             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 518             break;
 519 #else
 520             goto badcmd;
 521 #endif
 522
 523         case SVGA_CMD_DEFINE_CURSOR:
 524             cursor.id = vmsvga_fifo_read(s);
 525             cursor.hot_x = vmsvga_fifo_read(s);
 526             cursor.hot_y = vmsvga_fifo_read(s);
 527             cursor.width = x = vmsvga_fifo_read(s);
 528             cursor.height = y = vmsvga_fifo_read(s);
 529             vmsvga_fifo_read(s);
 530             cursor.bpp = vmsvga_fifo_read(s);
 531             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 532                 cursor.mask[args] = vmsvga_fifo_read(s);
 533             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 534                 cursor.image[args] = vmsvga_fifo_read(s);
 535 #ifdef HW_MOUSE_ACCEL
 536             vmsvga_cursor_define(s, &cursor);
 537             break;
 538 #else
 539             args = 0;
 540             goto badcmd;
 541 #endif
 542
 543         /*
 544          * Other commands that we at least know the number of arguments
 545          * for so we can avoid FIFO desync if driver uses them illegally.
 546          */
 547         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 548             vmsvga_fifo_read(s);
 549             vmsvga_fifo_read(s);
 550             vmsvga_fifo_read(s);
 551             x = vmsvga_fifo_read(s);
 552             y = vmsvga_fifo_read(s);
 553             args = x * y;
 554             goto badcmd;
 555         case SVGA_CMD_RECT_ROP_FILL:
 556             args = 6;
 557             goto badcmd;
 558         case SVGA_CMD_RECT_ROP_COPY:
 559             args = 7;
 560             goto badcmd;
 561         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 562             vmsvga_fifo_read(s);
 563             vmsvga_fifo_read(s);
 564             args = 7 + (vmsvga_fifo_read(s) >> 2);
 565             goto badcmd;
 566         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 567             args = 12;
 568             goto badcmd;
 569
 570         /*
 571          * Other commands that are not listed as depending on any
 572          * CAPABILITIES bits, but are not described in the README either.
 573          */
 574         case SVGA_CMD_SURFACE_FILL:
 575         case SVGA_CMD_SURFACE_COPY:
 576         case SVGA_CMD_FRONT_ROP_FILL:
 577         case SVGA_CMD_FENCE:
 578         case SVGA_CMD_INVALID_CMD:
 579             break; /* Nop */
 580
 581         default:
 582         badcmd:
 583             while (args --)
 584                 vmsvga_fifo_read(s);
 585             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 586                             __FUNCTION__, cmd);
 587             break;
 588         }
 589
 590     s->syncing = 0;
 591 }
 592
 593 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 594 {
 595     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 596     return s->index;
 597 }
 598
 599 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 600 {
 601     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 602     s->index = index;
 603 }
 604
 605 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 606 {
 607     uint32_t caps;
 608     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 609     switch (s->index) {
 610     case SVGA_REG_ID:
 611         return s->svgaid;
 612
 613     case SVGA_REG_ENABLE:
 614         return s->enable;
 615
 616     case SVGA_REG_WIDTH:
 617         return s->width;
 618
 619     case SVGA_REG_HEIGHT:
 620         return s->height;
 621
 622     case SVGA_REG_MAX_WIDTH:
 623         return SVGA_MAX_WIDTH;
 624
 625     case SVGA_REG_MAX_HEIGHT:
 626         return SVGA_MAX_HEIGHT;
 627
 628     case SVGA_REG_DEPTH:
 629         return s->depth;
 630
 631     case SVGA_REG_BITS_PER_PIXEL:
 632         return (s->depth + 7) & ~7;
 633
 634     case SVGA_REG_PSEUDOCOLOR:
 635         return 0x0;
 636
 637     case SVGA_REG_RED_MASK:
 638         return s->wred;
 639     case SVGA_REG_GREEN_MASK:
 640         return s->wgreen;
 641     case SVGA_REG_BLUE_MASK:
 642         return s->wblue;
 643
 644     case SVGA_REG_BYTES_PER_LINE:
 645         return ((s->depth + 7) >> 3) * s->new_width;
 646
 647     case SVGA_REG_FB_START:
 648         return s->vram_base;
 649
 650     case SVGA_REG_FB_OFFSET:
 651         return 0x0;
 652
 653     case SVGA_REG_VRAM_SIZE:
 654         return s->vram_size - SVGA_FIFO_SIZE;
 655
 656     case SVGA_REG_FB_SIZE:
 657         return s->fb_size;
 658
 659     case SVGA_REG_CAPABILITIES:
 660         caps = SVGA_CAP_NONE;
 661 #ifdef HW_RECT_ACCEL
 662         caps |= SVGA_CAP_RECT_COPY;
 663 #endif
 664 #ifdef HW_FILL_ACCEL
 665         caps |= SVGA_CAP_RECT_FILL;
 666 #endif
 667 #ifdef HW_MOUSE_ACCEL
 668         if (s->ds->mouse_set)
 669             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 670                     SVGA_CAP_CURSOR_BYPASS;
 671 #endif
 672         return caps;
 673
 674     case SVGA_REG_MEM_START:
 675         return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
 676
 677     case SVGA_REG_MEM_SIZE:
 678         return SVGA_FIFO_SIZE;
 679
 680     case SVGA_REG_CONFIG_DONE:
 681         return s->config;
 682
 683     case SVGA_REG_SYNC:
 684     case SVGA_REG_BUSY:
 685         return s->syncing;
 686
 687     case SVGA_REG_GUEST_ID:
 688         return s->guest;
 689
 690     case SVGA_REG_CURSOR_ID:
 691         return s->cursor.id;
 692
 693     case SVGA_REG_CURSOR_X:
 694         return s->cursor.x;
 695
 696     case SVGA_REG_CURSOR_Y:
 697         return s->cursor.x;
 698
 699     case SVGA_REG_CURSOR_ON:
 700         return s->cursor.on;
 701
 702     case SVGA_REG_HOST_BITS_PER_PIXEL:
 703         return (s->depth + 7) & ~7;
 704
 705     case SVGA_REG_SCRATCH_SIZE:
 706         return s->scratch_size;
 707
 708     case SVGA_REG_MEM_REGS:
 709     case SVGA_REG_NUM_DISPLAYS:
 710     case SVGA_REG_PITCHLOCK:
 711     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 712         return 0;
 713
 714     default:
 715         if (s->index >= SVGA_SCRATCH_BASE &&
 716                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 717             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 718         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 719     }
 720
 721     return 0;
 722 }
 723
 724 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 725 {
 726     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 727     switch (s->index) {
 728     case SVGA_REG_ID:
 729         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 730             s->svgaid = value;
 731         break;
 732
 733     case SVGA_REG_ENABLE:
 734         s->enable = value;
 735         s->config &= !!value;
 736         s->width = -1;
 737         s->height = -1;
 738         s->invalidated = 1;
 739 #ifdef EMBED_STDVGA
 740         s->invalidate(opaque);
 741 #endif
 742         if (s->enable)
 743             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 744         break;
 745
 746     case SVGA_REG_WIDTH:
 747         s->new_width = value;
 748         s->invalidated = 1;
 749         break;
 750
 751     case SVGA_REG_HEIGHT:
 752         s->new_height = value;
 753         s->invalidated = 1;
 754         break;
 755
 756     case SVGA_REG_DEPTH:
 757     case SVGA_REG_BITS_PER_PIXEL:
 758         if (value != s->depth) {
 759             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 760             s->config = 0;
 761         }
 762         break;
 763
 764     case SVGA_REG_CONFIG_DONE:
 765         if (value) {
 766             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 767             /* Check range and alignment.  */
 768             if ((s->cmd->min | s->cmd->max |
 769                         s->cmd->next_cmd | s->cmd->stop) & 3)
 770                 break;
 771             if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 772                 break;
 773             if (s->cmd->max > SVGA_FIFO_SIZE)
 774                 break;
 775             if (s->cmd->max < s->cmd->min + 10 * 1024)
 776                 break;
 777         }
 778         s->config = !!value;
 779         break;
 780
 781     case SVGA_REG_SYNC:
 782         s->syncing = 1;
 783         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 784         break;
 785
 786     case SVGA_REG_GUEST_ID:
 787         s->guest = value;
 788 #ifdef VERBOSE
 789         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 790                 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
 791             printf("%s: guest runs %s.\n", __FUNCTION__,
 792                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 793 #endif
 794         break;
 795
 796     case SVGA_REG_CURSOR_ID:
 797         s->cursor.id = value;
 798         break;
 799
 800     case SVGA_REG_CURSOR_X:
 801         s->cursor.x = value;
 802         break;
 803
 804     case SVGA_REG_CURSOR_Y:
 805         s->cursor.y = value;
 806         break;
 807
 808     case SVGA_REG_CURSOR_ON:
 809         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 810         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 811 #ifdef HW_MOUSE_ACCEL
 812         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 813             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 814 #endif
 815         break;
 816
 817     case SVGA_REG_MEM_REGS:
 818     case SVGA_REG_NUM_DISPLAYS:
 819     case SVGA_REG_PITCHLOCK:
 820     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 821         break;
 822
 823     default:
 824         if (s->index >= SVGA_SCRATCH_BASE &&
 825                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 826             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 827             break;
 828         }
 829         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 830     }
 831 }
 832
 833 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 834 {
 835     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 836     return 0xcafe;
 837 }
 838
 839 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 840 {
 841     printf("%s: what are we supposed to do with (%08x)?\n",
 842                     __FUNCTION__, data);
 843 }
 844
 845 static inline void vmsvga_size(struct vmsvga_state_s *s)
 846 {
 847     if (s->new_width != s->width || s->new_height != s->height) {
 848         s->width = s->new_width;
 849         s->height = s->new_height;
 850         dpy_resize(s->ds, s->width, s->height);
 851         s->invalidated = 1;
 852     }
 853 }
 854
 855 static void vmsvga_update_display(void *opaque)
 856 {
 857     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 858     if (!s->enable) {
 859 #ifdef EMBED_STDVGA
 860         s->update(opaque);
 861 #endif
 862         return;
 863     }
 864
 865     vmsvga_size(s);
 866
 867     vmsvga_fifo_run(s);
 868     vmsvga_update_rect_flush(s);
 869
 870     /*
 871      * Is it more efficient to look at vram VGA-dirty bits or wait
 872      * for the driver to issue SVGA_CMD_UPDATE?
 873      */
 874     if (s->invalidated) {
 875         s->invalidated = 0;
 876         vmsvga_update_screen(s);
 877     }
 878 }
 879
 880 static void vmsvga_reset(struct vmsvga_state_s *s)
 881 {
 882     s->index = 0;
 883     s->enable = 0;
 884     s->config = 0;
 885     s->width = -1;
 886     s->height = -1;
 887     s->svgaid = SVGA_ID;
 888     s->depth = s->ds->depth ? s->ds->depth : 24;
 889     s->bypp = (s->depth + 7) >> 3;
 890     s->cursor.on = 0;
 891     s->redraw_fifo_first = 0;
 892     s->redraw_fifo_last = 0;
 893     switch (s->depth) {
 894     case 8:
 895         s->wred   = 0x00000007;
 896         s->wgreen = 0x00000038;
 897         s->wblue  = 0x000000c0;
 898         break;
 899     case 15:
 900         s->wred   = 0x0000001f;
 901         s->wgreen = 0x000003e0;
 902         s->wblue  = 0x00007c00;
 903         break;
 904     case 16:
 905         s->wred   = 0x0000001f;
 906         s->wgreen = 0x000007e0;
 907         s->wblue  = 0x0000f800;
 908         break;
 909     case 24:
 910         s->wred   = 0x00ff0000;
 911         s->wgreen = 0x0000ff00;
 912         s->wblue  = 0x000000ff;
 913         break;
 914     case 32:
 915         s->wred   = 0x00ff0000;
 916         s->wgreen = 0x0000ff00;
 917         s->wblue  = 0x000000ff;
 918         break;
 919     }
 920     s->syncing = 0;
 921 }
 922
 923 static void vmsvga_invalidate_display(void *opaque)
 924 {
 925     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 926     if (!s->enable) {
 927 #ifdef EMBED_STDVGA
 928         s->invalidate(opaque);
 929 #endif
 930         return;
 931     }
 932
 933     s->invalidated = 1;
 934 }
 935
 936 /* save the vga display in a PPM image even if no display is
 937    available */
 938 static void vmsvga_screen_dump(void *opaque, const char *filename)
 939 {
 940     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 941     if (!s->enable) {
 942 #ifdef EMBED_STDVGA
 943         s->screen_dump(opaque, filename);
 944 #endif
 945         return;
 946     }
 947
 948     if (s->depth == 32) {
 949         ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
 950     }
 951 }
 952
 953 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
 954 {
 955     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 956
 957     if (s->text_update)
 958         s->text_update(opaque, chardata);
 959 }
 960
 961 #ifdef DIRECT_VRAM
 962 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
 963 {
 964     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 965     addr -= s->vram_base;
 966     if (addr < s->fb_size)
 967         return *(uint8_t *) (s->ds->data + addr);
 968     else
 969         return *(uint8_t *) (s->vram + addr);
 970 }
 971
 972 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
 973 {
 974     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 975     addr -= s->vram_base;
 976     if (addr < s->fb_size)
 977         return *(uint16_t *) (s->ds->data + addr);
 978     else
 979         return *(uint16_t *) (s->vram + addr);
 980 }
 981
 982 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
 983 {
 984     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 985     addr -= s->vram_base;
 986     if (addr < s->fb_size)
 987         return *(uint32_t *) (s->ds->data + addr);
 988     else
 989         return *(uint32_t *) (s->vram + addr);
 990 }
 991
 992 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
 993                 uint32_t value)
 994 {
 995     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 996     addr -= s->vram_base;
 997     if (addr < s->fb_size)
 998         *(uint8_t *) (s->ds->data + addr) = value;
 999     else
1000         *(uint8_t *) (s->vram + addr) = value;
1001 }
1002
1003 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1004                 uint32_t value)
1005 {
1006     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1007     addr -= s->vram_base;
1008     if (addr < s->fb_size)
1009         *(uint16_t *) (s->ds->data + addr) = value;
1010     else
1011         *(uint16_t *) (s->vram + addr) = value;
1012 }
1013
1014 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1015                 uint32_t value)
1016 {
1017     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1018     addr -= s->vram_base;
1019     if (addr < s->fb_size)
1020         *(uint32_t *) (s->ds->data + addr) = value;
1021     else
1022         *(uint32_t *) (s->vram + addr) = value;
1023 }
1024
1025 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1026     vmsvga_vram_readb,
1027     vmsvga_vram_readw,
1028     vmsvga_vram_readl,
1029 };
1030
1031 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1032     vmsvga_vram_writeb,
1033     vmsvga_vram_writew,
1034     vmsvga_vram_writel,
1035 };
1036 #endif
1037
1038 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1039 {
1040     qemu_put_be32(f, s->depth);
1041     qemu_put_be32(f, s->enable);
1042     qemu_put_be32(f, s->config);
1043     qemu_put_be32(f, s->cursor.id);
1044     qemu_put_be32(f, s->cursor.x);
1045     qemu_put_be32(f, s->cursor.y);
1046     qemu_put_be32(f, s->cursor.on);
1047     qemu_put_be32(f, s->index);
1048     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1049     qemu_put_be32(f, s->new_width);
1050     qemu_put_be32(f, s->new_height);
1051     qemu_put_be32s(f, &s->guest);
1052     qemu_put_be32s(f, &s->svgaid);
1053     qemu_put_be32(f, s->syncing);
1054     qemu_put_be32(f, s->fb_size);
1055 }
1056
1057 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1058 {
1059     int depth;
1060     depth=qemu_get_be32(f);
1061     s->enable=qemu_get_be32(f);
1062     s->config=qemu_get_be32(f);
1063     s->cursor.id=qemu_get_be32(f);
1064     s->cursor.x=qemu_get_be32(f);
1065     s->cursor.y=qemu_get_be32(f);
1066     s->cursor.on=qemu_get_be32(f);
1067     s->index=qemu_get_be32(f);
1068     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1069     s->new_width=qemu_get_be32(f);
1070     s->new_height=qemu_get_be32(f);
1071     qemu_get_be32s(f, &s->guest);
1072     qemu_get_be32s(f, &s->svgaid);
1073     s->syncing=qemu_get_be32(f);
1074     s->fb_size=qemu_get_be32(f);
1075
1076     if (s->enable && depth != s->depth) {
1077         printf("%s: need colour depth of %i bits to resume operation.\n",
1078                         __FUNCTION__, depth);
1079         return -EINVAL;
1080     }
1081
1082     s->invalidated = 1;
1083     if (s->config)
1084         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1085
1086     return 0;
1087 }
1088
1089 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1090                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1091                 int vga_ram_size)
1092 {
1093     s->ds = ds;
1094     s->vram = vga_ram_base;
1095     s->vram_size = vga_ram_size;
1096
1097     s->scratch_size = SVGA_SCRATCH_SIZE;
1098     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1099
1100     vmsvga_reset(s);
1101
1102     graphic_console_init(ds, vmsvga_update_display,
1103                     vmsvga_invalidate_display, vmsvga_screen_dump,
1104                     vmsvga_text_update, s);
1105
1106 #ifdef EMBED_STDVGA
1107     vga_common_init((VGAState *) s, ds,
1108                     vga_ram_base, vga_ram_offset, vga_ram_size);
1109     vga_init((VGAState *) s);
1110 #endif
1111 }
1112
1113 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1114 {
1115     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1116     pci_device_save(&s->card, f);
1117     vmsvga_save(&s->chip, f);
1118 }
1119
1120 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1121 {
1122     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1123     int ret;
1124
1125     ret = pci_device_load(&s->card, f);
1126     if (ret < 0)
1127         return ret;
1128
1129     ret = vmsvga_load(&s->chip, f);
1130     if (ret < 0)
1131         return ret;
1132
1133     return 0;
1134 }
1135
1136 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1137                 uint32_t addr, uint32_t size, int type)
1138 {
1139     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1140     struct vmsvga_state_s *s = &d->chip;
1141
1142     register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1143                     1, 4, vmsvga_index_read, s);
1144     register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1145                     1, 4, vmsvga_index_write, s);
1146     register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1147                     1, 4, vmsvga_value_read, s);
1148     register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1149                     1, 4, vmsvga_value_write, s);
1150     register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1151                     1, 4, vmsvga_bios_read, s);
1152     register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1153                     1, 4, vmsvga_bios_write, s);
1154 }
1155
1156 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1157                 uint32_t addr, uint32_t size, int type)
1158 {
1159     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1160     struct vmsvga_state_s *s = &d->chip;
1161     int iomemtype;
1162
1163     s->vram_base = addr;
1164 #ifdef DIRECT_VRAM
1165     iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1166                     vmsvga_vram_write, s);
1167 #else
1168     iomemtype = 0 | IO_MEM_RAM;
1169 #endif
1170     cpu_register_physical_memory(s->vram_base, s->vram_size,
1171                     iomemtype);
1172 }
1173
1174 #define PCI_VENDOR_ID_VMWARE            0x15ad
1175 #define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
1176 #define PCI_DEVICE_ID_VMWARE_SVGA       0x0710
1177 #define PCI_DEVICE_ID_VMWARE_NET        0x0720
1178 #define PCI_DEVICE_ID_VMWARE_SCSI       0x0730
1179 #define PCI_DEVICE_ID_VMWARE_IDE        0x1729
1180 #define PCI_CLASS_BASE_DISPLAY          0x03
1181 #define PCI_CLASS_SUB_VGA               0x00
1182 #define PCI_CLASS_HEADERTYPE_00h        0x00
1183
1184 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1185                      unsigned long vga_ram_offset, int vga_ram_size)
1186 {
1187     struct pci_vmsvga_state_s *s;
1188
1189     /* Setup PCI configuration */
1190     s = (struct pci_vmsvga_state_s *)
1191         pci_register_device(bus, "QEMUware SVGA",
1192                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1193     s->card.config[PCI_VENDOR_ID]       = PCI_VENDOR_ID_VMWARE & 0xff;
1194     s->card.config[PCI_VENDOR_ID + 1]   = PCI_VENDOR_ID_VMWARE >> 8;
1195     s->card.config[PCI_DEVICE_ID]       = SVGA_PCI_DEVICE_ID & 0xff;
1196     s->card.config[PCI_DEVICE_ID + 1]   = SVGA_PCI_DEVICE_ID >> 8;
1197     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1198     s->card.config[PCI_CLASS_DEVICE]    = PCI_CLASS_SUB_VGA;
1199     s->card.config[0x0b]                = PCI_CLASS_BASE_DISPLAY;
1200     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1201     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1202     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1203     s->card.config[0x10]                = ((SVGA_IO_BASE >>  0) & 0xff) | 1;
1204     s->card.config[0x11]                =  (SVGA_IO_BASE >>  8) & 0xff;
1205     s->card.config[0x12]                =  (SVGA_IO_BASE >> 16) & 0xff;
1206     s->card.config[0x13]                =  (SVGA_IO_BASE >> 24) & 0xff;
1207     s->card.config[0x18]                = (SVGA_MEM_BASE >>  0) & 0xff;
1208     s->card.config[0x19]                = (SVGA_MEM_BASE >>  8) & 0xff;
1209     s->card.config[0x1a]                = (SVGA_MEM_BASE >> 16) & 0xff;
1210     s->card.config[0x1b]                = (SVGA_MEM_BASE >> 24) & 0xff;
1211     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1212     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1213     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1214     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1215     s->card.config[0x3c]                = 0xff;         /* End */
1216
1217     pci_register_io_region(&s->card, 0, 0x10,
1218                     PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1219     pci_register_io_region(&s->card, 0, vga_ram_size,
1220                     PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1221
1222     vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1223
1224     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1225 }