4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug LANCE card */
30 #define DPRINTF(fmt, args...) \
31 do { printf("LANCE: " fmt , ##args); } while (0)
33 #define DPRINTF(fmt, args...)
36 #ifndef LANCE_LOG_TX_BUFFERS
37 #define LANCE_LOG_TX_BUFFERS 4
38 #define LANCE_LOG_RX_BUFFERS 4
45 #define LE_NREGS (LE_CSR3 + 1)
46 #define LE_MAXREG LE_CSR3
51 #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
53 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
54 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
55 #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
56 #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
57 #define LE_C0_MERR 0x0800 /* ME: Memory error */
58 #define LE_C0_RINT 0x0400 /* Received interrupt */
59 #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
60 #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
61 #define LE_C0_INTR 0x0080 /* Interrupt or error */
62 #define LE_C0_INEA 0x0040 /* Interrupt enable */
63 #define LE_C0_RXON 0x0020 /* Receiver on */
64 #define LE_C0_TXON 0x0010 /* Transmitter on */
65 #define LE_C0_TDMD 0x0008 /* Transmitter demand */
66 #define LE_C0_STOP 0x0004 /* Stop the card */
67 #define LE_C0_STRT 0x0002 /* Start the card */
68 #define LE_C0_INIT 0x0001 /* Init the card */
70 #define LE_C3_BSWP 0x4 /* SWAP */
71 #define LE_C3_ACON 0x2 /* ALE Control */
72 #define LE_C3_BCON 0x1 /* Byte control */
74 /* Receive message descriptor 1 */
75 #define LE_R1_OWN 0x80 /* Who owns the entry */
76 #define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
77 #define LE_R1_FRA 0x20 /* FRA: Frame error */
78 #define LE_R1_OFL 0x10 /* OFL: Frame overflow */
79 #define LE_R1_CRC 0x08 /* CRC error */
80 #define LE_R1_BUF 0x04 /* BUF: Buffer error */
81 #define LE_R1_SOP 0x02 /* Start of packet */
82 #define LE_R1_EOP 0x01 /* End of packet */
83 #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
85 #define LE_T1_OWN 0x80 /* Lance owns the packet */
86 #define LE_T1_ERR 0x40 /* Error summary */
87 #define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
88 #define LE_T1_EONE 0x08 /* Error: one retry needed */
89 #define LE_T1_EDEF 0x04 /* Error: deferred */
90 #define LE_T1_SOP 0x02 /* Start of packet */
91 #define LE_T1_EOP 0x01 /* End of packet */
92 #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
94 #define LE_T3_BUF 0x8000 /* Buffer error */
95 #define LE_T3_UFL 0x4000 /* Error underflow */
96 #define LE_T3_LCOL 0x1000 /* Error late collision */
97 #define LE_T3_CLOS 0x0800 /* Error carrier loss */
98 #define LE_T3_RTY 0x0400 /* Error retry */
99 #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
101 #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
102 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
103 #define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
105 #define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
106 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
107 #define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
109 #define PKT_BUF_SZ 1544
110 #define RX_BUFF_SIZE PKT_BUF_SZ
111 #define TX_BUFF_SIZE PKT_BUF_SZ
113 struct lance_rx_desc
{
114 unsigned short rmd0
; /* low address of packet */
115 unsigned char rmd1_bits
; /* descriptor bits */
116 unsigned char rmd1_hadr
; /* high address of packet */
117 short length
; /* This length is 2s complement (negative)!
120 unsigned short mblength
; /* This is the actual number of bytes received */
123 struct lance_tx_desc
{
124 unsigned short tmd0
; /* low address of packet */
125 unsigned char tmd1_bits
; /* descriptor bits */
126 unsigned char tmd1_hadr
; /* high address of packet */
127 short length
; /* Length is 2s complement (negative)! */
131 /* The LANCE initialization block, described in databook. */
132 /* On the Sparc, this block should be on a DMA region */
133 struct lance_init_block
{
134 unsigned short mode
; /* Pre-set mode (reg. 15) */
135 unsigned char phys_addr
[6]; /* Physical ethernet address */
136 unsigned filter
[2]; /* Multicast filter. */
138 /* Receive and transmit ring base, along with extra bits. */
139 unsigned short rx_ptr
; /* receive descriptor addr */
140 unsigned short rx_len
; /* receive len and high addr */
141 unsigned short tx_ptr
; /* transmit descriptor addr */
142 unsigned short tx_len
; /* transmit len and high addr */
144 /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
145 struct lance_rx_desc brx_ring
[RX_RING_SIZE
];
146 struct lance_tx_desc btx_ring
[TX_RING_SIZE
];
148 char tx_buf
[TX_RING_SIZE
][TX_BUFF_SIZE
];
149 char pad
[2]; /* align rx_buf for copy_and_sum(). */
150 char rx_buf
[RX_RING_SIZE
][RX_BUFF_SIZE
];
154 #define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1)
156 typedef struct LANCEState
{
158 uint8_t macaddr
[6]; /* init mac address */
161 uint16_t regs
[LE_NREGS
];
162 uint8_t phys
[6]; /* mac address */
164 unsigned int rxptr
, txptr
;
165 uint32_t ledmaregs
[LEDMA_REGS
];
168 static void lance_send(void *opaque
);
170 static void lance_reset(void *opaque
)
172 LANCEState
*s
= opaque
;
173 memcpy(s
->phys
, s
->macaddr
, 6);
176 memset(s
->regs
, 0, LE_NREGS
* 2);
177 s
->regs
[LE_CSR0
] = LE_C0_STOP
;
178 memset(s
->ledmaregs
, 0, LEDMA_REGS
* 4);
181 static uint32_t lance_mem_readw(void *opaque
, target_phys_addr_t addr
)
183 LANCEState
*s
= opaque
;
186 saddr
= addr
& LE_MAXREG
;
187 switch (saddr
>> 1) {
189 DPRINTF("read dreg[%d] = %4.4x\n", s
->addr
, s
->regs
[s
->addr
]);
190 return s
->regs
[s
->addr
];
192 DPRINTF("read areg = %4.4x\n", s
->addr
);
195 DPRINTF("read unknown(%d)\n", saddr
>>1);
201 static void lance_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
203 LANCEState
*s
= opaque
;
207 saddr
= addr
& LE_MAXREG
;
208 switch (saddr
>> 1) {
210 DPRINTF("write dreg[%d] = %4.4x\n", s
->addr
, val
);
213 if (val
& LE_C0_STOP
) {
214 s
->regs
[LE_CSR0
] = LE_C0_STOP
;
218 reg
= s
->regs
[LE_CSR0
];
220 // 1 = clear for some bits
221 reg
&= ~(val
& 0x7f00);
224 reg
&= ~(LE_C0_ERR
| LE_C0_INTR
);
232 reg
|= val
& LE_C0_INEA
;
235 if (val
& LE_C0_INIT
) {
236 reg
|= LE_C0_IDON
| LE_C0_INIT
;
239 else if (val
& LE_C0_STRT
) {
240 reg
|= LE_C0_STRT
| LE_C0_RXON
| LE_C0_TXON
;
244 s
->regs
[LE_CSR0
] = reg
;
247 s
->leptr
= (s
->leptr
& 0xffff0000) | (val
& 0xffff);
248 s
->regs
[s
->addr
] = val
;
251 s
->leptr
= (s
->leptr
& 0xffff) | ((val
& 0xffff) << 16);
252 s
->regs
[s
->addr
] = val
;
255 s
->regs
[s
->addr
] = val
;
260 DPRINTF("write areg = %4.4x\n", val
);
265 DPRINTF("write unknown(%d) = %4.4x\n", saddr
>>1, val
);
271 static CPUReadMemoryFunc
*lance_mem_read
[3] = {
277 static CPUWriteMemoryFunc
*lance_mem_write
[3] = {
284 #define MIN_BUF_SIZE 60
286 static void lance_can_receive(void *opaque
)
291 static void lance_receive(void *opaque
, const uint8_t *buf
, int size
)
293 LANCEState
*s
= opaque
;
294 uint32_t dmaptr
= s
->leptr
+ s
->ledmaregs
[3];
295 struct lance_init_block
*ib
;
296 unsigned int i
, old_rxptr
;
300 DPRINTF("receive size %d\n", size
);
301 if ((s
->regs
[LE_CSR0
] & LE_C0_STOP
) == LE_C0_STOP
)
304 ib
= (void *) iommu_translate(dmaptr
);
306 old_rxptr
= s
->rxptr
;
307 for (i
= s
->rxptr
; i
!= ((old_rxptr
- 1) & RX_RING_MOD_MASK
); i
= (i
+ 1) & RX_RING_MOD_MASK
) {
308 cpu_physical_memory_read((uint32_t)&ib
->brx_ring
[i
].rmd1_bits
, (void *) &temp8
, 1);
309 if (temp8
== (LE_R1_OWN
)) {
310 s
->rxptr
= (s
->rxptr
+ 1) & RX_RING_MOD_MASK
;
313 cpu_physical_memory_write((uint32_t)&ib
->brx_ring
[i
].mblength
, (void *) &temp16
, 2);
314 cpu_physical_memory_write((uint32_t)&ib
->rx_buf
[i
], buf
, size
);
316 cpu_physical_memory_write((uint32_t)&ib
->brx_ring
[i
].rmd1_bits
, (void *) &temp8
, 1);
317 s
->regs
[LE_CSR0
] |= LE_C0_RINT
| LE_C0_INTR
;
318 if (s
->regs
[LE_CSR0
] & LE_C0_INEA
)
319 pic_set_irq(s
->irq
, 1);
320 DPRINTF("got packet, len %d\n", size
);
326 static void lance_send(void *opaque
)
328 LANCEState
*s
= opaque
;
329 uint32_t dmaptr
= s
->leptr
+ s
->ledmaregs
[3];
330 struct lance_init_block
*ib
;
331 unsigned int i
, old_txptr
;
334 char pkt_buf
[PKT_BUF_SZ
];
336 DPRINTF("sending packet? (csr0 %4.4x)\n", s
->regs
[LE_CSR0
]);
337 if ((s
->regs
[LE_CSR0
] & LE_C0_STOP
) == LE_C0_STOP
)
340 ib
= (void *) iommu_translate(dmaptr
);
342 DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr
, ib
, &ib
->btx_ring
);
343 old_txptr
= s
->txptr
;
344 for (i
= s
->txptr
; i
!= ((old_txptr
- 1) & TX_RING_MOD_MASK
); i
= (i
+ 1) & TX_RING_MOD_MASK
) {
345 cpu_physical_memory_read((uint32_t)&ib
->btx_ring
[i
].tmd1_bits
, (void *) &temp8
, 1);
346 if (temp8
== (LE_T1_POK
|LE_T1_OWN
)) {
347 cpu_physical_memory_read((uint32_t)&ib
->btx_ring
[i
].length
, (void *) &temp16
, 2);
349 temp16
= (~temp16
) + 1;
350 cpu_physical_memory_read((uint32_t)&ib
->tx_buf
[i
], pkt_buf
, temp16
);
351 DPRINTF("sending packet, len %d\n", temp16
);
352 qemu_send_packet(s
->vc
, pkt_buf
, temp16
);
354 cpu_physical_memory_write((uint32_t)&ib
->btx_ring
[i
].tmd1_bits
, (void *) &temp8
, 1);
355 s
->txptr
= (s
->txptr
+ 1) & TX_RING_MOD_MASK
;
356 s
->regs
[LE_CSR0
] |= LE_C0_TINT
| LE_C0_INTR
;
359 if ((s
->regs
[LE_CSR0
] & LE_C0_INTR
) && (s
->regs
[LE_CSR0
] & LE_C0_INEA
))
360 pic_set_irq(s
->irq
, 1);
363 static uint32_t ledma_mem_readl(void *opaque
, target_phys_addr_t addr
)
365 LANCEState
*s
= opaque
;
368 saddr
= (addr
& LEDMA_MAXADDR
) >> 2;
369 return s
->ledmaregs
[saddr
];
372 static void ledma_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
374 LANCEState
*s
= opaque
;
377 saddr
= (addr
& LEDMA_MAXADDR
) >> 2;
378 s
->ledmaregs
[saddr
] = val
;
381 static CPUReadMemoryFunc
*ledma_mem_read
[3] = {
387 static CPUWriteMemoryFunc
*ledma_mem_write
[3] = {
393 static void lance_save(QEMUFile
*f
, void *opaque
)
395 LANCEState
*s
= opaque
;
398 qemu_put_be32s(f
, &s
->leptr
);
399 qemu_put_be16s(f
, &s
->addr
);
400 for (i
= 0; i
< LE_NREGS
; i
++)
401 qemu_put_be16s(f
, &s
->regs
[i
]);
402 qemu_put_buffer(f
, s
->phys
, 6);
403 qemu_put_be32s(f
, &s
->irq
);
404 for (i
= 0; i
< LEDMA_REGS
; i
++)
405 qemu_put_be32s(f
, &s
->ledmaregs
[i
]);
408 static int lance_load(QEMUFile
*f
, void *opaque
, int version_id
)
410 LANCEState
*s
= opaque
;
416 qemu_get_be32s(f
, &s
->leptr
);
417 qemu_get_be16s(f
, &s
->addr
);
418 for (i
= 0; i
< LE_NREGS
; i
++)
419 qemu_get_be16s(f
, &s
->regs
[i
]);
420 qemu_get_buffer(f
, s
->phys
, 6);
421 qemu_get_be32s(f
, &s
->irq
);
422 for (i
= 0; i
< LEDMA_REGS
; i
++)
423 qemu_get_be32s(f
, &s
->ledmaregs
[i
]);
427 void lance_init(NICInfo
*nd
, int irq
, uint32_t leaddr
, uint32_t ledaddr
)
430 int lance_io_memory
, ledma_io_memory
;
432 s
= qemu_mallocz(sizeof(LANCEState
));
438 lance_io_memory
= cpu_register_io_memory(0, lance_mem_read
, lance_mem_write
, s
);
439 cpu_register_physical_memory(leaddr
, 4, lance_io_memory
);
441 ledma_io_memory
= cpu_register_io_memory(0, ledma_mem_read
, ledma_mem_write
, s
);
442 cpu_register_physical_memory(ledaddr
, 16, ledma_io_memory
);
444 memcpy(s
->macaddr
, nd
->macaddr
, 6);
448 s
->vc
= qemu_new_vlan_client(nd
->vlan
, lance_receive
, lance_can_receive
, s
);
450 snprintf(s
->vc
->info_str
, sizeof(s
->vc
->info_str
),
451 "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
459 register_savevm("lance", leaddr
, 1, lance_save
, lance_load
, s
);
460 qemu_register_reset(lance_reset
, s
);