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Record configure commandline.
[qemu/mini2440.git] / cpu-exec.c
blob3bf4b370a4879c911a16195289b920e9a2dda3f0
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #ifndef TARGET_SPARC
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 cs_base = 0;
173 pc = env->regs[15];
174 #elif defined(TARGET_SPARC)
175 #ifdef TARGET_SPARC64
176 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
177 #else
178 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
179 #endif
180 cs_base = env->npc;
181 pc = env->pc;
182 #elif defined(TARGET_PPC)
183 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
184 (msr_se << MSR_SE) | (msr_le << MSR_LE);
185 cs_base = 0;
186 pc = env->nip;
187 #elif defined(TARGET_MIPS)
188 flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK);
189 cs_base = 0;
190 pc = env->PC;
191 #else
192 #error unsupported CPU
193 #endif
194 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
195 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
196 tb->flags != flags, 0)) {
197 tb = tb_find_slow(pc, cs_base, flags);
198 /* Note: we do it here to avoid a gcc bug on Mac OS X when
199 doing it in tb_find_slow */
200 if (tb_invalidated_flag) {
201 /* as some TB could have been invalidated because
202 of memory exceptions while generating the code, we
203 must recompute the hash index here */
204 T0 = 0;
205 }
206 }
207 return tb;
208 }
209
210
211 /* main execution loop */
212
213 int cpu_exec(CPUState *env1)
214 {
215 int saved_T0, saved_T1;
216 #if defined(reg_T2)
217 int saved_T2;
218 #endif
219 CPUState *saved_env;
220 #if defined(TARGET_I386)
221 #ifdef reg_EAX
222 int saved_EAX;
223 #endif
224 #ifdef reg_ECX
225 int saved_ECX;
226 #endif
227 #ifdef reg_EDX
228 int saved_EDX;
229 #endif
230 #ifdef reg_EBX
231 int saved_EBX;
232 #endif
233 #ifdef reg_ESP
234 int saved_ESP;
235 #endif
236 #ifdef reg_EBP
237 int saved_EBP;
238 #endif
239 #ifdef reg_ESI
240 int saved_ESI;
241 #endif
242 #ifdef reg_EDI
243 int saved_EDI;
244 #endif
245 #elif defined(TARGET_SPARC)
246 #if defined(reg_REGWPTR)
247 uint32_t *saved_regwptr;
248 #endif
249 #endif
250 #ifdef __sparc__
251 int saved_i7, tmp_T0;
252 #endif
253 int ret, interrupt_request;
254 void (*gen_func)(void);
255 TranslationBlock *tb;
256 uint8_t *tc_ptr;
257
258 #if defined(TARGET_I386)
259 /* handle exit of HALTED state */
260 if (env1->hflags & HF_HALTED_MASK) {
261 /* disable halt condition */
262 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
263 (env1->eflags & IF_MASK)) {
264 env1->hflags &= ~HF_HALTED_MASK;
265 } else {
266 return EXCP_HALTED;
267 }
268 }
269 #elif defined(TARGET_PPC)
270 if (env1->halted) {
271 if (env1->msr[MSR_EE] &&
272 (env1->interrupt_request &
273 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
274 env1->halted = 0;
275 } else {
276 return EXCP_HALTED;
277 }
278 }
279 #elif defined(TARGET_SPARC)
280 if (env1->halted) {
281 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
282 (env1->psret != 0)) {
283 env1->halted = 0;
284 } else {
285 return EXCP_HALTED;
286 }
287 }
288 #elif defined(TARGET_ARM)
289 if (env1->halted) {
290 /* An interrupt wakes the CPU even if the I and F CPSR bits are
291 set. */
292 if (env1->interrupt_request
293 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
294 env1->halted = 0;
295 } else {
296 return EXCP_HALTED;
297 }
298 }
299 #elif defined(TARGET_MIPS)
300 if (env1->halted) {
301 if (env1->interrupt_request &
302 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
303 env1->halted = 0;
304 } else {
305 return EXCP_HALTED;
306 }
307 }
308 #endif
309
310 cpu_single_env = env1;
311
312 /* first we save global registers */
313 saved_env = env;
314 env = env1;
315 saved_T0 = T0;
316 saved_T1 = T1;
317 #if defined(reg_T2)
318 saved_T2 = T2;
319 #endif
320 #ifdef __sparc__
321 /* we also save i7 because longjmp may not restore it */
322 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
323 #endif
324
325 #if defined(TARGET_I386)
326 #ifdef reg_EAX
327 saved_EAX = EAX;
328 #endif
329 #ifdef reg_ECX
330 saved_ECX = ECX;
331 #endif
332 #ifdef reg_EDX
333 saved_EDX = EDX;
334 #endif
335 #ifdef reg_EBX
336 saved_EBX = EBX;
337 #endif
338 #ifdef reg_ESP
339 saved_ESP = ESP;
340 #endif
341 #ifdef reg_EBP
342 saved_EBP = EBP;
343 #endif
344 #ifdef reg_ESI
345 saved_ESI = ESI;
346 #endif
347 #ifdef reg_EDI
348 saved_EDI = EDI;
349 #endif
350
351 env_to_regs();
352 /* put eflags in CPU temporary format */
353 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
354 DF = 1 - (2 * ((env->eflags >> 10) & 1));
355 CC_OP = CC_OP_EFLAGS;
356 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
357 #elif defined(TARGET_ARM)
358 #elif defined(TARGET_SPARC)
359 #if defined(reg_REGWPTR)
360 saved_regwptr = REGWPTR;
361 #endif
362 #elif defined(TARGET_PPC)
363 #elif defined(TARGET_MIPS)
364 #else
365 #error unsupported target CPU
366 #endif
367 env->exception_index = -1;
368
369 /* prepare setjmp context for exception handling */
370 for(;;) {
371 if (setjmp(env->jmp_env) == 0) {
372 env->current_tb = NULL;
373 /* if an exception is pending, we execute it here */
374 if (env->exception_index >= 0) {
375 if (env->exception_index >= EXCP_INTERRUPT) {
376 /* exit request from the cpu execution loop */
377 ret = env->exception_index;
378 break;
379 } else if (env->user_mode_only) {
380 /* if user mode only, we simulate a fake exception
381 which will be hanlded outside the cpu execution
382 loop */
383 #if defined(TARGET_I386)
384 do_interrupt_user(env->exception_index,
385 env->exception_is_int,
386 env->error_code,
387 env->exception_next_eip);
388 #endif
389 ret = env->exception_index;
390 break;
391 } else {
392 #if defined(TARGET_I386)
393 /* simulate a real cpu exception. On i386, it can
394 trigger new exceptions, but we do not handle
395 double or triple faults yet. */
396 do_interrupt(env->exception_index,
397 env->exception_is_int,
398 env->error_code,
399 env->exception_next_eip, 0);
400 #elif defined(TARGET_PPC)
401 do_interrupt(env);
402 #elif defined(TARGET_MIPS)
403 do_interrupt(env);
404 #elif defined(TARGET_SPARC)
405 do_interrupt(env->exception_index);
406 #elif defined(TARGET_ARM)
407 do_interrupt(env);
408 #endif
409 }
410 env->exception_index = -1;
411 }
412 #ifdef USE_KQEMU
413 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
414 int ret;
415 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
416 ret = kqemu_cpu_exec(env);
417 /* put eflags in CPU temporary format */
418 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
419 DF = 1 - (2 * ((env->eflags >> 10) & 1));
420 CC_OP = CC_OP_EFLAGS;
421 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
422 if (ret == 1) {
423 /* exception */
424 longjmp(env->jmp_env, 1);
425 } else if (ret == 2) {
426 /* softmmu execution needed */
427 } else {
428 if (env->interrupt_request != 0) {
429 /* hardware interrupt will be executed just after */
430 } else {
431 /* otherwise, we restart */
432 longjmp(env->jmp_env, 1);
433 }
434 }
435 }
436 #endif
437
438 T0 = 0; /* force lookup of first TB */
439 for(;;) {
440 #ifdef __sparc__
441 /* g1 can be modified by some libc? functions */
442 tmp_T0 = T0;
443 #endif
444 interrupt_request = env->interrupt_request;
445 if (__builtin_expect(interrupt_request, 0)) {
446 #if defined(TARGET_I386)
447 /* if hardware interrupt pending, we execute it */
448 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
449 (env->eflags & IF_MASK) &&
450 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
451 int intno;
452 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
453 intno = cpu_get_pic_interrupt(env);
454 if (loglevel & CPU_LOG_TB_IN_ASM) {
455 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
456 }
457 do_interrupt(intno, 0, 0, 0, 1);
458 /* ensure that no TB jump will be modified as
459 the program flow was changed */
460 #ifdef __sparc__
461 tmp_T0 = 0;
462 #else
463 T0 = 0;
464 #endif
465 }
466 #elif defined(TARGET_PPC)
467 #if 0
468 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
469 cpu_ppc_reset(env);
470 }
471 #endif
472 if (msr_ee != 0) {
473 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
474 /* Raise it */
475 env->exception_index = EXCP_EXTERNAL;
476 env->error_code = 0;
477 do_interrupt(env);
478 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
479 #ifdef __sparc__
480 tmp_T0 = 0;
481 #else
482 T0 = 0;
483 #endif
484 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
485 /* Raise it */
486 env->exception_index = EXCP_DECR;
487 env->error_code = 0;
488 do_interrupt(env);
489 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
490 #ifdef __sparc__
491 tmp_T0 = 0;
492 #else
493 T0 = 0;
494 #endif
495 }
496 }
497 #elif defined(TARGET_MIPS)
498 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
499 (env->CP0_Status & (1 << CP0St_IE)) &&
500 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
501 !(env->hflags & MIPS_HFLAG_EXL) &&
502 !(env->hflags & MIPS_HFLAG_ERL) &&
503 !(env->hflags & MIPS_HFLAG_DM)) {
504 /* Raise it */
505 env->exception_index = EXCP_EXT_INTERRUPT;
506 env->error_code = 0;
507 do_interrupt(env);
508 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
509 #ifdef __sparc__
510 tmp_T0 = 0;
511 #else
512 T0 = 0;
513 #endif
514 }
515 #elif defined(TARGET_SPARC)
516 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
517 (env->psret != 0)) {
518 int pil = env->interrupt_index & 15;
519 int type = env->interrupt_index & 0xf0;
520
521 if (((type == TT_EXTINT) &&
522 (pil == 15 || pil > env->psrpil)) ||
523 type != TT_EXTINT) {
524 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
525 do_interrupt(env->interrupt_index);
526 env->interrupt_index = 0;
527 #ifdef __sparc__
528 tmp_T0 = 0;
529 #else
530 T0 = 0;
531 #endif
532 }
533 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
534 //do_interrupt(0, 0, 0, 0, 0);
535 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
536 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
537 env1->halted = 1;
538 return EXCP_HALTED;
539 }
540 #elif defined(TARGET_ARM)
541 if (interrupt_request & CPU_INTERRUPT_FIQ
542 && !(env->uncached_cpsr & CPSR_F)) {
543 env->exception_index = EXCP_FIQ;
544 do_interrupt(env);
545 }
546 if (interrupt_request & CPU_INTERRUPT_HARD
547 && !(env->uncached_cpsr & CPSR_I)) {
548 env->exception_index = EXCP_IRQ;
549 do_interrupt(env);
550 }
551 #endif
552 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
553 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
554 /* ensure that no TB jump will be modified as
555 the program flow was changed */
556 #ifdef __sparc__
557 tmp_T0 = 0;
558 #else
559 T0 = 0;
560 #endif
561 }
562 if (interrupt_request & CPU_INTERRUPT_EXIT) {
563 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
564 env->exception_index = EXCP_INTERRUPT;
565 cpu_loop_exit();
566 }
567 }
568 #ifdef DEBUG_EXEC
569 if ((loglevel & CPU_LOG_TB_CPU)) {
570 #if defined(TARGET_I386)
571 /* restore flags in standard format */
572 #ifdef reg_EAX
573 env->regs[R_EAX] = EAX;
574 #endif
575 #ifdef reg_EBX
576 env->regs[R_EBX] = EBX;
577 #endif
578 #ifdef reg_ECX
579 env->regs[R_ECX] = ECX;
580 #endif
581 #ifdef reg_EDX
582 env->regs[R_EDX] = EDX;
583 #endif
584 #ifdef reg_ESI
585 env->regs[R_ESI] = ESI;
586 #endif
587 #ifdef reg_EDI
588 env->regs[R_EDI] = EDI;
589 #endif
590 #ifdef reg_EBP
591 env->regs[R_EBP] = EBP;
592 #endif
593 #ifdef reg_ESP
594 env->regs[R_ESP] = ESP;
595 #endif
596 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
597 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
598 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
599 #elif defined(TARGET_ARM)
600 cpu_dump_state(env, logfile, fprintf, 0);
601 #elif defined(TARGET_SPARC)
602 REGWPTR = env->regbase + (env->cwp * 16);
603 env->regwptr = REGWPTR;
604 cpu_dump_state(env, logfile, fprintf, 0);
605 #elif defined(TARGET_PPC)
606 cpu_dump_state(env, logfile, fprintf, 0);
607 #elif defined(TARGET_MIPS)
608 cpu_dump_state(env, logfile, fprintf, 0);
609 #else
610 #error unsupported target CPU
611 #endif
612 }
613 #endif
614 tb = tb_find_fast();
615 #ifdef DEBUG_EXEC
616 if ((loglevel & CPU_LOG_EXEC)) {
617 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
618 (long)tb->tc_ptr, tb->pc,
619 lookup_symbol(tb->pc));
620 }
621 #endif
622 #ifdef __sparc__
623 T0 = tmp_T0;
624 #endif
625 /* see if we can patch the calling TB. When the TB
626 spans two pages, we cannot safely do a direct
627 jump. */
628 {
629 if (T0 != 0 &&
630 #if USE_KQEMU
631 (env->kqemu_enabled != 2) &&
632 #endif
633 tb->page_addr[1] == -1
634 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
635 && (tb->cflags & CF_CODE_COPY) ==
636 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
637 #endif
638 ) {
639 spin_lock(&tb_lock);
640 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
641 #if defined(USE_CODE_COPY)
642 /* propagates the FP use info */
643 ((TranslationBlock *)(T0 & ~3))->cflags |=
644 (tb->cflags & CF_FP_USED);
645 #endif
646 spin_unlock(&tb_lock);
647 }
648 }
649 tc_ptr = tb->tc_ptr;
650 env->current_tb = tb;
651 /* execute the generated code */
652 gen_func = (void *)tc_ptr;
653 #if defined(__sparc__)
654 __asm__ __volatile__("call %0\n\t"
655 "mov %%o7,%%i0"
656 : /* no outputs */
657 : "r" (gen_func)
658 : "i0", "i1", "i2", "i3", "i4", "i5");
659 #elif defined(__arm__)
660 asm volatile ("mov pc, %0\n\t"
661 ".global exec_loop\n\t"
662 "exec_loop:\n\t"
663 : /* no outputs */
664 : "r" (gen_func)
665 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
666 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
667 {
668 if (!(tb->cflags & CF_CODE_COPY)) {
669 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
670 save_native_fp_state(env);
671 }
672 gen_func();
673 } else {
674 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
675 restore_native_fp_state(env);
676 }
677 /* we work with native eflags */
678 CC_SRC = cc_table[CC_OP].compute_all();
679 CC_OP = CC_OP_EFLAGS;
680 asm(".globl exec_loop\n"
681 "\n"
682 "debug1:\n"
683 " pushl %%ebp\n"
684 " fs movl %10, %9\n"
685 " fs movl %11, %%eax\n"
686 " andl $0x400, %%eax\n"
687 " fs orl %8, %%eax\n"
688 " pushl %%eax\n"
689 " popf\n"
690 " fs movl %%esp, %12\n"
691 " fs movl %0, %%eax\n"
692 " fs movl %1, %%ecx\n"
693 " fs movl %2, %%edx\n"
694 " fs movl %3, %%ebx\n"
695 " fs movl %4, %%esp\n"
696 " fs movl %5, %%ebp\n"
697 " fs movl %6, %%esi\n"
698 " fs movl %7, %%edi\n"
699 " fs jmp *%9\n"
700 "exec_loop:\n"
701 " fs movl %%esp, %4\n"
702 " fs movl %12, %%esp\n"
703 " fs movl %%eax, %0\n"
704 " fs movl %%ecx, %1\n"
705 " fs movl %%edx, %2\n"
706 " fs movl %%ebx, %3\n"
707 " fs movl %%ebp, %5\n"
708 " fs movl %%esi, %6\n"
709 " fs movl %%edi, %7\n"
710 " pushf\n"
711 " popl %%eax\n"
712 " movl %%eax, %%ecx\n"
713 " andl $0x400, %%ecx\n"
714 " shrl $9, %%ecx\n"
715 " andl $0x8d5, %%eax\n"
716 " fs movl %%eax, %8\n"
717 " movl $1, %%eax\n"
718 " subl %%ecx, %%eax\n"
719 " fs movl %%eax, %11\n"
720 " fs movl %9, %%ebx\n" /* get T0 value */
721 " popl %%ebp\n"
722 :
723 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
726 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
727 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
728 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
729 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
730 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
731 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
732 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
733 "a" (gen_func),
734 "m" (*(uint8_t *)offsetof(CPUState, df)),
735 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
736 : "%ecx", "%edx"
737 );
738 }
739 }
740 #elif defined(__ia64)
741 struct fptr {
742 void *ip;
743 void *gp;
744 } fp;
745
746 fp.ip = tc_ptr;
747 fp.gp = code_gen_buffer + 2 * (1 << 20);
748 (*(void (*)(void)) &fp)();
749 #else
750 gen_func();
751 #endif
752 env->current_tb = NULL;
753 /* reset soft MMU for next block (it can currently
754 only be set by a memory fault) */
755 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
756 if (env->hflags & HF_SOFTMMU_MASK) {
757 env->hflags &= ~HF_SOFTMMU_MASK;
758 /* do not allow linking to another block */
759 T0 = 0;
760 }
761 #endif
762 #if defined(USE_KQEMU)
763 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
764 if (kqemu_is_ok(env) &&
765 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
766 cpu_loop_exit();
767 }
768 #endif
769 }
770 } else {
771 env_to_regs();
772 }
773 } /* for(;;) */
774
775
776 #if defined(TARGET_I386)
777 #if defined(USE_CODE_COPY)
778 if (env->native_fp_regs) {
779 save_native_fp_state(env);
780 }
781 #endif
782 /* restore flags in standard format */
783 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
784
785 /* restore global registers */
786 #ifdef reg_EAX
787 EAX = saved_EAX;
788 #endif
789 #ifdef reg_ECX
790 ECX = saved_ECX;
791 #endif
792 #ifdef reg_EDX
793 EDX = saved_EDX;
794 #endif
795 #ifdef reg_EBX
796 EBX = saved_EBX;
797 #endif
798 #ifdef reg_ESP
799 ESP = saved_ESP;
800 #endif
801 #ifdef reg_EBP
802 EBP = saved_EBP;
803 #endif
804 #ifdef reg_ESI
805 ESI = saved_ESI;
806 #endif
807 #ifdef reg_EDI
808 EDI = saved_EDI;
809 #endif
810 #elif defined(TARGET_ARM)
811 /* XXX: Save/restore host fpu exception state?. */
812 #elif defined(TARGET_SPARC)
813 #if defined(reg_REGWPTR)
814 REGWPTR = saved_regwptr;
815 #endif
816 #elif defined(TARGET_PPC)
817 #elif defined(TARGET_MIPS)
818 #else
819 #error unsupported target CPU
820 #endif
821 #ifdef __sparc__
822 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
823 #endif
824 T0 = saved_T0;
825 T1 = saved_T1;
826 #if defined(reg_T2)
827 T2 = saved_T2;
828 #endif
829 env = saved_env;
830 /* fail safe : never use cpu_single_env outside cpu_exec() */
831 cpu_single_env = NULL;
832 return ret;
833 }
834
835 /* must only be called from the generated code as an exception can be
836 generated */
837 void tb_invalidate_page_range(target_ulong start, target_ulong end)
838 {
839 /* XXX: cannot enable it yet because it yields to MMU exception
840 where NIP != read address on PowerPC */
841 #if 0
842 target_ulong phys_addr;
843 phys_addr = get_phys_addr_code(env, start);
844 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
845 #endif
846 }
847
848 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
849
850 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
851 {
852 CPUX86State *saved_env;
853
854 saved_env = env;
855 env = s;
856 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
857 selector &= 0xffff;
858 cpu_x86_load_seg_cache(env, seg_reg, selector,
859 (selector << 4), 0xffff, 0);
860 } else {
861 load_seg(seg_reg, selector);
862 }
863 env = saved_env;
864 }
865
866 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
867 {
868 CPUX86State *saved_env;
869
870 saved_env = env;
871 env = s;
872
873 helper_fsave((target_ulong)ptr, data32);
874
875 env = saved_env;
876 }
877
878 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
879 {
880 CPUX86State *saved_env;
881
882 saved_env = env;
883 env = s;
884
885 helper_frstor((target_ulong)ptr, data32);
886
887 env = saved_env;
888 }
889
890 #endif /* TARGET_I386 */
891
892 #if !defined(CONFIG_SOFTMMU)
893
894 #if defined(TARGET_I386)
895
896 /* 'pc' is the host PC at which the exception was raised. 'address' is
897 the effective address of the memory exception. 'is_write' is 1 if a
898 write caused the exception and otherwise 0'. 'old_set' is the
899 signal set which should be restored */
900 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
901 int is_write, sigset_t *old_set,
902 void *puc)
903 {
904 TranslationBlock *tb;
905 int ret;
906
907 if (cpu_single_env)
908 env = cpu_single_env; /* XXX: find a correct solution for multithread */
909 #if defined(DEBUG_SIGNAL)
910 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
911 pc, address, is_write, *(unsigned long *)old_set);
912 #endif
913 /* XXX: locking issue */
914 if (is_write && page_unprotect(address, pc, puc)) {
915 return 1;
916 }
917
918 /* see if it is an MMU fault */
919 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
920 ((env->hflags & HF_CPL_MASK) == 3), 0);
921 if (ret < 0)
922 return 0; /* not an MMU fault */
923 if (ret == 0)
924 return 1; /* the MMU fault was handled without causing real CPU fault */
925 /* now we have a real cpu fault */
926 tb = tb_find_pc(pc);
927 if (tb) {
928 /* the PC is inside the translated code. It means that we have
929 a virtual CPU fault */
930 cpu_restore_state(tb, env, pc, puc);
931 }
932 if (ret == 1) {
933 #if 0
934 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
935 env->eip, env->cr[2], env->error_code);
936 #endif
937 /* we restore the process signal mask as the sigreturn should
938 do it (XXX: use sigsetjmp) */
939 sigprocmask(SIG_SETMASK, old_set, NULL);
940 raise_exception_err(env->exception_index, env->error_code);
941 } else {
942 /* activate soft MMU for this block */
943 env->hflags |= HF_SOFTMMU_MASK;
944 cpu_resume_from_signal(env, puc);
945 }
946 /* never comes here */
947 return 1;
948 }
949
950 #elif defined(TARGET_ARM)
951 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
952 int is_write, sigset_t *old_set,
953 void *puc)
954 {
955 TranslationBlock *tb;
956 int ret;
957
958 if (cpu_single_env)
959 env = cpu_single_env; /* XXX: find a correct solution for multithread */
960 #if defined(DEBUG_SIGNAL)
961 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
962 pc, address, is_write, *(unsigned long *)old_set);
963 #endif
964 /* XXX: locking issue */
965 if (is_write && page_unprotect(address, pc, puc)) {
966 return 1;
967 }
968 /* see if it is an MMU fault */
969 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
970 if (ret < 0)
971 return 0; /* not an MMU fault */
972 if (ret == 0)
973 return 1; /* the MMU fault was handled without causing real CPU fault */
974 /* now we have a real cpu fault */
975 tb = tb_find_pc(pc);
976 if (tb) {
977 /* the PC is inside the translated code. It means that we have
978 a virtual CPU fault */
979 cpu_restore_state(tb, env, pc, puc);
980 }
981 /* we restore the process signal mask as the sigreturn should
982 do it (XXX: use sigsetjmp) */
983 sigprocmask(SIG_SETMASK, old_set, NULL);
984 cpu_loop_exit();
985 }
986 #elif defined(TARGET_SPARC)
987 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
988 int is_write, sigset_t *old_set,
989 void *puc)
990 {
991 TranslationBlock *tb;
992 int ret;
993
994 if (cpu_single_env)
995 env = cpu_single_env; /* XXX: find a correct solution for multithread */
996 #if defined(DEBUG_SIGNAL)
997 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
998 pc, address, is_write, *(unsigned long *)old_set);
999 #endif
1000 /* XXX: locking issue */
1001 if (is_write && page_unprotect(address, pc, puc)) {
1002 return 1;
1003 }
1004 /* see if it is an MMU fault */
1005 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1006 if (ret < 0)
1007 return 0; /* not an MMU fault */
1008 if (ret == 0)
1009 return 1; /* the MMU fault was handled without causing real CPU fault */
1010 /* now we have a real cpu fault */
1011 tb = tb_find_pc(pc);
1012 if (tb) {
1013 /* the PC is inside the translated code. It means that we have
1014 a virtual CPU fault */
1015 cpu_restore_state(tb, env, pc, puc);
1016 }
1017 /* we restore the process signal mask as the sigreturn should
1018 do it (XXX: use sigsetjmp) */
1019 sigprocmask(SIG_SETMASK, old_set, NULL);
1020 cpu_loop_exit();
1021 }
1022 #elif defined (TARGET_PPC)
1023 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1024 int is_write, sigset_t *old_set,
1025 void *puc)
1026 {
1027 TranslationBlock *tb;
1028 int ret;
1029
1030 if (cpu_single_env)
1031 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1032 #if defined(DEBUG_SIGNAL)
1033 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1034 pc, address, is_write, *(unsigned long *)old_set);
1035 #endif
1036 /* XXX: locking issue */
1037 if (is_write && page_unprotect(address, pc, puc)) {
1038 return 1;
1039 }
1040
1041 /* see if it is an MMU fault */
1042 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1043 if (ret < 0)
1044 return 0; /* not an MMU fault */
1045 if (ret == 0)
1046 return 1; /* the MMU fault was handled without causing real CPU fault */
1047
1048 /* now we have a real cpu fault */
1049 tb = tb_find_pc(pc);
1050 if (tb) {
1051 /* the PC is inside the translated code. It means that we have
1052 a virtual CPU fault */
1053 cpu_restore_state(tb, env, pc, puc);
1054 }
1055 if (ret == 1) {
1056 #if 0
1057 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1058 env->nip, env->error_code, tb);
1059 #endif
1060 /* we restore the process signal mask as the sigreturn should
1061 do it (XXX: use sigsetjmp) */
1062 sigprocmask(SIG_SETMASK, old_set, NULL);
1063 do_raise_exception_err(env->exception_index, env->error_code);
1064 } else {
1065 /* activate soft MMU for this block */
1066 cpu_resume_from_signal(env, puc);
1067 }
1068 /* never comes here */
1069 return 1;
1070 }
1071
1072 #elif defined (TARGET_MIPS)
1073 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1074 int is_write, sigset_t *old_set,
1075 void *puc)
1076 {
1077 TranslationBlock *tb;
1078 int ret;
1079
1080 if (cpu_single_env)
1081 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1082 #if defined(DEBUG_SIGNAL)
1083 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1084 pc, address, is_write, *(unsigned long *)old_set);
1085 #endif
1086 /* XXX: locking issue */
1087 if (is_write && page_unprotect(address, pc, puc)) {
1088 return 1;
1089 }
1090
1091 /* see if it is an MMU fault */
1092 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1093 if (ret < 0)
1094 return 0; /* not an MMU fault */
1095 if (ret == 0)
1096 return 1; /* the MMU fault was handled without causing real CPU fault */
1097
1098 /* now we have a real cpu fault */
1099 tb = tb_find_pc(pc);
1100 if (tb) {
1101 /* the PC is inside the translated code. It means that we have
1102 a virtual CPU fault */
1103 cpu_restore_state(tb, env, pc, puc);
1104 }
1105 if (ret == 1) {
1106 #if 0
1107 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1108 env->nip, env->error_code, tb);
1109 #endif
1110 /* we restore the process signal mask as the sigreturn should
1111 do it (XXX: use sigsetjmp) */
1112 sigprocmask(SIG_SETMASK, old_set, NULL);
1113 do_raise_exception_err(env->exception_index, env->error_code);
1114 } else {
1115 /* activate soft MMU for this block */
1116 cpu_resume_from_signal(env, puc);
1117 }
1118 /* never comes here */
1119 return 1;
1120 }
1121
1122 #else
1123 #error unsupported target CPU
1124 #endif
1125
1126 #if defined(__i386__)
1127
1128 #if defined(USE_CODE_COPY)
1129 static void cpu_send_trap(unsigned long pc, int trap,
1130 struct ucontext *uc)
1131 {
1132 TranslationBlock *tb;
1133
1134 if (cpu_single_env)
1135 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1136 /* now we have a real cpu fault */
1137 tb = tb_find_pc(pc);
1138 if (tb) {
1139 /* the PC is inside the translated code. It means that we have
1140 a virtual CPU fault */
1141 cpu_restore_state(tb, env, pc, uc);
1142 }
1143 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1144 raise_exception_err(trap, env->error_code);
1145 }
1146 #endif
1147
1148 int cpu_signal_handler(int host_signum, struct siginfo *info,
1149 void *puc)
1150 {
1151 struct ucontext *uc = puc;
1152 unsigned long pc;
1153 int trapno;
1154
1155 #ifndef REG_EIP
1156 /* for glibc 2.1 */
1157 #define REG_EIP EIP
1158 #define REG_ERR ERR
1159 #define REG_TRAPNO TRAPNO
1160 #endif
1161 pc = uc->uc_mcontext.gregs[REG_EIP];
1162 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1163 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1164 if (trapno == 0x00 || trapno == 0x05) {
1165 /* send division by zero or bound exception */
1166 cpu_send_trap(pc, trapno, uc);
1167 return 1;
1168 } else
1169 #endif
1170 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1171 trapno == 0xe ?
1172 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1173 &uc->uc_sigmask, puc);
1174 }
1175
1176 #elif defined(__x86_64__)
1177
1178 int cpu_signal_handler(int host_signum, struct siginfo *info,
1179 void *puc)
1180 {
1181 struct ucontext *uc = puc;
1182 unsigned long pc;
1183
1184 pc = uc->uc_mcontext.gregs[REG_RIP];
1185 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1186 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1187 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1188 &uc->uc_sigmask, puc);
1189 }
1190
1191 #elif defined(__powerpc__)
1192
1193 /***********************************************************************
1194 * signal context platform-specific definitions
1195 * From Wine
1196 */
1197 #ifdef linux
1198 /* All Registers access - only for local access */
1199 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1200 /* Gpr Registers access */
1201 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1202 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1203 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1204 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1205 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1206 # define LR_sig(context) REG_sig(link, context) /* Link register */
1207 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1208 /* Float Registers access */
1209 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1210 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1211 /* Exception Registers access */
1212 # define DAR_sig(context) REG_sig(dar, context)
1213 # define DSISR_sig(context) REG_sig(dsisr, context)
1214 # define TRAP_sig(context) REG_sig(trap, context)
1215 #endif /* linux */
1216
1217 #ifdef __APPLE__
1218 # include <sys/ucontext.h>
1219 typedef struct ucontext SIGCONTEXT;
1220 /* All Registers access - only for local access */
1221 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1222 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1223 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1224 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1225 /* Gpr Registers access */
1226 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1227 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1228 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1229 # define CTR_sig(context) REG_sig(ctr, context)
1230 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1231 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1232 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1233 /* Float Registers access */
1234 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1235 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1236 /* Exception Registers access */
1237 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1238 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1239 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1240 #endif /* __APPLE__ */
1241
1242 int cpu_signal_handler(int host_signum, struct siginfo *info,
1243 void *puc)
1244 {
1245 struct ucontext *uc = puc;
1246 unsigned long pc;
1247 int is_write;
1248
1249 pc = IAR_sig(uc);
1250 is_write = 0;
1251 #if 0
1252 /* ppc 4xx case */
1253 if (DSISR_sig(uc) & 0x00800000)
1254 is_write = 1;
1255 #else
1256 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1257 is_write = 1;
1258 #endif
1259 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1260 is_write, &uc->uc_sigmask, puc);
1261 }
1262
1263 #elif defined(__alpha__)
1264
1265 int cpu_signal_handler(int host_signum, struct siginfo *info,
1266 void *puc)
1267 {
1268 struct ucontext *uc = puc;
1269 uint32_t *pc = uc->uc_mcontext.sc_pc;
1270 uint32_t insn = *pc;
1271 int is_write = 0;
1272
1273 /* XXX: need kernel patch to get write flag faster */
1274 switch (insn >> 26) {
1275 case 0x0d: // stw
1276 case 0x0e: // stb
1277 case 0x0f: // stq_u
1278 case 0x24: // stf
1279 case 0x25: // stg
1280 case 0x26: // sts
1281 case 0x27: // stt
1282 case 0x2c: // stl
1283 case 0x2d: // stq
1284 case 0x2e: // stl_c
1285 case 0x2f: // stq_c
1286 is_write = 1;
1287 }
1288
1289 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1290 is_write, &uc->uc_sigmask, puc);
1291 }
1292 #elif defined(__sparc__)
1293
1294 int cpu_signal_handler(int host_signum, struct siginfo *info,
1295 void *puc)
1296 {
1297 uint32_t *regs = (uint32_t *)(info + 1);
1298 void *sigmask = (regs + 20);
1299 unsigned long pc;
1300 int is_write;
1301 uint32_t insn;
1302
1303 /* XXX: is there a standard glibc define ? */
1304 pc = regs[1];
1305 /* XXX: need kernel patch to get write flag faster */
1306 is_write = 0;
1307 insn = *(uint32_t *)pc;
1308 if ((insn >> 30) == 3) {
1309 switch((insn >> 19) & 0x3f) {
1310 case 0x05: // stb
1311 case 0x06: // sth
1312 case 0x04: // st
1313 case 0x07: // std
1314 case 0x24: // stf
1315 case 0x27: // stdf
1316 case 0x25: // stfsr
1317 is_write = 1;
1318 break;
1319 }
1320 }
1321 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1322 is_write, sigmask, NULL);
1323 }
1324
1325 #elif defined(__arm__)
1326
1327 int cpu_signal_handler(int host_signum, struct siginfo *info,
1328 void *puc)
1329 {
1330 struct ucontext *uc = puc;
1331 unsigned long pc;
1332 int is_write;
1333
1334 pc = uc->uc_mcontext.gregs[R15];
1335 /* XXX: compute is_write */
1336 is_write = 0;
1337 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1338 is_write,
1339 &uc->uc_sigmask);
1340 }
1341
1342 #elif defined(__mc68000)
1343
1344 int cpu_signal_handler(int host_signum, struct siginfo *info,
1345 void *puc)
1346 {
1347 struct ucontext *uc = puc;
1348 unsigned long pc;
1349 int is_write;
1350
1351 pc = uc->uc_mcontext.gregs[16];
1352 /* XXX: compute is_write */
1353 is_write = 0;
1354 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1355 is_write,
1356 &uc->uc_sigmask, puc);
1357 }
1358
1359 #elif defined(__ia64)
1360
1361 #ifndef __ISR_VALID
1362 /* This ought to be in <bits/siginfo.h>... */
1363 # define __ISR_VALID 1
1364 # define si_flags _sifields._sigfault._si_pad0
1365 #endif
1366
1367 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1368 {
1369 struct ucontext *uc = puc;
1370 unsigned long ip;
1371 int is_write = 0;
1372
1373 ip = uc->uc_mcontext.sc_ip;
1374 switch (host_signum) {
1375 case SIGILL:
1376 case SIGFPE:
1377 case SIGSEGV:
1378 case SIGBUS:
1379 case SIGTRAP:
1380 if (info->si_code && (info->si_flags & __ISR_VALID))
1381 /* ISR.W (write-access) is bit 33: */
1382 is_write = (info->si_isr >> 33) & 1;
1383 break;
1384
1385 default:
1386 break;
1387 }
1388 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1389 is_write,
1390 &uc->uc_sigmask, puc);
1391 }
1392
1393 #elif defined(__s390__)
1394
1395 int cpu_signal_handler(int host_signum, struct siginfo *info,
1396 void *puc)
1397 {
1398 struct ucontext *uc = puc;
1399 unsigned long pc;
1400 int is_write;
1401
1402 pc = uc->uc_mcontext.psw.addr;
1403 /* XXX: compute is_write */
1404 is_write = 0;
1405 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1406 is_write,
1407 &uc->uc_sigmask, puc);
1408 }
1409
1410 #else
1411
1412 #error host CPU specific signal handler needed
1413
1414 #endif
1415
1416 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board