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bFLT 64-bit host fix.
[qemu/mini2440.git] / cpu-exec.c
blob0b5f7f3d86fa8a066e7534bcb8b42fce5178e5f8
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
181 #else
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
195 cs_base = 0;
196 pc = env->PC;
197 #elif defined(TARGET_SH4)
198 flags = env->sr & (SR_MD | SR_RB);
199 cs_base = 0; /* XXXXX */
200 pc = env->pc;
201 #else
202 #error unsupported CPU
203 #endif
204 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
205 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
206 tb->flags != flags, 0)) {
207 tb = tb_find_slow(pc, cs_base, flags);
208 /* Note: we do it here to avoid a gcc bug on Mac OS X when
209 doing it in tb_find_slow */
210 if (tb_invalidated_flag) {
211 /* as some TB could have been invalidated because
212 of memory exceptions while generating the code, we
213 must recompute the hash index here */
214 T0 = 0;
215 }
216 }
217 return tb;
218 }
219
220
221 /* main execution loop */
222
223 int cpu_exec(CPUState *env1)
224 {
225 int saved_T0, saved_T1;
226 #if defined(reg_T2)
227 int saved_T2;
228 #endif
229 CPUState *saved_env;
230 #if defined(TARGET_I386)
231 #ifdef reg_EAX
232 int saved_EAX;
233 #endif
234 #ifdef reg_ECX
235 int saved_ECX;
236 #endif
237 #ifdef reg_EDX
238 int saved_EDX;
239 #endif
240 #ifdef reg_EBX
241 int saved_EBX;
242 #endif
243 #ifdef reg_ESP
244 int saved_ESP;
245 #endif
246 #ifdef reg_EBP
247 int saved_EBP;
248 #endif
249 #ifdef reg_ESI
250 int saved_ESI;
251 #endif
252 #ifdef reg_EDI
253 int saved_EDI;
254 #endif
255 #elif defined(TARGET_SPARC)
256 #if defined(reg_REGWPTR)
257 uint32_t *saved_regwptr;
258 #endif
259 #endif
260 #if defined(__sparc__) && !defined(HOST_SOLARIS)
261 int saved_i7, tmp_T0;
262 #endif
263 int ret, interrupt_request;
264 void (*gen_func)(void);
265 TranslationBlock *tb;
266 uint8_t *tc_ptr;
267
268 #if defined(TARGET_I386)
269 /* handle exit of HALTED state */
270 if (env1->hflags & HF_HALTED_MASK) {
271 /* disable halt condition */
272 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
273 (env1->eflags & IF_MASK)) {
274 env1->hflags &= ~HF_HALTED_MASK;
275 } else {
276 return EXCP_HALTED;
277 }
278 }
279 #elif defined(TARGET_PPC)
280 if (env1->halted) {
281 if (env1->msr[MSR_EE] &&
282 (env1->interrupt_request &
283 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
284 env1->halted = 0;
285 } else {
286 return EXCP_HALTED;
287 }
288 }
289 #elif defined(TARGET_SPARC)
290 if (env1->halted) {
291 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
292 (env1->psret != 0)) {
293 env1->halted = 0;
294 } else {
295 return EXCP_HALTED;
296 }
297 }
298 #elif defined(TARGET_ARM)
299 if (env1->halted) {
300 /* An interrupt wakes the CPU even if the I and F CPSR bits are
301 set. */
302 if (env1->interrupt_request
303 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
304 env1->halted = 0;
305 } else {
306 return EXCP_HALTED;
307 }
308 }
309 #elif defined(TARGET_MIPS)
310 if (env1->halted) {
311 if (env1->interrupt_request &
312 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
313 env1->halted = 0;
314 } else {
315 return EXCP_HALTED;
316 }
317 }
318 #endif
319
320 cpu_single_env = env1;
321
322 /* first we save global registers */
323 saved_env = env;
324 env = env1;
325 saved_T0 = T0;
326 saved_T1 = T1;
327 #if defined(reg_T2)
328 saved_T2 = T2;
329 #endif
330 #if defined(__sparc__) && !defined(HOST_SOLARIS)
331 /* we also save i7 because longjmp may not restore it */
332 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
333 #endif
334
335 #if defined(TARGET_I386)
336 #ifdef reg_EAX
337 saved_EAX = EAX;
338 #endif
339 #ifdef reg_ECX
340 saved_ECX = ECX;
341 #endif
342 #ifdef reg_EDX
343 saved_EDX = EDX;
344 #endif
345 #ifdef reg_EBX
346 saved_EBX = EBX;
347 #endif
348 #ifdef reg_ESP
349 saved_ESP = ESP;
350 #endif
351 #ifdef reg_EBP
352 saved_EBP = EBP;
353 #endif
354 #ifdef reg_ESI
355 saved_ESI = ESI;
356 #endif
357 #ifdef reg_EDI
358 saved_EDI = EDI;
359 #endif
360
361 env_to_regs();
362 /* put eflags in CPU temporary format */
363 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
364 DF = 1 - (2 * ((env->eflags >> 10) & 1));
365 CC_OP = CC_OP_EFLAGS;
366 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
367 #elif defined(TARGET_ARM)
368 #elif defined(TARGET_SPARC)
369 #if defined(reg_REGWPTR)
370 saved_regwptr = REGWPTR;
371 #endif
372 #elif defined(TARGET_PPC)
373 #elif defined(TARGET_MIPS)
374 #elif defined(TARGET_SH4)
375 /* XXXXX */
376 #else
377 #error unsupported target CPU
378 #endif
379 env->exception_index = -1;
380
381 /* prepare setjmp context for exception handling */
382 for(;;) {
383 if (setjmp(env->jmp_env) == 0) {
384 env->current_tb = NULL;
385 /* if an exception is pending, we execute it here */
386 if (env->exception_index >= 0) {
387 if (env->exception_index >= EXCP_INTERRUPT) {
388 /* exit request from the cpu execution loop */
389 ret = env->exception_index;
390 break;
391 } else if (env->user_mode_only) {
392 /* if user mode only, we simulate a fake exception
393 which will be hanlded outside the cpu execution
394 loop */
395 #if defined(TARGET_I386)
396 do_interrupt_user(env->exception_index,
397 env->exception_is_int,
398 env->error_code,
399 env->exception_next_eip);
400 #endif
401 ret = env->exception_index;
402 break;
403 } else {
404 #if defined(TARGET_I386)
405 /* simulate a real cpu exception. On i386, it can
406 trigger new exceptions, but we do not handle
407 double or triple faults yet. */
408 do_interrupt(env->exception_index,
409 env->exception_is_int,
410 env->error_code,
411 env->exception_next_eip, 0);
412 #elif defined(TARGET_PPC)
413 do_interrupt(env);
414 #elif defined(TARGET_MIPS)
415 do_interrupt(env);
416 #elif defined(TARGET_SPARC)
417 do_interrupt(env->exception_index);
418 #elif defined(TARGET_ARM)
419 do_interrupt(env);
420 #elif defined(TARGET_SH4)
421 do_interrupt(env);
422 #endif
423 }
424 env->exception_index = -1;
425 }
426 #ifdef USE_KQEMU
427 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
428 int ret;
429 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
430 ret = kqemu_cpu_exec(env);
431 /* put eflags in CPU temporary format */
432 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
433 DF = 1 - (2 * ((env->eflags >> 10) & 1));
434 CC_OP = CC_OP_EFLAGS;
435 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
436 if (ret == 1) {
437 /* exception */
438 longjmp(env->jmp_env, 1);
439 } else if (ret == 2) {
440 /* softmmu execution needed */
441 } else {
442 if (env->interrupt_request != 0) {
443 /* hardware interrupt will be executed just after */
444 } else {
445 /* otherwise, we restart */
446 longjmp(env->jmp_env, 1);
447 }
448 }
449 }
450 #endif
451
452 T0 = 0; /* force lookup of first TB */
453 for(;;) {
454 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 /* g1 can be modified by some libc? functions */
456 tmp_T0 = T0;
457 #endif
458 interrupt_request = env->interrupt_request;
459 if (__builtin_expect(interrupt_request, 0)) {
460 #if defined(TARGET_I386)
461 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
462 !(env->hflags & HF_SMM_MASK)) {
463 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
464 do_smm_enter();
465 #if defined(__sparc__) && !defined(HOST_SOLARIS)
466 tmp_T0 = 0;
467 #else
468 T0 = 0;
469 #endif
470 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
471 (env->eflags & IF_MASK) &&
472 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
473 int intno;
474 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
475 intno = cpu_get_pic_interrupt(env);
476 if (loglevel & CPU_LOG_TB_IN_ASM) {
477 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
478 }
479 do_interrupt(intno, 0, 0, 0, 1);
480 /* ensure that no TB jump will be modified as
481 the program flow was changed */
482 #if defined(__sparc__) && !defined(HOST_SOLARIS)
483 tmp_T0 = 0;
484 #else
485 T0 = 0;
486 #endif
487 }
488 #elif defined(TARGET_PPC)
489 #if 0
490 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
491 cpu_ppc_reset(env);
492 }
493 #endif
494 if (msr_ee != 0) {
495 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
496 /* Raise it */
497 env->exception_index = EXCP_EXTERNAL;
498 env->error_code = 0;
499 do_interrupt(env);
500 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
501 #if defined(__sparc__) && !defined(HOST_SOLARIS)
502 tmp_T0 = 0;
503 #else
504 T0 = 0;
505 #endif
506 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
507 /* Raise it */
508 env->exception_index = EXCP_DECR;
509 env->error_code = 0;
510 do_interrupt(env);
511 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
512 #if defined(__sparc__) && !defined(HOST_SOLARIS)
513 tmp_T0 = 0;
514 #else
515 T0 = 0;
516 #endif
517 }
518 }
519 #elif defined(TARGET_MIPS)
520 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
521 (env->CP0_Status & (1 << CP0St_IE)) &&
522 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
523 !(env->hflags & MIPS_HFLAG_EXL) &&
524 !(env->hflags & MIPS_HFLAG_ERL) &&
525 !(env->hflags & MIPS_HFLAG_DM)) {
526 /* Raise it */
527 env->exception_index = EXCP_EXT_INTERRUPT;
528 env->error_code = 0;
529 do_interrupt(env);
530 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
531 #if defined(__sparc__) && !defined(HOST_SOLARIS)
532 tmp_T0 = 0;
533 #else
534 T0 = 0;
535 #endif
536 }
537 #elif defined(TARGET_SPARC)
538 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
539 (env->psret != 0)) {
540 int pil = env->interrupt_index & 15;
541 int type = env->interrupt_index & 0xf0;
542
543 if (((type == TT_EXTINT) &&
544 (pil == 15 || pil > env->psrpil)) ||
545 type != TT_EXTINT) {
546 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
547 do_interrupt(env->interrupt_index);
548 env->interrupt_index = 0;
549 #if defined(__sparc__) && !defined(HOST_SOLARIS)
550 tmp_T0 = 0;
551 #else
552 T0 = 0;
553 #endif
554 }
555 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
556 //do_interrupt(0, 0, 0, 0, 0);
557 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
558 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
559 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
560 env->halted = 1;
561 env->exception_index = EXCP_HLT;
562 cpu_loop_exit();
563 }
564 #elif defined(TARGET_ARM)
565 if (interrupt_request & CPU_INTERRUPT_FIQ
566 && !(env->uncached_cpsr & CPSR_F)) {
567 env->exception_index = EXCP_FIQ;
568 do_interrupt(env);
569 }
570 if (interrupt_request & CPU_INTERRUPT_HARD
571 && !(env->uncached_cpsr & CPSR_I)) {
572 env->exception_index = EXCP_IRQ;
573 do_interrupt(env);
574 }
575 #elif defined(TARGET_SH4)
576 /* XXXXX */
577 #endif
578 /* Don't use the cached interupt_request value,
579 do_interrupt may have updated the EXITTB flag. */
580 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
581 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
582 /* ensure that no TB jump will be modified as
583 the program flow was changed */
584 #if defined(__sparc__) && !defined(HOST_SOLARIS)
585 tmp_T0 = 0;
586 #else
587 T0 = 0;
588 #endif
589 }
590 if (interrupt_request & CPU_INTERRUPT_EXIT) {
591 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
592 env->exception_index = EXCP_INTERRUPT;
593 cpu_loop_exit();
594 }
595 }
596 #ifdef DEBUG_EXEC
597 if ((loglevel & CPU_LOG_TB_CPU)) {
598 #if defined(TARGET_I386)
599 /* restore flags in standard format */
600 #ifdef reg_EAX
601 env->regs[R_EAX] = EAX;
602 #endif
603 #ifdef reg_EBX
604 env->regs[R_EBX] = EBX;
605 #endif
606 #ifdef reg_ECX
607 env->regs[R_ECX] = ECX;
608 #endif
609 #ifdef reg_EDX
610 env->regs[R_EDX] = EDX;
611 #endif
612 #ifdef reg_ESI
613 env->regs[R_ESI] = ESI;
614 #endif
615 #ifdef reg_EDI
616 env->regs[R_EDI] = EDI;
617 #endif
618 #ifdef reg_EBP
619 env->regs[R_EBP] = EBP;
620 #endif
621 #ifdef reg_ESP
622 env->regs[R_ESP] = ESP;
623 #endif
624 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
625 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
626 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
627 #elif defined(TARGET_ARM)
628 cpu_dump_state(env, logfile, fprintf, 0);
629 #elif defined(TARGET_SPARC)
630 REGWPTR = env->regbase + (env->cwp * 16);
631 env->regwptr = REGWPTR;
632 cpu_dump_state(env, logfile, fprintf, 0);
633 #elif defined(TARGET_PPC)
634 cpu_dump_state(env, logfile, fprintf, 0);
635 #elif defined(TARGET_MIPS)
636 cpu_dump_state(env, logfile, fprintf, 0);
637 #elif defined(TARGET_SH4)
638 cpu_dump_state(env, logfile, fprintf, 0);
639 #else
640 #error unsupported target CPU
641 #endif
642 }
643 #endif
644 tb = tb_find_fast();
645 #ifdef DEBUG_EXEC
646 if ((loglevel & CPU_LOG_EXEC)) {
647 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
648 (long)tb->tc_ptr, tb->pc,
649 lookup_symbol(tb->pc));
650 }
651 #endif
652 #if defined(__sparc__) && !defined(HOST_SOLARIS)
653 T0 = tmp_T0;
654 #endif
655 /* see if we can patch the calling TB. When the TB
656 spans two pages, we cannot safely do a direct
657 jump. */
658 {
659 if (T0 != 0 &&
660 #if USE_KQEMU
661 (env->kqemu_enabled != 2) &&
662 #endif
663 tb->page_addr[1] == -1
664 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
665 && (tb->cflags & CF_CODE_COPY) ==
666 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
667 #endif
668 ) {
669 spin_lock(&tb_lock);
670 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
671 #if defined(USE_CODE_COPY)
672 /* propagates the FP use info */
673 ((TranslationBlock *)(T0 & ~3))->cflags |=
674 (tb->cflags & CF_FP_USED);
675 #endif
676 spin_unlock(&tb_lock);
677 }
678 }
679 tc_ptr = tb->tc_ptr;
680 env->current_tb = tb;
681 /* execute the generated code */
682 gen_func = (void *)tc_ptr;
683 #if defined(__sparc__)
684 __asm__ __volatile__("call %0\n\t"
685 "mov %%o7,%%i0"
686 : /* no outputs */
687 : "r" (gen_func)
688 : "i0", "i1", "i2", "i3", "i4", "i5",
689 "l0", "l1", "l2", "l3", "l4", "l5",
690 "l6", "l7");
691 #elif defined(__arm__)
692 asm volatile ("mov pc, %0\n\t"
693 ".global exec_loop\n\t"
694 "exec_loop:\n\t"
695 : /* no outputs */
696 : "r" (gen_func)
697 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
698 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
699 {
700 if (!(tb->cflags & CF_CODE_COPY)) {
701 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
702 save_native_fp_state(env);
703 }
704 gen_func();
705 } else {
706 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
707 restore_native_fp_state(env);
708 }
709 /* we work with native eflags */
710 CC_SRC = cc_table[CC_OP].compute_all();
711 CC_OP = CC_OP_EFLAGS;
712 asm(".globl exec_loop\n"
713 "\n"
714 "debug1:\n"
715 " pushl %%ebp\n"
716 " fs movl %10, %9\n"
717 " fs movl %11, %%eax\n"
718 " andl $0x400, %%eax\n"
719 " fs orl %8, %%eax\n"
720 " pushl %%eax\n"
721 " popf\n"
722 " fs movl %%esp, %12\n"
723 " fs movl %0, %%eax\n"
724 " fs movl %1, %%ecx\n"
725 " fs movl %2, %%edx\n"
726 " fs movl %3, %%ebx\n"
727 " fs movl %4, %%esp\n"
728 " fs movl %5, %%ebp\n"
729 " fs movl %6, %%esi\n"
730 " fs movl %7, %%edi\n"
731 " fs jmp *%9\n"
732 "exec_loop:\n"
733 " fs movl %%esp, %4\n"
734 " fs movl %12, %%esp\n"
735 " fs movl %%eax, %0\n"
736 " fs movl %%ecx, %1\n"
737 " fs movl %%edx, %2\n"
738 " fs movl %%ebx, %3\n"
739 " fs movl %%ebp, %5\n"
740 " fs movl %%esi, %6\n"
741 " fs movl %%edi, %7\n"
742 " pushf\n"
743 " popl %%eax\n"
744 " movl %%eax, %%ecx\n"
745 " andl $0x400, %%ecx\n"
746 " shrl $9, %%ecx\n"
747 " andl $0x8d5, %%eax\n"
748 " fs movl %%eax, %8\n"
749 " movl $1, %%eax\n"
750 " subl %%ecx, %%eax\n"
751 " fs movl %%eax, %11\n"
752 " fs movl %9, %%ebx\n" /* get T0 value */
753 " popl %%ebp\n"
754 :
755 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
756 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
757 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
758 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
759 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
760 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
761 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
762 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
763 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
764 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
765 "a" (gen_func),
766 "m" (*(uint8_t *)offsetof(CPUState, df)),
767 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
768 : "%ecx", "%edx"
769 );
770 }
771 }
772 #elif defined(__ia64)
773 struct fptr {
774 void *ip;
775 void *gp;
776 } fp;
777
778 fp.ip = tc_ptr;
779 fp.gp = code_gen_buffer + 2 * (1 << 20);
780 (*(void (*)(void)) &fp)();
781 #else
782 gen_func();
783 #endif
784 env->current_tb = NULL;
785 /* reset soft MMU for next block (it can currently
786 only be set by a memory fault) */
787 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
788 if (env->hflags & HF_SOFTMMU_MASK) {
789 env->hflags &= ~HF_SOFTMMU_MASK;
790 /* do not allow linking to another block */
791 T0 = 0;
792 }
793 #endif
794 #if defined(USE_KQEMU)
795 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
796 if (kqemu_is_ok(env) &&
797 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
798 cpu_loop_exit();
799 }
800 #endif
801 }
802 } else {
803 env_to_regs();
804 }
805 } /* for(;;) */
806
807
808 #if defined(TARGET_I386)
809 #if defined(USE_CODE_COPY)
810 if (env->native_fp_regs) {
811 save_native_fp_state(env);
812 }
813 #endif
814 /* restore flags in standard format */
815 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
816
817 /* restore global registers */
818 #ifdef reg_EAX
819 EAX = saved_EAX;
820 #endif
821 #ifdef reg_ECX
822 ECX = saved_ECX;
823 #endif
824 #ifdef reg_EDX
825 EDX = saved_EDX;
826 #endif
827 #ifdef reg_EBX
828 EBX = saved_EBX;
829 #endif
830 #ifdef reg_ESP
831 ESP = saved_ESP;
832 #endif
833 #ifdef reg_EBP
834 EBP = saved_EBP;
835 #endif
836 #ifdef reg_ESI
837 ESI = saved_ESI;
838 #endif
839 #ifdef reg_EDI
840 EDI = saved_EDI;
841 #endif
842 #elif defined(TARGET_ARM)
843 /* XXX: Save/restore host fpu exception state?. */
844 #elif defined(TARGET_SPARC)
845 #if defined(reg_REGWPTR)
846 REGWPTR = saved_regwptr;
847 #endif
848 #elif defined(TARGET_PPC)
849 #elif defined(TARGET_MIPS)
850 #elif defined(TARGET_SH4)
851 /* XXXXX */
852 #else
853 #error unsupported target CPU
854 #endif
855 #if defined(__sparc__) && !defined(HOST_SOLARIS)
856 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
857 #endif
858 T0 = saved_T0;
859 T1 = saved_T1;
860 #if defined(reg_T2)
861 T2 = saved_T2;
862 #endif
863 env = saved_env;
864 /* fail safe : never use cpu_single_env outside cpu_exec() */
865 cpu_single_env = NULL;
866 return ret;
867 }
868
869 /* must only be called from the generated code as an exception can be
870 generated */
871 void tb_invalidate_page_range(target_ulong start, target_ulong end)
872 {
873 /* XXX: cannot enable it yet because it yields to MMU exception
874 where NIP != read address on PowerPC */
875 #if 0
876 target_ulong phys_addr;
877 phys_addr = get_phys_addr_code(env, start);
878 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
879 #endif
880 }
881
882 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
883
884 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
885 {
886 CPUX86State *saved_env;
887
888 saved_env = env;
889 env = s;
890 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
891 selector &= 0xffff;
892 cpu_x86_load_seg_cache(env, seg_reg, selector,
893 (selector << 4), 0xffff, 0);
894 } else {
895 load_seg(seg_reg, selector);
896 }
897 env = saved_env;
898 }
899
900 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
901 {
902 CPUX86State *saved_env;
903
904 saved_env = env;
905 env = s;
906
907 helper_fsave((target_ulong)ptr, data32);
908
909 env = saved_env;
910 }
911
912 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
913 {
914 CPUX86State *saved_env;
915
916 saved_env = env;
917 env = s;
918
919 helper_frstor((target_ulong)ptr, data32);
920
921 env = saved_env;
922 }
923
924 #endif /* TARGET_I386 */
925
926 #if !defined(CONFIG_SOFTMMU)
927
928 #if defined(TARGET_I386)
929
930 /* 'pc' is the host PC at which the exception was raised. 'address' is
931 the effective address of the memory exception. 'is_write' is 1 if a
932 write caused the exception and otherwise 0'. 'old_set' is the
933 signal set which should be restored */
934 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
935 int is_write, sigset_t *old_set,
936 void *puc)
937 {
938 TranslationBlock *tb;
939 int ret;
940
941 if (cpu_single_env)
942 env = cpu_single_env; /* XXX: find a correct solution for multithread */
943 #if defined(DEBUG_SIGNAL)
944 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
945 pc, address, is_write, *(unsigned long *)old_set);
946 #endif
947 /* XXX: locking issue */
948 if (is_write && page_unprotect(h2g(address), pc, puc)) {
949 return 1;
950 }
951
952 /* see if it is an MMU fault */
953 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
954 ((env->hflags & HF_CPL_MASK) == 3), 0);
955 if (ret < 0)
956 return 0; /* not an MMU fault */
957 if (ret == 0)
958 return 1; /* the MMU fault was handled without causing real CPU fault */
959 /* now we have a real cpu fault */
960 tb = tb_find_pc(pc);
961 if (tb) {
962 /* the PC is inside the translated code. It means that we have
963 a virtual CPU fault */
964 cpu_restore_state(tb, env, pc, puc);
965 }
966 if (ret == 1) {
967 #if 0
968 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
969 env->eip, env->cr[2], env->error_code);
970 #endif
971 /* we restore the process signal mask as the sigreturn should
972 do it (XXX: use sigsetjmp) */
973 sigprocmask(SIG_SETMASK, old_set, NULL);
974 raise_exception_err(env->exception_index, env->error_code);
975 } else {
976 /* activate soft MMU for this block */
977 env->hflags |= HF_SOFTMMU_MASK;
978 cpu_resume_from_signal(env, puc);
979 }
980 /* never comes here */
981 return 1;
982 }
983
984 #elif defined(TARGET_ARM)
985 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
986 int is_write, sigset_t *old_set,
987 void *puc)
988 {
989 TranslationBlock *tb;
990 int ret;
991
992 if (cpu_single_env)
993 env = cpu_single_env; /* XXX: find a correct solution for multithread */
994 #if defined(DEBUG_SIGNAL)
995 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
996 pc, address, is_write, *(unsigned long *)old_set);
997 #endif
998 /* XXX: locking issue */
999 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1000 return 1;
1001 }
1002 /* see if it is an MMU fault */
1003 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
1004 if (ret < 0)
1005 return 0; /* not an MMU fault */
1006 if (ret == 0)
1007 return 1; /* the MMU fault was handled without causing real CPU fault */
1008 /* now we have a real cpu fault */
1009 tb = tb_find_pc(pc);
1010 if (tb) {
1011 /* the PC is inside the translated code. It means that we have
1012 a virtual CPU fault */
1013 cpu_restore_state(tb, env, pc, puc);
1014 }
1015 /* we restore the process signal mask as the sigreturn should
1016 do it (XXX: use sigsetjmp) */
1017 sigprocmask(SIG_SETMASK, old_set, NULL);
1018 cpu_loop_exit();
1019 }
1020 #elif defined(TARGET_SPARC)
1021 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1022 int is_write, sigset_t *old_set,
1023 void *puc)
1024 {
1025 TranslationBlock *tb;
1026 int ret;
1027
1028 if (cpu_single_env)
1029 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1030 #if defined(DEBUG_SIGNAL)
1031 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1032 pc, address, is_write, *(unsigned long *)old_set);
1033 #endif
1034 /* XXX: locking issue */
1035 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1036 return 1;
1037 }
1038 /* see if it is an MMU fault */
1039 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1040 if (ret < 0)
1041 return 0; /* not an MMU fault */
1042 if (ret == 0)
1043 return 1; /* the MMU fault was handled without causing real CPU fault */
1044 /* now we have a real cpu fault */
1045 tb = tb_find_pc(pc);
1046 if (tb) {
1047 /* the PC is inside the translated code. It means that we have
1048 a virtual CPU fault */
1049 cpu_restore_state(tb, env, pc, puc);
1050 }
1051 /* we restore the process signal mask as the sigreturn should
1052 do it (XXX: use sigsetjmp) */
1053 sigprocmask(SIG_SETMASK, old_set, NULL);
1054 cpu_loop_exit();
1055 }
1056 #elif defined (TARGET_PPC)
1057 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1058 int is_write, sigset_t *old_set,
1059 void *puc)
1060 {
1061 TranslationBlock *tb;
1062 int ret;
1063
1064 if (cpu_single_env)
1065 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1066 #if defined(DEBUG_SIGNAL)
1067 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1068 pc, address, is_write, *(unsigned long *)old_set);
1069 #endif
1070 /* XXX: locking issue */
1071 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1072 return 1;
1073 }
1074
1075 /* see if it is an MMU fault */
1076 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1077 if (ret < 0)
1078 return 0; /* not an MMU fault */
1079 if (ret == 0)
1080 return 1; /* the MMU fault was handled without causing real CPU fault */
1081
1082 /* now we have a real cpu fault */
1083 tb = tb_find_pc(pc);
1084 if (tb) {
1085 /* the PC is inside the translated code. It means that we have
1086 a virtual CPU fault */
1087 cpu_restore_state(tb, env, pc, puc);
1088 }
1089 if (ret == 1) {
1090 #if 0
1091 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1092 env->nip, env->error_code, tb);
1093 #endif
1094 /* we restore the process signal mask as the sigreturn should
1095 do it (XXX: use sigsetjmp) */
1096 sigprocmask(SIG_SETMASK, old_set, NULL);
1097 do_raise_exception_err(env->exception_index, env->error_code);
1098 } else {
1099 /* activate soft MMU for this block */
1100 cpu_resume_from_signal(env, puc);
1101 }
1102 /* never comes here */
1103 return 1;
1104 }
1105
1106 #elif defined (TARGET_MIPS)
1107 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1108 int is_write, sigset_t *old_set,
1109 void *puc)
1110 {
1111 TranslationBlock *tb;
1112 int ret;
1113
1114 if (cpu_single_env)
1115 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1116 #if defined(DEBUG_SIGNAL)
1117 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1118 pc, address, is_write, *(unsigned long *)old_set);
1119 #endif
1120 /* XXX: locking issue */
1121 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1122 return 1;
1123 }
1124
1125 /* see if it is an MMU fault */
1126 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1127 if (ret < 0)
1128 return 0; /* not an MMU fault */
1129 if (ret == 0)
1130 return 1; /* the MMU fault was handled without causing real CPU fault */
1131
1132 /* now we have a real cpu fault */
1133 tb = tb_find_pc(pc);
1134 if (tb) {
1135 /* the PC is inside the translated code. It means that we have
1136 a virtual CPU fault */
1137 cpu_restore_state(tb, env, pc, puc);
1138 }
1139 if (ret == 1) {
1140 #if 0
1141 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1142 env->nip, env->error_code, tb);
1143 #endif
1144 /* we restore the process signal mask as the sigreturn should
1145 do it (XXX: use sigsetjmp) */
1146 sigprocmask(SIG_SETMASK, old_set, NULL);
1147 do_raise_exception_err(env->exception_index, env->error_code);
1148 } else {
1149 /* activate soft MMU for this block */
1150 cpu_resume_from_signal(env, puc);
1151 }
1152 /* never comes here */
1153 return 1;
1154 }
1155
1156 #elif defined (TARGET_SH4)
1157 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1158 int is_write, sigset_t *old_set,
1159 void *puc)
1160 {
1161 TranslationBlock *tb;
1162 int ret;
1163
1164 if (cpu_single_env)
1165 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1166 #if defined(DEBUG_SIGNAL)
1167 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1168 pc, address, is_write, *(unsigned long *)old_set);
1169 #endif
1170 /* XXX: locking issue */
1171 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1172 return 1;
1173 }
1174
1175 /* see if it is an MMU fault */
1176 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1177 if (ret < 0)
1178 return 0; /* not an MMU fault */
1179 if (ret == 0)
1180 return 1; /* the MMU fault was handled without causing real CPU fault */
1181
1182 /* now we have a real cpu fault */
1183 tb = tb_find_pc(pc);
1184 if (tb) {
1185 /* the PC is inside the translated code. It means that we have
1186 a virtual CPU fault */
1187 cpu_restore_state(tb, env, pc, puc);
1188 }
1189 #if 0
1190 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1191 env->nip, env->error_code, tb);
1192 #endif
1193 /* we restore the process signal mask as the sigreturn should
1194 do it (XXX: use sigsetjmp) */
1195 sigprocmask(SIG_SETMASK, old_set, NULL);
1196 cpu_loop_exit();
1197 /* never comes here */
1198 return 1;
1199 }
1200 #else
1201 #error unsupported target CPU
1202 #endif
1203
1204 #if defined(__i386__)
1205
1206 #if defined(USE_CODE_COPY)
1207 static void cpu_send_trap(unsigned long pc, int trap,
1208 struct ucontext *uc)
1209 {
1210 TranslationBlock *tb;
1211
1212 if (cpu_single_env)
1213 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1214 /* now we have a real cpu fault */
1215 tb = tb_find_pc(pc);
1216 if (tb) {
1217 /* the PC is inside the translated code. It means that we have
1218 a virtual CPU fault */
1219 cpu_restore_state(tb, env, pc, uc);
1220 }
1221 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1222 raise_exception_err(trap, env->error_code);
1223 }
1224 #endif
1225
1226 int cpu_signal_handler(int host_signum, struct siginfo *info,
1227 void *puc)
1228 {
1229 struct ucontext *uc = puc;
1230 unsigned long pc;
1231 int trapno;
1232
1233 #ifndef REG_EIP
1234 /* for glibc 2.1 */
1235 #define REG_EIP EIP
1236 #define REG_ERR ERR
1237 #define REG_TRAPNO TRAPNO
1238 #endif
1239 pc = uc->uc_mcontext.gregs[REG_EIP];
1240 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1241 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1242 if (trapno == 0x00 || trapno == 0x05) {
1243 /* send division by zero or bound exception */
1244 cpu_send_trap(pc, trapno, uc);
1245 return 1;
1246 } else
1247 #endif
1248 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1249 trapno == 0xe ?
1250 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1251 &uc->uc_sigmask, puc);
1252 }
1253
1254 #elif defined(__x86_64__)
1255
1256 int cpu_signal_handler(int host_signum, struct siginfo *info,
1257 void *puc)
1258 {
1259 struct ucontext *uc = puc;
1260 unsigned long pc;
1261
1262 pc = uc->uc_mcontext.gregs[REG_RIP];
1263 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1264 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1265 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1266 &uc->uc_sigmask, puc);
1267 }
1268
1269 #elif defined(__powerpc__)
1270
1271 /***********************************************************************
1272 * signal context platform-specific definitions
1273 * From Wine
1274 */
1275 #ifdef linux
1276 /* All Registers access - only for local access */
1277 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1278 /* Gpr Registers access */
1279 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1280 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1281 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1282 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1283 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1284 # define LR_sig(context) REG_sig(link, context) /* Link register */
1285 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1286 /* Float Registers access */
1287 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1288 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1289 /* Exception Registers access */
1290 # define DAR_sig(context) REG_sig(dar, context)
1291 # define DSISR_sig(context) REG_sig(dsisr, context)
1292 # define TRAP_sig(context) REG_sig(trap, context)
1293 #endif /* linux */
1294
1295 #ifdef __APPLE__
1296 # include <sys/ucontext.h>
1297 typedef struct ucontext SIGCONTEXT;
1298 /* All Registers access - only for local access */
1299 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1300 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1301 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1302 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1303 /* Gpr Registers access */
1304 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1305 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1306 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1307 # define CTR_sig(context) REG_sig(ctr, context)
1308 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1309 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1310 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1311 /* Float Registers access */
1312 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1313 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1314 /* Exception Registers access */
1315 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1316 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1317 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1318 #endif /* __APPLE__ */
1319
1320 int cpu_signal_handler(int host_signum, struct siginfo *info,
1321 void *puc)
1322 {
1323 struct ucontext *uc = puc;
1324 unsigned long pc;
1325 int is_write;
1326
1327 pc = IAR_sig(uc);
1328 is_write = 0;
1329 #if 0
1330 /* ppc 4xx case */
1331 if (DSISR_sig(uc) & 0x00800000)
1332 is_write = 1;
1333 #else
1334 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1335 is_write = 1;
1336 #endif
1337 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1338 is_write, &uc->uc_sigmask, puc);
1339 }
1340
1341 #elif defined(__alpha__)
1342
1343 int cpu_signal_handler(int host_signum, struct siginfo *info,
1344 void *puc)
1345 {
1346 struct ucontext *uc = puc;
1347 uint32_t *pc = uc->uc_mcontext.sc_pc;
1348 uint32_t insn = *pc;
1349 int is_write = 0;
1350
1351 /* XXX: need kernel patch to get write flag faster */
1352 switch (insn >> 26) {
1353 case 0x0d: // stw
1354 case 0x0e: // stb
1355 case 0x0f: // stq_u
1356 case 0x24: // stf
1357 case 0x25: // stg
1358 case 0x26: // sts
1359 case 0x27: // stt
1360 case 0x2c: // stl
1361 case 0x2d: // stq
1362 case 0x2e: // stl_c
1363 case 0x2f: // stq_c
1364 is_write = 1;
1365 }
1366
1367 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1368 is_write, &uc->uc_sigmask, puc);
1369 }
1370 #elif defined(__sparc__)
1371
1372 int cpu_signal_handler(int host_signum, struct siginfo *info,
1373 void *puc)
1374 {
1375 uint32_t *regs = (uint32_t *)(info + 1);
1376 void *sigmask = (regs + 20);
1377 unsigned long pc;
1378 int is_write;
1379 uint32_t insn;
1380
1381 /* XXX: is there a standard glibc define ? */
1382 pc = regs[1];
1383 /* XXX: need kernel patch to get write flag faster */
1384 is_write = 0;
1385 insn = *(uint32_t *)pc;
1386 if ((insn >> 30) == 3) {
1387 switch((insn >> 19) & 0x3f) {
1388 case 0x05: // stb
1389 case 0x06: // sth
1390 case 0x04: // st
1391 case 0x07: // std
1392 case 0x24: // stf
1393 case 0x27: // stdf
1394 case 0x25: // stfsr
1395 is_write = 1;
1396 break;
1397 }
1398 }
1399 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1400 is_write, sigmask, NULL);
1401 }
1402
1403 #elif defined(__arm__)
1404
1405 int cpu_signal_handler(int host_signum, struct siginfo *info,
1406 void *puc)
1407 {
1408 struct ucontext *uc = puc;
1409 unsigned long pc;
1410 int is_write;
1411
1412 pc = uc->uc_mcontext.gregs[R15];
1413 /* XXX: compute is_write */
1414 is_write = 0;
1415 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1416 is_write,
1417 &uc->uc_sigmask, puc);
1418 }
1419
1420 #elif defined(__mc68000)
1421
1422 int cpu_signal_handler(int host_signum, struct siginfo *info,
1423 void *puc)
1424 {
1425 struct ucontext *uc = puc;
1426 unsigned long pc;
1427 int is_write;
1428
1429 pc = uc->uc_mcontext.gregs[16];
1430 /* XXX: compute is_write */
1431 is_write = 0;
1432 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1433 is_write,
1434 &uc->uc_sigmask, puc);
1435 }
1436
1437 #elif defined(__ia64)
1438
1439 #ifndef __ISR_VALID
1440 /* This ought to be in <bits/siginfo.h>... */
1441 # define __ISR_VALID 1
1442 #endif
1443
1444 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1445 {
1446 struct ucontext *uc = puc;
1447 unsigned long ip;
1448 int is_write = 0;
1449
1450 ip = uc->uc_mcontext.sc_ip;
1451 switch (host_signum) {
1452 case SIGILL:
1453 case SIGFPE:
1454 case SIGSEGV:
1455 case SIGBUS:
1456 case SIGTRAP:
1457 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1458 /* ISR.W (write-access) is bit 33: */
1459 is_write = (info->si_isr >> 33) & 1;
1460 break;
1461
1462 default:
1463 break;
1464 }
1465 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1466 is_write,
1467 &uc->uc_sigmask, puc);
1468 }
1469
1470 #elif defined(__s390__)
1471
1472 int cpu_signal_handler(int host_signum, struct siginfo *info,
1473 void *puc)
1474 {
1475 struct ucontext *uc = puc;
1476 unsigned long pc;
1477 int is_write;
1478
1479 pc = uc->uc_mcontext.psw.addr;
1480 /* XXX: compute is_write */
1481 is_write = 0;
1482 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1483 is_write,
1484 &uc->uc_sigmask, puc);
1485 }
1486
1487 #else
1488
1489 #error host CPU specific signal handler needed
1490
1491 #endif
1492
1493 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board